diff options
| author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
|---|---|---|
| committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
| commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
| tree | eebe9b0d0ca03062955223097e57da84dd618b9a /ReferenceCode/AcpiTables/Dsdt | |
| download | zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz | |
Diffstat (limited to 'ReferenceCode/AcpiTables/Dsdt')
35 files changed, 14276 insertions, 0 deletions
diff --git a/ReferenceCode/AcpiTables/Dsdt/98_LINK.ASL b/ReferenceCode/AcpiTables/Dsdt/98_LINK.ASL new file mode 100644 index 0000000..b4b67be --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/98_LINK.ASL @@ -0,0 +1,628 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + +// Use this information when determining the Possible IRQs that can be +// used in a given system. +// +// The following IRQs are always in use by legacy devices: +// 0 = System Timer +// 2 = 8259 PIC +// 8 = RTC +// 9 = SCI Interrupt (It may be used, we choose not to) +// 13 = Co-processor Error +// +// The following may be in use by legacy devices: +// 1 = If using PS/2 Keyboard +// 3 = If COMx Port Enabled and IRQ = 3 +// 4 = If COMx Port Enabled and IRQ = 4 +// 5 = If LPT Port Enabled and IRQ = 5 +// 6 = If FDC Enabled +// 7 = If LPT Port Enabled and IRQ = 7 +// 12 = If using PS/2 Mouse +// 14 = Primary IDE (If populated and in Compatibility Mode) +// 15 = Secondary IDE (If populated and in Compatibility Mode) +// +// The following will never be in use by legacy devices: +// 10 = Assign to PARC, PCRC, PERC, PGRC +// 11 = Assign to PBRC, PDRC, PFRC, PHRC + +Device(LNKA) // PARC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) // PCI Interrupt Link Device + + Name(_UID,1) // Unique to other Link Devices + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PARC,0x80,PARC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSA) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLA,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLA,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PARC,0x0F),IRQ0) + + Return(RTLA) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PARC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PARC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKB) // PBRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,2) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PBRC,0x80,PBRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSB) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLB,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLB,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PBRC,0x0F),IRQ0) + + Return(RTLB) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PBRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PBRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKC) // PCRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,3) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PCRC,0x80,PCRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSC) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLC,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLC,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PCRC,0x0F),IRQ0) + + Return(RTLC) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PCRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PCRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKD) // PDRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,4) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PDRC,0x80,PDRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSD) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLD,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLD,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PDRC,0x0F),IRQ0) + + Return(RTLD) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PDRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PDRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKE) // PERC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,5) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PERC,0x80,PERC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSE) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLE,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLE,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PERC,0x0F),IRQ0) + + Return(RTLE) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PERC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PERC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKF) // PFRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,6) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PFRC,0x80,PFRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSF) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLF,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLF,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PFRC,0x0F),IRQ0) + + Return(RTLF) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PFRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PFRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKG) // PGRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,7) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PGRC,0x80,PGRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSG) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLG,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLG,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PGRC,0x0F),IRQ0) + + Return(RTLG) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PGRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PGRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKH) // PHRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,8) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PHRC,0x80,PHRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSH) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLH,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLH,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PHRC,0x0F),IRQ0) + + Return(RTLH) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PHRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PHRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/ALS.ASL b/ReferenceCode/AcpiTables/Dsdt/ALS.ASL new file mode 100644 index 0000000..517aa49 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/ALS.ASL @@ -0,0 +1,57 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + +Device(ALSD) +{ + Name(_HID,"ACPI0008") + + Method(_STA,0) + { + If(LEqual(ALSE,2)) + { + Return(0x000B) // ALS Enabled. Don't show it in UI. + } + + Return(0x0000) // ALS Disabled. Hide it. + } + + Method(_ALI) + { + Return (Or(ShiftLeft(LHIH,8),LLOW)) + } + + Name(_ALR, Package() + { + Package() {70, 0}, + Package() {73, 10}, + Package() {85, 80}, + Package() {100, 300}, + Package() {150, 1000} + }) + +} diff --git a/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.cif b/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.cif new file mode 100644 index 0000000..4dfcbd6 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.cif @@ -0,0 +1,43 @@ +<component> + name = "AcpiAsl" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\Dsdt\" + RefName = "AcpiAsl" +[files] +"AcpiAsl.sdl" +"AcpiAsl.mak" +"Platform.asl" +"GloblNvs.asl" +"CPU.asl" +"THERMAL.ASL" +"PCI_DRC.ASL" +"Video.asl" +"PCIEDOCK.ASL" +"LpcB.asl" +"98_LINK.ASL" +"EC.ASL" +"ALS.ASL" +"Bat0Virt.asl" +"Bat1Real.asl" +"Bat2Real.asl" +"LPC_DEV.ASL" +"NAT_SIO.ASL" +"NAT_LPT.ASL" +"NAT_COM.ASL" +"SMSC1007_SIO.ASL" +"SMSC1007_COM.ASL" +"Gpe.asl" +"WPCN381U_SIO.asl" +"WPCN381U_COM.asl" +"WPCN381U_LPT.ASL" +"SMSC1000_SIO.asl" +"SMSC1000_COM.asl" +"SMSC1000_LPT.asl" +"DSDT.ASL" +"token.asl" +"H8S2113_SIO.ASL" +"Nfc.asl" +"wcam.asl" +[parts] +"AcpiAslWrap" +<endComponent> diff --git a/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.mak b/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.mak new file mode 100644 index 0000000..72b2e84 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.mak @@ -0,0 +1,39 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: AcpiAsl.mak +# +# Description: MAke file to build Aptio ACPI ASL components +# +# +#<AMI_FHDR_END> +#************************************************************************* + + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.sdl b/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.sdl new file mode 100644 index 0000000..a75ed2e --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.sdl @@ -0,0 +1,417 @@ +IODEVICE + Name = "System PS2 Keyboard Controller" + ASLfile = "core\em\acpi\PS2KB.asl" + ASLdeviceName = "PS2K" + GPEbit = 01dh + SleepNum = 03h + Token = "PCH_SKU" "=" "1" + Token = "CRB_SIO_SUPPORT" "=" "0" + Token = "VirtualSerial_SUPPORT" "=" "1" +End + +IODEVICE + Name = "System PS2 Mouse Controller" + ASLfile = "core\em\acpi\PS2MS.asl" + ASLdeviceName = "PS2M" + GPEbit = 01dh + SleepNum = 03h + Token = "PCH_SKU" "=" "1" + Token = "CRB_SIO_SUPPORT" "=" "0" + Token = "VirtualSerial_SUPPORT" "=" "1" +End + +IODEVICE + Name = "System PS2 Keyboard Controller" + ASLfile = "core\em\acpi\PS2KB.asl" + ASLdeviceName = "PS2K" + GPEbit = 01dh + SleepNum = 03h + Token = "PCH_SKU" "=" "1" + Token = "EC_H8SMC" "=" "1" + Token = "CRB_EC_SUPPORT" "=" "1" +End + +IODEVICE + Name = "System PS2 Mouse Controller" + ASLfile = "core\em\acpi\PS2MS.asl" + ASLdeviceName = "PS2M" + GPEbit = 01dh + SleepNum = 03h + Token = "PCH_SKU" "=" "1" + Token = "EC_H8SMC" "=" "1" + Token = "CRB_EC_SUPPORT" "=" "1" +End + +TOKEN + Name = "PlatformAcpiTables_SUPPORT" + Value = "1" + Help = "Main switch to enable SaAcpiTables support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +TOKEN + Name = "TRTP" + Value = "0x01" + Help = "TRAP_TYPE_PPM" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "WDTE" + Value = "0x01" + Help = "WDT enabled" + TokenType = Integer + TargetASL = Yes + Token = "CougarPoint_SUPPORT" "=" "1" +End + +TOKEN + Name = "WDTE" + Value = "0x00" + Help = "WDT enabled" + TokenType = Integer + TargetASL = Yes + Token = "Ibexpeak_SUPPORT" "=" "1" +End + +TOKEN + Name = "TRTD" + Value = "0x02" + Help = "TRAP_TYPE_DTS" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "TRTI" + Value = "0x03" + Help = "TRAP_TYPE_IGD" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "PFTI" + Value = "0x04" + Help = "PFAT IO Trap flag" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "GCDD" + Value = "0x01" + Help = "SW_SMI_GET_CURRENT_DISPLAY_DEVICE" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "DSTA" + Value = "0x0A" + Help = "SW_SMI_DISPLAY_SWITCH_TOGGLE_ACPI" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "DSLO" + Value = "0x0C" + Help = "SW_SMI_DISPLAY_SWITCH_LID_OPEN_ACPI" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "DSLC" + Value = "0x0E" + Help = "SW_SMI_DISPLAY_SWITCH_LID_CLOSE_ACPI" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "PITS" + Value = "0x10" + Help = "SW_SMI_POPUP_ICON_TOGGLE" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "SBCS" + Value = "0x12" + Help = "SW_SMI_SET_BACKLIGHT_CONTROL" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "SALS" + Value = "0x13" + Help = "SW_SMI_SET_ALI_LEVEL" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "LSSS" + Value = "0x2A" + Help = "SW_SMI_LID_STATE_SWITCH" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "SOOT" + Value = "0x35" + Help = "SW_SMI_SAVE_OSB_OS_TYPE" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "PDBR" + Value = "0x4D" + Help = "SW_SMI_PCIE_DOCK_BRIDGE_RESOURCE_PATCH" + TokenType = Integer + TargetASL = Yes +End + +TOKEN + Name = "BW1P" + Value = "0x21" + Help = "Haswell - WhiteTip Mountain1 PPV Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BW2C" + Value = "0x22" + Help = "Haswell - WhiteTip Mountain2 Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BW2P" + Value = "0x23" + Help = "Haswell - WhiteTip Mountain2 PPV Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BSPC" + Value = "0x24" + Help = "Haswell - Sawtooth Peak Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BSPP" + Value = "0x25" + Help = "Haswell - Sawtooth Peak PPV Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BICO" + Value = "0x27" + Help = "Haswell - WhiteTip Mountain2 CDK Open Chasis Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BICC" + Value = "0x28" + Help = "Haswell - WhiteTip Mountain2 CDK Close Chasis Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BHB" + Value = "0x30" + Help = "Haswell - Harris Beach FFRD Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BFS2" + Value = "0x31" + Help = "Haswell - FFRD SKU2 Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BFS3" + Value = "0x32" + Help = "Haswell - FFRD SKU3 Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BFS4" + Value = "0x33" + Help = "Haswell - FFRD SKU4 Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BRH" + Value = "0x35" + Help = "Haswell - Reed Harbor TDV Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +PATH + Name = "INTEL_ACPI_ASL_DIR" +End + +MODULE + Help = "Includes AcpiAsl.mak to Project" + File = "AcpiAsl.mak" +End + +ELINK + Name = "INTEL_EC_ASL" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "INTEL_GENERIC_ASL" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "$(INTEL_GENERIC_ASL)" + Parent = "GENERIC_ASL" + Priority = 10 + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\Cpu.asl" + Parent = "GENERIC_ASL" + Disable = Yes + InvokeOrder = AfterParent + Lock = Yes +End + +ELINK + Name = "Board\Em\Acpi\oemdsdt.asl" + Parent = "GENERIC_ASL" + Disable = Yes + InvokeOrder = AfterParent + Lock = Yes +End + +ELINK + Name = "Board\Em\Acpi\OEMRMISC.asl" + Parent = "GENERIC_ASL" + Disable = Yes + InvokeOrder = AfterParent + Lock = Yes +End + +ELINK + Name = "$(SB_CHIPSET_DIR)\IRQLink.asl" + Parent = "GENERIC_ASL" + Token = "PlatformAcpiTables_SUPPORT" "=" "0" + InvokeOrder = BeforeParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\GloblNvs.asl" + Parent = "GENERIC_ASL_BEFORE_PCITREE" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\CPU.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\Platform.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\PCI_DRC.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\Video.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\Gpe.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\PCIEDOCK.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent + Token = "FACP_FLAG_DCK_CAP" "=" "1" + Token = "CRB_EC_SUPPORT" "=" "1" +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\Thermal.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\wcam.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/AcpiTables/Dsdt/Bat0Virt.asl b/ReferenceCode/AcpiTables/Dsdt/Bat0Virt.asl new file mode 100644 index 0000000..a87232c --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Bat0Virt.asl @@ -0,0 +1,322 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Scope(\) +{ + // these fields come from the Global NVS area + Field(GNVS,AnyAcc,Lock,Preserve) + { + Offset(31), + B0SC, 8, // (31) Battery 0 Stored Capacity + Offset(34), + B0SS, 8, // (34) Battery 0 Stored Status + } +} + + +Method(_Q53) +{ + P8XH(0,0x53) // show query number on Port 80 + VBSE() // Virtual Battery Switch Event, remove if not needed. +} + + +// Virtual Battery Switch Event: +// This method handles the Virtual Battery switch on the CRB. +// +// Arguments: +// None +// +// Return Value: +// None +Method(VBSE,0,Serialized) // called from EC.asl +{ + // Check for Virtual Battery Mode. If the CRB is + // running on real batteries, skip this whole section. + + If(LEqual(BNUM,0)) + { + // Check that the current and NVS Power States + // are different. The 2 may be out of sync due to + // Virtual Battery hot-key support. + + If(LNotEqual(ECRD(RefOf(VPWR)),PWRS)) + { + // Update NVS Power State. + + Store(ECRD(RefOf(VPWR)),PWRS) + + + // Perform needed ACPI Notifications. + + PNOT() + } + } +} + + +// +// called from EC.asl _Q52 method +// +// Virtual Battery Hot Keys: +// This method passes the hot key scan code to the BTTM method. +// +// Arguments: +// None +// +// Return Value: +// None +Method(VBHK,0,Serialized) +{ + // 1/! Scan Code = 0x02 + + Store(ECRD(RefOf(SCAN)), Local0) + + If(LEqual(Local0,0x02)) // Battery = 10%. + { + BTTM(10) + } + + // 2/@ Scan Code = 0x03 + + If(LEqual(Local0,0x03)) // Battery = 20%. + { + BTTM(20) + } + + // 3/# Scan Code = 0x04 + + If(LEqual(Local0,0x04)) // Battery = 30%. + { + BTTM(30) + } + + // 4/$ Scan Code = 0x05 + + If(LEqual(Local0,0x05)) // Battery = 40%. + { + BTTM(40) + } + + // 5/% Scan Code = 0x06 + + If(LEqual(Local0,0x06)) // Battery = 50%. + { + BTTM(50) + } + + // 6/^ Scan Code = 0x07 + + If(LEqual(Local0,0x07)) // Battery = 60%. + { + BTTM(60) + } + + // 7/& Scan Code = 0x08 + + If(LEqual(Local0,0x08)) // Battery = 70%. + { + BTTM(70) + } + + // 8/* Scan Code = 0x09 + + If(LEqual(Local0,0x09)) // Battery = 80%. + { + BTTM(80) + } + + // 9/( Scan Code = 0x0A + + If(LEqual(Local0,0x0A)) // Battery = 90%. + { + BTTM(90) + } + + // 0/) Scan Code = 0x0B + + If(LEqual(Local0,0x0B)) // Battery = 100%. + { + BTTM(100) + } + + // _/- Scan Code = 0x0C + + If(LEqual(Local0,0x0C)) // Battery = Battery - 2%. + { + If(LGreaterEqual(B0SC,2)) + { + BTTM(Subtract(B0SC,2)) + } + } + + // +/= Scan Code = 0x0D + + If(LEqual(Local0,0x0D)) // Battery = Battery + 2%. + { + If(LLessEqual(B0SC,98)) + { + BTTM(Add(B0SC,2)) + } + } + + // F5 Scan Code = 0x3F + + If(LEqual(Local0,0x3F)) // Virtual Power State Change. + { + // Check for Virtual Battery Mode. If the CRB is + // running on real batteries, skip this whole section. + + If(LEqual(BNUM,0)) + { + // Toggle the Virtual Power State. + Xor(PWRS,1,PWRS) + + + // Perform needed ACPI Notifications. + PNOT() + } + } +} + + +// Battery Test Method: +// This method updates the Virtual Battery percentages and +// notifies the OS of these changes. +// +// Arguments: +// Arg0: The desired Virtual Battery Percentage. +// +// Return Value: +// None + +Method(BTTM,1,Serialized) +{ + If(PWRS) + { + If(LGreaterEqual(Arg0,B0SC)) + { + Store(Arg0,B0SC) + Notify(BAT0,0x80) + } + } + Else + { + If(LLessEqual(Arg0,B0SC)) + { + Store(Arg0,B0SC) + Notify(BAT0,0x80) + } + } +} + + // Define the Virtual Battery 0 Control Method. + + Device(BAT0) + { + Name(_HID,EISAID("PNP0C0A")) + + Name(_UID,0) + + Method(_STA,0) + { + If(LOr(LOr(LEqual(BID,BHB), LEqual(BID,BFS2)), LOr(LEqual(BID,BFS3), LEqual(BID,BFS4)))) //BoardIdHarrisBeachFfrd, BoardIdFfrdSku2, BoardIdFfrdSku3, BoardIdFfrdSku4 + { + Return(0x0000) // Yes. Hide Virtual. + } + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + Return(0x0000) // Yes. Hide it. + } + + If(And(BNUM,3)) // Battery 1 or 2 present? + { + If(LLessEqual(OSYS,2002)) + { + Return(0x000A) // Yes. Hide Virtual for Win XP + } + + Return(0x000B) // Yes. Hide Virtual. + } + + Return(0x001F) // No. Show Virtual. + } + + Method(_BIF,0) + { + Return(Package() { + 0x00000000, // Power Unit = mWh. + 0x00002710, // 10000 mWh Design Capacity. + 0x00002710, // 10000 mWh Last Full Charge. + 0x00000001, // Secondary Battery Technology. + 0xFFFFFFFF, // Unknown Design Voltage. + 0x000003E8, // 10% Warning Level. + 0x00000190, // 4% Low Level. + 0x00000064, // 1% Granularity Level 1. + 0x00000064, // 1% Granularity Level 2. + "CRB Battery 0", + "Battery 0", + "Fake", + "-Virtual Battery 0-"}) + } + + Method(_BST,0) + { + Name(PKG0,Package() { + 0xFFFFFFFF, // Battery State. + 0xFFFFFFFF, // Battery Present Rate. + 0xFFFFFFFF, // Battery Remaining Capacity. + 0xFFFFFFFF // Battery Present Voltage. + }) + + // Virtual AC/Battery Check. + + If(PWRS) + { + // Return Charging. + + Store(2,Index(PKG0,0)) + } + Else + { + // Return Discharging. + + Store(1,Index(PKG0,0)) + } + Store(0x7FFFFFFF,Index(PKG0,1)) + Store(Multiply(B0SC,100),Index(PKG0,2)) + Return(PKG0) + } + + // Return that everything runs off Battery. + + Method(_PCL,0) + { + Return(\_SB) + } + } + diff --git a/ReferenceCode/AcpiTables/Dsdt/Bat1Real.asl b/ReferenceCode/AcpiTables/Dsdt/Bat1Real.asl new file mode 100644 index 0000000..500d1d4 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Bat1Real.asl @@ -0,0 +1,198 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Scope(\) +{ + // these fields come from the Global NVS area + Field(GNVS,AnyAcc,Lock,Preserve) + { + Offset(30), // Battery Support Registers: + BNUM, 8, // (30) Battery Number Present + Offset(32), + B1SC, 8, // (32) Battery 1 Stored Capacity + Offset(35), + B1SS, 8, // (35) Battery 1 Stored Status + } +} + + // Define the Real Battery 1 Control Method. + + Device(BAT1) + { + Name(_HID,EISAID("PNP0C0A")) + + Name(_UID,1) + + Method(_STA,0) + { + If(And(BNUM,1)) // Battery 1 present? + { + Return(0x001F) // Yes. Show it. + } + + If(LLessEqual(OSYS,2002)) + { + Return(0x000A) // hide it for Win XP support + } + + Return(0x000B) // No. Hide it. + } + + Method(_BIF,0) + { + Name(BPKG, Package() { + 0x00000000, // Power Unit = mWh. + 0xFFFFFFFF, // Unknown Design Capacity. + 0xFFFFFFFF, // Unknown Last Full Charge. + 0x00000001, // Secondary Battery Technology. + 0xFFFFFFFF, // Unknown Design Voltage. + 0x00000000, // 10% Warning Level. + 0x00000000, // 4% Low Level. + 0x00000064, // 1% Granularity Level 1. + 0x00000000, // 1% Granularity Level 2. + "SR Real Battery", + "123456789", + "Real", + "Intel SR 1" + }) + + If (LAnd(LAnd(ECRD(RefOf(B1DV)),ECRD(RefOf(B1FC))),ECRD(RefOf(B1DC)))) + { + // Convert mAh and mV to mWh + Store(Divide(Multiply(ECRD(RefOf(B1DC)), ECRD(RefOf(B1DV))),1000), Index(BPKG,1)) + Store(Divide(Multiply(ECRD(RefOf(B1FC)), ECRD(RefOf(B1DV))),1000), Index(BPKG,2)) + Store(B1DV, Index(BPKG,4)) + Store(Divide(Multiply(ECRD(RefOf(B1FC)), ECRD(RefOf(B1DV))),10000), Index(BPKG,5)) + Store(Divide(Multiply(ECRD(RefOf(B1FC)), ECRD(RefOf(B1DV))),25000), Index(BPKG,6)) + Store(Divide(Multiply(ECRD(RefOf(B1DC)), ECRD(RefOf(B1DV))),100000), Index(BPKG,7)) + } + + Return (BPKG) + } + + Method(_BST,0, Serialized) + { + Name(PKG1,Package() { + 0xFFFFFFFF, // Battery State. + 0xFFFFFFFF, // Battery Present Rate. (in mWh) + 0xFFFFFFFF, // Battery Remaining Capacity. (in mWh) + 0xFFFFFFFF // Battery Present Voltage. (in mV) + }) + + // Optimization for EC Low Power Mode due to many EC accesses in this method + // Wake EC for whole _BST method + Store(Zero, Local1) + if (LGreaterEqual(OSYS, 2013)) { + if (LEqual(ECLP, 0x1)) { + Store (Acquire(\EHLD, 100), Local2) + if (LEqual(Local2, Zero)) { // check for Mutex acquired, if Mutex not acquired _BST could take longer than expected to execute + if (LEqual(\ECUP,Zero)) { + Store(One, Local1) + \_SB.WTGP(88,1) + Sleep(8) + Store(One, \ECUP) + \_SB.PCI0.LPCB.H_EC.ECMD (0x2D) // Notify EC of CS exit + } else { + Release(\EHLD) + } + } + } + } + + // Fix up the Battery Status. + Store(And(ECRD(RefOf(B1ST)), 0x07),Index(PKG1,0)) + If(And(ECRD(RefOf(B1ST)), 0x01)) + { + // Calculate discharge rate + // Return Rate in mW since we report _BIF data in mW + Store(Multiply(ECRD(RefOf(B1DI)), ECRD(RefOf(B1FV))), Local0) + Store(Divide(Local0, 1000), Local0) + Store(Local0, Index(PKG1,1)) + } + Else + { + // Calculate charge rate + // Return Rate in mW since we report _BIF data in mW + Store(Multiply(ECRD(RefOf(B1CI)), ECRD(RefOf(B1FV))), Local0) + Store(Divide(Local0, 1000), Local0) + Store(Local0, Index(PKG1,1)) + } + + // Calculate Remaining Capacity in mWh = + // (Remaininng Capacity (mAh) * Design Voltage (mV))/1000 + // Use Remaininng Capacity in mAh multiply with a fixed Design Voltage + // for Remaininng Capacity in mWh + Store(Divide(Multiply(ECRD(RefOf(B1RC)), ECRD(RefOf(B1DV))),1000),Index(PKG1,2)) + + // Report Battery Present Voltage (mV) + Store(ECRD(RefOf(B1FV)), Index(PKG1,3)) + + // Optimization for EC Low Power Mode due to many EC accesses in this method + // Put EC back into Low Power Mode + if (LGreaterEqual(OSYS, 2013)) { + if (LEqual(ECLP, 0x1)) { + if (LEqual(Local1, One)) { + \_SB.WTGP(88,0) + \_SB.PCI0.LPCB.H_EC.ECMD (0x2C) // Notify EC of CS entry + Store(Zero, \ECUP) + Release(\EHLD) + } + } + } + + Return(PKG1) + } + + Method(_BTP,1) + { + // arg0 = Trip Point, sent to EC as Threshold. + // transfer input value from mWh to % + If(LAnd(LNotEqual(ECRD(RefOf(B1FC)),0),LNotEqual(ECRD(RefOf(B1FV)),0))) + { + Store(Divide(Multiply(Arg0, 100), Divide(Multiply(ECRD(RefOf(B1FC)), ECRD(RefOf(B1FV))),1000)),Local0) + + // adjust offset between OS & EC + Add(Local0,1,Local0) + + // store TP value in EC name space offset 219 + Store(Local0, ECRD(RefOf(BTP1))) + + // Send EC Battery Threshold Update Command - 0x34 + ECMD(0x34) + } + + Return() + + } + // Return that everything runs off Battery. + + Method(_PCL,0) + { + Return(\_SB) + } + } + diff --git a/ReferenceCode/AcpiTables/Dsdt/Bat2Real.asl b/ReferenceCode/AcpiTables/Dsdt/Bat2Real.asl new file mode 100644 index 0000000..13ad9d4 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Bat2Real.asl @@ -0,0 +1,182 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Scope(\) +{ + // these fields come from the Global NVS area + Field(GNVS,AnyAcc,Lock,Preserve) + { + Offset(33), + B2SC, 8, // (33) Battery 2 Stored Capacity + Offset(36), + B2SS, 8 // (36) Battery 2 Stored Status + } +} + + // Define the Real Battery 2 Control Method. + + Device(BAT2) + { + Name(_HID,EISAID("PNP0C0A")) + Name(_UID,2) + + Method(_STA,0) + { + If(LOr(LOr(LEqual(BID,BHB), LEqual(BID,BFS2)), LOr(LEqual(BID,BFS3), LEqual(BID,BFS4)))) //BoardIdHarrisBeachFfrd, BoardIdFfrdSku2, BoardIdFfrdSku3, BoardIdFfrdSku4 + { + Return(0x0000) // Yes. Hide it. + } + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + Return(0x0000) // Yes. Hide it. + } + + If(And(BNUM,2)) // Battery 2 present? + { + Return(0x001F) // Yes. Show it. + } + + If(LLessEqual(OSYS,2002)) + { + Return(0x000A) // hide it for Win XP support + } + + Return(0x000B) // No. Hide it. + } + + Method(_BIF,0) + { + Name(BPK2, Package() { + 0x00000000, // Power Unit = mWh. + 0xFFFFFFFF, // Unknown Design Capacity. + 0xFFFFFFFF, // Unknown Last Full Charge. + 0x00000001, // Secondary Battery Technology. + 0xFFFFFFFF, // Unknown Design Voltage. + 0x00000000, // 10% Warning Level. + 0x00000000, // 4% Low Level. + 0x00000064, // 1% Granularity Level 1. + 0x00000000, // 1% Granularity Level 2. + "SR Real Battery", + "123456789", + "Real", + "Intel SR 2" + }) + + If (LAnd(LAnd(ECRD(RefOf(B1DV)),ECRD(RefOf(B2FC))),ECRD(RefOf(B1DC)))) + { + // Convert mAh and mV to mWh + Store(Divide(Multiply(ECRD(RefOf(B1DC)), ECRD(RefOf(B1DV))),1000), Index(BPK2,1)) + Store(Divide(Multiply(ECRD(RefOf(B2FC)), ECRD(RefOf(B1DV))),1000), Index(BPK2,2)) + Store(B1DV, Index(BPK2,4)) + Store(Divide(Multiply(ECRD(RefOf(B2FC)), ECRD(RefOf(B1DV))),10000), Index(BPK2,5)) + Store(Divide(Multiply(ECRD(RefOf(B2FC)), ECRD(RefOf(B1DV))),25000), Index(BPK2,6)) + Store(Divide(Multiply(ECRD(RefOf(B1DC)), ECRD(RefOf(B1DV))),100000), Index(BPK2,7)) + } + + Return (BPK2) + } + + Method(_BST,0, Serialized) + { + Name(PKG2,Package() { + 0xFFFFFFFF, // Battery State. + 0xFFFFFFFF, // Battery Present Rate. (in mWh) + 0xFFFFFFFF, // Battery Remaining Capacity. (in mWh) + 0xFFFFFFFF // Battery Present Voltage. (in mV) + }) + + // Optimization for EC Low Power Mode due to many EC accesses in this method + // Wake EC for whole _BST method + Store(Zero, Local1) + if (LGreaterEqual(OSYS, 2013)) { + if (LEqual(ECLP, 0x1)) { + Store (Acquire(\EHLD, 100), Local2) + if (LEqual(Local2, Zero)) { // check for Mutex acquired, if Mutex not acquired _BST could take longer than expected to execute + if (LEqual(\ECUP,Zero)) { + Store(One, Local1) + \_SB.WTGP(88,1) + Sleep(8) + Store(One, \ECUP) + \_SB.PCI0.LPCB.H_EC.ECMD (0x2D) // Notify EC of CS exit + } else { + Release(\EHLD) + } + } + } + } + + // Fix up the Battery Status. + Store(And(ECRD(RefOf(B2ST)), 0x07),Index(PKG2,0)) + If(And(ECRD(RefOf(B2ST)), 0x01)) + { + // Calculate discharge rate + // Return Rate in mW since we report _BIF data in mW + Store(Multiply(ECRD(RefOf(B2DI)), ECRD(RefOf(B2FV))), Local0) + Store(Divide(Local0, 1000), Local0) + Store(Local0, Index(PKG2,1)) + } + Else + { + // Calculate charge rate + // Return Rate in mW since we report _BIF data in mW + Store(Multiply(ECRD(RefOf(B2CI)), ECRD(RefOf(B2FV))), Local0) + Store(Divide(Local0, 1000), Local0) + Store(Local0, Index(PKG2,1)) + } + + // Calculate Remaining Capacity in mWh = + // (Remaininng Charge (mAh) * Present Voltage (mV))/1000 + Store(Divide(Multiply(ECRD(RefOf(B2RC)), ECRD(RefOf(B2FV))),1000),Index(PKG2,2)) + + // Report Battery Present Voltage (mV) + Store(ECRD(RefOf(B2FV)), Index(PKG2,3)) + + // Optimization for EC Low Power Mode due to many EC accesses in this method + // Put EC back into Low Power Mode + if (LGreaterEqual(OSYS, 2013)) { + if (LEqual(ECLP, 0x1)) { + if (LEqual(Local1, One)) { + \_SB.WTGP(88,0) + \_SB.PCI0.LPCB.H_EC.ECMD (0x2C) // Notify EC of CS entry + Store(Zero, \ECUP) + Release(\EHLD) + } + } + } + + Return(PKG2) + } + + // Return that everything runs off Battery. + + Method(_PCL,0) + { + Return(\_SB) + } + } + + diff --git a/ReferenceCode/AcpiTables/Dsdt/CPU.asl b/ReferenceCode/AcpiTables/Dsdt/CPU.asl new file mode 100644 index 0000000..7e6f6aa --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/CPU.asl @@ -0,0 +1,171 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + + // NOTE: The _PDC Implementation is out of the scope of this + // reference code. Please see the latest Hyper-Threading Technology + // Reference Code for complete implementation details. + + Scope(\_PR) + { + Processor(CPU0, // Unique name for Processor 0. + 1, // Unique ID for Processor 0. + 0x1810, // CPU0 ACPI P_BLK address = ACPIBASE + 10h. + 6) // CPU0 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU0 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU0 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU0 DEP NULL") + Return(Package() {}) + } + } + } + + Processor(CPU1, // Unique name for Processor 1. + 2, // Unique ID for Processor 1. + 0x1810, + 6) // CPU1 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU1 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU1 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU1 DEP NULL") + Return(Package() {}) + } + } + } + + Processor(CPU2, // Unique name for Processor 2. + 3, // Unique ID for Processor 2. + 0x1810, + 6) // CPU2 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU2 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU2 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU2 DEP NULL") + Return(Package() {}) + } + } + } + + Processor(CPU3, // Unique name for Processor 3. + 4, // Unique ID for Processor 3. + 0x1810, + 6) // CPU3 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU3 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU3 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU3 DEP NULL") + Return(Package() {}) + } + } + } + Processor(CPU4, // Unique name for Processor 4. + 5, // Unique ID for Processor 4. + 0x1810, + 6) // CPU4 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU4 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU4 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU4 DEP NULL") + Return(Package() {}) + } + } + } + + Processor(CPU5, // Unique name for Processor 5. + 6, // Unique ID for Processor 5. + 0x1810, + 6) // CPU5 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU5 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU5 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU5 DEP NULL") + Return(Package() {}) + } + } + } + Processor(CPU6, // Unique name for Processor 6. + 7, // Unique ID for Processor 6. + 0x1810, + 6) // CPU6 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU6 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU6 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU6 DEP NULL") + Return(Package() {}) + } + } + } + + Processor(CPU7, // Unique name for Processor 7. + 8, // Unique ID for Processor 7. + 0x1810, + 6) // CPU7 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU7 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU7 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU7 DEP NULL") + Return(Package() {}) + } + } + } + + } // End _PR + + diff --git a/ReferenceCode/AcpiTables/Dsdt/DSDT.ASL b/ReferenceCode/AcpiTables/Dsdt/DSDT.ASL new file mode 100644 index 0000000..748996f --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/DSDT.ASL @@ -0,0 +1,96 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +DefinitionBlock ( + "DSDT.aml", + "DSDT", + 0x02, // DSDT revision. + // A Revision field value greater than or equal to 2 signifies that integers + // declared within the Definition Block are to be evaluated as 64-bit values + "INTEL", // OEM ID (6 byte string) + "HSW-LPT", // OEM table ID (8 byte string) + 0x0 // OEM version of DSDT table (4 byte Integer) + ) + +// BEGIN OF ASL SCOPE +{ + +External(LHIH) +External(LLOW) +External(IGDS) +External(LIDS) +External(BRTL) +External(ALSE) +External(GSMI) +External(\_SB.PCI0.GFX0.ALSI) +External(\_SB.PCI0.GFX0.CDCK) +External(\_SB.PCI0.GFX0.CBLV) +External(\_SB.PCI0.GFX0.GSSE) +External(\_SB.PCI0.PEG0, DeviceObj) +External(\_SB.PCI0.PEG0.PEGP, DeviceObj) +External(\_SB.PCI0.PEG1, DeviceObj) +External(\_SB.PCI0.PEG2, DeviceObj) +External(\_SB.PCI0.GFX0.DD1F, DeviceObj) +External(\_SB.PCI0.GFX0.GDCK, MethodObj) +External(\_SB.PCI0.GFX0.GHDS, MethodObj) +External(\_SB.PCI0.GFX0.AINT, MethodObj) +External(\_SB.PCI0.GFX0.GLID, MethodObj) +External(\_SB.PCI0.GFX0.GSCI, MethodObj) +External(\_PR.CPU0, DeviceObj) +External(\_PR.CPU0._PSS, MethodObj) +External(\_PR.CPU0._PPC, IntObj) + + +// Miscellaneous services enabled in Project + include ("amlupd.asl") + include ("token.asl") + include ("GloblNvs.asl") + include ("PCItree.asl") + include ("Platform.asl") + include ("CPU.asl") + include ("Thermal.asl") + include ("PCI_DRC.asl") + include ("Video.asl") + include ("Gpe.asl") + include ("PCIEDOCK.asl") + include ("Pch.asl") // Not in this package. Refer to the PCH Reference Code accordingly +//---------------------------------------------------------------------- + Name(\_S0, Package(4){0x0,0x0,0,0}) // mandatory System state + if(SS1) { Name(\_S1, Package(4){0x1,0x0,0,0})} + if(SS3) { Name(\_S3, Package(4){0x5,0x0,0,0})} + if(SS4) { Name(\_S4, Package(4){0x6,0x0,0,0})} + Name(\_S5, Package(4){0x7,0x0,0,0}) // mandatory System state + + Method(PTS, 1) { // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SLEEP STATE + If(Arg0) // entering any sleep state + { + } + } + Method(WAK, 1) { // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP + } +}// End of ASL File + diff --git a/ReferenceCode/AcpiTables/Dsdt/EC.ASL b/ReferenceCode/AcpiTables/Dsdt/EC.ASL new file mode 100644 index 0000000..b223a9a --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/EC.ASL @@ -0,0 +1,1893 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +External(\_SB.IETM, DeviceObj) + +External(TBAB) +External(RTIP) +External(HGAS, MethodObj) +External(HPFS, MethodObj) +External(HBRT, MethodObj) +External(CHPS, MethodObj) +External(UP1D) +External(UPRW) +External(SVRF, MethodObj) +External(\_SB.PCI0.CTCU, MethodObj) +External(\_SB.PCI0.CTCN, MethodObj) +External(\_SB.PCI0.CTCD, MethodObj) +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) +External(\_SB.PCI0.GFX0.CLID) +External(\_SB.PCI0.GFX0.IUEH, MethodObj) +External(\_SB.PCI0.GFX0.IUER, DeviceObj) +#endif +#define POWER_BUTTON 0 +#define WINDOWS_BUTTON 1 +#define VOLUME_UP_BUTTON 2 +#define VOLUME_DOWN_BUTTON 3 +#define ROTATION_LOCK_BUTTON 4 +#define CONVERTIBLE_BUTTON 6 +#define DOCK_INDICATOR 7 + +Device(H_EC) // Hitachi Embedded Controller +{ + Name(_HID, EISAID("PNP0C09")) + + Name(_UID,1) + + Name(ECAV, Zero) // OS Bug Checks if EC OpRegion accessed before Embedded Controller Driver loaded + + Method(_CRS,0) + { + Name(BFFR, ResourceTemplate() + { + IO(Decode16,0x62,0x62,0,1) // DIN/DOUT + IO(Decode16,0x66,0x66,0,1) // CMD/STS + }) + + Return(BFFR) + } + + Method(_STA) + { + If (LEqual(ECON,1)){ + Return(0x0F) + } + Return(0x00) + } + + OperationRegion(ECF2,EmbeddedControl,0,0xFF) + Field(ECF2,ByteAcc,Lock,Preserve) + { + Offset(1), + PLMX, 8, // 1 Max Platform temprature + LTMP, 8, // 2 Sensor Temperature + RPWR, 1, // 3.0 Real AC Power (AC Present = 1) + , 2, // 3.2:1 Reserved + CFAN, 1, // 3.3 CPU Fan (Fan On = 1) + , 2, // 3.5:4 Reserved + LSTE, 1, // 3.6 Lid State (Lid Open = 1) + , 1, // 3.7 Reserved + SPTR, 8, // 4 SMBus Protocol Register + SSTS, 8, // 5 SMBus Status Register + SADR, 8, // 6 SMBus Address Register + SCMD, 8, // 7 SMBus Command Register + SBFR, 256, // 8 SMBus Block Buffer + SCNT, 8, // 40 SMBus Block Count + Offset(47), + CTMP, 8, // 47 EC Critical Temperature + DOCK, 1, // 48.0 Docking state (docked = 1) + EJET, 1, // 48.1 Eject switch state (Eject (Q-Switch off) = 1) + , 1, // 48.2 Reserved + PBNS, 1, // 48.3 Power Button State (0 = Pressed) + VPWR, 1, // 48.4 Virtual AC Power (AC Present = 1) + , 3, // 48.7:5 Reserved + SCAN, 8, // 49 Hot-Key Scan Code + B1ST, 8, // 50 Battery 1 Status + B1CR, 8, // 51 Battery 1 Current Rate + B1CC, 8, // 52 Battery 1 Current Capacity + B1VT, 8, // 53 Battery 1 Voltage + B2ST, 8, // 54 Battery 2 Status + B2CR, 8, // 55 Battery 2 Current Rate + B2CC, 8, // 56 Battery 2 Current Capacity + B2VT, 8, // 57 Battery 2 Voltage + CMDR, 8, // 58 KSC command register + LUXL, 8, // 59 LUX - Low Byte + LUXH, 8, // 60 LUX - High Byte + ACH0, 8, // 61 Channel 0 RAW Value + ACH1, 8, // 62 Channel 1 RAW Value + Offset(65), + PPSL, 8, // 65 PWM Port Select low byte + PPSH, 8, // 66 PWM Port Select high byte + PINV, 8, // 67 PWM initial value + PENV, 8, // 68 PWM ending value + PSTP, 8, // 69 PWM ms delay between steps + Offset(71), + CPUP, 16, // 71 CPU Power mW + BPWR, 16, // 73 Brick Power cW(100ths) + PPWR, 16, // 75 Platform Power cW(100ths) + CVRT, 8, // 77 CPU VR (IMVP) Temp + FANT, 8, // 78 Heat exchanger fan temp + SKNT, 8, // 79 Skin temp + AMBT, 8, // 80 Ambient temp + Offset(82), // 82-85 DPTF fields + TSI, 4, // Hysteresis selection is global and meant for all four sensors. + // # 0 = CPU VR (IMVP) temperature sensor + // # 1 = Heat Exchanger temperature sensor + // # 2 = Skin temperature sensor + // # 3 = Ambient temperature sensor + // # 4 = DIMM temperature sensor + // # Above 4 invalid + HYST, 4, // 82.4-7 Hysteresis in deg C + TSHT, 8, // 83 Thermal Sensor (N) high trip point + TSLT, 8, // 84 Thermal Sensor (N) low trip point + TSSR, 8, // 85 TSSR- thermal sensor status register: + // TSSR bits defined: + // BIT0: CPU VR Temp Sensor Trip Flag + // BIT1: Fan Temp Sensor Trip Flag + // BIT2: Skin Temp Sensor Trip Flag + // BIT3: Ambient Temp Sensor Trip Flag + // BIT4: DIMM Trip Point Flag + // BIT[7:5] Reserved + Offset(86), + B1CM, 8, // 86 Battery 1 Command (Place holder for now) + B1DC, 16, // 87 Battery 1 Design Capacity (mWh) + B1RC, 16, // 89 Battery 1 Remaining Capacity (mWh) + B1FC, 16, // 91 Battery 1 Full Charge Capacity (mWh) + B1FV, 16, // 93 Battery 1 Full Resolution Voltage (mV) + B1DI, 16, // 95 Battery 1 Full Resolution Discharge Current (mA) + B1CI, 16, // 97 Battery 1 Full Resolution Charge Current (mA) + B2RC, 16, // 99 Battery 2 Remaining Capacity (mWh) + B2FC, 16, // 101 Battery 2 Full Charge Capacity (mWh) + B2FV, 16, // 103 Battery 2 Full Resolution Voltage (mV) + B2DI, 16, // 105 Battery 2 Full Resolution Discharge Current (mA) + B2CI, 16, // 107 Battery 2 Full Resolution Charge Current (mA) + CPAP, 16, // 109 CPU average power in mW + BKAP, 16, // 111 Brick average power in cW(0.01) + PLAP, 16, // 113 Platform average power in cW(0.01) + CFSP, 16, // 115 CPU Fan speed in rpm + BRTV, 8, // 117 Brightness value for San Rafael second panel + , 8, // 118 reserved + SLPC, 8, // 119 Select Performance Counters + DLED, 1, // 120.0 EC Connected Standby Debug LED (CAPS LOCK) + PB10, 1, // 120.1 10 Second Power Button Control + Offset(124), + PTIM, 8, // 124 CPU,GFX pwr sample timer + DHPD, 8, // 125 Digital display hot-plug detect + DIM0, 8, // 126 DIMM0 temperature + DIM1, 8, // 127 DIMM1 temperature + PMAX, 8, // 128 CPU,MCH & PCH Max temp + PPDT, 8, // 129 PCH DTS reading from PCH + PECL, 8, // 130 CPU PECI reading fractional value (1/64 Celcius) + PECH, 8, // 131 CPU PECI reading integer value (unit Celicus) + PMDT, 8, // 132 MCH DTS reading from PCH + TSD0, 8, // 133 TS-on-DIMM0 temperature + TSD1, 8, // 134 TS-on-DIMM1 temperature + TSD2, 8, // 135 TS-on-DIMM2 temperature + TSD3, 8, // 136 TS-on-DIMM3 temperature + PAKN, 8, // 137 Packet sequence number + CPUE, 32, // 138 CPU energy + Offset(155), + PRCL, 8, // 155 Repeat cycle (LSB) + PRC0, 8, // 156 Repeat cycle + PRC1, 8, // 157 Repeat cycle + PRCM, 8, // 158 Repeat cycle (MSB) + PRIN, 8, // 159 Repear Intervel + PSTE, 8, // 160 Stop on Error + PCAD, 8, // 161 Peci Clinet Addess + PEWL, 8, // 162 Write Length + PWRL, 8, // 163 Read lenght + PECD, 8, // 164 Command Code + PEHI, 8, // 165 Host ID + PECI, 8, // 166 Index + PEPL, 8, // 167 Parameter (LSB) + PEPM, 8, // 168 Parameter (MSB) + PWFC, 8, // 169 Write FCS + PECC, 8, // 170 Completion code + PDT0, 8, // 171 Data 0 + PDT1, 8, // 172 Data 1 + PDT2, 8, // 173 Data 2 + PDT3, 8, // 174 Data 3 + PRFC, 8, // 175 Read FCS + PRS0, 8, // 176 Reserved + PRS1, 8, // 177 Reserved + PRS2, 8, // 178 Reserved + PRS3, 8, // 179 Reserved + PRS4, 8, // 180 Reserved + Offset(187), + PRCS, 8, // 187 Peci Repeat Command Status + PEC0, 8, // 188 Peci Error Count(LSB) + PEC1, 8, // 189 Peci Error Count + PEC2, 8, // 190 Peci Error Count + PEC3, 8, // 191 Peci Error Count(MSB) + GTVR, 8, // 192 CPU GT VR temp + MCRT, 8, // 193 Minicard Region Temp + Offset(194), + IBT1, 8, // 194 ISCT Byte 1 + // 194.0 Enable/Disable ISCT - SAOS bit + // 194.1 WLAN powered in S3 + // 194.2 WLAN powered in S4 + // 194.3 WLAN powered in S5 + // 194.4 WWAN powered in S3 + // 194.5 WWAN powered in S4 + // 194.6 WWAN powered in S5 + // 194.7 Reserved + IBT2, 8, // 195 ISCT Byte 2 + // 195.0 WLAN Wireless Status (0 = Disabled, 1 = Enabled) + // 195.1 WWAN Wireless Status (0 = Disabled, 1 = Enabled) + // 195.2:7 Reserved + WTMS, 8, // 196 Wake timer Settings + // 196.0 Timer Enabled in S3 + // 196.1 Timer Enabled in S4 + // 196.2 Timer Enabled in S5 + // 196.3:6 Reserved + // 196.7 Enable/Disable EC Timer + AWT2, 8, // 197 ACPIWakeTmrByte2 - Wake timer value (BIT23-16) + AWT1, 8, // 198 ACPIWakeTmrByte1 - Wake timer value (BIT15-8) + AWT0, 8, // 199 ACPIWakeTmrByte0 - Wake timer value (BIT7-0) + SPT2, 1, // 200.0 SATA Por2 - Cable connect power control. 1=ON;0=OFF + ,7, // 200.7-1 Reserved + Offset(211), + B1DV, 16, // 211 Battery 1 Design Voltage (mV) + Offset(215), + B1ML, 8, // 215 BattAPmaxL - Battery Pack A maximum low byte + B1MH, 8, // 216 BattAPmaxH - Battery Pack A maximum high byte + B2ML, 8, // 217 BattBPmaxL - Battery Pack B maximum low byte + B2MH, 8, // 218 BattBPmaxH - Battery Pack B maximum high byte + BTP1, 8, // 219 Battery 1 Trip Point in % + } + + + // ECRD (Embedded Read Method) + // + // Handle all commands sent to EC by BIOS + // + // Arguments: (1) + // Arg0 - Object to Read + // Return Value: + // Read Value + // + Method(ECRD,1,Serialized, 0, IntObj, FieldUnitObj) + { + If(LAnd(LEqual(\ECUP,Zero),LEqual(\_SB.RDGP(88),0))) + { + \_SB.WTGP(88,1) + Sleep(16) + } + Store(DerefOf (Arg0), Local0) + Return(Local0) + } + + // ECWT (Embedded Write Method) + // + // Handle all commands sent to EC by BIOS + // + // Arguments: (2) + // Arg0 - Value to Write + // Arg1 - Object to Write to + // + Method(ECWT,2,Serialized,,,{IntObj, FieldUnitObj}) + { + If(LAnd(LEqual(\ECUP,Zero),LEqual(\_SB.RDGP(88),0))) + { + \_SB.WTGP(88,1) + Sleep(16) + } + Store(Arg0,Arg1) + } + + // ECMD (Embedded Controller Command) + // + // Handle all commands sent to EC by BIOS + // + // Arguments: (1) + // Arg0 - EC command + // Return Value: + // 0x00 = Success + // 0xFF = Failure + // + Method(ECMD,1,Serialized) + { + While(ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.CMDR))){Stall(20)} // make sure no command is currently being processed so we don't overwrite it + ECWT(Arg0, RefOf(\_SB.PCI0.LPCB.H_EC.CMDR)) + Return (0x00) + } + + Include("ALS.ASL") + + + // Virtual battery code + // + Include("Bat0Virt.asl") + + // Real battery code + // + Include("Bat1Real.asl") + Include("Bat2Real.asl") + + // The _REG Method is needed because communication with the EC + // before the driver is loaded is prohibited in WIN2000/WINXP. + + Method(_REG,2) + { + If(LAnd(LEqual(Arg0,3),LEqual(Arg1,1))) + { + // Must be running NT 5.0 OS. + // Update ECAV Object. ASL should check for this value to be One before accessing EC OpRegion. + Store(One, ECAV) + + // Turn off the CPU Fan if Active Cooling + // is disabled. + + If(LEqual(0,ACTT)) + { + ECWT(0,RefOf(CFAN)) + } + + // Turn off pwm fan so it starts in a known state + If(LEqual(1, THOF)) + { + \_TZ.FN00._OFF() + } + + // Update the Ambiant Light Illuminence Values. + + Store(ECRD(RefOf(LUXH)),LHIH) + Store(ECRD(RefOf(LUXL)),LLOW) + + If(LAnd(LEqual(ALSE,2),IGDS)) + { + Store(ECRD(RefOf(LUXH)), Local0) + Or(ShiftLeft(Local0, 8), ECRD(RefOf(LUXL)), \_SB.PCI0.GFX0.ALSI) + } + + // Save the Lid State in global NVS and IGD OpRegion. + //Store(LSTE,\_SB.PCI0.GFX0.CLID) + If (LEqual(ECRD(RefOf(LSTE)), 0)) + { + Store(0,\_SB.PCI0.GFX0.CLID) + } + If (LEqual(ECRD(RefOf(LSTE)), 1)) + { + Store(3,\_SB.PCI0.GFX0.CLID) + } + Store(ECRD(RefOf(LSTE)),LIDS) + + // Update the Dock Status + Store(\DSTS,\_SB.PCI0.GFX0.CDCK) + + // Unconditionally fix up the Battery and Power State. + + // Initialize the Number of Present Batteries. + // 1 = Real Battery 1 is present + // 2 = Real Battery 2 is present + // 3 = Real Battery 1 and 2 are present + + Store(0,BNUM) + Or(BNUM,ShiftRight(And(ECRD(RefOf(B1ST)),0x08),3),BNUM) + Or(BNUM,ShiftRight(And(ECRD(RefOf(B2ST)),0x08),2),BNUM) + + // Save the current Power State for later. + + Store(PWRS,Local0) + + // Initialize the Power State. + // BNUM = 0 = Virtual Power State + // BNUM > 0 = Real Power State + + If(LEqual(BNUM,0)) + { + Store(ECRD(RefOf(VPWR)),PWRS) + } + Else + { + Store(ECRD(RefOf(RPWR)),PWRS) + } + + // Perform needed ACPI Notifications. + + PNOT() + + // + // Call Power button init method for 10sec PB OVR + // + ^VGBI.PBIN() + } + } + + Method(_GPE) + { + Store (23, Local0) // GPI7 for other boards + + If(LOr(LOr(LEqual(BID,BWT1), LEqual(BID,BW1P)), LOr(LEqual(BID,BW2C), LEqual(BID,BW2P)))) // BoardIdWhiteTipMountain1, BoardIdWhiteTipMountain1Ppv, BoardIdWhiteTipMountain2, BoardIdWhiteTipMountain2Ppv + { + Store(10, Local0) // GPI10 + } + + If(LOr(LOr(LEqual(BID,BSPC), LEqual(BID,BSPP)), LEqual(BID,BRH))) // BoardIdSawToothPeak, BoardIdSawToothPeakPpv, BoardIdReedHarborTdv + { + Store(10, Local0) // GPI10 + } + + return (Local0) + } + + // For the below _Qxx Methods, The Runtime SCI has been asserted, + // the EC Driver performed it's query, and the value returned from + // the Query = xx. + + Method(_Q30) // Real Battery AC Insertion Event. + { + P8XH(0,0x30) + + // Set Global Power State = AC Mode. + + Store(1,PWRS) + + // Perform needed ACPI Notifications. + + PNOT() + } + + Method(_Q31) // Real Battery AC Removal Event. + { + P8XH(0,0x31) + + // Set Global Power State = Battery Mode. + + Store(0,PWRS) + + // Perform needed ACPI Notifications. + + PNOT() + } + + Method(_Q32) // Real Battery Capacity Change. + { + P8XH(0,0x32) + + // Perform needed ACPI Notifications. + + PNOT() + } + + Method(_Q33) // Real Battery Insertion/Removal Event. + { + P8XH(0,0x33) + + // Initialize the Number of Present Batteries. + // 1 = Real Battery 1 is present + // 2 = Real Battery 2 is present + // 3 = Real Battery 1 and 2 are present + + Store(0,BNUM) + Or(BNUM,ShiftRight(And(ECRD(RefOf(B1ST)),0x08),3),BNUM) + Or(BNUM,ShiftRight(And(ECRD(RefOf(B2ST)),0x08),2),BNUM) + + // Perform needed ACPI Notifications. + + PNOT() + } + + Method(_Q40, 0, Serialized) // Dock complete Event + { + P8XH(0,0x40) + If(LEqual(\_SB.PCI0.HDEF.DCKS, 1)) + { + If(LEqual(\_SB.PCI0.HDEF.DCKM, 0)) + { + Store(1, \_SB.PCI0.HDEF.DCKA) + Stall(50) + While(LNotEqual(\_SB.PCI0.HDEF.DCKM, 1)) + { + Stall(50) + } + } + } + + Sleep(1000) // Delay 1 second for hot docking stability + Store(\PDBR, \SSMP) + Store(1, \DSTS) + Sleep(1000) // Delay 1 second for hot docking stability + Notify(\_SB.PCI0.DOCK, 0x00) + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Or(PB1E, 0x10, PB1E) // Set Dock status + ^VGBI.UPBT(DOCK_INDICATOR, One) + ADBG("Notify 0xCA") + Notify(^VGBI, 0xCA) // Notify Virtual GPIO driver that Docking event happens. + } + + If(IGDS) + { + \_SB.PCI0.GFX0.GDCK(1) + } + } + + Method(_Q41) // Surprise Removal + { + P8XH(0,0x41) + If(LEqual(\_SB.PCI0.HDEF.DCKS, 1)) + { + If(LEqual(\_SB.PCI0.HDEF.DCKM, 1)) + { + Store(0, \_SB.PCI0.HDEF.DCKA) + } + } + Store(0, \DSTS) + Notify(\_SB.PCI0.DOCK, 0x01) + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + And(PB1E, Not(0x10), PB1E) // Clear Dock Status + ^VGBI.UPBT(DOCK_INDICATOR, Zero) + ADBG("Notify 0xCB") + Notify(^VGBI, 0xCB) // Notify Virtual GPIO driver that Undocking event happens. + } Else { + If(IGDS) + { + \_SB.PCI0.GFX0.GDCK(0) + } + } + } + + Method(_Q42) // Undocking request Event + { + P8XH(0,0x42) + If(LAnd(\_SB.PCI0.HDEF.DCKS, 1)) + { + Store(0, \_SB.PCI0.HDEF.DCKA) + } + Notify(\_SB.PCI0.DOCK, 0x01) + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + And(PB1E, Not(0x10), PB1E) // Clear Dock Status + ^VGBI.UPBT(DOCK_INDICATOR, Zero) + If(CondRefOf(\_SB.PCI0.GFX0.IUER)) + { + Store(\_SB.PCI0.GFX0.IUER, Local0) + And(Local0, Not(0x80), \_SB.PCI0.GFX0.IUER) + } + ADBG("Notify 0xCB") + Notify(^VGBI, 0xCB) // Notify Virtual GPIO driver that Undocking event happens. + } Else { + If(IGDS) + { + \_SB.PCI0.GFX0.GDCK(0) + } + } + } + + Method(_Q43) // Express Card Presence Changed on Saddlestring (Docking) + { + P8XH(0,0x43) + + Notify(\_SB.PCI0.RP07, 0x0) + } + + Method(_Q44) // Virtual Dock Presence Changed + { + If(\DSTS) + { + Notify(\_SB.PCI0.DOCK, 1) //UnDocked + Store(0, \DSTS) + } + Else + { + Notify(\_SB.PCI0.DOCK, 0) //Docked + Store(1, \DSTS) + } + } + + Method(_Q51) // Lid Switch Event. + { + P8XH(0,0x51) + + // Update Lid NVS State. + + Store(ECRD(RefOf(LSTE)),LIDS) + + \_SB.PCI0.GFX0.GLID(LIDS) + + // If ETM is not disabled, notify IETM device + If (LEqual(\_TZ.ETMD, 0)) + { + If(CondRefOf(\_SB.IETM)) + { + Notify(\_SB.IETM,0x83) + } + } + Notify(\_SB.LID0,0x80) + } + + + Method(_Q52) // Hot-Key Event. + { + P8XH(0,0x52) + + // This event will be generated whenever a + // CRTL+ALT+SHIFT+"Next Key" is hit. This event handler + // will base code execution on the "Next Key" Scan Code + // stored in the EC Memory Space. + + Store(ECRD(RefOf(SCAN)),Local2) + P8XH(1,Local2) + + + // "D" Scan Code = 0x20 + + If(LEqual(SCAN,0x20)) + { + ADBG("CAS+D") + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + // + // CAS+D test emulation mode + // 1. Windows press notify 0xC2 + // 2. Volume up press notify 0xC4 + // 3. Volume up release notify 0xC5 + // 4. Windows release notify 0xC3 + // + + Sleep(1000) // 1sec delay is needed for Powerbutton and Windows Home button. + + ^VGBI.UPBT(WINDOWS_BUTTON, One) // Update VBDS + ADBG("Notify 0xC2") + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + + ^VGBI.UPBT(VOLUME_UP_BUTTON, One) + ADBG("Notify 0xC4") + Notify(^VGBI, 0xC4) // Notify Virtual GPIO driver that Vol up button is pressed. + + ^VGBI.UPBT(VOLUME_UP_BUTTON, Zero) + ADBG("Notify 0xC5") + Notify(^VGBI, 0xC5) // Notify Virtual GPIO driver that Vol up button is released. + + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) + ADBG("Notify 0xC3") + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } + } + + // "F" Scan Code = 0x21 + + If(LEqual(SCAN,0x21)) + { + ADBG("CAS+F") + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + // + // CAS+F test emulation mode + // 1. Windows press notify 0xC2 + // 2. Volume down press notify 0xC6 + // 3. Volume down release notify 0xC7 + // 4. Windows release notify 0xC3 + // + + Sleep(1000) // 1sec delay is needed for Powerbutton and Windows Home button + + ^VGBI.UPBT(WINDOWS_BUTTON, One) // Update VBDS + ADBG("Notify 0xC2") + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, One) + ADBG("Notify 0xC6") + Notify(^VGBI, 0xC6) // Notify Virtual GPIO driver that Vol down button is pressed. + + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, Zero) + ADBG("Notify 0xC7") + Notify(^VGBI, 0xC7) // Notify Virtual GPIO driver that Vol down button is released. + + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) // Update VBDS + ADBG("Notify 0xC3") + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } + } + + // Intel Ultrabook Event Handlers. + + // "G" Scan Code = 0x22 + + If(LEqual(Local2,0x22)) + { + ADBG("CAS+G") + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + // + // CAS+G test emulation mode + // 1. Windows press notify 0xC2 + // 2. Powerbutton press notify 0xC0 + // 3. Powerbutton release notify 0xC1 + // 4. Windows release notify 0xC3 + // + + Sleep(1000) // 1sec delay is needed for Powerbutton and Windows Home button + + ^VGBI.UPBT(WINDOWS_BUTTON, One) + ADBG("Notify 0xC2") + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + If(And(PB1E, 1)) + { + ^VGBI.UPBT(POWER_BUTTON, One) + ADBG("Notify 0xC0") + Notify(^VGBI, 0xC0) // Notify Virtual GPIO driver that Power button is pressed. + + ^VGBI.UPBT(POWER_BUTTON, Zero) + ADBG("Notify 0xC1") + Notify(^VGBI, 0xC1) // Notify Virtual GPIO driver that Power button is released. + } + + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) + ADBG("Notify 0xC3") + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } Else { + // Power Button. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + If(LEqual(\_SB.HIDD.HRDY, 1)) + { + \_SB.HIDD.HPEM(9) + } Else { + ADBG("IUEH") + \_SB.PCI0.GFX0.IUEH(0) + } + } + } + + // "H" Scan Code = 0x23 + + If(LEqual(Local2,0x23)) + { + ADBG("CAS+H") + // Windows Button. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + Sleep(1000) + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + ^VGBI.UPBT(WINDOWS_BUTTON, One) + ADBG("Notify 0xC2") + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) + ADBG("Notify 0xC3") + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } Else { + If(LEqual(\_SB.HIDD.HRDY, 1)) + { + \_SB.HIDD.HPEM(1) + } Else { + ADBG("IUEH") + \_SB.PCI0.GFX0.IUEH(1) + } + } + } + + // "J" Scan Code = 0x24 + If(LEqual(Local2,0x24)) + { + ADBG("CAS+J") + // Volume Up. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + ^VGBI.UPBT(VOLUME_UP_BUTTON, One) + ADBG("Notify 0xC4") + Notify(^VGBI, 0xC4) // Notify Virtual GPIO driver that Volume UP button is pressed. + + ^VGBI.UPBT(VOLUME_UP_BUTTON, Zero) + ADBG("Notify 0xC5") + Notify(^VGBI, 0xC5) // Notify Virtual GPIO driver that Volume UP button is released. + } Else { + If(LEqual(\_SB.HIDD.HRDY, 1)) + { + \_SB.HIDD.HPEM(17) + } Else { + ADBG("IUEH") + \_SB.PCI0.GFX0.IUEH(2) + }// End of If(LEqual(\_SB.HIDD.HRDY, 1)) + } // If(LAnd(CondRefOf(^VGBI._STA)),(LEqual(And(^VGBI._STA(),One),One))) + } + + // "K" Scan Code = 0x25 + + If(LEqual(Local2,0x25)) + { + ADBG("CAS+K") + // Volume Down. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, One) + ADBG("Notify 0xC6") + Notify(^VGBI, 0xC6) // Notify Virtual GPIO driver that Volue Down button is pressed. + + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, Zero) + ADBG("Notify 0xC7") + Notify(^VGBI, 0xC7) // Notify Virtual GPIO driver that Volue Down button is released. + } Else { + If(LEqual(\_SB.HIDD.HRDY, 1)) + { + \_SB.HIDD.HPEM(18) + } Else { + ADBG("IUEH") + \_SB.PCI0.GFX0.IUEH(3) + } + } + } + + // "L" Scan Code = 0x26 + + If(LEqual(Local2,0x26)) + { + ADBG("CAS+L") + // Rotation Lock. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + Sleep(1000) + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Xor(PB1E, 0x04, PB1E) // Toggle Rotation Lock Status (bit2 of PB1E) + ^VGBI.UPBT(ROTATION_LOCK_BUTTON, One) + ADBG("Notify 0xC8") + Notify(^VGBI, 0xC8) // Notify Virtual GPIO driver that Rotation Lock button is pressed. + + ^VGBI.UPBT(ROTATION_LOCK_BUTTON, Zero) + ADBG("Notify 0xC9") + Notify(^VGBI, 0xC9) // Notify Virtual GPIO driver that Rotation Lock button is released. + } Else { + If(LEqual(\_SB.HIDD.HRDY, 1)) + { + \_SB.HIDD.HPEM(2) + } Else { + ADBG("IUEH") + \_SB.PCI0.GFX0.IUEH(4) + } + } + } + + // ";" Scan Code = 0x27 + If(LEqual(Local2,0x27)) + { + ADBG("CAS+;") + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Xor(PB1E, 0x08, PB1E) // Toggle Slate/Laptop Lock Status + If(And(PB1E, 0x08)) // Slave/Laptop Mode changed 0 -> 1 Laptop mode + { + ^VGBI.UPBT(CONVERTIBLE_BUTTON, One) + ADBG("Notify 0xCD") + Notify(^VGBI, 0xCD) // Notify Virtual GPIO driver that the system is now in Laptop mode. + } Else { // Slave/Laptop Mode Changed 1 -> 0 Slate/Tablet Mode + ^VGBI.UPBT(CONVERTIBLE_BUTTON, Zero) + ADBG("Notify 0xCC") + Notify(^VGBI, 0xCC) // Notify Virtual GPIO driver that the system is now in Slate/Tablet mode. + } + } Else { + \_SB.PCI0.GFX0.IUEH(6) // Convertible Indicator lock + } + } + + // "'" Scan Code = 0x28 + If(LEqual(Local2,0x28)) + { + ADBG("CAS+'") + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Xor(PB1E, 0x10, PB1E) // Toggle Dock/Undock Status + If(And(PB1E, 0x10)) // Dock/Undock status changed 0 -> 1 Dock mode + { + ^VGBI.UPBT(DOCK_INDICATOR, One) + ADBG("Notify 0xCA") + Notify(^VGBI, 0xCA) // Notify Virtual GPIO driver that the system is now in Dock mode. + } Else { // Dock/Undock status Changed 1 -> 0 Undock mode + ^VGBI.UPBT(DOCK_INDICATOR, Zero) + ADBG("Notify 0xCB") + Notify(^VGBI, 0xCB) // Notify Virtual GPIO driver that the system is now in Undock mode. + } + } Else { + \_SB.PCI0.GFX0.IUEH(7) // Docking Indicator lock + } + } + + // F1 Scan Code = 0x3B + If(LEqual(Local2,0x3B)) // EC passes directly to kbd buffer, Windows handles this + { + ADBG("FN+F1") // Sleep + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + ADBG("Sleep") + } Else { + If(IGDS) + { + \_SB.PCI0.GFX0.GHDS(0) // GMCH SCI hotkey display switch, table index 0 + } + } + } + + // F2 Scan Code = 0x3C + If(LEqual(Local2,0x3C)) + { + ADBG("FN+F2") + If(LEqual(BID,BRH)){ // BoardIdReedHarborTdv +// TODO: Display Sleep for Reed Harbor + ADBG("Display Sleep") + } Else { + If(IGDS) // all other boards + { + \_SB.PCI0.GFX0.GHDS(1) // GMCH SCI hotkey display switch, table index 1 + } + } + } + + // F3 Scan Code = 0x3D + If(LEqual(Local2,0x3D)) + { + ADBG("FN+F3") + If(LEqual(BID,BRH)){ // BoardIdReedHarborTdv +// TODO: GPIO_57 RFKILL for WiFi for Reed Harbor + ADBG("RFKILL") + } Else { + If(IGDS) // all other boards + { + \_SB.PCI0.GFX0.GHDS(2) // GMCH SCI hotkey display switch, table index 2 + } + } + } + + // F4 Scan Code = 0x3E + If(LEqual(Local2,0x3E)) + { + ADBG("FN+F4") + // BoardIdReedHarborTdv + If(LEqual(BID,BRH)) // Hot Key decrease brightness. + { + If(And(4,DSEN)) + { + BRTN(0x87) + } Else { + Store(BRTL, Local0) + // Current brightness is a percentage. + // This must be done if ALS if enabled, as the driver will change the brightness based on ambient light. + Store(\_SB.PCI0.GFX0.CBLV, BRTL) + // 1 % will be lost in the conversion so need to make sure we account for it. + AND(Add(BRTL, 1),0xFE, BRTL) + If(LGreaterEqual(BRTL, 10)) + { + Subtract(BRTL, 10, BRTL) + } + \_SB.PCI0.GFX0.AINT(1, BRTL) + } + } Else { // Hot Key Display Switch for all other boards. + If(IGDS) + { + \_SB.PCI0.GFX0.GHDS(3) // GMCH SCI hotkey display switch, table index 3 + } + } + } + + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + // F5 Scan Code = 0x3F + If(LEqual(Local2,0x3F)) + { + ADBG("FN+F5") // brightness up + If(And(4,DSEN)) + { + BRTN(0x86) + } Else { + Store(BRTL, Local0) + // Current brightness is a percentage. + // This must be done if ALS if enabled, as the driver will change the brightness based on ambient light. + Store(\_SB.PCI0.GFX0.CBLV, BRTL) + // 1 % will be lost in the conversion so need to make sure we account for it. + AND(Add(BRTL, 1),0xFE, BRTL) + If(LLessEqual(BRTL, 90)) + { + Add(BRTL, 10, BRTL) + } + \_SB.PCI0.GFX0.AINT(1, BRTL) + } + } // end If(LEqual(Local2,0x3E)) + } Else { // all other boards + // Virtual Battery Hot Keys(VBHK) - VBHK uses keys 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, -, + and F5. + If(LEqual(BNUM,0)) // Check for Virtual Battery Mode before testing the hot-keys specific to Virtual Battery Support. + { + VBHK() // remove this call if no virtual battery is needed. + } + } + + // F6 Scan Code = 0x40 + If(LEqual(Local2,0x40)) + { + ADBG("FN+F6") + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + If(IGDS) // toggle display + { + \_SB.PCI0.GFX0.GHDS(0) // GMCH SCI hotkey display switch, table index 0 + } + } Else { + If(IGDS) // Cycle Brightness for all other boards + { + If(CondRefOf(HGAS)) + { + HGAS() + } Else { + If(And(4,DSEN)) + { + BRTN(0x85) + } + } + } + } + } + + // Disable these Function keys for Reed Harbor. + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + // F7 Scan Code = 0x41 + If(LEqual(Local2,0x41)) // EC passes directly to kbd buffer + { + ADBG("FN+F7") // mute + } + // F8 Scan Code = 0x42 + If(LEqual(Local2,0x42)) // EC passes directly to kbd buffer + { + ADBG("FN+F8") // volume down + } + // F9 Scan Code = 0x43 + If(LEqual(Local2,0x43)) // EC passes directly to kbd buffer + { + ADBG("FN+F9") // volume up + } + // F10 Scan Code = 0x44 + If(LEqual(Local2,0x44)) // blank + { + ADBG("FN+10") + } + } Else { + + // F7 Scan Code = 0x41 + If(LEqual(Local2,0x41)) // Zero Brightness + { + If(IGDS) + { + If(CondRefOf(CHPS)) + { + CHPS() //Display the current hybrid policy on Port 80 header + } Else { + If(And(4,DSEN)) + { + BRTN(0x88) + } + } + } + } + + // F8 Scan Code = 0x42 + If(LEqual(Local2,0x42)) // Panel Fitting Hot Key. + { + If(IGDS) + { + If(CondRefOf(HPFS)) + { + HPFS() + } Else { + \_SB.PCI0.GFX0.AINT(2, 0) + } + } + } + + // F9 Scan Code = 0x43 + If(LEqual(Local2,0x43)) // Decrease Brightness Level. + { + If(CondRefOf(HBRT)) + { + HBRT(4) + } + If(IGDS) + { + If(And(4,DSEN)) + { + BRTN(0x87) + } Else { + Store(BRTL, Local0) + // Current brightness is a percentage. + // This must be done if ALS if enabled, as the driver will change the brightness based on ambient light. + Store(\_SB.PCI0.GFX0.CBLV, BRTL) + // 1 % will be lost in the conversion so need to make sure we account for it. + AND(Add(BRTL, 1),0xFE, BRTL) + If(LGreaterEqual(BRTL, 10)) + { + Subtract(BRTL, 10, BRTL) + } + \_SB.PCI0.GFX0.AINT(1, BRTL) + } + } + } + + // F10 Scan Code = 0x44 + If(LEqual(Local2,0x44)) // Increase Brightness Level. + { + If(CondRefOf(HBRT)) + { + HBRT(3) + } + If(IGDS) + { + If(And(4,DSEN)) + { + BRTN(0x86) + } Else { + Store(BRTL, Local0) + // Current brightness is a percentage. + // This must be done if ALS if enabled, as the driver will change the brightness based on ambient light. + Store(\_SB.PCI0.GFX0.CBLV, BRTL) + // 1 % will be lost in the conversion so need to make sure we account for it. + AND(Add(BRTL, 1),0xFE, BRTL) + If(LLessEqual(BRTL, 90)) + { + Add(BRTL, 10, BRTL) + } + \_SB.PCI0.GFX0.AINT(1, BRTL) + } + } + } + } // end If(LEqual(BID,BRH)) + + // "F12" Scan Code = 0x58 + If(LEqual(Local2,0x58)) + { + // Airplane Mode toggle. + If(\_SB.HIDD.HRDY) + { + \_SB.HIDD.HPEM(8) + } + } + + // Calculator (-) Key = 0x4A + + If(LEqual(Local2,0x4A)) // ACPI Debug Mode is Off. + { + Store(0,DBGS) + } + + // Calculator (+) Key = 0x4E + + If(LEqual(Local2,0x4E)) // ACPI Debug Mode is On. + { + Store(1,DBGS) + } + + // Calculator (Enter) Key = 0x1C + If(LEqual(Local2,0x1C)) // Set ACPI Break Point. + { + BreakPoint + } + + + // "D" Scan Code = 0x20 + If(LEqual(Local2,0x20)) // Virtual Dock + { + \_SB.PCI0.GFX0.GDCK(1) + } + + // "U" Scan Code = 0x16 + If(LEqual(Local2,0x16)) // Virtual Undock + { + \_SB.PCI0.GFX0.GDCK(0) + } + + // "0" Scan Code = 0x01 + If(LEqual(Local2,0x01)) // Toggle Wireless On/Off state. + { + + } + + + + // HK: "O" Scan Code = 0x18 + If(LEqual(Local2,0x18)) // CTDP Up + { + If(LAnd(CondRefOf(\_SB.PCI0.CTCU),LEqual(CTDB,1))){ // only allow this feature if it is enabled in SETUP + \_SB.PCI0.CTCU() + } + } + + // HK: "[" Scan Code = 0x1A + If(LEqual(Local2,0x1A)) // CTDP Nominal + { + If(LAnd(CondRefOf(\_SB.PCI0.CTCN),LEqual(CTDB,1))){ // only allow this feature if it is enabled in SETUP + \_SB.PCI0.CTCN() + } + } + + // HK: "]" Scan Code = 0x1B + If(LEqual(Local2,0x1B)) // CTDP Down + { + If(LAnd(CondRefOf(\_SB.PCI0.CTCD),LEqual(CTDB,1))){ // only allow this feature if it is enabled in SETUP + \_SB.PCI0.CTCD() + } + } + + // "Fn+F12" Scan Code = 0x62 + If(LEqual(Local2,0x62)) // Web-Cam power control + { + P8XH(0, 0x62) + } + + } // end Method(_Q52) hot key event + + Method(_Q54) // Power Button Event for iSCT and Control method Power Button(10sec PB Override without V-GPIO driver) + { + + P8XH(0,0x54) + + // + // iSCT and 10Sec PB Override are now mutual exclusive at least for this event. + // Make sure iSCT is enabled before notifying IAOE. + // + If(And(ICNF, 1)) + { + Notify(IAOE,0x80) + } + + // + // Check if 10sec PB Override and EC 10sec mode. + // If 10sec PB OVR is enabled but EC 10sec mode is not enabled, then BIOS has to handle + // Power button event. + // PB1E Bit0 -> Setup setting for 10sec PB OVR + // PB10 -> EC setting for 10sec PB OVR + // + If(LAnd(And(PB1E, 1), LNot(ECRD(RefOf(PB10))))){ + + // + // Check UAMS(User Absent Mode State) to notify the power button event. + // + If(UAMS){ // UAMS has a non-Zero value, means the system is under User Absent Mode. Send Wake up event. + ADBG("PB Wake up 0x02") + If(CondRefOf(\_SB.PWRB)){ + Notify(\_SB.PWRB, 0x02) + } + } Else { // UAMS is Zero, means the system is ON. Send Sleep event. + ADBG("PB Sleep 0x80") + If(CondRefOf(\_SB.PWRB)){ + Notify(\_SB.PWRB, 0x80) + } + } + } + } // end Method(_Q54) Power button event. + + Method (_Q70) // ALS "Light Intensity" event + { + P8XH(0,0x70) + + // Update the LUX Values. + + Store(ECRD(RefOf(LUXH)),LHIH) + Store(ECRD(RefOf(LUXL)),LLOW) + + If(LAnd(LEqual(ALSE,2),IGDS)) + { + // Handle the ALS event via the OpRegion method + + Store(ECRD(RefOf(LUXH)), Local0) + Or(ShiftLeft(Local0, 8), ECRD(RefOf(LUXL)), Local0) + \_SB.PCI0.GFX0.AINT(0, Local0) + Notify(ALSD,0x80) // notify MS driver of change + } + } + + Method(_QD5) // 10 second power button press. + { + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + ^VGBI.UPBT(POWER_BUTTON, One) + ADBG("Notify 0xC0") + ECMD (0x2D) // Wake up EC first. This is needed to get the release event immediately after press event. + Notify(^VGBI, 0xC0) // Notify Virtual GPIO driver that the power button is pressed. + } Else { + If(CondRefOf(\_SB.PCI0.GFX0.IUER)) + { + Store(\_SB.PCI0.GFX0.IUER, Local0) + And(Local0, 0xC0, \_SB.PCI0.GFX0.IUER) // Clear 4:0 button events on entry. + Store(\_SB.PCI0.GFX0.IUER, Local0) + Or(Local0, 0x01, \_SB.PCI0.GFX0.IUER) // Set Power Button Status = pressed. + } + } // End IF + }// End of Method + + Method(_QD6) // 10 second power button de-press. + { + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + ^VGBI.UPBT(POWER_BUTTON, Zero) + ADBG("Notify 0xC1") + Notify(^VGBI, 0xC1) // Notify Virtual GPIO driver that the power button is released. + } Else { + If(CondRefOf(\_SB.PCI0.GFX0.IUER)) + { + Store(\_SB.PCI0.GFX0.IUER, Local0) + And(Local0, 0xC0, \_SB.PCI0.GFX0.IUER) // Clear 4:0 button events on entry. + } + } + } +// +// Reed Harbor hardware buttons. +// + Method(_Q80) // Volume Up + { + If(LEqual(BID,BRH)){ // BoardIdReedHarborTdv +ADBG("Volume Up") + \_SB.PCI0.GFX0.IUEH(2) + } + } + Method(_Q81) // Volume Down + { + If(LEqual(BID,BRH)){ // BoardIdReedHarborTdv +ADBG("Volume Down") + \_SB.PCI0.GFX0.IUEH(3) + } + } + Method(_Q85) // Windows Home button + { + If(LEqual(BID,BRH)){ // BoardIdReedHarborTdv +ADBG("Windows Home") + Sleep(1000) + \_SB.PCI0.GFX0.IUEH(1) + } + } + + Method(_QF0) // Thermal Event. + { + If(LEqual(DBGS,0)) + { + // Only handle the numerous Thermal Events if + // we are NOT doing ACPI Debugging. + Notify(\_TZ.TZ00,0x80) + Notify(\_TZ.TZ01,0x80) + } + } + +Device(WDT0) // WDT Device Resource Consumption +{ + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,3) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x6A4,0x6A4,0x1,0x1) // 1 Byte EC Prv Intfc. + IO(Decode16,0x6A0,0x6A0,0x1,0x1) // 1 Byte EC Prv Intfc. + }) +} + +/************************************************************************; +;* +;* Name: CHDK +;* +;* Description: Check DOCK status, returen True if Dock status equal Arg0 +;* +;************************************************************************/ + + Method(CHDK, 1) + { + // If not Mobile Platform then skip the code and return 0 + If(LEqual(ECON,1)){ + If(LEqual(ECRD(RefOf(DOCK)), Arg0)) + { // If not docked then it's hot plug + Return(1) + } + } + Return(0) + } + + // + // Hardware Button Array support + // + + Device(BIND) // Button Indicators. + { + Name(_HID, "INT33D2") + Name(_CID, "PNP0C40") + + Method(_STA, 0,Serialized) + { + If(LAnd(And(IUBE,1), LGreaterEqual(OSYS, 2012))) + { + Return(0x000F) + } + Return(0x00) + } + // + // _DSM : Device Specific Method for the Windows Compatible Button Array. + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) + { + // Compare passed in UUID to supported UUID. + + If (LEqual(Arg0, ToUUID ("DFBCF3C5-E7A5-44E6-9C1F-29C76F6E059C"))) + { + If (LEqual(0,ToInteger(Arg1))) // Revision 0. + { + Switch (ToInteger(Arg2)) // Switch to Function Index. + { + // + // Function 0, Query of supported functions. + // + + Case (0) + { + Return (Buffer() {0x03}) + } + + // + // Function 1, Windows Compatible Button Array Power Button Properties. + // + + Case (1) + { + // Only return support if platform enabled via setup. + // PB1E's Bit0 is set only when both CS and 10s PB OVR are enabled. + If(LEqual(And(PB1E, 1), 1)) + { + Return (0x07) + } + + Return(0x00) + + } + } // End Switch statement + } // End Revision check + } // End UUID check + + // If the code falls through to this point, just return a buffer of 0. + + Return (Buffer() {0x00}) + + } // End _DSM Method + } + + Device(CIND) // Convertible Indicators. + { + Name(_HID, "INT33D3") + Name(_CID, "PNP0C60") + + Method(_STA, 0,Serialized) + { + If(LAnd(And(IUCE,1), LGreaterEqual(OSYS, 2012))) + { + Return(0x000F) + } + Return(0x00) + } + } + + Device(DIND) // Docking Indicators. + { + Name(_HID, "INT33D4") + Name(_CID, "PNP0C70") + Method(_STA, 0,Serialized) + { + If(LAnd(And(IUDE,1), LGreaterEqual(OSYS, 2012))) + { + Return(0x000F) + } + Return(0x00) + } + } + + Device(VGBI) // Virtual GPIO Button "Interface." + { + + Name(_HID, EISAID("INT33D6")) // HID for Intel Virtual GPIO Button Interface. + Name(VBDS,0) + Name(ONTM,0) // Temporary variable to initialise VBDS only once in the boot + + Method(_STA,0,Serialized) + { + If(LGreaterEqual(OSYS,2013)) // Virtual Button applicable for Winblue and higher version of WinOS + { + ADBG("WinB VGBI STA") + Return(0x0F) // Device present,enabled and should be shown in UI. + } Else { + Return(0x00) // Device NOT present + } + }// End of _STA + + Method(VBDL,0,Serialized) // Virtual Button Driver Load - Refer Bios Arch Spec + { + ADBG("VBDL") + If(LEqual(And(PB1E,One),One)){ // 10 Sec Power Button Enabled in setup? + ADBG("VBDL EN") + + // + // Clear PBST so that we can hide the default power button. + // + If(CondRefOf(\_SB.PWRB.PBST)) + { + Store(0, \_SB.PWRB.PBST) + Notify(\_SB.PWRB, 1) // Device check + } + + // First send 0x74 to EC to disable _Q54 event for Power button. + If(CondRefOf(ECMD)){ + ADBG("Disable _Q54") + ECMD(0x74) + } + + // Set EC 10s enable bit. + ECWT(1, RefOf(PB10)) + + } Else { + // 10s power button disabled, clear EC 10s enable bit. + ADBG("VBDL DIS") + ECWT(0, RefOf(PB10)) + + // + // Here we know V-GPIO driver is loaded but 10s PB is disabled. + // Set PBST so that the default power button can handle the request. + // + If(CondRefOf(\_SB.PWRB.PBST)) + { + Store(1, \_SB.PWRB.PBST) + Notify(\_SB.PWRB, 1) // Device check + } + } + } + + Method(VGBS,0,Serialized) // Virtual GPIO Button Status - Refer Bios Arch Spec + { + // Bit[7] : Docking Indicatory Status + // Bit[6] : Convertible/Slate Indicator Status + // Bit[5] : Reserved + // Bit[4] : Rotation Lock Button Status + // Bit[3] : Volume Down Button Status + // Bit[2] : Volume Up Button Status + // Bit[1] : Windows Home Button Status + // Bit[0] : Power Button Status + + ADBG("VGBS") + If(LEqual(ONTM,0)) + { + // Initial setup option on VBDS and thereafter hotkeys should be updating the VBDS + if(LEqual(And(PB1E,0x04),0x04)) // Rotation Lock + { + UPBT(ROTATION_LOCK_BUTTON,One) + } + + if(LEqual(And(PB1E,0x08),0x08)) // Slate/Laptop + { + UPBT(CONVERTIBLE_BUTTON,One) + } + + if(LEqual(And(PB1E,0x10),0x10)) // Undock/Dock + { + UPBT(DOCK_INDICATOR,One) + } + Store(One,ONTM) + } + Return(VBDS) + }// End of Method + + // + // UPBT Update Button Status + // + // Arg0: Bit location of the target button + // 0: Power Button + // 1: Windows Button + // 2: Volume up Button + // 3: Volume down Button + // 4: Rotation Lock Button + // 5: Reserved + // 6: Convertible state 0 - Slate, 1 - Notebook + // 7: Dock Indicator 0 - Undock, 1 - Dock + // + // Arg1: On/Off state, 0 - Clear the target bit, 1 - Set the target bit. + // + Method(UPBT,2,Serialized) // Update Button Status + { + ShiftLeft(One, Arg0, Local0) + if(Arg1){ // Button Press/ON + Or(VBDS, Local0, VBDS) + } Else { // Button Press/OFF + And(VBDS, Not(Local0),VBDS) + } + } // End of UPBT + + Method(PBIN, 0, Serialized) + { + ADBG("VGBI PB INIT") + // + // Send EC 0x73 command to make 0x54 Power button notification is available. + // This is needed to support no Virtual GPIO driver case. + // Once the driver calls VBDL, VBDL sends 0x74(disable PB 0x54) to EC. + // + If(LAnd(And(PB1E, 1), LNot(ECRD(RefOf(PB10))))) + { + If(CondRefOf(\_SB.PWRB.PBST)) + { + Store(1, \_SB.PWRB.PBST) + Notify(\_SB.PWRB, 1) // Device check + } + If(CondRefOf(ECMD)){ + ADBG("Enable _Q54") + ECMD(0x73) // Enable Power Button 0x54 Notification + } + } + } + } // End of VGBI + +} // End H_EC + + // System Bus + +Scope(\_SB) +{ + + // Define an AC Device. + + Device(ADP1) + { + Name(_HID,"ACPI0003") + + Method(_STA) + { + If (LEqual(ECON,1)){ + Return(0x0F) + } + Return(0x00) + } + + // Return the value that determines if running + // from AC or not. + + Method(_PSR,0) + { + Return(PWRS) + } + + // Return that everything runs off of AC. + + Method(_PCL,0) + { + Return(\_SB) + } + } + + // Define a Lid Switch. + + Device(LID0) + { + Name(_HID,EISAID("PNP0C0D")) + + Method(_STA) + { + If(LEqual(ECON,1)){ + Return(0x0F) + } + Return(0x00) + } + + Method(_LID,0) + { + // 0 = Closed, 1 = Open. + + Return(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.LSTE))) + } + } + + // Define a (Control Method) Power Button. + + Device(PWRB) + { + Name(_HID,EISAID("PNP0C0C")) + + // The PRW isn't working when + // placed in any of the logical locations ( PS2K, PS2M, + // H_EC ), so a Power Button Device was created specifically + // for the WAKETIME_SCI PRW. + + // + // Power button status flag used to communicate H_EC.VBDL + // + Name(PBST, 1) + + Method(_PRW, 0) { + If(LEqual(LANP,1)){ + // + // When LAN is present, GPIO27 becomes ME GPIO(HSD 4834440). Remove PBT. + // + Return(Package(){0,0}) + } + If(LEqual(BID, BWT1)) + { + Return(Package(){27,4}) // GPI027 = GPE27 for WhiteTipMountain1 + } + If(LEqual(BID, BW1P)) + { + Return(Package(){27,4}) // GPI027 = GPE27 for WhiteTipMountain1 PPV + } + If(LEqual(BID, BW2C)) + { + Return(Package(){27,4}) // GPI027 = GPE27 for WhiteTipMountain2 + } + If(LEqual(BID, BW2P)) + { + Return(Package(){27,4}) // GPI027 = GPE27 for WhiteTipMountain2 PPV + } + If(LEqual(BID, BSPC)) + { + Return(Package(){27,4}) // GPI027 = GPE27 for SawToothPeak + } + If(LEqual(BID, BSPP)) + { + Return(Package(){27,4}) // GPI027 = GPE27 for SawToothPeak PPV + } + + Return(Package(){30,4}) //GPI14 = GPE30 = Waketime SCI for Haswell Traditional boards + } + + Method(_STA, 0) + { + If(LAnd(LEqual(ECON,1), PBST)){ + Return(0x0F) + } + Return(0x00) + } + + }//end device PWRB + + Device(HIDD) // HID Device. + { + Name(_HID,"INT33D5") // Intel Ultrabook HID Platform Event Driver. + Name(_CID,"PNP0C02") // Generic Motherboard Resources. + + Name (HBSY, 0) // HID Busy + Name (HIDX, 0) // HID Index + Name (HMDE, 0) // HID Mode + Name (HRDY, 0) // HID Ready + + Method(_STA,0,Serialized) // Status Method. + { + If(LEqual(BID, BHB)) // Hide device for HarrisBeach + { + Return(0x00) + } + Else + { + Return(0x0F) + } + } + + // + // HID Driver Descriptor Method - Called by HID Driver during initialization + // to obtain HID Descriptor information. + // + // Input: None + // + // Output: Package containing a complete HID Descriptor information. + // + Method(HDDM,0,Serialized) + { + // Placeholder. + Name(DPKG, Package(4) {0x11111111, 0x22222222, 0x33333333, 0x44444444}) + Return(DPKG) + } + + // + // HID Driver Event Method - Called by HID Driver to get the specific + // platform event. + // + // Input: None + // + // Output: Plastform HID Event. + // Mode 0 = Index of HID Input Report, per pre-defined Table. + // Mode 1 = Package containing a complete HID Input Report. + // + Method(HDEM,0,Serialized) + { + Store(0,HBSY) // Clear HID Busy. + // Simple Mode is hardcoded for now. Return Simple Mode HID Index Value. + If(LEqual(HMDE,0)) + { + Return(HIDX) + } + Return(HMDE) + } + + // + // HID Driver Mode Method - Called by HID Driver during initialization to get + // the platform mode of operation. + // + // Input: None + // + // Output: Mode the platform is running in. + // 0 = Simple Mode. + // 1 = Advanced Mode. + // + Method(HDMM,0,Serialized) + { + Return(HMDE) // Return Mode of operation. + } + + // + // HID Driver Status Method - called by HID Driver to report platform readiness status. + // Input: Driver Status. + // 0 = Driver Unloaded. + // 1 = Driver Loaded and Ready. + // + // Output: None + // + Method(HDSM,1,Serialized) + { + Store(Arg0,HRDY) // Store HID Ready Status. + // Eventually code will communicate to platform the Driver status (enabled/disabled). + } + + // + // HID Platform Event Method - called by Platform to communicate HID Event to Driver. + // Input: + // Mode 0 = Index of HID Event. + // Mode 1 = Package containing a complete HID Report. + // + Method(HPEM,1,Serialized) // HID Platform Event Method. + { + Store(1,HBSY) // Set HID Busy. + // Simple Mode is hardcoded for now. Simply store HID Index value. + If(LEqual(HMDE,0)) + { + Store(Arg0,HIDX) + } Else { + Store(Arg0,HIDX) + } + Notify(\_SB.HIDD,0xC0) // Notify Driver to get HID Event. + Store(0,Local0) // Initialize Local0 as a timeout counter. + While(LAnd(LLess(Local0,250),HBSY)) // Wait <= 1 second for Driver to ACK success. + { + Sleep(4) // Delay 4 ms. + Increment(Local0) // Increment Timeout. + } + If(LEqual(HBSY,1)) // Failure? + { + Store(0,HBSY) // Yes. Clear HID Busy Flag. + Store(0,HIDX) // Set HID Simple Mode Index = 0 = Undefined. + Return(1) // Return Failure. + } Else { + Return(0) // Return Success. + } + } + } + + +}//end scope _SB + + diff --git a/ReferenceCode/AcpiTables/Dsdt/GloblNvs.asl b/ReferenceCode/AcpiTables/Dsdt/GloblNvs.asl new file mode 100644 index 0000000..07f4381 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/GloblNvs.asl @@ -0,0 +1,560 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + + // Define a Global region of ACPI NVS Region that may be used for any + // type of implementation. The starting offset and size will be fixed + // up by the System BIOS during POST. Note that the Size must be a word + // in size to be fixed up correctly. + + OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55) + Field(GNVS,AnyAcc,Lock,Preserve) + { + Offset(0), // Miscellaneous Dynamic Registers: + OSYS, 16, // (000) Operating System + SMIF, 8, // (002) SMI Function Call (ASL to SMI via I/O Trap) + PRM0, 8, // (003) SMIF - Parameter 0 + PRM1, 8, // (004) SMIF - Parameter 1 + SCIF, 8, // (005) SCI Function Call (SMI to ASL via _L00) + PRM2, 8, // (006) SCIF - Parameter 0 + PRM3, 8, // (007) SCIF - Parameter 1 + LCKF, 8, // (008) Global Lock Function Call (EC Communication) + PRM4, 8, // (009) LCKF - Parameter 0 + PRM5, 8, // (010) LCKF - Parameter 1 + P80D, 32, // (011) Port 80 Debug Port Value + PWRS, 8, // (015) Power State (AC Mode = 1) + DBGS, 8, // (016) Debug State + Offset(17), // Thermal Policy Registers: + THOF, 8, // (017) Enable Thermal Offset for KSC + ACT1, 8, // (018) Active Trip Point 1 + ACTT, 8, // (019) Active Trip Point + PSVT, 8, // (020) Passive Trip Point + TC1V, 8, // (021) Passive Trip Point TC1 Value + TC2V, 8, // (022) Passive Trip Point TC2 Value + TSPV, 8, // (023) Passive Trip Point TSP Value + CRTT, 8, // (024) Critical Trip Point + DTSE, 8, // (025) Digital Thermal Sensor Enable + DTS1, 8, // (026) Digital Thermal Sensor 1 Reading + DTS2, 8, // (027) Digital Thermal Sensor 2 Reading + DTSF, 8, // (028) DTS SMI Function Call + Offset(30), // Battery Support Registers: (Moved outside this ASL code but still in used) +// BNUM, 8, // (030) Battery Number Present +// B0SC, 8, // (031) Battery 0 Stored Capacity +// B1SC, 8, // (032) Battery 1 Stored Capacity +// B2SC, 8, // (033) Battery 2 Stored Capacity +// B0SS, 8, // (034) Battery 0 Stored Status +// B1SS, 8, // (035) Battery 1 Stored Status +// B2SS, 8, // (036) Battery 2 Stored Status + Offset(37), // Revision Field: + REVN, 8, // (037) Revison of GlobalNvsArea + Offset(40), // CPU Identification Registers: + APIC, 8, // (040) APIC Enabled by SBIOS (APIC Enabled = 1) + TCNT, 8, // (041) Number of Enabled Threads + PCP0, 8, // (042) PDC Settings, Processor 0 + PCP1, 8, // (043) PDC Settings, Processor 1 + PPCM, 8, // (044) Maximum PPC state + PPMF, 32, // (045) PPM Flags (Same as CFGD) + C67L, 8, // (049) C6/C7 Entry/Exit latency + Offset(50), // SIO CMOS Configuration Registers: + NATP, 8, // (050) National SIO Present + CMAP, 8, // (051) COM A Port + CMBP, 8, // (052) COM B Port + LPTP, 8, // (053) LPT Port + FDCP, 8, // (054) FDC Port + CMCP, 8, // (055) SMSC Com Port + CIRP, 8, // (056) SMSC Com CIR Port + SMSC, 8, // (057) SMSC1007 SIO Present + W381, 8, // (058) WPCN381U SIO Present + SMC1, 8, // (059) SMSC1000 SIO Present + EMAE, 8, // (060) EMA Enable + EMAP, 16, // (061) EMA Pointer + EMAL, 16, // (063) EMA Length + Offset(66), // MEF Registers: + MEFE, 8, // (066) MEF Enable + Offset(67), // PCIe Dock: + DSTS, 8, // (067) PCIe Dock Status + Offset(72), // TPM Registers: + MORD, 8, // (072) Memory Overwrite Request Data + TCGP, 8, // (073) Used for save the Mor and/or physical presence paramter + PPRP, 32, // (074) Physical Presence request operation response + PPRQ, 8, // (078) Physical Presence request operation + LPPR, 8, // (079) Last Physical Presence request operation + Offset(80), // SATA Registers: + GTF0, 56, // (080) GTF Task File Buffer for Port 0 + GTF2, 56, // (087) GTF Task File Buffer for Port 2 + IDEM, 8, // (094) IDE Mode (Compatible\Enhanced) + GTF1, 56, // (095) GTF Task File Buffer for Port 1 + BID, 16, // (102) Platform board id + PLID, 8, // (104) Platform id + ECTG, 8, // (105) Toggle EC + Offset(112), + OSCC, 8, // (112) PCIE OSC Control + NEXP, 8, // (113) Native PCIE Setup Value + Offset(114), + SBV1, 8, // (114) USB Sideband Deferring GPE Vector (HOST_ALERT#1) + SBV2, 8, // (115) USB Sideband Deferring GPE Vector (HOST_ALERT#2) + Offset(122), // Global Variables + DSEN, 8, // (122) _DOS Display Support Flag. + ECON, 8, // (123) Embedded Controller Availability Flag. + GPIC, 8, // (124) Global IOAPIC/8259 Interrupt Mode Flag. + CTYP, 8, // (125) Global Cooling Type Flag. + L01C, 8, // (126) Global L01 Counter. + VFN0, 8, // (127) Virtual Fan0 Status. + VFN1, 8, // (128) Virtual Fan1 Status. + VFN2, 8, // (129) Virtual Fan2 Status. + VFN3, 8, // (130) Virtual Fan3 Status. + VFN4, 8, // (131) Virtual Fan4 Status. + VFN5, 8, // (132) Virtual Fan5 Status. + VFN6, 8, // (133) Virtual Fan6 Status. + VFN7, 8, // (134) Virtual Fan7 Status. + VFN8, 8, // (135) Virtual Fan8 Status. + VFN9, 8, // (136) Virtual Fan9 Status. + + Offset(143), + ATMC, 8, // (143) Active Trip Point for MCH + PTMC, 8, // (144) Passive Trip Point for MCH + ATRA, 8, // (145) Active Trip Point for TMEM + PTRA, 8, // (146) Passive Trip Point for TMEM + PNHM, 32, // (147) CPUID Feature Information [EAX] + TBAB, 32, // (151) Thermal Base Low Address for BIOS + TBAH, 32, // (155) Thermal Base High Address for BIOS + RTIP, 8, // (159) Run Time Interface for Intelligent Power Savings + TSOD, 8, // (160) TS-on-DIMM is chosen in SETUP and present on the DIMM + ATPC, 8, // (161) Active Trip Point for PCH + PTPC, 8, // (162) Passive Trip Point for PCH + PFLV, 8, // (163) Platform Flavor + BREV, 8, // (164) Board Rev + Offset(165), + PDTS, 8, // (165) Package Temperature + PKGA, 8, // (166) Package Temperature MSR available + PAMT, 8, // (167) Peci Access Method + AC0F, 8, // (168) _AC0 Fan Speed + AC1F, 8, // (169) _AC1 Fan Speed + DTS3, 8, // (170) Digital Thermal Sensor 3 Reading + DTS4, 8, // (171) Digital Thermal Sensor 4 Reading + Offset(176), // (172):(175) are reserved for future use + LTR1, 8, // (176) Latency Tolerance Reporting Enable + LTR2, 8, // (177) Latency Tolerance Reporting Enable + LTR3, 8, // (178) Latency Tolerance Reporting Enable + LTR4, 8, // (179) Latency Tolerance Reporting Enable + LTR5, 8, // (180) Latency Tolerance Reporting Enable + LTR6, 8, // (181) Latency Tolerance Reporting Enable + LTR7, 8, // (182) Latency Tolerance Reporting Enable + LTR8, 8, // (183) Latency Tolerance Reporting Enable + Offset(184), + OBF1, 8, // (184) Optimized Buffer Flush and Fill + OBF2, 8, // (185) Optimized Buffer Flush and Fill + OBF3, 8, // (186) Optimized Buffer Flush and Fill + OBF4, 8, // (187) Optimized Buffer Flush and Fill + OBF5, 8, // (188) Optimized Buffer Flush and Fill + OBF6, 8, // (189) Optimized Buffer Flush and Fill + OBF7, 8, // (190) Optimized Buffer Flush and Fill + OBF8, 8, // (191) Optimized Buffer Flush and Fill + Offset (192), + XHCI, 8, // (192) xHCI controller mode + XTUB, 32, // (193) XTU Continous structure Base Address + XTUS, 32, // (197) XMP Size + XMPB, 32, // (201) XMP Base Address + DDRF, 8, // (205) DDR Reference Frequency + + RTD3, 8, // (206) Runtime D3 support. + PEP0, 8, // (207) User selctable Delay for Device D0 transition. + PEP3, 8, // (208) User selctable Delay for Device D3 transition. + // + // DPTF Devices and trip points + // + DPTF, 8, // (209) EnableDptf + + SADE, 8, // (210) EnableSaDevice + SACR, 8, // (211) CriticalThermalTripPointSa + SAHT, 8, // (212) HotThermalTripPointSa + + PCHD, 8, // (213) EnablePchDevice + PCHC, 8, // (214) CriticalThermalTripPointPch + PCHH, 8, // (215) HotThermalTripPointPch + // + // DPTF Policies + // + CTDP, 8, // (216) EnableCtdpPolicy + LPMP, 8, // (217) EnableLpmPolicy + LPMV, 8, // (218) CurrentLowPowerMode for LPM + ECEU, 8, // (219) EnableCurrentExecutionUnit + TGFG, 16, // (220) TargetGfxFreq + // + // DPPM Devices and trip points + // + MEMD, 8, // (222) EnableMemoryDevice + MEMC, 8, // (223) CriticalThermalTripPointTMEM + MEMH, 8, // (224) HotThermalTripPointTMEM + + FND1, 8, // (225) EnableFan1Device + FND2, 8, // (226) EnableFan2Device + + AMBD, 8, // (227) EnableAmbientDevice + AMAT, 8, // (228) ActiveThermalTripPointAmbient + AMPT, 8, // (229) PassiveThermalTripPointAmbient + AMCT, 8, // (230) CriticalThermalTripPointAmbient + AMHT, 8, // (231) HotThermalTripPointAmbient + + SKDE, 8, // (232) EnableSkinDevice + SKAT, 8, // (233) ActiveThermalTripPointSkin + SKPT, 8, // (234) PassiveThermalTripPointSkin + SKCT, 8, // (235) CriticalThermalTripPointSkin + SKHT, 8, // (236) HotThermalTripPointSkin + + EFDE, 8, // (237) EnableExhaustFanDevice + EFAT, 8, // (238) ActiveThermalTripPointExhaustFan + EFPT, 8, // (239) PassiveThermalTripPointExhaustFan + EFCT, 8, // (240) CriticalThermalTripPointExhaustFan + EFHT, 8, // (241) HotThermalTripPointExhaustFan + + VRDE, 8, // (242) EnableVRDevice + VRAT, 8, // (243) ActiveThermalTripPointVR + VRPT, 8, // (244) PassiveThermalTripPointVR + VRCT, 8, // (245) CriticalThermalTripPointVR + VRHT, 8, // (246) HotThermalTripPointVR + // + // DPPM Policies + // + DPAP, 8, // (247) EnableActivePolicy + DPPP, 8, // (248) EnablePassivePolicy + DPCP, 8, // (249) EnableCriticalPolicy + DCMP, 8, // (250) EnableCoolingModePolicy + TRTV, 8, // (251) TrtRevision + // + // CLPO (Current Logical Processor Off lining Setting) + // + LPOE, 8, // (252) LPOEnable + LPOP, 8, // (253) LPOStartPState + LPOS, 8, // (254) LPOStepSize + LPOW, 8, // (255) LPOPowerControlSetting + LPER, 8, // (256) LPOPerformanceControlSetting + // + // Miscellaneous DPTF + // + PPSZ, 32, // (257) PPCC Step Size + DISE, 8, // (261) EnableDisplayParticipant + // + // PFAT + // + PFMA, 64, // (262) PFAT Memory Address for Tool Interface + PFMS, 8, // (270) PFAT Memory Size for Tool Interface + PFIA, 16, // (271) PFAT IoTrap Address for Tool Interface + // + // ISCT + // + ICNF, 8, // (273) Isct Configuration + // + // ADSP + // + DSP0, 32, // (274) Audio DSP BAR0 + DSP1, 32, // (278) Audio DSP BAR1 + // + // NFC + // + NFCE, 8, // (282) NFC module selection + // + // ADSP Codec Selection + // + CODS, 8, // (283) Audio Codec selection + // + // Sensor Hub Enable + // + SNHE, 8, // (284) Sensor Hub Enable + + S0ID, 8, // (285) Low Power S0 Idle Enable + + // + // BIOS only version of Config TDP + // + CTDB, 8, // (286) enable/disable BIOS only version of Config TDP + + Offset(519), + PWRE, 8, // (519) EnablePowerDevice + PWRP, 8, // (520) EnablePowerPolicy + XHPR, 8, // (521) RTD3 USB Power Resource config + // + // Intel Serial(R) IO Sensor Device Selection + // + SDS0, 8, // (522) I2C0 Sensor Device Selection + SDS1, 16, // (523) I2C1 Sensor Device Selection + SDS2, 8, // (525) SPI0 Sensor Device Selection + SDS3, 8, // (526) SPI1 Sensor Device Selection + SDS4, 8, // (527) UART0 Sensor Device Selection + SDS5, 8, // (528) UART1 Sensor Device Selection + Offset(530), // 529 no longer used + RIC0, 8, // (530) RTD3 support for I2C0 SH + PEPY, 8, // (531) RTD3 PEP support list(BIT0 - GFx , BIT1 - Sata, BIT2 - UART, BIT3 - SDHC, Bit4 - I2C0, BIT5 - I2C1, Bit6 - XHCI, Bit7 - Audio) + DVS0, 8, // (532) Port0 DevSlp Enable + DVS1, 8, // (533) Port1 DevSlp Enable + DVS2, 8, // (534) Port2 DevSlp Enable + DVS3, 8, // (535) Port3 DevSlp Enable + GBSX, 8, // (536) Virtual GPIO button Notify Sleep State Change + IUBE, 8, // (537) IUER Button Enable + IUCE, 8, // (538) IUER Convertible Enable + IUDE, 8, // (539) IUER Dock Enable + ECNO, 8, // (540) EC Notification of Low Power S0 Idle State + AUDD, 16, // (541) RTD3 Audio Codec device delay + DSPD, 16, // (543) RTD3 ADSP device delay + IC0D, 16, // (545) RTD3 SensorHub delay time after applying power to device + IC1D, 16, // (547) RTD3 TouchPanel delay time after applying power to device + IC1S, 16, // (549) RTD3 TouchPad delay time after applying power to device + VRRD, 16, // (551) VR Ramp up delay + PSCP, 8, // (553) P-state Capping + RWAG, 8, // (554) Rtd3 W/A Gpio, allow W/A for port 1 and 6 to use GPIO from SDHC device + I20D, 16, // (555) Delay in _PS0 after powering up I2C0 Controller + I21D, 16, // (557) Delay in _PS0 after powering up I2C1 Controller + + Offset(561), + RCG0, 8 , // (561) RTD3 Config Setting(BIT0:ZPODD,BIT1:USB Camera Port4, BIT2/3:SATA Port3) + ECDB, 8, // (562) EC Debug Light (CAPS LOCK) for when in Low Power S0 Idle State + P2ME, 8, // (563) Ps2 Mouse Enable + + SSH0, 16, // (564) SSCN-LOW for I2C0 + SSL0, 16, // (566) SSCN-HIGH for I2C0 + SSD0, 16, // (568) SSCN-HOLD for I2C0 + FMH0, 16, // (570) FMCN-LOW for I2C0 + FML0, 16, // (572) FMCN-HIGH for I2C0 + FMD0, 16, // (574) FMCN-HOLD for I2C0 + FPH0, 16, // (576) FPCN-LOW for I2C0 + FPL0, 16, // (578) FPCN-HIGH for I2C0 + FPD0, 16, // (580) FPCN-HOLD for I2C0 + SSH1, 16, // (582) SSCN-LOW for I2C1 + SSL1, 16, // (584) SSCN-HIGH for I2C1 + SSD1, 16, // (586) SSCN-HOLD for I2C1 + FMH1, 16, // (588) FMCN-LOW for I2C1 + FML1, 16, // (590) FMCN-HIGH for I2C1 + FMD1, 16, // (592) FMCN-HOLD for I2C1 + FPH1, 16, // (594) FPCN-LOW for I2C1 + FPL1, 16, // (596) FPCN-HIGH for I2C1 + FPD1, 16, // (598) FPCN-HOLD for I2C1 + M0C0, 16, // (600) M0D3 for I2C0 + M1C0, 16, // (602) M1D3 for I2C0 + M2C0, 16, // (604) M0D0 for I2C0 + M0C1, 16, // (606) M0D3 for I2C1 + M1C1, 16, // (608) M1D3 for I2C1 + M2C1, 16, // (610) M0D0 for I2C1 + M0C2, 16, // (612) M0D3 for SPI0 + M1C2, 16, // (614) M1D3 for SPI0 + M0C3, 16, // (616) M0D3 for SPI1 + M1C3, 16, // (618) M1D3 for SPI1 + M0C4, 16, // (620) M0D3 for UA00 + M1C4, 16, // (622) M1D3 for UA00 + M0C5, 16, // (624) M0D3 for UA01 + M1C5, 16, // (626) M1D3 for UA01 + TBSF, 8, // (628) ThunderBolt SMI Function Number + GIRQ, 32, // (629) GPIO IRQ + DMTP, 8, // (633) PIRQS 34,50(GPIO) + DMTD, 8, // (634) PIRQX 39,55(GPIO) + DMSH, 8, // (635) PIRQM 28,14(GPIO) + LANP, 8, // (636) LAN PHY Status 0 = Not Present, 1 = Present + Offset(638), // 637 no longer used. + SHSB, 8, // (638) Sensor Standby mode + PLCS, 8, // (639) set PL1 limit when entering CS + PLVL, 16, // (640) PL1 limit value + GN1E, 8, // (642) EnableGen1Participant + G1AT, 8, // (643) ActiveThermalTripPointGen1 + G1PT, 8, // (644) PassiveThermalTripPointGen1 + G1CT, 8, // (645) CriticalThermalTripPointGen1 + G1HT, 8, // (646) HotThermalTripPointGen1 + GN2E, 8, // (647) EnableGen2Participant + G2AT, 8, // (648) ActiveThermalTripPointGen2 + G2PT, 8, // (649) PassiveThermalTripPointGen2 + G2CT, 8, // (650) CriticalThermalTripPointGen2 + G2HT, 8, // (651) HotThermalTripPointGen2 + WWSD, 8, // (652) EnableWwanTempSensorDevice + CVSD, 8, // (653) EnableCpuVrTempSensorDevice + SSDD, 8, // (654) EnableSsdTempSensorDevice + INLD, 8, // (655) EnableInletFanTempSensorDevice + IFAT, 8, // (656) ActiveThermalTripPointInletFan + IFPT, 8, // (657) PassiveThermalTripPointInletFan + IFCT, 8, // (658) CriticalThermalTripPointInletFan + IFHT, 8, // (659) HotThermalTripPointInletFan + DOSD, 8, // (660) DMA OS detection, 1 = check for OS version when enabling DMA, 0 = don't care about OS + USBH, 8, // (661) USB Sensor Hub Enable/Disable + BCV4, 8, // (662) Broadcom's Bluetooth adapter's revision + WTV0, 8, // (663) I2C0/WITT devices version + WTV1, 8, // (664) I2C1/WITT devices version + APFU, 8, // (665) Atmel panel FW update Enable/Disable + SOHP, 8, // (666) SMI on Hot Plug for TBT devices + NOHP, 8, // (667) Notify on Hot Plug for TBT devices + TBSE, 8, // (668) ThunderBolt Root port selector + WKFN, 8, // (669) WAK Finished + PEPC, 16, // (670) PEP Constraints + VRSD, 16, // (672) VR Staggering delay + PB1E, 8, // (674) 10sec Power button support Bit0: 10 sec P-button Enable/Disable + // Bit1: Internal Flag + // Bit2: Rotation Lock flag, 0:unlock, 1:lock + // Bit3: Slate/Laptop Mode Flag, 0: Slate, 1: Laptop + // Bit4: Undock / Dock Flag, 0: Undock, 1: Dock + // Bit5, 6: reserved for future use. + // Bit7: EC 10sec PB Override state for S3/S4 wake up. + WAND, 8, // (675) EnableWWANParticipant + WWAT, 8, // (676) ActiveThermalTripPointWWAN + WWPT, 8, // (677) PassiveThermalTripPointWWAN + WWCT, 8, // (678) CriticalThermalTripPointWWAN + WWHT, 8, // (679) HotThermalTripPointWWAN + Offset(685), + MPLT, 16, // (685) Minimum Power Limit for DPTF use via PPCC Object + GR13, 8, // (687) GPIO13 Rework for Sawtooth Peak + SPST, 8, // (688) SATA port state, Bit0 - Port0, Bit1 - Port1, Bit2 - Port2, Bit3 - Port3 + ECLP, 8, // (689) EC Low Power Mode: 1 - Enabled, 0 - Disabled + INSC, 8, // (690) Intel RMT Configuration + } + +#if defined(ASL_Remove_SaSsdt_Data_To_Dsdt) && (ASL_Remove_SaSsdt_Data_To_Dsdt == 1) +/// +/// Below Data structure is copy from SaSsdt.asl +/// + OperationRegion(SANV,SystemMemory,0xFFFF0000,0xAA55) + Field(SANV,AnyAcc,Lock,Preserve) + { + SARV, 32, /// (000) SA RC Revision + ASLB, 32, /// (004) IGD OpRegion base address + IMON, 8, /// (008) IMON Current Value + IGDS, 8, /// (009) IGD State (Primary Display = 1) + CADL, 8, /// (010) Current Attached Device List + PADL, 8, /// (011) Previous Attached Device List + CSTE, 16, /// (012) Current Display State + NSTE, 16, /// (014) Next Display State + DID9, 32, /// (016) Device Id 9 + DIDA, 32, /// (020) Device Id 10 + DIDB, 32, /// (024) Device Id 11 + IBTT, 8, /// (028) IGD Boot Display Device + IPAT, 8, /// (029) IGD Panel Type CMOs option + IPSC, 8, /// (030) IGD Panel Scaling + IBLC, 8, /// (031) IGD BLC Configuration + IBIA, 8, /// (032) IGD BIA Configuration + ISSC, 8, /// (033) IGD SSC Configuration + IPCF, 8, /// (034) IGD Power Conservation Feature Flag + IDMS, 8, /// (035) IGD DVMT Memory Size + IF1E, 8, /// (036) IGD Function 1 Enable + HVCO, 8, /// (037) HPLL VCO + NXD1, 32, /// (038) Next state DID1 for _DGS + NXD2, 32, /// (042) Next state DID2 for _DGS + NXD3, 32, /// (046) Next state DID3 for _DGS + NXD4, 32, /// (050) Next state DID4 for _DGS + NXD5, 32, /// (054) Next state DID5 for _DGS + NXD6, 32, /// (058) Next state DID6 for _DGS + NXD7, 32, /// (062) Next state DID7 for _DGS + NXD8, 32, /// (066) Next state DID8 for _DGS + GSMI, 8, /// (070) GMCH SMI/SCI mode (0=SCI) + PAVP, 8, /// (071) IGD PAVP data + LIDS, 8, /// (072) Lid State (Lid Open = 1) + KSV0, 32, /// (073) First four bytes of AKSV (mannufacturing mode) + KSV1, 8, /// (077) Fifth byte of AKSV (mannufacturing mode) + BBAR, 32, /// (078) IGFX Audio (D3F0) MMIO BAR Address + BLCS, 8, /// (082) Backlight Control Support + BRTL, 8, /// (083) Brightness Level Percentage + ALSE, 8, /// (084) ALS Enable + ALAF, 8, /// (085) Ambient Light Adjusment Factor + LLOW, 8, /// (086) LUX Low Value + LHIH, 8, /// (087) LUX High Value + ALFP, 8, /// (088) Active LFP + AUDA, 32, /// (089) Audio MMIO WA 1 + AUDB, 32, /// (093) Audio MMIO WA 2 + AUDC, 32, /// (097) Audio MMIO WA 3 + DIDC, 32, /// (101) Device Id 12 + DIDD, 32, /// (105) Device Id 13 + DIDE, 32, /// (109) Device Id 14 + DIDF, 32, /// (113) Device Id 15 +//AMI_OVERRIDE --- Change name from CADR to CCSA to fix that the system has BsOD issue. It is due to the name(CADR) is conflict with AMI Aptio definition name. >> + CCSA, 32, /// (117) Codec Save Address + CCNT, 32, /// (121) Codec Save Count +//CADR, 32, /// (117) Codec Save Address +//CCNT, 8, /// (121) Codec Save Count +//AMI_OVERRIDE --- << + /// + /// Switchable Graphics Info + /// + Offset(200), + SGMD, 8, /// (200) SG Mode (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=DGPU Only) + SGFL, 8, /// (201) SG Feature List + PWOK, 8, /// (202) dGPU PWROK GPIO assigned + HLRS, 8, /// (203) dGPU HLD RST GPIO assigned + PWEN, 8, /// (204) dGPU PWR Enable GPIO assigned + PRST, 8, /// (205) dGPU Present Detect GPIO assigned + CPSP, 32, /// (206) PEG Endpoint Capability Structure Presence (Bit 0: Virtual Channel Capability) + EECP, 8, /// (210) PEG Endpoint PCIe Capability Structure Offset + EVCP, 16, /// (211) PEG Endpoint Virtual Channel Capability Structure Offset + XBAS, 32, /// (213) Any Device's PCIe Config Space Base Address + GBAS, 16, /// (217) GPIO Base Address + SGGP, 8, /// (219) SG GPIO Support + NVGA, 32, /// (220) NVIG opregion address + NVHA, 32, /// (224) NVHM opregion address + AMDA, 32, /// (228) AMDA opregion address + NDID, 8, /// (232) Number of Valid Device IDs + DID1, 32, /// (233) Device ID 1 + DID2, 32, /// (237) Device ID 2 + DID3, 32, /// (241) Device ID 3 + DID4, 32, /// (245) Device ID 4 + DID5, 32, /// (249) Device ID 5 + DID6, 32, /// (253) Device ID 6 + DID7, 32, /// (257) Device ID 7 + DID8, 32, /// (261) Device ID 8 + OBS1, 32, /// (265) Occupied Buses - from 0 to 31 + OBS2, 32, /// (269) Occupied Buses - from 32 to 63 + OBS3, 32, /// (273) Occupied Buses - from 64 to 95 + OBS4, 32, /// (277) Occupied Buses - from 96 to 127 + OBS5, 32, /// (281) Occupied Buses - from 128 to 159 + OBS6, 32, /// (285) Occupied Buses - from 160 to 191 + OBS7, 32, /// (289) Occupied Buses - from 192 to 223 + OBS8, 32, /// (293) Occupied Buses - from 224 to 255 + LTRA, 8, /// (297) Latency Tolerance Reporting Enable + OBFA, 8, /// (298) Optimized Buffer Flush and Fill + LTRB, 8, /// (299) Latency Tolerance Reporting Enable + OBFB, 8, /// (300) Optimized Buffer Flush and Fill + LTRC, 8, /// (301) Latency Tolerance Reporting Enable + OBFC, 8, /// (302) Optimized Buffer Flush and Fill + SMSL, 16, /// (303) SA Peg Latency Tolerance Reporting Max Snoop Latency + SNSL, 16, /// (305) SA Peg Latency Tolerance Reporting Max No Snoop Latency + P0UB, 8, /// (307) Peg0 Unused Bundle Control + P1UB, 8, /// (308) Peg1 Unused Bundle Control + P2UB, 8, /// (309) Peg2 Unused Bundle Control + EDPV, 8, /// (310) Check for eDP display device + NXDX, 32, /// (311) Next state DID for eDP + DIDX, 32, /// (315) Device ID for eDP device + PCSL, 8, /// (319) The lowest C-state for the package + SC7A, 8, /// (316) Run-time C7 Allowed feature (0=Disabled, 1=Enabled) +// AMI_OVERRIDE... + DSEL, 8, /// (319) dGPU Display Select GPIO assigned + ESEL, 8, /// (320) dGPU EDID Select GPIO assigned + PSEL, 8, /// (321) dGPU PWM Select GPIO assigned + MXD1, 32, /// (322) DID1 Mux Setting + MXD2, 32, /// (326) DID2 Mux Setting + MXD3, 32, /// (330) DID3 Mux Setting + MXD4, 32, /// (334) DID4 Mux Setting + MXD5, 32, /// (338) DID5 Mux Setting + MXD6, 32, /// (342) DID6 Mux Setting + MXD7, 32, /// (346) DID7 Mux Setting + MXD8, 32, /// (350) DID8 Mux Setting + PXFD, 8, /// (354) ATI 5.0 Fixed/Dynamic ATI 5.0 Fixed/Dynamic + EBAS, 32, /// (355) Endpoint PCIe Base Address + HYSS, 32, /// (359) dGPU SSID for MSHyBrid restore +// AMI_OVERRIDE...end. + } +#endif diff --git a/ReferenceCode/AcpiTables/Dsdt/Gpe.asl b/ReferenceCode/AcpiTables/Dsdt/Gpe.asl new file mode 100644 index 0000000..5a0b222 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Gpe.asl @@ -0,0 +1,947 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + // General Purpose Events. This Scope handles the Run-time and + // Wake-time SCIs. The specific method called will be determined by + // the _Lxx value, where xx equals the bit location in the General + // Purpose Event register(s). + + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue >> + //External(D1F0) + //External(D1F1) + //External(D1F2) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue << +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) + External(\_SB.PCI0.PEG0.HPME, MethodObj) + External(\_SB.PCI0.PEG1.HPME, MethodObj) + External(\_SB.PCI0.PEG2.HPME, MethodObj) +#endif + + Scope(\_GPE) + { + // Note: + // Originally, the two GPE methods below are automatically generated, but, for ASL code restructuring, + // disabled the automatic generation and declare the ASL code here. + // + +#if 0 //AMI_OVERRIDE --- PciTree.asl has this Gpe event. >> + Method(XL0B, 0) { + Notify(\_SB.PCI0.P0P1, 0x02) + } +#endif //AMI_OVERRIDE --- PciTree.asl has this Gpe event. << + + + // + // This PME event (PCH's GPE #9) is received on one or more of the PCI Express* ports or + // an assert PMEGPE message received via DMI + // + Method(XL09, 0) { + // + // If the Root Port is enabled, run PCI_EXP_STS handler + // +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + If(LAnd(LEqual(RP1D,0), LEqual(\_SB.PCI0.RP01.RPAV,1))) + { + \_SB.PCI0.RP01.HPME() + Notify(\_SB.PCI0.RP01, 0x02) + } +#endif // ASL_RC_PORT_0 + +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + If(LAnd(LEqual(RP2D,0), LEqual(\_SB.PCI0.RP02.RPAV,1))) + { + \_SB.PCI0.RP02.HPME() + Notify(\_SB.PCI0.RP02, 0x02) + } +#endif // ASL_RC_PORT_1 + +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + If(LAnd(LEqual(RP3D,0), LEqual(\_SB.PCI0.RP03.RPAV,1))) + { + \_SB.PCI0.RP03.HPME() + Notify(\_SB.PCI0.RP03, 0x02) + } +#endif // ASL_RC_PORT_2 + +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + If(LAnd(LEqual(RP4D,0), LEqual(\_SB.PCI0.RP04.RPAV,1))) + { + \_SB.PCI0.RP04.HPME() + Notify(\_SB.PCI0.RP04, 0x02) + } +#endif // ASL_RC_PORT_3 + +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + If(LAnd(LEqual(RP5D,0), LEqual(\_SB.PCI0.RP05.RPAV,1))) + { + \_SB.PCI0.RP05.HPME() + Notify(\_SB.PCI0.RP05, 0x02) + } +#endif // ASL_RC_PORT_4 + +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + If(LAnd(LEqual(RP6D,0), LEqual(\_SB.PCI0.RP06.RPAV,1))) + { + \_SB.PCI0.RP06.HPME() + Notify(\_SB.PCI0.RP06, 0x02) + } +#endif // ASL_RC_PORT_5 + +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + If(LAnd(LEqual(RP7D,0), LEqual(\_SB.PCI0.RP07.RPAV,1))) + { + \_SB.PCI0.RP07.HPME() + Notify(\_SB.PCI0.RP07, 0x02) + } +#endif // ASL_RC_PORT_6 + +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + If(LAnd(LEqual(RP8D,0), LEqual(\_SB.PCI0.RP08.RPAV,1))) + { + \_SB.PCI0.RP08.HPME() + Notify(\_SB.PCI0.RP08, 0x02) + } +#endif // ASL_RC_PORT_7 + +#if defined(ASL_RC_PEG_0) && (ASL_RC_PEG_0 == 1) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue >> + If(LEqual(\_SB.PCI0.D1F0,1)) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue << + { + \_SB.PCI0.PEG0.HPME() + Notify(\_SB.PCI0.PEG0, 0x02) + Notify(\_SB.PCI0.PEG0.PEGP, 0x02) + } +#if defined(ASL_RC_PEG_1) && (ASL_RC_PEG_1 == 1) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue >> + If(LEqual(\_SB.PCI0.D1F1,1)) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue << + { + \_SB.PCI0.PEG1.HPME() + Notify(\_SB.PCI0.PEG1, 0x02) + } +#if defined(ASL_RC_PEG_2) && (ASL_RC_PEG_2 == 1) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue >> + If(LEqual(\_SB.PCI0.D1F2,1)) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue << + { + \_SB.PCI0.PEG2.HPME() + Notify(\_SB.PCI0.PEG2, 0x02) + } +#endif // ASL_RC_PEG_2 +#endif // ASL_RC_PEG_1 +#endif // ASL_RC_PEG_0 + } + + // + // This PME event (PCH's GPE #13) is received when any PCH internal device with PCI Power Management capabilities + // on bus 0 asserts the equivalent of the PME# signal. + // + Method(XL0D, 0) { + If(LAnd(\_SB.PCI0.EHC1.PMEE, \_SB.PCI0.EHC1.PMES)){ + Notify(\_SB.PCI0.EHC1, 0x02) + } + If(LAnd(\_SB.PCI0.EHC2.PMEE, \_SB.PCI0.EHC2.PMES)){ + Notify(\_SB.PCI0.EHC2, 0x02) + } + If(LAnd(\_SB.PCI0.XHC.PMEE, \_SB.PCI0.XHC.PMES)){ + Notify(\_SB.PCI0.XHC, 0x02) + } + ElseIf(LEqual(\_SB.PCI0.XHC.PMEE, 0)) { + Store(1, \_SB.PCI0.XHC.PMES) // Clear PMES Bit because an SCI is occurring when PMEE bit is not set + } + If(LAnd(\_SB.PCI0.HDEF.PMEE, \_SB.PCI0.HDEF.PMES)){ + Notify(\_SB.PCI0.HDEF, 0x02) + } + Notify(\_SB.PCI0.GLAN, 0x02) + } + + // PCI Express Hot-Plug caused the wake event. + + Method(XL01) + { + Add(L01C,1,L01C) // Increment L01 Entry Count. + + P8XH(0,0x01) // Output information to Port 80h. + P8XH(1,L01C) + + + // Check Root Port 1 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + If(LAnd(LEqual(RP1D,0),\_SB.PCI0.RP01.HPSX)) + { + // Delay for 100ms to meet the timing requirements + // of the PCI Express Base Specification, Revision + // 1.0A, Section 6.6 ("...software must wait at + // least 100ms from the end of reset of one or more + // device before it is permitted to issue + // Configuration Requests to those devices"). +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x1)){ + Sleep(100) + } +#else + Sleep(100) +#endif + + If(\_SB.PCI0.RP01.PDCX) + { + // Clear all status bits first. + + Store(1,\_SB.PCI0.RP01.PDCX) + Store(1,\_SB.PCI0.RP01.HPSX) + + // + // PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support + // In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on + // hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is + // disabled on empty slots prior booting to OS. + // + If(LNot(\_SB.PCI0.RP01.PDSX)) { + // The PCI Express slot is empty, so disable L0s on hot unplug + // + Store(0,\_SB.PCI0.RP01.L0SE) + + } + + // Perform proper notification + // to the OS. +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x1)){ + Notify(\_SB.PCI0.RP01,0) + } +#else + Notify(\_SB.PCI0.RP01,0) +#endif + } + Else + { + // False event. Clear Hot-Plug Status + // then exit. + + Store(1,\_SB.PCI0.RP01.HPSX) + } + } +#endif // ASL_RC_PORT_0 + + // Check Root Port 2 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + If(LAnd(LEqual(RP2D,0),\_SB.PCI0.RP02.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x2)){ + Sleep(100) + } +#else + Sleep(100) +#endif + + If(\_SB.PCI0.RP02.PDCX) + { + Store(1,\_SB.PCI0.RP02.PDCX) + Store(1,\_SB.PCI0.RP02.HPSX) + + If(LNot(\_SB.PCI0.RP02.PDSX)) { + Store(0,\_SB.PCI0.RP02.L0SE) + } + +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x2)){ + Notify(\_SB.PCI0.RP02,0) + } +#else + Notify(\_SB.PCI0.RP02,0) +#endif + } + Else + { + Store(1,\_SB.PCI0.RP02.HPSX) + } + } +#endif // ASL_RC_PORT_1 + + // Check Root Port 3 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + If(LAnd(LEqual(RP3D,0),\_SB.PCI0.RP03.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x3)){ + Sleep(100) + } +#else + If(LAnd(LNotEqual(BID, BICO),LNotEqual(BID, BICC))) { + Sleep(100) + } +#endif + + If(\_SB.PCI0.RP03.PDCX) + { + Store(1,\_SB.PCI0.RP03.PDCX) + Store(1,\_SB.PCI0.RP03.HPSX) + + If(LNot(\_SB.PCI0.RP03.PDSX)) { + Store(0,\_SB.PCI0.RP03.L0SE) + } + +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x3)){ + Notify(\_SB.PCI0.RP03,0) + } +#else + If(LAnd(LNotEqual(BID, BICO),LNotEqual(BID, BICC))) { + Notify(\_SB.PCI0.RP03,0) + } +#endif + } + Else + { + Store(1,\_SB.PCI0.RP03.HPSX) + } + } +#endif // ASL_RC_PORT_2 + + // Check Root Port 4 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + If(LAnd(LEqual(RP4D,0),\_SB.PCI0.RP04.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x4)){ + Sleep(100) + } +#else + Sleep(100) +#endif + + If(\_SB.PCI0.RP04.PDCX) + { + Store(1,\_SB.PCI0.RP04.PDCX) + Store(1,\_SB.PCI0.RP04.HPSX) + + If(LNot(\_SB.PCI0.RP04.PDSX)) { + Store(0,\_SB.PCI0.RP04.L0SE) + } + +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x4)){ + Notify(\_SB.PCI0.RP04,0) + } +#else + Notify(\_SB.PCI0.RP04,0) +#endif + } + Else + { + Store(1,\_SB.PCI0.RP04.HPSX) + } + } +#endif // ASL_RC_PORT_3 + + // Check Root Port 5 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + If(LAnd(LEqual(RP5D,0),\_SB.PCI0.RP05.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x5)){ + Sleep(100) + } +#else + If(LAnd(LNotEqual(BID, BICO),LNotEqual(BID, BICC))) { + Sleep(100) + } +#endif + + If(\_SB.PCI0.RP05.PDCX) + { + Store(1,\_SB.PCI0.RP05.PDCX) + Store(1,\_SB.PCI0.RP05.HPSX) + + If(LNot(\_SB.PCI0.RP05.PDSX)) { + Store(0,\_SB.PCI0.RP05.L0SE) + } + +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x5)){ + Notify(\_SB.PCI0.RP05,0) + } +#else + If(LAnd(LNotEqual(BID, BICO),LNotEqual(BID, BICC))) { + Notify(\_SB.PCI0.RP05,0) + } +#endif + } + Else + { + Store(1,\_SB.PCI0.RP05.HPSX) + } + } +#endif // ASL_RC_PORT_4 + + // Check Root Port 6 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + If(LAnd(LEqual(RP6D,0),\_SB.PCI0.RP06.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x6)){ + Sleep(100) + } +#else + Sleep(100) +#endif + + If(\_SB.PCI0.RP06.PDCX) + { + Store(1,\_SB.PCI0.RP06.PDCX) + Store(1,\_SB.PCI0.RP06.HPSX) + + If(LNot(\_SB.PCI0.RP06.PDSX)) { + Store(0,\_SB.PCI0.RP06.L0SE) + } + +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x6)){ + Notify(\_SB.PCI0.RP06,0) + } +#else + Notify(\_SB.PCI0.RP06,0) +#endif + } + Else + { + Store(1,\_SB.PCI0.RP06.HPSX) + } + } +#endif // ASL_RC_PORT_5 + + // Check Root Port 7 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + If(LAnd(LEqual(RP7D,0),\_SB.PCI0.RP07.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x7)){ + Sleep(100) + } +#else + Sleep(100) +#endif + + If(\_SB.PCI0.RP07.PDCX) + { + Store(1,\_SB.PCI0.RP07.PDCX) + Store(1,\_SB.PCI0.RP07.HPSX) + + If(LNot(\_SB.PCI0.RP07.PDSX)) { + Store(0,\_SB.PCI0.RP07.L0SE) + } + + If(LEqual(PFLV,FDTP)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x7)){ + Notify(\_SB.PCI0.RP07,0) + } +#else + Notify(\_SB.PCI0.RP07,0) +#endif + } + Else + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If (LAnd(LNotEqual(\TBRP,0x7), \ECON)) +#else + If (\ECON) +#endif + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DOCK)), 0)) + { // If not docked then it's hot plug + Notify(\_SB.PCI0.RP07,0) + } + } + } + } + Else + { + Store(1,\_SB.PCI0.RP07.HPSX) + } + } +#endif // ASL_RC_PORT_6 + + // Check Root Port 8 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + If(LAnd(LEqual(RP8D,0),\_SB.PCI0.RP08.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x8)){ + Sleep(100) + } +#else + Sleep(100) +#endif + + If(\_SB.PCI0.RP08.PDCX) + { + Store(1,\_SB.PCI0.RP08.PDCX) + Store(1,\_SB.PCI0.RP08.HPSX) + + If(LNot(\_SB.PCI0.RP08.PDSX)) { + Store(0,\_SB.PCI0.RP08.L0SE) + } + + If(LEqual(PFLV,FDTP)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x8)){ + Notify(\_SB.PCI0.RP08,0) + } +#else + Notify(\_SB.PCI0.RP08,0) +#endif + } + Else + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If (LAnd(LNotEqual(\TBRP,0x8), \ECON)) +#else + If (\ECON) +#endif + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DOCK)), 0)) + { // If not docked then it's hot plug + Notify(\_SB.PCI0.RP08,0) + } + } + } + } + Else + { + Store(1,\_SB.PCI0.RP08.HPSX) + } + } +#endif // ASL_RC_PORT_7 + } + + // + // Software GPE caused the event. + // + Method(XL02) + { + // Clear GPE status bit. + Store(0,GPEC) + + // + // Handle DTS Thermal Events. + // + External(DTSE, IntObj) + If(CondRefOf(DTSE)){ + If(LGreaterEqual(DTSE, 0x01)){ + Notify(\_TZ.TZ00,0x80) + Notify(\_TZ.TZ01,0x80) + } + } + // + // CPPC Begin + // + // If GPE was asserted on doorbell ring, notify CPPC driver. If GPE was asserted by CPPC to signal + // command completion, clear internal flag. This method is required for CPPC driver to function. + // + External(\_SB.PCCD.PENB, IntObj) + If(CondRefOf(\_SB.PCCD.PENB)){ + If(LEqual(\_SB.PCCD.PENB, 1)) // If CPPC is enabled in BIOS setup, then process command. + { + Notify(\_SB.PCCD, 0x80) + } + } + // + // CPPC End + // + } + + // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC). + Method(XL06) + { + If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI event? + { + \_SB.PCI0.GFX0.GSCI() // Handle the SWSCI + } + } + + // SMBus Alert caused the wake event + Method(XL07) + { + Store(0x20,\_SB.PCI0.SBUS.HSTS) + } + +#if 0 //AMI_OVERRIDE --- It is for CRB SIO using,OEM doesn't need to it. >> + // RI# caused the wake event (COMA). + + Method(XL08) + { + Notify(\_SB.PCI0.LPCB.SM17.UAR1,0x02) + } +#endif //AMI_OVERRIDE --- It is for CRB SIO using,OEM doesn't need to it. << + +#if define ASL_CRB_EC_SUPPORT && ASL_CRB_EC_SUPPORT = 1 //AMI_OVERRIDE + // + // GPI014 = EC WAKETIME SCI + // + Method(XL1E) + { + // Do nothing if Desktop platform + If (LEqual(\ECON,0)) + { + Return () + } + + // If the wake event is not a Virtual Lid or Battery, then + // it must be a Wake from either the Keyboard or Mouse. A + // Power Button Event will be sent for both events such + // that the video turns back on for these "attended wake" + // events. + + // Check for Virtual Lid Event. + + If(LNotEqual(LIDS,\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.LSTE)))) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.LSTE)),LIDS) + + If(IGDS) + { + // Upon waking a lid event may fail if driver is not ready. + // If it does, set the high bit of the variable to indicate that + // another notification is required during system callbacks. + If(\_SB.PCI0.GFX0.GLID(LIDS)) + { + Or(0x80000000,\_SB.PCI0.GFX0.CLID, \_SB.PCI0.GFX0.CLID) + } + } + Notify(\_SB.LID0,0x80) + } + Else + { + // Check for Virtual Power Event. + + If(LEqual(BNUM,0)) + { + If(LNotEqual(PWRS,\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.VPWR)))) + { + // Update NVS Power State. + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.VPWR)),PWRS) + + // Perform needed ACPI Notifications. + PNOT() + } + } + + // Make it an attended wake event, no matter what. + Notify(\_SB.PWRB,0x02) + } + Return () + } +#endif //AMI_OVERRIDE + +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> + // + //OS up handshake procedure to host router upstream port each time + //exiting from Sx State .Avoids intermediate + //PCIe Scan by OS during resorce allocation + // + Method(OSUP, 1) + { + Add(Arg0, 0x548, Local0) + OperationRegion(PXVD,SystemMemory,Local0,0x08) + Field(PXVD,DWordAcc, NoLock, Preserve) + { + TB2P, 32, + P2TB, 32 + } + + Store(100, Local1) + Store(0x0D, P2TB) // Write OS_Up to PCIe2TBT + While(LGreater(Local1, 0)) + { + Store(Subtract(Local1, 1), Local1) + Store(TB2P, Local2) + If(LEqual(Local2, 0xFFFFFFFF))// Device gone + { + Return(2) + } + If(And(Local2, 1)) // Done + { + break + } + Sleep(50) + } + Store(0x00, P2TB) // Write 0 to PCIe2TBT + Return(1) + } + + Method(MMTB) + { + ADBG("MMTB") + Store(PEBS, Local0) // MMIO Base address + + Add(Local0, 0xE0000, Local0) // RP01 + Subtract(ToInteger(TBSE), 1, Local1) + Multiply(Local1, 0x1000, Local1) + Add(Local0, Local1, Local0) // RP0x + + OperationRegion (MMMM, SystemMemory, Local0, 0x1A) + Field (MMMM, AnyAcc, NoLock, Preserve) + { + Offset(0x19), + SBUS, 8 + } + Store(SBUS, Local2) + Store(PEBS, Local0) + Multiply(Local2, 0x100000, Local2) + Add(Local2, Local0, Local0) // TBT HR US port + Return(Local0) + } + + // + //OS up handshake Method ,invokes OSUP based on + //Vendor/Device ID Check + // + Method(OSUW) + { + ADBG("OSUW") + Store(MMTB(), Local0) + OperationRegion(PXVD,SystemMemory,Local0,0x4) + Field(PXVD,DWordAcc, NoLock, Preserve) + { + VEDI, 32 // Vendor/Device ID + } + Store(VEDI, Local1) + + If(LNotEqual(Local1, 0xFFFFFFFF)) + { + Return (OSUP(Local0)) + } + Else + { + Return (0) + } + } + + Method(TBFF)// Check for FFFF in TBT + { + ADBG("TBFF") + Store(MMTB(), Local0) + OperationRegion(PXVD,SystemMemory,Local0,0x4) + Field(PXVD,DWordAcc, NoLock, Preserve) + { + VEDI, 32 // Vendor/Device ID + } + Store(VEDI, Local1) + + If(LEqual(Local1, 0xFFFFFFFF)) + { + Return (OSUP(Local0)) + } + Else + { + Return (0) + } + } + + // Subordinate bus of TBT RP + Method(TSUB) + { + Store(PEBS, Local0) // MMIO Base address + + Add(Local0, 0xE0000, Local0) // RP01 + Subtract(ToInteger(TBSE), 1, Local1) + Multiply(Local1, 0x1000, Local1) + Add(Local0, Local1, Local0) // RP0x + + OperationRegion (MMMM, SystemMemory, Local0, 0x1A) + Field (MMMM, AnyAcc, NoLock, Preserve) + { + Offset(0x19), + SBUS, 8 + } + Return(SBUS) + } + + // Wait for subordinate bus in TBT RP + Method(WSUB) + { + Store(0, Local0) + Store(0, Local1) + While(1) + { + Store(TSUB(), Local1) + If(Local1) + { + Break + } + Else + { + Add(Local0, 1, Local0) + If(LGreater(Local0, 1000)) + { + Sleep(1000) + ADBG("WSUB Deadlock") + } + Else + { + Sleep(16) + } + } + } + } + + // Wait for _WAK finished + Method(WWAK) + { + Store(0, Local0) + Store(0, Local1) + While(1) + { + Acquire(WFDM, 0xFFFF) + Store(WKFN, Local0) + Release(WFDM) + + If(Local0) + { + Break + } + Else + { + Add(Local1, 1, Local1) + If(LGreater(Local1, 1000)) + { + Sleep(1000) + ADBG("WWAK Deadlock") + } + Else + { + Sleep(16) + } + } + } + Return(Local1) + } + // + // Method to Handle enumerate PCIe structure through + // SMI for Thunderbolt devices + // + Method(_E2A) + { + + WWAK() + WSUB() + OperationRegion(SPRT,SystemIO, 0xB2,2) + Field (SPRT, ByteAcc, Lock, Preserve) + { + SSMP, 8 + } + + ADBG("_E2A") + Acquire(OSUM, 0xFFFF) + Store(TBFF(), Local0) + If(LEqual(Local0, 1))// Only HR + { + Sleep(16) + Release(OSUM) + Return () + } + If(LEqual(Local0, 2)) // Disconnect + { + If(NOHP) + { + ADBG("_E2A Ntfy") + If(LEqual(TBSE, 5)) + { + Notify(\_SB.PCI0.RP05,0) + } + If(LEqual(TBSE, 3)) + { + Notify(\_SB.PCI0.RP03,0) + } + } + Sleep(16) + Release(OSUM) + Return () + } + + // HR and EP + If(LEqual(SOHP, 1)) + { + // Trigger SMI to enumerate PCIe Structure + ADBG("_E2A SMI") + Store(21, TBSF) + Store(0xF7, SSMP) + } + If(LEqual(NOHP, 1)) + { + //Notify Rootports + ADBG("_E2A Ntfy") + If(LEqual(TBSE, 5)) + { + Notify(\_SB.PCI0.RP05,0) + } + If(LEqual(TBSE, 3)) + { + Notify(\_SB.PCI0.RP03,0) + } + } + Sleep(16) + Release(OSUM) + } +#endif //AMI_OVERRIDE --- it is for Thunderbolt, AMI thunderbolt module has taken care it already. << + + +// For Reed Harbor only: Rotation Lock button is connected to GPI00. +#if define ASL_RHT_BOARD && ASL_RHT_BOARD = 1 //AMI_OVERRIDE + Method(_L00) + { + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + ADBG("Rotation Lock") + Sleep(1000) + \_SB.PCI0.GFX0.IUEH(4) // Rotation lock + } + } +#endif //AMI_OVERRIDE + +} diff --git a/ReferenceCode/AcpiTables/Dsdt/H8S2113_SIO.ASL b/ReferenceCode/AcpiTables/Dsdt/H8S2113_SIO.ASL new file mode 100644 index 0000000..e3bbd80 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/H8S2113_SIO.ASL @@ -0,0 +1,134 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ +Device(H8S2) +{ + Name(_HID,EISAID("PNP0A05")) + + Name(_UID, 5) + + Method(_STA,0,Serialized) + { + If(LEqual(PFLV,FMBL)) + { + Return(0x000F) + } + + Return(0x0000) + } + + Device(UAR9) // Serial Port UART 9 + { + Name(_HID, EISAID("PNP0501")) + + Name(_UID, 1) + + // + // Status Method for UART 9. + // + Method(_STA, 0, Serialized) + { + If(LAnd(LEqual(PFLV,FMBL), LNotEqual(BID, BHB))) + { + Return(0x000F) + } + + Return(0x0000) + } + + // + // Disable Method for UART 9. + // + // + // Current Resource Setting Method for UART 9. + // + Method(_CRS, 0, Serialized) + { + // + // Create the Buffer that stores the resources to be returned. + // + Name(BUF0, ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags(){4} + }) + + // + // TO-DO: Need to implement the code updating BUF0 (I/O 0x3F8~0x3FF and IRQ 4 are the default setting) + // according to the real resources assigned when the EC commands are available. + // + + Return(BUF0) + } + + + // + // Set Resource Setting Method for UART 9. + // + Method(_SRS,1,Serialized) + { + CreateByteField(Arg0, 0x02, IOLO) + CreateByteField(Arg0, 0x03, IOHI) + CreateWordField(Arg0, 0x09, IRQW) + + If(LEqual(IOHI, 0x03)) + { + If(LEqual(IOLO, 0xF8)) + { + If(LEqual(IRQW, 4)) + { + Store(1, HSCS) + } + } + } + + // + // TO-DO: Need to implement the code setting the resources based on the arguments when the EC commands are available. + // + } + + // + // D0 Method for COM Port. + // + Method(_PS0,0,Serialized) + { + // + // TO-DO: Need to implement the code put the device on D0 state when the EC commands are available. + // + } + + // + // D3 Method for COM Port. + // + Method(_PS3,0,Serialized) + { + // + // TO-DO: Need to implement the code putting the device on D3 state when the EC commands are available. + // + } + } +} + +
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Dsdt/LPC_DEV.ASL b/ReferenceCode/AcpiTables/Dsdt/LPC_DEV.ASL new file mode 100644 index 0000000..6908a3e --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/LPC_DEV.ASL @@ -0,0 +1,302 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + +Device(DMAC) // DMA Controller +{ + Name(_HID,EISAID("PNP0200")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x00,0x00,0x01,0x20) + IO(Decode16,0x81,0x81,0x01,0x11) + IO(Decode16,0x93,0x93,0x01,0x0D) + IO(Decode16,0xC0,0xC0,0x01,0x20) + DMA(Compatibility,NotBusMaster,Transfer8_16) {4} + }) +} + +Device(FWHD) // Firmware Hub Device +{ + Name(_HID,EISAID("INT0800")) + + Name(_CRS,ResourceTemplate() + { + Memory32Fixed(ReadOnly,0xFF000000,0x1000000) + }) +} + + +Device(HPET) // High Performance Event Timer +{ + Name(_HID,EISAID("PNP0103")) + Name(_UID, 0) + + Name(BUF0,ResourceTemplate() + { + Memory32Fixed(ReadWrite,0xFED00000,0x400,FED0) + }) + + Method(_STA,0) + { + // Show this Device only if the OS is WINXP or beyond. + + If(LGreaterEqual(OSYS,2001)) + { + If(HPAE) + { + Return(0x000F) // Enabled, do Display. + } + } + Else + { + // OS = WIN98, WINME, or WIN2000. + + If(HPAE) + { + Return(0x000B) // Enabled, don't Display. + } + } + + Return(0x0000) // Return Nothing. + } + + Method(_CRS,0,Serialized) + { + If(HPAE) + { + // Check if HPETimer Base should be modified. + + CreateDwordField(BUF0,^FED0._BAS,HPT0) + + If(LEqual(HPAS,1)) + { + Store(0xFED01000,HPT0) + } + + If(LEqual(HPAS,2)) + { + Store(0xFED02000,HPT0) + } + + If(LEqual(HPAS,3)) + { + Store(0xFED03000,HPT0) + } + } + + Return(BUF0) + } +} + +Device(IPIC) // 8259 PIC +{ + Name(_HID,EISAID("PNP0000")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x20,0x20,0x01,0x02) + IO(Decode16,0x24,0x24,0x01,0x02) + IO(Decode16,0x28,0x28,0x01,0x02) + IO(Decode16,0x2C,0x2C,0x01,0x02) + IO(Decode16,0x30,0x30,0x01,0x02) + IO(Decode16,0x34,0x34,0x01,0x02) + IO(Decode16,0x38,0x38,0x01,0x02) + IO(Decode16,0x3C,0x3C,0x01,0x02) + IO(Decode16,0xA0,0xA0,0x01,0x02) + IO(Decode16,0xA4,0xA4,0x01,0x02) + IO(Decode16,0xA8,0xA8,0x01,0x02) + IO(Decode16,0xAC,0xAC,0x01,0x02) + IO(Decode16,0xB0,0xB0,0x01,0x02) + IO(Decode16,0xB4,0xB4,0x01,0x02) + IO(Decode16,0xB8,0xB8,0x01,0x02) + IO(Decode16,0xBC,0xBC,0x01,0x02) + IO(Decode16,0x4D0,0x4D0,0x01,0x02) + IRQNoFlags() {2} + }) +} + +#ifdef TRAD_FLAG +Device(MATH) // Math Co-Processor +{ + Name(_HID,EISAID("PNP0C04")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0xF0,0xF0,0x01,0x01) + IRQNoFlags() {13} + }) + + // + // Report device present for LPT-H. + // + Method (_STA, 0x0, NotSerialized) + { + // LPT-H Chipset DID start with 0x8xxx while LPT-LP start with 0x9xxx + If(LEqual(And(CDID,0xF000), 0x8000)) { + Return(0x1F) + } else { + Return(0x0) + } + } +} +#endif // TRAD_FLAG + +Device(LDRC) // LPC Device Resource Consumption +{ + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,2) + +#if 0 + Name(_CRS,ResourceTemplate() // This is for Cougar Point + { + IO(Decode16,0x2E,0x2E,0x1,0x02) // SIO Access. + IO(Decode16,0x4E,0x4E,0x1,0x02) // LPC Slot Access. + IO(Decode16,0x61,0x61,0x1,0x1) // NMI Status. + IO(Decode16,0x63,0x63,0x1,0x1) // Processor I/F. + IO(Decode16,0x65,0x65,0x1,0x1) // Processor I/F. + IO(Decode16,0x67,0x67,0x1,0x1) // Processor I/F. + IO(Decode16,0x70,0x70,0x1,0x1) // NMI Enable. + IO(Decode16,0x80,0x80,0x1,0x1) // Port 80h. + IO(Decode16,0x92,0x92,0x1,0x1) // Processor I/F. + IO(Decode16,0xB2,0xB2,0x01,0x02) // Software SMI. + IO(Decode16,0x680,0x680,0x1,0x20) // 32 Byte I/O. + IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // ACPI IO Trap. + IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // DTS IO Trap. + IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // HotKey IO Trap. + + IO(Decode16, 0x800,0x800,0x1,0xFF) // PCH GPIO Base. + IO(Decode16, 0x900,0x900,0x1,0xFF) // PCH GPIO Base. + IO(Decode16, 0xA00,0xA00,0x1,0xFF) // PCH GPIO Base. + IO(Decode16, 0xB00,0xB00,0x1,0xFF) // PCH GPIO Base. + IO(Decode16, 0x1800,0x1800,0x1,0xFF) // PCH ACPI Base + + IO(Decode16,0x164e,0x164e,0x1,0x02) // 16 Byte I/O. + }) +#else + Name(BUF0,ResourceTemplate() // This is for Cougar Point + { + IO(Decode16,0x2E,0x2E,0x1,0x02) // SIO Access. + IO(Decode16,0x4E,0x4E,0x1,0x02) // LPC Slot Access. + IO(Decode16,0x61,0x61,0x1,0x1) // NMI Status. + IO(Decode16,0x63,0x63,0x1,0x1) // Processor I/F. + IO(Decode16,0x65,0x65,0x1,0x1) // Processor I/F. + IO(Decode16,0x67,0x67,0x1,0x1) // Processor I/F. + IO(Decode16,0x70,0x70,0x1,0x1) // NMI Enable. + IO(Decode16,0x80,0x80,0x1,0x1) // Port 80h. + IO(Decode16,0x92,0x92,0x1,0x1) // Processor I/F. + IO(Decode16,0xB2,0xB2,0x01,0x02) // Software SMI. + IO(Decode16,0x680,0x680,0x1,0x20) // 32 Byte I/O. + IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // ACPI IO Trap. + IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // DTS IO Trap. + IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // HotKey IO Trap. + + IO(Decode16, 0x800,0x800,0x1,0xFF, GIO0) // PCH GPIO Base. + IO(Decode16, 0x900,0x900,0x1,0xFF, GIO1) // PCH GPIO Base. + IO(Decode16, 0xA00,0xA00,0x1,0xFF, GIO2) // PCH GPIO Base. + IO(Decode16, 0xB00,0xB00,0x1,0xFF, GIO3) // PCH GPIO Base. + IO(Decode16, 0x1800,0x1800,0x1,0xFF) // PCH ACPI Base + + IO(Decode16,0x164e,0x164e,0x1,0x02) // 16 Byte I/O. + }) + + Method(_CRS,0) + { + CreateWordField(BUF0, ^GIO0._MIN, IO0M) + CreateWordField(BUF0, ^GIO0._MAX, IO0X) + Store(GPBS, IO0M) + Store(GPBS, IO0X) + + CreateWordField(BUF0, ^GIO1._MIN, IO1M) + CreateWordField(BUF0, ^GIO1._MAX, IO1X) + Store(Add(GPBS, 0x100), IO1M) + Store(Add(GPBS, 0x100), IO1X) + + CreateWordField(BUF0, ^GIO2._MIN, IO2M) + CreateWordField(BUF0, ^GIO2._MAX, IO2X) + Store(Add(GPBS, 0x200), IO2M) + Store(Add(GPBS, 0x200), IO2X) + + CreateWordField(BUF0, ^GIO3._MIN, IO3M) + CreateWordField(BUF0, ^GIO3._MAX, IO3X) + Store(Add(GPBS, 0x300), IO3M) + Store(Add(GPBS, 0x300), IO3X) + + Return(BUF0) + } +#endif +} + +Device(RTC) // RTC +{ + Name(_HID,EISAID("PNP0B00")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x70,0x70,0x01,0x08) + IRQNoFlags() {8} + }) +} + +Device(TIMR) // 8254 Timer +{ + Name(_HID,EISAID("PNP0100")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x40,0x40,0x01,0x04) + IO(Decode16,0x50,0x50,0x10,0x04) + IRQNoFlags() {0} + }) +} + +Device(CWDT) +{ + Name(_HID,EISAID("INT3F0D")) + Name(_CID,EISAID("PNP0C02")) + Name(BUF0,ResourceTemplate() + { + IO(Decode16, 0x1854, 0x1854, 0x4, 0x4) // PMBS 0x1800 + Offset 0x54 + } + ) + + Method(_STA,0,Serialized) + { + If(LEqual(WDTE,1)) + { + Return(0x0F) + } + Else + { + Return(0x00) + } + } + + Method(_CRS,0,Serialized) + { + Return(BUF0) + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/LpcB.asl b/ReferenceCode/AcpiTables/Dsdt/LpcB.asl new file mode 100644 index 0000000..647a34d --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/LpcB.asl @@ -0,0 +1,178 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +// LPC Bridge - Device 31, Function 0 +// Define the needed LPC registers used by ASL. + +scope(\_SB){ + OperationRegion(\_SB.PCI0.LPCB.LPC1, PCI_Config, 0x00, 0x100) + Field(\_SB.PCI0.LPCB.LPC1, AnyAcc, NoLock, Preserve) + { + Offset(0x02), + CDID,16, + Offset(0x08), + CRID, 8, + Offset(0x60), + PARC, 8, + PBRC, 8, + PCRC, 8, + PDRC, 8, + Offset(0x68), + PERC, 8, + PFRC, 8, + PGRC, 8, + PHRC, 8, + Offset(0xAC), + , 8, + , 8, + XUSB, 1 + } + + Include ("98_LINK.ASL") +} + OperationRegion(LPC0, PCI_Config, 0x40, 0xC0) + Field(LPC0, AnyAcc, NoLock, Preserve) + { + Offset(0x40), // 0x80h + IOD0, 8, + IOD1, 8, + Offset(0x78), // 0xB8h + , 6, + GR03, 2, + , 8, + GR08, 2, + GR09, 2, + GR0A, 2, + GR0B, 2, + , 8, + Offset(0x7C), // 0xBCh + , 2, + GR19, 2, + , 28, + Offset(0x0B0), // 0xF0h + RAEN, 1, + , 13, + RCBA, 18 + } + +#if 0 //AMI_OVERRIDE --- Include EC.ASL in EC module. >> + Include ("EC.ASL") +#endif //AMI_OVERRIDE --- Include EC.ASL in EC module. << + Include ("LPC_DEV.ASL") +#if 0 //AMI_OVERRIDE --- Using AMI SIO module. >> + Include ("NAT_SIO.ASL") + Include ("SMSC1007_SIO.ASL") + Include ("WPCN381U_SIO.ASL") + Include ("SMSC1000_SIO.ASL") + Include ("H8S2113_SIO.ASL") +#endif //AMI_OVERRIDE --- Using AMI SIO module. << + + // Define the KBC_COMMAND_REG-64, KBC_DATA_REG-60 Registers as an ACPI Operating + // Region. These registers will be used to skip kbd mouse + // resource settings if not present. +#if 0 //AMI_OVERRIDE --- Using AMI ACPI ASL code and SIO module. >> + OperationRegion(PKBS, SystemIO, 0x60, 0x05) + Field(PKBS, ByteAcc, Lock, Preserve) + { + PKBD, 8, + , 8, + , 8, + , 8, + PKBC, 8 + } + Device(PS2K) // PS2 Keyboard + { + Name(_HID,"MSFT0001") + Name(_CID,EISAID("PNP0303")) + + Method(_STA) + { + If(LEqual(BID, BHB)) + { + Return(0x000F) + } + // Only report resources to the OS if the Keyboard is present + If(LOr(And(LEqual(PKBD,0xFF), LEqual(PKBC, 0xFF)), LEqual(BID, BFCC))) + { + Return(0x0000) + } + Return(0x000F) + } + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x60,0x60,0x01,0x01) + IO(Decode16,0x64,0x64,0x01,0x01) + IRQ(Edge,ActiveHigh,Exclusive){0x01} + }) + + Name(_PRS, ResourceTemplate(){ + StartDependentFn(0, 0) { + FixedIO(0x60,0x01) + FixedIO(0x64,0x01) + IRQNoFlags(){1} + } + EndDependentFn() + }) + + } + + Device(PS2M) // PS/2 Mouse + { + Name(_HID,"MSFT0003") + Name(_CID,EISAID("PNP0F03")) + + Method(_STA) + { + If(LOr(LEqual(BID, BHB), LEqual(BID, BFCC))) + { + Return(0x0000) + } + + If (P2ME) + { + Return(0x000F) + } + + Return(0x0000) + } + + Name(_CRS,ResourceTemplate() + { + IRQ(Edge,ActiveHigh,Exclusive){0x0C} + }) + + Name(_PRS, ResourceTemplate(){ + StartDependentFn(0, 0) { + IRQNoFlags(){12} + } + EndDependentFn() + }) + } +#endif //AMI_OVERRIDE --- Using AMI ACPI ASL code and SIO module. << + + diff --git a/ReferenceCode/AcpiTables/Dsdt/NAT_COM.ASL b/ReferenceCode/AcpiTables/Dsdt/NAT_COM.ASL new file mode 100644 index 0000000..6a1b9c5 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/NAT_COM.ASL @@ -0,0 +1,481 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + +Device(UAR3) // Serial Port A +{ + Name(_HID, EISAID("PNP0501")) + + Name(_UID,2) + + // Status Method for COM A. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // not set to Disabled in BIOS Setup. + + If(LAnd(NATP,CMAP)) + { + // Set the SIO to COM A. + + Store(3,R07H) + + // Display COMA and return status. + + If(R30H) + { + Return(0x000F) + } + + Return(0x000D) + } + + Return(0x0000) + } + + // Disable Method for COM A. + + Method(_DIS,0,Serialized) + { + Store(3,R07H) + Store(0,R30H) + } + + // Current Resource Setting Method for COM A. + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags(){4} + }) + + // Set SIO to COM A. + + Store(3,R07H) + + // Skip this sequence if the COMA Port is Disabled + // in BIOS Setup. + + If(LAnd(NATP,CMAP)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Write IO and Length values into the Buffer. + + Store(R60H,IOH0) + Store(R61H,IOL0) + Store(R60H,IOH1) + Store(R61H,IOL1) + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + And(R70H,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for COM A. + + // Build a Buffer with all valid COM Port Resources. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){3,4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){3,4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){3,4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){3,4,5,6,7,10,11,12} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for COM A. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQW) + + // Set the SIO to COM A. + + Store(3,R07H) + + // Disable the device. + + Store(0,R30H) + + // Set the Base IO Address. + + Store(IOLO,R61H) + Store(IOHI,R60H) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If(LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,R70H) + + // Set the Decode Range so COM A works on ICH7 and + // future platforms. + + AND(IOD0,0xF8,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x07,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x01,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x05,IOD0) + } + } + + // Enable the device. + + Store(1,R30H) + } + + // D0 Method for COM Port. + + Method(_PS0,0,Serialized) + { + Store(3,R07H) + Store(1,R30H) + } + + // D3 Method for COM Port. + + Method(_PS3,0,Serialized) + { + Store(3,R07H) + Store(0,R30H) + } +} + +Device(UAR4) // Serial Port B +{ + Name(_HID, EISAID("PNP0501")) + + Name(_UID,3) + + // Status Method for COM B. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // not set to Disabled in BIOS Setup. + + If(LAnd(NATP,CMBP)) + { + // Set the SIO to COM B. + + Store(2,R07H) + + // Display COM B and return status. + + If(R30H) + { + Return(0x000F) + } + + Return(0x000D) + } + + Return(0x0000) + } + + // Disable Method for COM B. + + Method(_DIS,0,Serialized) + { + Store(2,R07H) + Store(0,R30H) + } + + // Current Resource Setting Method for COM B. + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x02F8,0x02F8,0x01,0x08) + IRQNoFlags(){3} + }) + + // Set SIO to COM B. + + Store(2,R07H) + + // Skip this sequence if the COM B Port is Disabled + // in BIOS Setup. + + If(LAnd(NATP,CMBP)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Write IO and Length values into the Buffer. + + Store(R60H,IOH0) + Store(R61H,IOL0) + Store(R60H,IOH1) + Store(R61H,IOL1) + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + And(R70H,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for COM B. + + // Build a Buffer with all valid COM B Port Resources. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for COM B. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQW) + + // Set the SIO to COM B. + + Store(2,R07H) + + // Disable the device. + + Store(0,R30H) + + // Set the Base IO Address. + + Store(IOLO,R61H) + Store(IOHI,R60H) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If(LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,R70H) + + // Set the Decode Range so COM B works on ICH7 and + // future platforms. + + AND(IOD0,0x8F,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x70,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x10,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x50,IOD0) + } + } + + // Enable the device. + + Store(1,R30H) + } + + // D0 Method for COM B Port. + + Method(_PS0,0,Serialized) + { + Store(2,R07H) + Store(1,R30H) + } + + // D3 Method for COM B Port. + + Method(_PS3,0,Serialized) + { + Store(2,R07H) + Store(0,R30H) + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/NAT_LPT.ASL b/ReferenceCode/AcpiTables/Dsdt/NAT_LPT.ASL new file mode 100644 index 0000000..72b2208 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/NAT_LPT.ASL @@ -0,0 +1,942 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + +// This ASL file will support the LPT in Output, BiDirectional, EPP, +// & ECP mode. Only 1 of these devices will be shown by the OS at any +// given time, and that one will depend on the BIOS configuration. + +Device(LPT1) // Printer, Output Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,1) + + // Status Method for LPT-Output Mode. + + Method(_STA,0,Serialized) + { + // Output mode = 000xxxxxb - check that no bits are set. + Store(1,R07H) + If(LEqual(And(RF0H,0xE0),0x00)) + { + // LPT is in Output Mode. Only report resources + // to the OS if the SIO Device is not set to + // Disabled in BIOS Setup. + + If(LAnd(NATP,LPTP)) + { + // Set SIO to LPT. + + + // Display POUT and return Status. + + If(R30H) + { + Return(0x000F) + } + + Return(0x000D) + } + } + + Return(0x0000) + } + + // Disable Method for LPT-Output Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,R07H) + + If(LEqual(And(RF0H,0xE0),0x00)) + { + Store(0,R30H) + } + } + + // Current Resource Setting Method for LPT-Output Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x04) + IRQNoFlags(){7} + }) + + // Skip this sequence if the LPT Device is not set + // to Output Mode. + + If(LEqual(And(RF0H,0xE0),0x00)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,R07H) + + // Write IO and Length values into the Buffer. + + Store(R61H,IOL0) + Store(R60H,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(4,LEN0) + + // Write the IRQ value into the Buffer. + + If(And(R70H,0x0F)) + { + ShiftLeft(One,And(R70H,0x0F),IRQW) + } + Else + { + Store(Zero,IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-Output Mode. + + // Build a Buffer with all valid LPT Port Resources. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){5} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-Output Mode. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,R07H) + + // Disable the LPT. + + Store(0,R30H) + + // Set to Output Mode. + + And(RF0H,0x0F,RF0H) + + // Disable the DMA channels. + + Store(4,R74H) + + // Set the Base IO Address. + + Store(IOL0,R61H) + Store(IOH0,R60H) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,R70H) + + // Set the Decode Range so POUT works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x3xx + { + If(LEqual(IOL0,0x78)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else + { + Or(IOD1,0x02,IOD1) // Address = 0x3BC + } + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,R30H) + } + + // D0 Method for LPT-Output Mode. + + Method(_PS0,0,Serialized) + { + Store(1,R07H) + Store(1,R30H) + } + + // D3 Method for LPT-Output Mode. + + Method(_PS3,0,Serialized) + { + Store(1,R07H) + Store(0,R30H) + } +} + +Device(PBI1) // Printer, BiDirectional Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,2) + + // Status Method for LPT-BiDirectional Mode. + + Method(_STA,0,Serialized) + { + // BiDirectional mode = 001xxxxxb, so check that only + // bit 5 is set. + + Store(1,R07H) + If(LEqual(And(RF0H,0xE0),0x20)) + { + // LPT is in BiDirectional Mode. Only report + // resources to the OS if the SIO Device is not + // set to Disabled in BIOS Setup. + + If(LAnd(NATP,LPTP)) + { + // Display PBID and return Status. + + If(R30H) + { + Return(0x000F) + } + + Return(0x000D) + } + } + + Return(0x0000) + } + + // Disable Method for LPT-BiDirectional Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,R07H) + + If(LEqual(And(RF0H,0xE0),0x20)) + { + Store(0,R30H) + } + } + + // Current Resource Setting Method for LPT-BiDirectional Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x04) + IRQNoFlags(){7} + }) + + // Skip this sequence if the LPT Device is not set + // to BiDirectional Mode. + + If(LEqual(And(RF0H,0xE0),0x20)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,R07H) + + // Write IO and Length values into the Buffer. + + Store(R61H,IOL0) + Store(R60H,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(4,LEN0) + + // Write the IRQ value into the Buffer. + + If(And(R70H,0x0F)) + { + ShiftLeft(One,And(R70H,0x0F),IRQW) + } + Else + { + Store(Zero, IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-BiDirectional Mode. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){5} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-BiDirectional Mode. + + Method(_SRS,1,Serialized) + { + // Arg0 passed into _SRS is the buffer identical to BUF0. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + Store(1,R07H) + + // Disable the LPT. + + Store(0,R30H) + + // Set to Bi-Directional Mode. + + Or(And(RF0H,0x0F),0x20,RF0H) + + // Disable the DMA channels. + + Store(4,R74H) + + // Set the Base IO Address. + + Store(IOL0,R61H) + Store(IOH0,R60H) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,R70H) + + // Set the Decode Range so PBID works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x3xx + { + If(LEqual(IOL0,0x78)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else + { + Or(IOD1,0x02,IOD1) // Address = 0x3BC + } + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,R30H) + } + + // D0 Method for LPT-BiDirectional Mode. + + Method(_PS0,0,Serialized) + { + Store(1,R07H) + Store(1,R30H) + } + + // D3 Method for LPT-BiDirectional Mode. + + Method(_PS3,0,Serialized) + { + Store(1,R07H) + Store(0,R30H) + } +} + +Device(PEP1) // Printer, EPP Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,3) + + // Status Method for LPT-EPP Mode. + + Method(_STA,0,Serialized) + { + // EPP 1.9 mode = 011xxxxxb. + + Store(1,R07H) + If(LOr(LEqual(And(RF0H,0xE0),0x60), LEqual(And(RF0H,0xE0),0x40))) + { + // LPT is in EPP Mode. Only report resources + // to the OS if the SIO Device is not set to + // Disabled in BIOS Setup. + + If(LAnd(NATP,LPTP)) + { + // Display PEPP and return Status. + + If(R30H) + { + Return(0x000F) + } + Else + { + Return(0x000D) + } + } + } + + Return(0x0000) + } + + // Disable Method for LPT-EPP Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,R07H) + + If(LOr(LEqual(And(RF0H,0xE0),0x60), LEqual(And(RF0H,0xE0),0x40))) + { + Store(0,R30H) + } + } + + // Current Resource Setting Method for LPT-EPP Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x08) + IRQNoFlags(){7} + }) + + // Skip this sequence if the LPT Device is not set + // to EPP Mode. + + If(LOr(LEqual(And(RF0H,0xE0),0x60), LEqual(And(RF0H,0xE0),0x40))) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,R07H) + + // Write IO and Length values into the Buffer. + + Store(R61H,IOL0) + Store(R60H,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + If(And(R70H,0x0F)) + { + ShiftLeft(One,And(R70H,0x0F),IRQW) + } + Else + { + Store(Zero, IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-EPP Mode. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IRQNoFlags(){5} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-EPP Mode. + + Method(_SRS,1,Serialized) + { + // Arg0 passed into _SRS is the buffer identical to BUF0. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + Store(1,R07H) + + // Disable the LPT. + + Store(0,R30H) + + // Set to EPP 1.9 Mode. + + Or(And(RF0H,0x0F),0x60,RF0H) + + // Disable the DMA channels. + + Store(4,R74H) + + // Set the Base IO Address. + + Store(IOL0,R61H) + Store(IOH0,R60H) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,R70H) + + // Set the Decode Range so PEPP works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,R30H) + } + + // D0 Method for LPT-EPP Mode. + + Method(_PS0,0,Serialized) + { + Store(1,R07H) + Store(1,R30H) + } + + // D3 Method for LPT-EPP Mode. + + Method(_PS3,0,Serialized) + { + Store(1,R07H) + Store(0,R30H) + } +} + +Device(PEC1) // Printer, ECP Mode +{ + Name(_HID,EISAID("PNP0401")) + Name(_UID,4) + + // Status Method for LPT-ECP Mode. + + Method(_STA,0,Serialized) + { + // ECP mode = 1111xxxxxb. + + Store(1,R07H) + If(LOr(LEqual(And(RF0H,0xE0),0xE0), LEqual(And(RF0H,0xE0),0x80))) + { + // LPT is in ECP Mode. Only report resources + // to the OS if the SIO Device is not set to + // Disabled in BIOS Setup. + + If(LAnd(NATP,LPTP)) + { + // Display PECP and return Status. + + If(R30H) + { + Return(0x000F) + } + Else + { + Return(0x000D) + } + } + } + + Return(0x0000) + } + + // Disable Method for LPT-ECP Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,R07H) + + If(LOr(LEqual(And(RF0H,0xE0),0xE0), LEqual(And(RF0H,0xE0),0x80))) + { + Store(0,R30H) + } + } + + // Current Resource Setting Method for LPT-ECP Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x08) + IO(Decode16,0x0778,0x0778,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16,){1} + }) + + // Skip this sequence if the LPT Device is not set + // to ECP Mode. + + If(LOr(LEqual(And(RF0H,0xE0),0xE0), LEqual(And(RF0H,0xE0),0x80))) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateByteField(BUF0,0x0A,IOL2) + CreateByteField(BUF0,0x0B,IOH2) + CreateByteField(BUF0,0x0C,IOL3) + CreateByteField(BUF0,0x0D,IOH3) + CreateByteField(BUF0,0x0F,LEN1) + CreateWordField(BUF0,0x11,IRQW) + CreateByteField(BUF0,0x14,DMA0) + + // Set SIO to LPT. + + Store(1,R07H) + + // Write IO and Length values into the Buffer. + + Store(R61H,IOL0) + Store(R60H,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(IOL0,IOL2) + Store(Add(0x4,IOH0),IOH2) + Store(IOL0,IOL3) + Store(Add(0x4,IOH0),IOH3) + Store(8,LEN0) + Store(8,LEN1) + + // Write the IRQ value into the Buffer. + + And(R70H,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + + // Write the DMA value into the Buffer. + + Store(R74H,Local0) + If(LEqual(Local0,0x04)) + { + Store(Zero,DMA0) + } + Else + { + ShiftLeft(One,Local0,DMA0) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-ECP Mode. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IO(Decode16,0x778,0x778,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IO(Decode16,0x678,0x678,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16){1,2,3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IO(Decode16,0x778,0x778,0x01,0x08) + IRQNoFlags(){5} + DMA(Compatibility,NotBusMaster,Transfer8_16){1,2,3} + + + + + + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-ECP Mode. + + Method(_SRS,1,Serialized) + { + // Arg0 passed into _SRS is the buffer identical to BUF0. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x11,IRQW) + CreateByteField(Arg0,0x14,DMA0) + + Store(1,R07H) + + // Disable the LPT. + + Store(0,R30H) + + // Set to ECP Mode with EPP Mode 4 support. + + Or(RF0H,0xF0,RF0H) + + // Set the Base I/O Address + + Store(IOL0,R61H) + Store(IOH0,R60H) + + // Set the IRQ + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,R70H) + + // Set the DMA Channel + + FindSetRightBit(DMA0,Local0) + If (LNotEqual(DMA0,Zero)) + { + Decrement(Local0) + } + Store(Local0,R74H) + + // Set the Decode Range so PECP works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,R30H) + } + + // D0 Method for LPT-ECP Mode. + + Method(_PS0,0,Serialized) + { + Store(1,R07H) + Store(1,R30H) + } + + // D3 Method for LPT-ECP Mode. + + Method(_PS3,0,Serialized) + { + Store(1,R07H) + Store(0,R30H) + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/NAT_SIO.ASL b/ReferenceCode/AcpiTables/Dsdt/NAT_SIO.ASL new file mode 100644 index 0000000..a09b4c8 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/NAT_SIO.ASL @@ -0,0 +1,96 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(N393) +{ + Name(_HID,EISAID("PNP0A05")) + + Name(_UID,1) + + // Status Method for the National SIO. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // present on the Docking Board. + + If(NATP) + { + Return(0x000F) + } + + Return(0x0000) + } + + // Define the SIO Index/Data Registers as an ACPI Operating + // Region. These registers will be used communicate to the SIO. + + OperationRegion(N393, SystemIO, 0x02E, 0x02) + Field(N393, ByteAcc, Lock, Preserve) + { + INDX, 8, + DATA, 8 + } + + // Use ACPI Defined IndexField so consecutive Index/Data I/Os are + // assured to be uninterrupted. + + IndexField(INDX, DATA, ByteAcc, Lock, Preserve) + { + Offset(0x07), // Logical Device Number. + R07H, 8, + Offset(0x20), // SIO Configuration and ID. + R20H, 8, + R21H, 8, + R22H, 8, + R23H, 8, + R24H, 8, + R25H, 8, + R26H, 8, + R27H, 8, + R28H, 8, + R29H, 8, + R2AH, 8, + Offset(0x30), // Logical Device Activate. + R30H, 8, + Offset(0x60), // I/O Space Configuration. + R60H, 8, + R61H, 8, + Offset(0x70), // Interrupt Configuration. + R70H, 8, + R71H, 8, + Offset(0x74), // DMA Configuration. + R74H, 8, + R75H, 8, + Offset(0xF0), // Special Logical Device Configuration. + RF0H, 8, + RF1H, 8 + } + + Include ("NAT_COM.ASL") + Include ("NAT_LPT.ASL") +} diff --git a/ReferenceCode/AcpiTables/Dsdt/Nfc.asl b/ReferenceCode/AcpiTables/Dsdt/Nfc.asl new file mode 100644 index 0000000..c828ac7 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Nfc.asl @@ -0,0 +1,93 @@ + /**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Ivy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + +// +// NFC modules definitions. +// + +scope (\) +{ + // + // Magnetics Peak NFC module + // + Device(NFC1) + { + Name(_HID, EISAID("SKTD000")) + + Method(_STA) + { + If(LEqual(NFCE, 3)) + { + Return(0x0F) // NFC enabled, show it + } + Else + { + Return(0x00) // NFC disabled, hide it + } + } + } + + // + // NXP NFC module + // + Device(NFC2) + { + Name(_HID, EISAID("NXP5442")) + + Method(_STA) + { + If(LEqual(NFCE, 2)) + { + Return(0x0F) // NFC enabled, show it + } + Else + { + Return(0x00) // NFC disabled, hide it + } + } + } + + // + // Magnetics Peak 2 NFC module + // + Device(NFC3) + { + Name(_HID, EISAID("ICV0A12")) + + Method(_STA) + { + If(LEqual(NFCE, 1)) + { + Return(0x0F) // NFC enabled, show it + } + Else + { + Return(0x00) // NFC disabled, hide it + } + } + } +} + diff --git a/ReferenceCode/AcpiTables/Dsdt/PCIEDOCK.ASL b/ReferenceCode/AcpiTables/Dsdt/PCIEDOCK.ASL new file mode 100644 index 0000000..6c2c18b --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/PCIEDOCK.ASL @@ -0,0 +1,89 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device (\_SB.PCI0.DOCK) +{ + + Name(_HID, "ABCD0000") + Name(_CID, EISAID("PNP0C15")) + Name(_UID,"SADDLESTRING") + + Method(_EJ0, 1) { + P8XH(0,0xED) + If(LEqual(ECON,1)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(1, RefOf(\_SB.PCI0.LPCB.H_EC.EJET)) + } + Return () + } + + Method(_STA, 0) { + If(LEqual(ECON,0)) + { + Return(0x0) + } + If(LEqual(S0ID,1)) + { + Return(0x0) + } + if(\DSTS) { + P8XH(1,0x13) + P8XH(0,0x13) + Return(0x0F) + } else { + P8XH(1,0x14) + P8XH(0,0x14) + Return(0x0) + } + } + + Method(_DCK, 1) { + P8XH(0,0xD3) + + If (Arg0) { + Return (1) + } + Else { + Store(0, \DSTS) + If(LEqual(ECON,1)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.EJET)) + } + Return (1) + } + } + + + Name(_EDL, Package( ) { // DOCK1 has several dependent devices + \_SB.PCI0.RP07.PXSX, + \_SB.PCI0.RP08.PXSX, + \_SB.PCI0.EHC1, + \_SB.PCI0.SAT0, + \_SB.PCI0.HDEF, + }) + +} diff --git a/ReferenceCode/AcpiTables/Dsdt/PCI_DRC.ASL b/ReferenceCode/AcpiTables/Dsdt/PCI_DRC.ASL new file mode 100644 index 0000000..a461e59 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/PCI_DRC.ASL @@ -0,0 +1,138 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Scope (\_SB.PCI0){ + + Device(PDRC) + { + // + // PCI Device Resource Consumption + // + + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,1) + + Name(BUF0,ResourceTemplate() + { + // + // RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0 + // + Memory32Fixed(ReadWrite,0,0x04000,RCRB) + // + // MCH BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.48h + // + Memory32Fixed(ReadWrite,0,0x08000,MCHB) + // + // DMI BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.68h + // + Memory32Fixed(ReadWrite,0,0x01000,DMIB) + // + // EP BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.40h + // + Memory32Fixed(ReadWrite,0,0x01000,EGPB) + // + // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h + // + Memory32Fixed(ReadWrite,0,0,PCIX) + + // + // MISC ICH TTT base address reserved for the TxT module use. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed(ReadWrite,0xFED20000,0x20000) + + // + // VTD engine memory range. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed(ReadOnly, 0xFED90000, 0x00004000) + + // + // MISC ICH. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed(ReadWrite,0xFED45000,0x4B000,TPMM) + + // + // FLASH range + // + Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) //16MB as per IOH spec + + // + // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) + // + Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) + + // + // Thermal Base Address. TBAR _BAS and _LEN will be updated in _CRS below according to B0:D31:F6:Reg.40h + // + Memory32Fixed (ReadWrite, 0, 0x01000, TBAR) + + // + // S3 Save And Restore temporay memory bar + // + Memory32Fixed (ReadWrite, 0, 0x10000, SNRB) + + }) + + + Method(_CRS,0,Serialized) + { + CreateDwordField(BUF0,^RCRB._BAS,RBR0) + ShiftLeft(\_SB.PCI0.LPCB.RCBA,14,RBR0) + + CreateDwordField(BUF0,^TBAR._BAS,TBR0) + Store(TBAB,TBR0) + CreateDwordField(BUF0,^TBAR._LEN,TBLN) + If(LEqual(TBAB,0)){ + Store(0,TBLN) + } + + CreateDwordField(BUF0,^SNRB._BAS,SNR0) + Store(\SRMB,SNR0) // SRMB is defined in PCH.asl + + + CreateDwordField(BUF0,^MCHB._BAS,MBR0) + ShiftLeft(\_SB.PCI0.MHBR,15,MBR0) + + CreateDwordField(BUF0,^DMIB._BAS,DBR0) + ShiftLeft(\_SB.PCI0.DIBR,12,DBR0) + + CreateDwordField(BUF0,^EGPB._BAS,EBR0) + ShiftLeft(\_SB.PCI0.EPBR,12,EBR0) + + CreateDwordField(BUF0,^PCIX._BAS,XBR0) + ShiftLeft(\_SB.PCI0.PXBR,26,XBR0) + + CreateDwordField(BUF0,^PCIX._LEN,XSZ0) + ShiftRight(0x10000000, \_SB.PCI0.PXSZ,XSZ0) + + Return(BUF0) + } + } //end of PDRC +} // end of SB diff --git a/ReferenceCode/AcpiTables/Dsdt/Platform.asl b/ReferenceCode/AcpiTables/Dsdt/Platform.asl new file mode 100644 index 0000000..401f94a --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Platform.asl @@ -0,0 +1,1880 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +// Define the following External variables to prevent a WARNING when +// using ASL.EXE and an ERROR when using IASL.EXE. + +External(PDC0) +External(PDC1) +External(PDC2) +External(PDC3) +External(PDC4) +External(PDC5) +External(PDC6) +External(PDC7) +External(\_PR.CFGD) + +External(\_SB.IAOE.PTSL) +External(\_SB.IAOE.ECTM) +External(\_SB.IAOE.RCTM) +External(\_SB.IAOE.ITMR) +External(\_SB.IAOE.FFSE) +External(\_SB.IFFS.FFSS) +External(\_SB.IAOE.PCIS) + +External(\_SB.IAOE.IBT1) // Isct Byte1 for EC +External(\_SB.IAOE.WKRS) // ISCT Wake Reason +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) +External(\_SB.PCI0.GFX0.TCHE) // Technology enabled indicator +External(\_SB.PCI0.GFX0.STAT) // State Indicator +External(\_SB.PCI0.B0D3.ABAR) +External(\_SB.PCI0.B0D3.BARA) +External(\SGMD) +#endif + +External(\_SB.TPM.PTS, MethodObj) +External(\_SB.PCI0.I2C0.SHUB.PI2C.PUAM, MethodObj) //DUAM - Device User Absent Mode +External(\_SB.PCI0.PAUD.PUAM, MethodObj) //PUAM - PowerResource User Absent Mode +External(\_SB.PCI0.XHC.DUAM, MethodObj) //DUAM - Device User Absent Mode for XHCI controller +#ifndef AMI_OVERRIDE_FOR_ACPI_DEBUG +External(\MDBG, MethodObj) +#endif // AMI_OVERRIDE_FOR_ACPI_DEBUG + +External(\_SB.PCI0.PEG0.PEGP.EPON, MethodObj) +External(\_SB.PCI0.RP05.PEGP.EPON, MethodObj) + +#define CONVERTIBLE_BUTTON 6 +#define DOCK_INDICATOR 7 + +Name(ECUP, 1) // EC State indicator: 1- Normal Mode 0- Low Power Mode +Mutex(EHLD, 0) // EC Hold indicator: 0- No one accessing the EC Power State 1- Someone else is accessing the EC Power State + +// NFC module support +include("Nfc.asl") + +// Create a Global MUTEX. + +Mutex(MUTX,0) + +//AMI_OVERRIDE --- Debug output registers. >> +//------------------------------------------------------------------------ +// Procedure: DBG8 +// Procedure: DBG9 +// Description: Logical names for Debug ports 0x80(byte) and 0x90(word). +// If such debug ports exist in the System, the value, stored +// into the Port will be displayed to LED +// Input: Nothing +// Output: Nothing +//------------------------------------------------------------------------- + +OperationRegion (DEB0, SystemIO, 0x80, 1) +Field (DEB0, ByteAcc, NoLock, Preserve) +{ DBG8, 8 } + +OperationRegion (DEB1, SystemIO, 0x90, 2) +Field (DEB1, WordAcc, NoLock, Preserve) +{ DBG9, 16 } +//AMI_OVERRIDE --- Debug output registers. << + +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> +// OS Up mutex +Mutex(OSUM, 0) +// WAK Finished mutex +Mutex(WFDM, 0) +#endif //AMI_OVERRIDE --- it is for Thunderbolt, AMI thunderbolt module has taken care it already. << + +// Define Port 80 as an ACPI Operating Region to use for debugging. Please +// note that the Intel CRBs have the ability to ouput an entire DWord to +// Port 80h for debugging purposes, so the model implemented here may not be +// able to be used on OEM Designs. + +OperationRegion(PRT0,SystemIO,0x80,4) +Field(PRT0,DwordAcc,Lock,Preserve) +{ + P80H, 32 +} + + +// Port 80h Update: +// Update 8 bits of the 32-bit Port 80h. +// +// Arguments: +// Arg0: 0 = Write Port 80h, Bits 7:0 Only. +// 1 = Write Port 80h, Bits 15:8 Only. +// 2 = Write Port 80h, Bits 23:16 Only. +// 3 = Write Port 80h, Bits 31:24 Only. +// Arg1: 8-bit Value to write +// +// Return Value: +// None + +Method(P8XH,2,Serialized) +{ + If(LEqual(Arg0,0)) // Write Port 80h, Bits 7:0. + { + Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D) + } + + If(LEqual(Arg0,1)) // Write Port 80h, Bits 15:8. + { + Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D) + } + + If(LEqual(Arg0,2)) // Write Port 80h, Bits 23:16. + { + Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D) + } + + If(LEqual(Arg0,3)) // Write Port 80h, Bits 31:24. + { + Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D) + } + + Store(P80D,P80H) +} + +Method(ADBG,1,Serialized) +{ +#ifndef AMI_OVERRIDE_FOR_ACPI_DEBUG + If(CondRefOf(MDBG)) + { + Return(MDBG(Arg0)) + } + Return(0) +#endif // AMI_OVERRIDE_FOR_ACPI_DEBUG +} + +// +// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI. +// +OperationRegion(SPRT,SystemIO, 0xB2,2) +Field (SPRT, ByteAcc, Lock, Preserve) { + SSMP, 8 +} + +// The _PIC Control Method is optional for ACPI design. It allows the +// OS to inform the ASL code which interrupt controller is being used, +// the 8259 or APIC. The reference code in this document will address +// PCI IRQ Routing and resource allocation for both cases. +// +// The values passed into _PIC are: +// 0 = 8259 +// 1 = IOAPIC + +Method(\_PIC,1) +{ + Store(Arg0,GPIC) + Store(Arg0,PICM) +} + +// Prepare to Sleep. The hook is called when the OS is about to +// enter a sleep state. The argument passed is the numeric value of +// the Sx state. + +Method(_PTS,1) +{ + Store(0,P80D) // Zero out the entire Port 80h DWord. + P8XH(0,Arg0) // Output Sleep State to Port 80h, Byte 0. + + PTS(Arg0) //AMI_OVERRIDE --- Invoke PTS Method PRIOR TO ENTER ANY SLEEP STATE + ADBG(Concatenate("_PTS=",ToHexString(Arg0))) +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> + If(LOr(LEqual(BID, BICO),LEqual(BID, BICC))) { + Acquire(WFDM, 0xFFFF) + Store(0, WKFN) + Release(WFDM) + } + +#endif //AMI_OVERRIDE --- it is for Thunderbolt, AMI thunderbolt module has taken care it already. << + // + // Save Sleep state if iSCT is present + // + If(And(ICNF, 0x10)) + { + If(CondRefOf(\_SB.IAOE.PTSL)) + { + Store(Arg0, \_SB.IAOE.PTSL) + } + } + + // If code is executed, Wake from RI# via Serial Modem will be + // enabled. If code is not executed, COM Port Debugging throughout + // all Sx states will be enabled. + + If(LEqual(Arg0,3)) + { + // + // Disable update DTS temperature and threshold value in every SMI + // + If(LAnd(DTSE, LGreater(TCNT, 1))) + { + TRAP(\TRTD,30) + } + + // + // Set EC timer if iSCT enabled and EC timer is being used + // +#ifndef AMI_OVERRIDE_FOR_EC_SUPPORT + If(LEqual(\ECON,1)) + { +#endif // AMI_OVERRIDE_FOR_EC_SUPPORT + If(And(ICNF, 0x01)) + { + // + // ISCT SASD - Set EC based timer. + // + If(LAnd(And(ICNF, 0x10), LEqual(\_SB.IAOE.ITMR, 0))) + { + If (LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.AWT0), CondRefOf(\_SB.IAOE.ECTM))) + { + If (LGreater(\_SB.IAOE.ECTM, 0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(And(\_SB.IAOE.ECTM, 0xFF), RefOf(\_SB.PCI0.LPCB.H_EC.AWT0)) + \_SB.PCI0.LPCB.H_EC.ECWT(ShiftRight(And(\_SB.IAOE.ECTM, 0xFF00), 8), RefOf(\_SB.PCI0.LPCB.H_EC.AWT1)) + \_SB.PCI0.LPCB.H_EC.ECWT(ShiftRight(And(\_SB.IAOE.ECTM, 0xFF0000), 16), RefOf(\_SB.PCI0.LPCB.H_EC.AWT2)) + // + // Enable EC timer - BIT7 + // Enable wake from S3 on timer exiry - BIT0 + // + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.WTMS)), Local0) + \_SB.PCI0.LPCB.H_EC.ECWT(Or(0x81,Local0), RefOf(\_SB.PCI0.LPCB.H_EC.WTMS)) + } + } + } + + // + // ISCT - Check if RapidStart service exist or not + // If RapidStart then enable EC timer wake from S4. + // + If(LAnd(And(ICNF, 0x10), CondRefOf(\_SB.IFFS.FFSS))) + { + If (And(\_SB.IFFS.FFSS, 0x01)) + { + Store(1, \_SB.IAOE.FFSE) + If (LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.WTMS), LEqual(\_SB.IAOE.PTSL, 0x03))) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.WTMS)), Local0) + // + // Enable wake from S4 on timer exiry - BIT1 + // + \_SB.PCI0.LPCB.H_EC.ECWT(Or(0x02,Local0), RefOf(\_SB.PCI0.LPCB.H_EC.WTMS)) + } + } + Else + { + Store(0, \_SB.IAOE.FFSE) + } + } + } +#ifndef AMI_OVERRIDE_FOR_EC_SUPPORT + } +#endif // AMI_OVERRIDE_FOR_EC_SUPPORT + + } + // + // Save EC 10Sec mode to NVS data PB1E Bit7 at S3/S4 entry + // + If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) + { + If(LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.PB10), \ECON)){ + // + // Check EC 10sec PB mode is enabled.(H_EC.PB10) + // PB10 is cleared at every boot so we need to keep the state before entering S3/S4. + // + If(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PB10))) + { + // + // EC 10sec PB mode is enabled. Save the state in PB1E bit7 + // + Or(PB1E, 0x80, PB1E) + } + Else + { + // + // EC 10sec PB mode is not enabled. Clear PB1E bit7. + // + And(PB1E, 0x7F, PB1E) + } + } + } + + +#if 0 //AMI_OVERRIDE --- It is for CRB SIO using, OEM doesn't need to it. >> + If(LEqual(DBGS,0)) + { + Store(0,RT10) // Set MAXIM Transceiver = FORCEOFF. + Store(0x20,PME1) // Set SMSC GPI15 = Wake Event. + Store(1,PME0) // Set SMSC PME Enable. + Store(0x20,PMS1) // Clear GPI15 Status. + Store(1,PMS0) // Clear PME Status. + } +#endif //AMI_OVERRIDE --- It is for CRB SIO using, OEM doesn't need to it. << + + // Generate a SW SMI trap to save some NVRAM data back to CMOS. + + // Don't enable IGD OpRegion support yet. + // TRAP(1, 81) + // + // Call TPM.PTS + // + If(CondRefOf(\_SB.TPM.PTS)) + { + // + // Call TPM PTS method + // + \_SB.TPM.PTS (Arg0) + } + + // StandBy LED Drive. Program High for sleep state s3, s4 and s5 only fro desktop. + If(LOr(LOr(LEqual(Arg0,3), LEqual(Arg0,4)), LEqual(Arg0,5))){ + If(LEqual(PFLV,FDTP)){ + Store(1, \GP27) + } + } +} + +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> +External(\_GPE.OSUP, MethodObj) +External(\_GPE.MMTB, MethodObj) + + Method(MMRP) + { + Store(PEBS, Local0) // MMIO Base address + Add(Local0, 0xE0000, Local0) // RP01 + Subtract(ToInteger(TBSE), 1, Local1) + Multiply(Local1, 0x1000, Local1) + Add(Local0, Local1, Local0) // RP0x + + Return(Local0) + } +#endif //AMI_OVERRIDE --- It is for CRB SIO using, OEM doesn't need to it. << + +// Wake. This hook is called when the OS is about to wake from a +// sleep state. The argument passed is the numeric value of the +// sleep state the system is waking from. + +Method(_WAK,1,Serialized) +{ + P8XH(1,0xAB) // Beginning of _WAK. + + WAK(Arg0) //AMI_OVERRIDE --- Invoke WAK Method WHILE WAKE FROM ANY SLEEP STATE + + ADBG("_WAK") + + If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume + { + // + // During S3/S4 wake add indicator for 'Switchable/Hybrid Graphics endpoint device is on' + // + If(CondRefOf(\_SB.PCI0.PEG0.PEGP.EPON)) + { + \_SB.PCI0.PEG0.PEGP.EPON() + } + + If(CondRefOf(\_SB.PCI0.RP05.PEGP.EPON)) + { + \_SB.PCI0.RP05.PEGP.EPON() + } + } + + // + // Save a valid Audio BAR for the ABWA W/A + // + If (LAnd (LNotEqual (And(\_SB.PCI0.B0D3.ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (\_SB.PCI0.B0D3.ABAR, 0xFFFFC000), 0))) { + Store (\_SB.PCI0.B0D3.ABAR, \_SB.PCI0.B0D3.BARA) + } + + // + // Clear iSCT timers and sleep settings if iSCT is present + // + If(And(ICNF, 0x10)) + { + // + // If Graphics Driver supports disable display notification in ISCT mode + // + If (And(\_SB.PCI0.GFX0.TCHE, 0x100)) + { + // + // Notify Gfx driver that the platform is in Isct Mode + // + If (LEqual(\_SB.IAOE.ITMR, 1)) + { + // + // If ISCT Mode and Wake Reason is ISCT wake (RTC Timer or Network PME) + // Then notify graphics driver to turn off display + // + If (LAnd(And(\_SB.IAOE.IBT1, 0x01), LOr(And(\_SB.IAOE.WKRS, 0x02), And(\_SB.IAOE.WKRS, 0x10)))) { + Store(Or(And(\_SB.PCI0.GFX0.STAT, Not(0x03)), 0x01), \_SB.PCI0.GFX0.STAT) // BITS[1:0] = 01, ISCT Resume + } else { + Store(And(\_SB.PCI0.GFX0.STAT, Not(0x03)), \_SB.PCI0.GFX0.STAT) // BITS[1:0] = 00, Normal Resume to S0 + } + } else { + If(LEqual(\ECON,1)) { + If(CondRefOf(\_SB.PCI0.LPCB.H_EC.IBT1)) { + // + // If ISCT Mode and Wake Reason is ISCT wake (EC Timer or Network PME) + // Then notify graphics driver to turn off display + // + If (LAnd(And(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.IBT1)), 0x01), LOr(And(\_SB.IAOE.WKRS, 0x02), And(\_SB.IAOE.WKRS, 0x10)))) { + Store(Or(And(\_SB.PCI0.GFX0.STAT, Not(0x03)), 0x01), \_SB.PCI0.GFX0.STAT) // BITS[1:0] = 01, ISCT Resume + } else { + Store(And(\_SB.PCI0.GFX0.STAT, Not(0x03)), \_SB.PCI0.GFX0.STAT) // BITS[1:0] = 00, Normal Resume to S0 + } + } + } // (LEqual(\ECON,1)) + } + } + + If(CondRefOf(\_SB.IAOE.PTSL)) + { + Store(0, \_SB.IAOE.PTSL) + } + If (LEqual(\_SB.IAOE.ITMR, 0)) { + If(CondRefOf(\_SB.PCI0.LPCB.H_EC.WTMS)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.WTMS)) + } + } + If (CondRefOf(\_SB.IAOE.ECTM)) + { + Store(0, \_SB.IAOE.ECTM) + } + If (CondRefOf(\_SB.IAOE.RCTM)) + { + Store(0, \_SB.IAOE.RCTM) + } + } + + If(NEXP) + { + // Reinitialize the Native PCI Express after resume + + If(And(OSCC,0x02)) + { + \_SB.PCI0.NHPG() + } + If(And(OSCC,0x04)) // PME control granted? + { + \_SB.PCI0.NPME() + } + } + + If(LEqual(Arg0,3)) + { + // Turn off the CPU Fan for all OSes if Active Cooling + // is disabled. + + If(LEqual(0,ACTT)) + { + If(LEqual(\ECON,1)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.CFAN)) + } + } + } + + If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume + { + + // + // Restore EC 10sec PB override mode + // + If(LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.PB10), \ECON)){ + If(And(PB1E, 0x80)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(1, RefOf(\_SB.PCI0.LPCB.H_EC.PB10)) + } + } + + // Check to send Convertible/Dock state changes upon resume from Sx. + + If(And(GBSX,0x40)) + { + \_SB.PCI0.GFX0.IUEH(6) + + // + // Do the same thing for Virtul Button device. + // Toggle Bit3 of PB1E(Slate/Notebook status) + // +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Xor(PB1E, 0x08, PB1E) + + // + // Update VGBS(V-GPIO Button state) accordingly. + // + If(And(PB1E, 0x08)){ + If(LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.VGBI), \ECON)) + { + \_SB.PCI0.LPCB.H_EC.VGBI.UPBT(CONVERTIBLE_BUTTON, One) + } + } + Else + { + If(LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.VGBI), \ECON)) + { + \_SB.PCI0.LPCB.H_EC.VGBI.UPBT(CONVERTIBLE_BUTTON, Zero) + } + } +#endif //#ifdef ASL_CRB_EC_SUPPORT + } + + If(And(GBSX,0x80)) + { + \_SB.PCI0.GFX0.IUEH(7) + + // + // Do the same thing for Virtul Button device. + // Toggle Bit4 of PB1E (Dock/Undock status) + // +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Xor(PB1E, 0x10, PB1E) + + // + // Update VGBS(Virtual Button state) accordingly. + // + If(And(PB1E, 0x10)) + { + If(LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.VGBI), \ECON)) + { + \_SB.PCI0.LPCB.H_EC.VGBI.UPBT(DOCK_INDICATOR, One) + } + } + Else + { + If(LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.VGBI), \ECON)) + { + \_SB.PCI0.LPCB.H_EC.VGBI.UPBT(DOCK_INDICATOR, Zero) + } + } + +#endif //#ifdef ASL_CRB_EC_SUPPORT + } + + +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + // + // Prevent reinitializing Virtual GPIO Button status + // + If(CondRefOf(\_SB.PCI0.LPCB.H_EC.VGBI.ONTM)) + { + Store(1, \_SB.PCI0.LPCB.H_EC.VGBI.ONTM) + } +#endif //#ifdef ASL_CRB_EC_SUPPORT + If(LAnd(DTSE, LGreater(TCNT, 1))) + { + TRAP(\TRTD, 20) + } + + // Windows XP SP2 does not properly restore the P-State + // upon resume from S4 or S3 with degrade modes enabled. + // Use the existing _PPC methods to cycle the available + // P-States such that the processor ends up running at + // the proper P-State. + // + // Note: For S4, another possible W/A is to always boot + // the system in LFM. + // + + If(LEqual(OSYS,2002)) + { + If(And(\_PR.CFGD,0x01)) + { + If(LGreater(\_PR.CPU0._PPC,0)) + { + Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + } + Else + { + Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + } + } + } + + If(LEqual(\ECON,1)) + { + // Update Lid state after S3 or S4 resume + If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.LSTE)), LIDS) + + If(IGDS) + { + If (LEqual(LIDS, 0)) + { + Store(0x80000000,\_SB.PCI0.GFX0.CLID) + } + If (LEqual(LIDS, 1)) + { + Store(0x80000003,\_SB.PCI0.GFX0.CLID) + } + } + Notify(\_SB.LID0,0x80) + } + + // Detect the change of Dock state + If(LNotEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DOCK)), \DSTS)) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DOCK)), \DSTS) + If(LAnd(\_SB.PCI0.HDEF.DCKS, 1)) + { + Store(\DSTS, \_SB.PCI0.HDEF.DCKA) + } + If(LEqual(\DSTS, 1)) // Docked. + { + If(LEqual(Arg0,3)) + { + Sleep(1000) // Delay 1 second for hot docking stability + Store(\PDBR, \SSMP) + Sleep(1000) // Delay 1 second for hot docking stability + } + Notify(\_SB.PCI0.DOCK, 0) + } + Else // Undocked. + { + Notify(\_SB.PCI0.DOCK, 1) + } + } + + // Detect the change of Power State. + If(LEqual(BNUM,0)) + { + If(LNotEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.VPWR)),PWRS)) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.VPWR)),PWRS) + // Perform needed ACPI Notifications. + PNOT() + } + } + Else + { + If(LNotEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.RPWR)),PWRS)) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.RPWR)),PWRS) + // Perform needed ACPI Notifications. + PNOT() + } + } + } + +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> + If(LOr(LEqual(BID, BICO),LEqual(BID, BICC))) { + Acquire(OSUM, 0xFFFF) + Store(MMRP(), Local0) + OperationRegion(RP_X,SystemMemory,Local0,0x20) + Field(RP_X,DWordAcc, NoLock, Preserve) + { + REG0, 32, + REG1, 32, + REG2, 32, + REG3, 32, + REG4, 32, + REG5, 32, + REG6, 32, + REG7, 32 + } + Store(REG6, Local1) + Store(0x00F0F000, REG6) + Store(\_GPE.MMTB(), Local2) + \_GPE.OSUP(Local2) + Store(Local1, REG6) + Release(OSUM) + } +#endif //AMI_OVERRIDE --- it is for Thunderbolt, AMI thunderbolt module has taken care it already. << + + // For PCI Express Express Cards, it is possible a device was + // either inserted or removed during an Sx State. The problem + // is that no wake event will occur for a given warm inseration + // or removal, so the OS will not become aware of any change. + // To get around this, re-enumerate all Express Card slots. + // + // If the Root Port is enabled, it may be assumed to be hot-pluggable. + +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + If(LEqual(RP1D,0)) + { + Notify (\_SB.PCI0.RP01,0) + } +#endif // ASL_RC_PORT_0 + +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + If(LEqual(RP2D,0)) + { + Notify (\_SB.PCI0.RP02,0) + } +#endif // ASL_RC_PORT_1 + +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + If(LEqual(RP3D,0)) + { + Notify (\_SB.PCI0.RP03,0) + } +#endif // ASL_RC_PORT_2 + +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + If(LEqual(RP4D,0)) + { + Notify (\_SB.PCI0.RP04,0) + } +#endif // ASL_RC_PORT_3 + +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + If(LEqual(RP5D,0)) + { + Notify (\_SB.PCI0.RP05,0) + } +#endif // ASL_RC_PORT_4 + +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + If(LEqual(\RP6D,0)) + { + Notify (\_SB.PCI0.RP06,0) + } +#endif // ASL_RC_PORT_5 + +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + If(LEqual(RP7D,0)) + { + If(LEqual(\DSTS,0)) // UnDocked. + { + Notify (\_SB.PCI0.RP07,0) + } + } +#endif // ASL_RC_PORT_6 + +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + If(LEqual(RP8D,0)) + { + If(LEqual(\DSTS,0)) // UnDocked. + { + Notify (\_SB.PCI0.RP08,0) + } + } +#endif // ASL_RC_PORT_7 + } + + If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume + { + // + // To support Win8, RapidStart resume from G3 and resume from DeepSx state + // + \_SB.PCI0.XHC.XWAK() + } +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> + If(LOr(LEqual(BID, BICO),LEqual(BID, BICC))) { + Acquire(WFDM, 0xFFFF) + Store(1, WKFN) + Release(WFDM) + ADBG(Concatenate("_WAK=", ToHexString(Timer))) + } +#endif //AMI_OVERRIDE --- it is for Thunderbolt, AMI thunderbolt module has taken care it already. << + Return(Package(){0,0}) +} + +// Get Buffer: +// This method will take a buffer passed into the method and +// create then return a smaller buffer based on the pointer +// and size parameters passed in. +// +// Arguments: +// Arg0: Pointer to start of new Buffer in passed in Buffer. +// Arg1: Size of Buffer to create. +// Arg2: Original Buffer +// +// Return Value: +// Newly created buffer. + +Method(GETB,3,Serialized) +{ + Multiply(Arg0,8,Local0) // Convert Index. + Multiply(Arg1,8,Local1) // Convert Size. + CreateField(Arg2,Local0,Local1,TBF3) // Create Buffer. + + Return(TBF3) // Return Buffer. +} + +// Power Notification: +// Perform all needed OS notifications during a +// Power Switch. +// +// Arguments: +// None +// +// Return Value: +// None + +Method(PNOT,0,Serialized) +{ + // + // If MP enabled and driver support is present, notify all + // processors. + // + If(CondRefOf(\_SB.PCCD.PENB)) { // is CPPC enabled in SETUP? + Notify(\_SB.PCCD,0x82) // CPPC notify + } Else { + If(LGreater(TCNT, 1)) + { + If(And(PDC0,0x0008)){ + Notify(\_PR.CPU0,0x80) // Eval CPU0 _PPC. + } + If(And(PDC1,0x0008)){ + Notify(\_PR.CPU1,0x80) // Eval CPU1 _PPC. + } + If(And(PDC2,0x0008)){ + Notify(\_PR.CPU2,0x80) // Eval CPU2 _PPC. + } + If(And(PDC3,0x0008)){ + Notify(\_PR.CPU3,0x80) // Eval CPU3 _PPC. + } + If(And(PDC4,0x0008)){ + Notify(\_PR.CPU4,0x80) // Eval CPU4 _PPC. + } + If(And(PDC5,0x0008)){ + Notify(\_PR.CPU5,0x80) // Eval CPU5 _PPC. + } + If(And(PDC6,0x0008)){ + Notify(\_PR.CPU6,0x80) // Eval CPU6 _PPC. + } + If(And(PDC7,0x0008)){ + Notify(\_PR.CPU7,0x80) // Eval CPU7 _PPC. + } + }Else{ + Notify(\_PR.CPU0,0x80) // Eval _PPC. + } + } + + If(LGreater(TCNT, 1)){ + If(LAnd(And(PDC0,0x0008),And(PDC0,0x0010))){ + Notify(\_PR.CPU0,0x81) // Eval CPU0 _CST. + } + If(LAnd(And(PDC1,0x0008),And(PDC1,0x0010))){ + Notify(\_PR.CPU1,0x81) // Eval CPU1 _CST. + } + If(LAnd(And(PDC2,0x0008),And(PDC2,0x0010))){ + Notify(\_PR.CPU2,0x81) // Eval CPU2 _CST. + } + If(LAnd(And(PDC3,0x0008),And(PDC3,0x0010))){ + Notify(\_PR.CPU3,0x81) // Eval CPU3 _CST. + } + If(LAnd(And(PDC4,0x0008),And(PDC4,0x0010))){ + Notify(\_PR.CPU4,0x81) // Eval CPU4 _CST. + } + If(LAnd(And(PDC5,0x0008),And(PDC5,0x0010))){ + Notify(\_PR.CPU5,0x81) // Eval CPU5 _CST. + } + If(LAnd(And(PDC6,0x0008),And(PDC6,0x0010))){ + Notify(\_PR.CPU6,0x81) // Eval CPU6 _CST. + } + If(LAnd(And(PDC7,0x0008),And(PDC7,0x0010))){ + Notify(\_PR.CPU7,0x81) // Eval CPU7 _CST. + } + }Else{ + Notify(\_PR.CPU0,0x81) // Eval _CST. + } + + // Update the Battery 1 and 2 Stored Capacity and + // Stored Status. Battery 0 information is always accurrate. + + If(LEqual(\ECON,1)) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1CC)),B1SC) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1ST)),B1SS) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B2CC)),B2SC) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B2ST)),B2SS) + + // Perform update to all Batteries in the System. + If(LGreaterEqual(OSYS,2006)) // Vista and Win7 later on OS + { + Notify(\_SB.PCI0.LPCB.H_EC.BAT0,0x81) // Eval BAT0 _BST. + Notify(\_SB.PCI0.LPCB.H_EC.BAT1,0x81) // Eval BAT1 _BST. + Notify(\_SB.PCI0.LPCB.H_EC.BAT2,0x81) // Eval BAT2 _BST. + } + Else + { + Notify(\_SB.PCI0.LPCB.H_EC.BAT0,0x80) // Eval BAT0 _BST. + Notify(\_SB.PCI0.LPCB.H_EC.BAT1,0x80) // Eval BAT1 _BST. + Notify(\_SB.PCI0.LPCB.H_EC.BAT2,0x80) // Eval BAT2 _BST. + } + } + + If (LEqual(DPTF,1)){ + Notify(\_SB.IETM, 0x86) // Notification sent to DPTF driver (Policy) for PDRT reevaluation after AC/DC transtion has occurred. + } +} + +// +// Memory window to the CTDP registers starting at MCHBAR+5000h. +// +OperationRegion (MBAR, SystemMemory, Add(ShiftLeft(\_SB.PCI0.MHBR,15),0x5000), 0x1000) + Field (MBAR, ByteAcc, NoLock, Preserve) + { + Offset (0x938), // PACKAGE_POWER_SKU_UNIT (MCHBAR+0x5938) + PWRU, 4, // Power Units [3:0] unit value is calculated by 1 W / Power(2,PWR_UNIT). The default value of 0011b corresponds to 1/8 W. + Offset (0x9A0), // TURBO_POWER_LIMIT1 (MCHBAR+0x59A0) + PPL1, 15, // PKG_PWR_LIM_1 [14:0] + PL1E,1, // PKG_PWR_LIM1_EN [15] + CLP1,1, // Package Clamping Limitation 1 + } +Name(CLMP, 0) // save the clamp bit +Name(PLEN,0) // save the power limit enable bit +Name(PLSV,0x8000) // save value of PL1 upon entering CS +Name(CSEM, 0) //semaphore to avoid multiple calls to SPL1. SPL1/RPL1 must always be called in pairs, like push/pop off a stack +// +// SPL1 (Set PL1 to 4.5 watts with clamp bit set) +// Per Legacy Thermal management CS requirements, we would like to set the PL1 limit when entering CS to 4.5W with clamp bit set via MMIO. +// This can be done in the ACPI object which gets called by graphics driver during CS Entry. +// Likewise, during CS exit, the BIOS must reset the PL1 value to the previous value prior to CS entry and reset the clamp bit. +// +// Arguments: +// None +// +// Return Value: +// None +Method(SPL1,0,Serialized) +{ + Name(PPUU,0) // units + If (LEqual(CSEM, 1)) + { + Return() // we have already been called, must have CS exit before calling again + } + Store(1, CSEM) // record first call + + Store (PPL1, PLSV) // save PL1 value upon entering CS + Store (PL1E, PLEN) // save PL1 Enable bit upon entering CS + Store (CLP1, CLMP) // save PL1 Clamp bit upon entering CS + + If (LEqual(PWRU,0)) { // use PACKAGE_POWER_SKU_UNIT - Power Units[3:0] + Store(1,PPUU) + } Else { + ShiftLeft(Decrement(PWRU),2,PPUU) // get units + } + + Multiply(PLVL,PPUU,Local0) // convert SETUP value to power units in milli-watts + Divide(Local0,1000,,Local1) // convert SETUP value to power units in watts + Store(Local1, PPL1) // copy value to PL1 + Store(1, PL1E) // set Enable bit + Store(1, CLP1) // set Clamp bit +} +// +// RPL1 (Restore the PL1 register to the values prior to CS entry) +// +// Arguments: +// None +// +// Return Value: +// None +Method(RPL1,0,Serialized) +{ + Store (PLSV, PPL1) // restore value of PL1 upon exiting CS + Store(PLEN, PL1E) // restore the PL1 enable bit + Store(CLMP, CLP1) // restore the PL1 Clamp bit + Store(0, CSEM) // restore semaphore +} + +Name(DDPS, 0) // Current Display Power Status. 0= D0; non-zero = Dx state;. Initial value is zero. +Name(UAMS, 0) // User Absent Mode state, Zero - User Present; non-Zero - User not present +// GUAM - Global User Absent Mode +// Run when a change to User Absent mode is made, e.g. screen/display on/off events. +// Any device that needs notifications of these events includes its own UAMN Control Method. +// +// Arguments: +// Power State: +// 00h = On +// 01h = Standby +// 02h = Suspend +// 04h = Off +// 08h = Reduced On +// +// Return Value: +// None +// +Method(GUAM,1,Serialized) +{ + If(LNotEqual(Arg0, DDPS)){ // Display controller D-State changed? + Store(Arg0, DDPS) //Update DDPS to current state + Store(LAnd(Arg0, Not(PWRS)), UAMS) // UAMS: User Absent Mode state, Zero - User Present; non-Zero - User not present + + //Port 80 code for CS + If(Arg0){ + if(LEqual(ECNO,0x01)){ // Check EC notification enabled in Setup + ADBG("EC Notify") + if(LEqual(ECDB,0x01)){ + ADBG("EC Debug") + \_SB.PCI0.LPCB.H_EC.ECWT(1, RefOf(\_SB.PCI0.LPCB.H_EC.DLED)) //Set EC CS Debug Light (CAPS LOCK) + } + \_SB.PCI0.LPCB.H_EC.ECMD (0x2C) // Notify EC of CS entry + If(LEqual(ECLP, 0x1)) { + Store(Zero,\ECUP) + } + } + P8XH(0, 0xC5) + P8XH(1, 00) + ADBG("Enter CS") + If(PSCP){ + // if P-state Capping is enabled + If (LAnd(CondRefOf(\_PR.CPU0._PSS), CondRefOf(\_PR.CPU0._PPC))) + { + Subtract(SizeOf(\_PR.CPU0._PSS), One, \_PR.CPU0._PPC) + PNOT() + } + } + If(PLCS){ + SPL1() // set PL1 to low value upon CS entry + } + } Else { + if(LEqual(ECNO,0x01)){ // Check EC notification enabled in Setup + ADBG("EC Notify") + Store (Acquire(\EHLD, 0xFFFF), Local0) // Wait for Mutex for telling EC to exit Low Power Mode + if (LEqual(Local0, Zero)) { + \_SB.PCI0.LPCB.H_EC.ECMD (0x2D) // Notify EC of CS exit + If(LEqual(ECLP, 0x1)) { + Store(One,\ECUP) + } + Release(\EHLD) + } + ADBG("EC Debug") + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.DLED)) //Clear EC CS Debug Light (CAPS LOCK) + } + P8XH(0, 0xC5) + P8XH(1, 0xAB) + ADBG("Exit CS") + If(PSCP){ + // if P-state Capping s enabled + If (CondRefOf(\_PR.CPU0._PPC)) + { + Store(Zero, \_PR.CPU0._PPC) + PNOT() + } + } + If(PLCS){ + RPL1() // restore PL1 to pre-CS value upon exiting CS + } + } + + P_CS() // Powergating during CS + } +} + +// Power CS Powergated Devices: +// Method to enable/disable power during CS +Method(P_CS,0,Serialized) +{ + // NOTE: Do not turn ON Touch devices from here. Touch does not have PUAM + If(CondRefOf(\_SB.PCI0.PAUD.PUAM)){ // Notify Codec(HD-A/ADSP) + \_SB.PCI0.PAUD.PUAM() + } + // Adding back USB powergating (ONLY for Win8) until RTD3 walkup port setup implementation is complete */ + If(LEqual(OSYS,2012)){ // ONLY for Win8 OS + If(CondRefOf(\_SB.PCI0.XHC.DUAM)){ // Notify USB port- RVP + \_SB.PCI0.XHC.DUAM() + } + } + // TODO: Add calls to UAMN methods for + // * USB controller(s) + // * Embedded Controller + // * Sensor devices + // * Audio DSP? + // * Any other devices dependent on User Absent mode for power controls +} + +// SMI I/O Trap: +// Generate a Mutex protected SMI I/O Trap. +// +// Arguments: +// Arg0: I/O Trap type. +// 2 - For DTS +// 3 - For IGD +// 4 - For Pfat Tools +// Arg1: SMI I/O Trap Function to call. +// +// Return Value: +// SMI I/O Trap Return value. +// 0 = Success. Non-zero = Failure. + +Method(TRAP,2,Serialized) +{ + Store(Arg1,SMIF) // Store SMI Function. + + If(LEqual(Arg0,\TRTD)) // Is DTS IO Trap? + { + Store(Arg1,DTSF) // Store the function number global NVS + Store(0,TRPD) // Generate IO Trap. + Return(DTSF) // Return status from SMI handler + } + + If(LEqual(Arg0,\TRTI)) // Is IGD IO Trap? + { + Store(0,TRPH) // Generate IO Trap. + } + + If(LEqual(Arg0,\PFTI)) // Is PFAT TOOLS IO Trap? + { + Store(0,TRPF) // Generate IO Trap + } + + Return(SMIF) // Return SMIF. 0 = Success. +} + +// Note: Only add the indicator device needed by the platform. + +// +// System Bus +// +Scope(\_SB.PCI0) +{ + + Method(PTMA) + { + Return(PFMA) + } + + Method(PTMS) + { + Return(PFMS) + } + + Method(PTIA) + { + Return(PFIA) + } + + Method(_INI,0) + { + // Determine the OS and store the value, where: + // + // OSYS = 1000 = Linux. + // OSYS = 2000 = WIN2000. + // OSYS = 2001 = WINXP, RTM or SP1. + // OSYS = 2002 = WINXP SP2. + // OSYS = 2006 = Vista. + // OSYS = 2009 = Windows 7 and Windows Server 2008 R2. + // OSYS = 2012 = Windows 8 and Windows Server 2012. + // OSYS = 2013 = Windows Blue. + // + // Assume Windows 2000 at a minimum. + + Store(2000,OSYS) + + // Check for a specific OS which supports _OSI. + + If(CondRefOf(\_OSI,Local0)) + { + If(\_OSI("Linux")) + { + Store(1000,OSYS) + } + + If(\_OSI("Windows 2001")) + { + Store(2001,OSYS) + } + + If(\_OSI("Windows 2001 SP1")) + { + Store(2001,OSYS) + } + + If(\_OSI("Windows 2001 SP2")) + { + Store(2002,OSYS) + } + + If (\_OSI( "Windows 2001.1")) + { + Store (2003, OSYS) + } + + If(\_OSI("Windows 2006")) + { + Store(2006,OSYS) + } + + If(\_OSI("Windows 2009")) + { + Store(2009,OSYS) + } + + If(\_OSI("Windows 2012")) + { + Store(2012,OSYS) + } + + If(\_OSI("Windows 2013")) + { + Store(2013,OSYS) + } + } +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> + If(LOr(LEqual(BID, BICO),LEqual(BID, BICC))) { + Acquire(OSUM, 0xFFFF) + Store(MMRP(), Local1) + OperationRegion(RP_X,SystemMemory,Local1,0x20) + Field(RP_X,DWordAcc, NoLock, Preserve) + { + REG0, 32, + REG1, 32, + REG2, 32, + REG3, 32, + REG4, 32, + REG5, 32, + REG6, 32, + REG7, 32 + } + Store(REG6, Local2) + Store(0x00F0F000, REG6) + Store(\_GPE.MMTB(), Local3) + \_GPE.OSUP(Local3) + Store(Local2, REG6) + Release(OSUM) + Acquire(WFDM, 0xFFFF) + Store(1, WKFN) + + Release(WFDM) + } +#endif //AMI_OVERRIDE --- it is for Thunderbolt, AMI thunderbolt module has taken care it already. << + PINI() + } + + Method(NHPG,0,Serialized) + { +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + Store(0,^RP01.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_0 +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + Store(0,^RP02.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_1 +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + Store(0,^RP03.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_2 +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + Store(0,^RP04.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_3 +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + Store(0,^RP05.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_4 +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + Store(0,^RP06.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_5 +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + Store(0,^RP07.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_6 +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + Store(0,^RP08.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_7 +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + Store(1,^RP01.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_0 +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + Store(1,^RP02.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_1 +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + Store(1,^RP03.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_2 +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + Store(1,^RP04.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_3 +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + Store(1,^RP05.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_4 +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + Store(1,^RP06.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_5 +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + Store(1,^RP07.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_6 +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + Store(1,^RP08.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_7 + } + + Method(NPME,0,Serialized) + { +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + Store(0,^RP01.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + Store(0,^RP02.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + Store(0,^RP03.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + Store(0,^RP04.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + Store(0,^RP05.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + Store(0,^RP06.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + Store(0,^RP07.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + Store(0,^RP08.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + Store(1,^RP01.PMSX) // clear the PME SCI status bit +#endif +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + Store(1,^RP02.PMSX) // clear the PME SCI status bit +#endif +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + Store(1,^RP03.PMSX) // clear the PME SCI status bit +#endif +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + Store(1,^RP04.PMSX) // clear the PME SCI status bit +#endif +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + Store(1,^RP05.PMSX) // clear the PME SCI status bit +#endif +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + Store(1,^RP06.PMSX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + Store(1,^RP07.PMSX) // clear the PME SCI status bit +#endif +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + Store(1,^RP08.PMSX) // clear the PME SCI status bit +#endif + } +} + +Scope (\) +{ + // + // Global Name, returns current Interrupt controller mode; + // updated from _PIC control method + // + Name(PICM, 0) + + // + // Procedure: GPRW + // + // Description: Generic Wake up Control Method ("Big brother") + // to detect the Max Sleep State available in ASL Name scope + // and Return the Package compatible with _PRW format. + // Input: Arg0 = bit offset within GPE register space device event will be triggered to. + // Arg1 = Max Sleep state, device can resume the System from. + // If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the System. + // Output: _PRW package + // + Name(PRWP, Package(){Zero, Zero}) // _PRW Package + + Method(GPRW, 2) + { + Store(Arg0, Index(PRWP, 0)) // copy GPE# + // + // SS1-SS4 - enabled in BIOS Setup Sleep states + // + Store(ShiftLeft(SS1,1),Local0) // S1 ? + Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ? + Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ? + Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ? + // + // Local0 has a bit mask of enabled Sx(1 based) + // bit mask of enabled in BIOS Setup Sleep states(1 based) + // + If(And(ShiftLeft(1, Arg1), Local0)) + { + // + // Requested wake up value (Arg1) is present in Sx list of available Sleep states + // + Store(Arg1, Index(PRWP, 1)) // copy Sx# + } + Else + { + // + // Not available -> match Wake up value to the higher Sx state + // + ShiftRight(Local0, 1, Local0) + // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x + // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Max Sx + // } Else { // ??? Win2k / XP + FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Min Sx + // } + } + + Return(PRWP) + } +} + + +Scope (\_SB) +{ + Name(OSCI, 0) // \_SB._OSC DWORD2 input + Name(OSCO, 0) // \_SB._OSC DWORD2 output + // _OSC (Operating System Capabilities) + // _OSC under \_SB scope is used to convey platform wide OSPM capabilities. + // ACPI 5.0 specification enables OSPM to query for Platform CPPC support + // through _OSC evaluation. Upon _OSC evaluation, platform can indicate + // support/non-support for CPPC through the return buffer. For a complete + // description of _OSC ACPI Control Method, refer to ACPI 5.0 + // specification, section 6.2.10. + // Arguments: (4) + // Arg0 - A Buffer containing the UUID "0811B06E-4A27-44F9-8D60-3CBBC22E7B48" + // Arg1 - An Integer containing the Revision ID of the buffer format + // Arg2 - An Integer containing a count of entries in Arg3 + // Arg3 - A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing the list of capabilities + // + Method(_OSC,4,Serialized) + { + +//ami override + If(LNotEqual(OSCM(Arg0,Arg1,Arg2,Arg3),0)) + { + Return(Arg3) + } +//ami override + + // + // Point to Status DWORD in the Arg3 buffer (STATUS) + // + CreateDWordField(Arg3, 0, STS0) + // + // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES) + // + CreateDwordField(Arg3, 4, CAP0) + + // + // Check UUID + // + If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) + { + // + // Check Revision + // + If(LEqual(Arg1,One)) + { + If(And(CAP0,0x04)) // Check _PR3 Support(BIT2) + { + Store(0x04, OSCO) + If(LNotEqual(And(SGMD,0x0F),2)) // Check Switchable/Hybrid graphics is not enabled in bios setup [SgModeMuxless]? + { + If(LEqual(RTD3,0)) // Is RTD3 support disabled in Bios Setup? + { + // RTD3 is disabled via BIOS Setup. + And(CAP0, 0x3B, CAP0) // Clear _PR3 capability + Or(STS0, 0x10, STS0) // Indicate capability bit is cleared + } + } + } + + // Process command. Regardless of query or control, we do the same thing. + If(And(CAP0,0x20)) // Check CPC Support + { + If(CondRefOf(\_SB.PCCD.PENB)){ + If(LEqual(\_SB.PCCD.PENB, 0)){ + // PENB = 0 => CPPC is disabled via BIOS Setup. + And(CAP0, 0x1F, CAP0) // Clear _CPC capability + Or(STS0, 0x10, STS0) // Indicate capability bit is cleared + } + } Else { + // PENB object not found in namespace => CPPC is disabled via BIOS Setup. + And(CAP0, 0x1F, CAP0) // Clear _CPC capability + Or(STS0, 0x10, STS0) // Indicate capability bit is cleared + } + } + } Else{ + And(STS0,0xFFFFFF00,STS0) + Or(STS0,0xA, STS0) // Unrecognised Revision and report OSC failure + } + } Else { + And(STS0,0xFFFFFF00,STS0) + Or (STS0,0x6, STS0) // Unrecognised UUID and report OSC failure + } + + Return(Arg3) + } // End _OSC + + Device (PEPD) + { + Name (_HID, "INT33A1") + Name (_CID, EISAID ("PNP0D80")) + Name (_UID, 0x1) + + Name(PEPP, Zero) + Name (DEVS, Package() + { + 2, + Package() {"\\_SB.PCI0.GFX0"}, + Package() {"\\_SB.PCI0.SAT0.PRT1"} + }) + + Name (DEVX, Package() + { + Package() {"\\_SB.PCI0.GFX0",0xffffffff}, + Package() {"\\_SB.PCI0.SAT0.PRT1",0xffffffff}, + Package() {"\\_SB.PCI0.UA01", 0xffffffff}, + Package() {"\\_SB.PCI0.SDHC", 0xffffffff }, + Package() {"\\_SB.PCI0.I2C0", 0xffffffff }, + Package() {"\\_SB.PCI0.I2C1", 0xffffffff }, + Package() {"\\_SB.PCI0.XHC", 0xffffffff }, + Package() {"HDAUDIO\\FUNC_01&VEN_10EC&DEV_0282&SUBSYS_00000000&REV_1000\\4&a02b74b&0&0001", 0xffffffff }, + }) + + Name(DEVY, Package() // uPEP Device List + { + // + // 1: ACPI Device Descriptor: Fully Qualified namestring + // 2: Enabled/Disabled Field + // 0 = This device is disabled and applies no constraints + // >0 = This device is enabled and applies constraints + // 3: Constraint Package: entry per LPI state in LPIT + // a. Associated LPI State UID + // ID == 0xFF: same constraints apply to all states in LPIT + // b: minimum Dx state as pre-condition + // c: (optional) OEM specific OEM may provide an additional encoding + // which further defines the D-state Constraint + // 0x0-0x7F - Reserved + // 0x80-0xFF - OEM defined + // + Package() {"\\_PR.CPU0", 0x1, Package() {0, Package(){0xFF, 0}}}, + Package() {"\\_PR.CPU1", 0x1, Package() {0, Package(){0xFF, 0}}}, + Package() {"\\_PR.CPU2", 0x1, Package() {0, Package(){0xFF, 0}}}, + Package() {"\\_PR.CPU3", 0x1, Package() {0, Package(){0xFF, 0}}}, + Package() {"\\_SB.PCI0.GFX0", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.SAT0", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.SAT0.PRT0", 0x1, Package() {0, Package(){0xFF, 0, 0x81}}}, + Package() {"\\_SB.PCI0.SAT0.PRT1", 0x1, Package() {0, Package(){0xFF, 0, 0x81}}}, + Package() {"\\_SB.PCI0.SAT0.PRT2", 0x1, Package() {0, Package(){0xFF, 0, 0x81}}}, + Package() {"\\_SB.PCI0.SAT0.PRT3", 0x1, Package() {0, Package(){0xFF, 0, 0x81}}}, + Package() {"\\_SB.PCI0.UA00", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.UA01", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.SDHC", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.I2C0", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.I2C1", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.XHC", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"HDAUDIO\\FUNC_01&VEN_10EC&DEV_0282*", 0x1, Package() {0, Package(){0x0, 0}, Package(){0x1, 3}}}, + Package() {"\\_SB.PCI0.ADSP", 0x1, Package() {0, Package(){0x0, 0}, Package(){0x1, 3}}}, + }) + + Name(BCCD, Package() // Bugcheck Critical Device(s) + { + // + // 1: ACPI Device Descriptor: Fully Qualified name string + // 2: Package of packages: 1 or more specific commands to power up critical device + // 2a: Package: GAS-structure describing location of PEP accessible power control + // Refer to ACPI 5.0 spec section 5.2.3.1 for details + // a: Address Space ID (0 = System Memory) + // NOTE: A GAS Address Space of 0x7F (FFH) indicates remaining package + // elements are Intel defined + // b: Register bit width (32 = DWORD) + // c: Register bit offset + // d: Access size (3 = DWORD Access) + // e: Address (for System Memory = 64-bit physical address) + // 2b: Package containing: + // a: AND mask - not applicable for all Trigger Types + // b: Value (bits required to power up the critical device) + // c: Trigger Type: + // 0 = Read + // 1 = Write + // 2 = Write followed by Read + // 3 = Read Modify Write + // 4 = Read Modify Write followed by Read + // 2c: Power up delay: Time delay before next operation in uSec + // + Package() {"\\_SB.PCI0.SAT0", Package() { + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + Package() {"\\_SB.PCI0.SAT0.PRT0", Package(){ + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + Package() {"\\_SB.PCI0.SAT0.PRT1", Package(){ + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + Package() {"\\_SB.PCI0.SAT0.PRT2", Package(){ + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + Package() {"\\_SB.PCI0.SAT0.PRT3", Package(){ + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + }) + + Method(_STA, 0x0, NotSerialized) + { + If(LGreaterEqual(OSYS,2012)) + { + If(LEqual(And(CDID,0xF000), 0x9000)) // LPT-H Chipset DID start with 0x8xxx while LPT-LP start with 0x9xxx + { + If(LEqual(S0ID, 1)) + { + Return(0xf) + } + } + } + Return(0) + } + + Method(_DSM, 0x4, Serialized) + { + If(LEqual(Arg0,ToUUID("B8FEBFE0-BAF8-454b-AECD-49FB91137B21"))) //PEP driver should use same UUID + { + If(LEqual(Arg2, Zero)) + { + Return(Buffer(One) + { + 0x07 + }) + } + If(LEqual(Arg2, One)) + { + Store(0x1, PEPP) + Return(0xf) + } + If(LEqual(Arg2, 2)) + { + If(LEqual(Arg1, Zero)) { // Revision ID is Zero + // TBD Needs to find a better logic here.... + Switch(PEPY){ + Case(1){ // Grpahics alone enabled + Return(Package(){1,Package() {"\\_SB.PCI0.GFX0"}}) + } + Case(2){ // SATA alone enabled + Return(Package(){1,Package() {"\\_SB.PCI0.SAT0.PRT1"}}) + } + Case(3){ // Both SATA and Gfx enabled + Return(DEVS) + } + Default{ // All devices are disabled + Return(Package(){0}) + } + } // End of Switch(PEPY) + } + + If(LEqual(Arg1, One)) { // Revision ID is One + If(LNot(And(PEPY,0x01))){ // Check if PEP GFx disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 0)), 1)) // Disable Gfx + } + If(LNot(And(PEPY,0x02))){ // Check if PEP Sata disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 1)), 1)) // Disable Sata + } + If(LNot(And(PEPY,0x04))){ // Check if PEP UART disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 2)), 1)) // Disable UART + } + If(LNot(And(PEPY,0x08))){ // Check if PEP SDHC disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 3)), 1)) // Disable SDHC + } + If(LNot(And(PEPY,0x10))){ // Check if PEP I2C0 disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 4)), 1)) // Disable I2C0 + } + If(LNot(And(PEPY,0x20))){ // Check if PEP I2C1 disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 5)), 1)) // Disable I2C1 + } + If(LNot(And(PEPY,0x40))){ // Check if PEP XHCI disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 6)), 1)) // Disable XHCI + } + If(LNot(And(PEPY,0x80))){ // Check if PEP audio disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 7)), 1)) // Disable Audio + } + Return(DEVX) + } + } //If(LEqual(Arg2, 2)) + }// If(LEqual(Arg0,ToUUID("B8FEBFE0-BAF8-454b-AECD-49FB91137B21"))) + + If(LEqual(Arg0,ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))) + { + // Number of Functions (including this one) + If(LEqual(Arg2, Zero)) + { + Return(Buffer(One){0x07}) + } + // Device Constraints Enumeration + If(LEqual(Arg2, One)) + { + // Update uPEP device list based on PEPC (Low Power S0 Constraint) + // Bit[1:0] - SATA (0:None, 1:SATA Ports[all], 2:SATA Controller) + // [2] - En/Dis UART 0 + // [3] - UART 1 + // [4] - SDIO + // [5] - I2C 0 + // [6] - I2C 1 + // [7] - XHCI + // [8] - Azalia + // [9] - ADSP + + If(LNotEqual(And(PEPC, 0x0003), 1)) // PEPC Bit[1:0] - SATA (0:None, 1:SATA Ports[all], 2:SATA Controller) + { + // No Constraint for SATA Ports (SAT0.PRT0, PRT1, PRT2, PRT3) + Store (0x00, Index (DeRefOf(Index (DEVY, 6)), 1)) // SAT0.PRT0 + Store (0x00, Index (DeRefOf(Index (DEVY, 7)), 1)) // SAT0.PRT1 + Store (0x00, Index (DeRefOf(Index (DEVY, 8)), 1)) // SAT0.PRT2 + Store (0x00, Index (DeRefOf(Index (DEVY, 9)), 1)) // SAT0.PRT3 + } + + If(LNotEqual(And(PEPC, 0x0003), 2)) // PEPC Bit[1:0] - SATA (0:None, 1:SATA Ports[all], 2:SATA Controller) + { + // No Constraint for SATA Controller (SAT0) + Store (0x00, Index (DeRefOf(Index (DEVY, 5)), 1)) // SAT0 + + // Disable SATA Ports if no drive is connected + If(LNot(And(SPST,1))) + { + // Disable SATA Ports 0 + Store (0x00, Index (DeRefOf(Index (DEVY, 6)), 1)) // SAT0.PRT0 + } + If(LNot(And(SPST, 2))) + { + // Disable SATA Ports 1 + Store (0x00, Index (DeRefOf(Index (DEVY, 7)), 1)) // SAT0.PRT1 + } + If(LNot(And(SPST, 4))) + { + // Disable SATA Ports 2 + Store (0x00, Index (DeRefOf(Index (DEVY, 8)), 1)) // SAT0.PRT2 + } + If(LNot(And(SPST, 8))) + { + // Disable SATA Ports 3 + Store (0x00, Index (DeRefOf(Index (DEVY, 9)), 1)) // SAT0.PRT3 + } + } + + If(LEqual(And(PEPC,0x0004),0)) // PEPC Bit[2] - En/Dis UART 0 + { + // Disabled UA00 + Store (0x00, Index (DeRefOf(Index (DEVY, 10)), 1)) // UA00 + } + + If(LEqual(And(PEPC,0x0008),0)) // PEPC Bit[3] - En/Dis UART 1 + { + // Disabled UA01 + Store (0x00, Index (DeRefOf(Index (DEVY, 11)), 1)) // UA01 + } + + If(LEqual(And(PEPC,0x0010),0)) // PEPC Bit[4] - En/Dis SDIO + { + // Disabled SDHC + Store (0x00, Index (DeRefOf(Index (DEVY, 12)), 1)) // SDHC + } + + If(LEqual(And(PEPC,0x0020),0)) // PEPC Bit[5] - En/Dis I2C 0 + { + // Disabled I2C0 + Store (0x00, Index (DeRefOf(Index (DEVY, 13)), 1)) // I2C0 + } + + If(LEqual(And(PEPC,0x0040),0)) // PEPC Bit[6] - En/Dis I2C 1 + { + // Disabled I2C1 + Store (0x00, Index (DeRefOf(Index (DEVY, 14)), 1)) // I2C1 + } + + If(LEqual(And(PEPC,0x0080),0)) // PEPC Bit[7] - En/Dis XHCI + { + // Disabled XHCI + Store (0x00, Index (DeRefOf(Index (DEVY, 15)), 1)) // XHC + } + + If(LEqual(And(PEPC,0x0100),0)) // PEPC Bit[9] - En/Dis Azalia + { + // Disabled Azalia + Store (0x00, Index (DeRefOf(Index (DEVY, 16)), 1)) // Azalia + } + + If(LEqual(And(PEPC,0x0200),0)) // PEPC Bit[10] - En/Dis ADSP + { + // Disabled ADSP + Store (0x00, Index (DeRefOf(Index (DEVY, 17)), 1)) // ADSP + } + + Return(DEVY) + } + // BCCD + If(LEqual(Arg2, 2)) + { + Return(BCCD) + } + }// If(LEqual(Arg0,ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))) + Return(One) + } // Method(_DSM) + } //device (PEPD) + +} // End Scope(\_SB) + +Scope (\_SB) +{ + // + // define a BT RF-Kill device. + // + Device (BTKL) + { + Name(_HID, "INT3420") + + Method (_STA, 0x0, NotSerialized) + { + If (\_OSI ("Windows 2012")) { // WIN8? + If (LEqual(BID, BW2C)) { // WTM2? + Return(0x0F) + } + } + Return(0x00) // not support BT RF-Kill, device hide. + } + + // D0 Method for BTKL + Method(_PS0,0,Serialized) + { + // de-assert GPIO87 + And(\GL0A, 0x7F, \GL0A) + } + + // D3 Method for BTKL + Method(_PS3,0,Serialized) + { + // assert GPIO87 + Or(\GL0A, 0x80, \GL0A) + } + + // detect GPIO pin status + Method(PSTS) + { + Return(RDGP(87)) + } + } +} // End Scope(\_SB) diff --git a/ReferenceCode/AcpiTables/Dsdt/SMSC1000_COM.asl b/ReferenceCode/AcpiTables/Dsdt/SMSC1000_COM.asl new file mode 100644 index 0000000..0de4c73 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/SMSC1000_COM.asl @@ -0,0 +1,574 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(UAR6) // SMSC1000 UART 1. +{ + // Identify UART 2 as a COM Port. + + Name(_HID, EISAID("PNP0501")) + + Name(_UID,5) + + // Status Method for UART 1. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // not set to Disabled in BIOS Setup. + + If(SMC1) + { + // Display UART 1 and return status. + + Store(0,CR55) + Store(CR02,Local0) + Store(0,CRAA) + + If(And(Local0,0x08)) + { + Return(0x000F) + } + + Return(0x000D) + } + + Return(0x0000) + } + + // Disable Method for UART 1. + + Method(_DIS,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0xF0),CR02) + Store(0,CRAA) + } + + // Current Resource Setting Method for UART 1. + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags(){4} + }) + + // Skip this sequence if SIO device is not connected + + If(SMC1) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Write the base address into the Buffer. + + Store(0,CR55) + + ShiftLeft(CR24,2,IOL0) // Low Byte. + ShiftLeft(CR24,2,IOL1) + + ShiftRight(CR24,6,IOH0) // High Byte. + ShiftRight(CR24,6,IOH1) + + // Write the length into the Buffer. + + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + ShiftLeft(One,ShiftRight(And(CR28,0xF0),4),IRQW) + + Store(0,CRAA) + } + + Return(BUF0) + } + + // Possible Resource Setting Method for UART 1. + Name(_PRS,ResourceTemplate() + { + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4} + } + EndDependentFn() + }) + + + // Set Resource Setting Method for UART 1. + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQW) + + // Disable the device. + + Store(0,CR55) + Store(And(CR02,0xF0),CR02) + + // Set the Base IO Address. + + Store(ShiftRight(IOLO,2),CR24) + Or(CR24,ShiftLeft(IOHI,6),CR24) + + // Set the IRQ. + + And(CR28,0x0F,CR28) + Or(CR28,ShiftLeft(Subtract(FindSetRightBit(IRQW),1),4),CR28) + + // Set the Decode Range so UART 1 works with ICH7 and + // future platforms. + + AND(IOD0,0xF8,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x07,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x01,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x05,IOD0) + } + } + + // Enable the device. + + Store(Or(CR02,0x08),CR02) + Store(0,CRAA) + } + + // D0 Method for UART 1. + + Method(_PS0,0,Serialized) + { + Store(0,CR55) + Store(Or(CR02,0x08),CR02) + Store(0,CRAA) + } + + // D3 Method for UART 1. + + Method(_PS3,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0xF0),CR02) + Store(0,CRAA) + } +} + +Device(UAR7) // SMSC1000 UART 2. +{ + // Identify UART 2 as an IR Device. + + Name(_HID, EISAID("PNP0510")) + + Name(_UID,1) + + // Status Method for UART 2. + Method(_STA,0,Serialized) + { + // + //Check SIO Device is Present or not. + // + If (SMC1) + { + Store(0,CR55) + Store(CR02,Local0) + Store(0,CRAA) + If (And(Local0,0x80)) + { + Return (0x000F) + } + Return (0x000D) // Not present + } + Return (0x0000) + } + + // Disable Method for UART 2. + Method(_DIS,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0x0F),CR02) + // + // Disable IR on Logical Device Activate Register + // + Store(And(CR3A,0xFA),CR02) + Store(0,CRAA) + } + + + // + // Current Resource Setting Method for UART 2. + // + Method(_CRS,0,Serialized) + { + // Create the FIR Buffer that stores the Resources to + // be returned. + Name(BUF0,ResourceTemplate() + { + IO(Decode16, 0x0000, 0x0000, 0x01, 0x08) + IO(Decode16, 0x0000, 0x0000, 0x01, 0x08) + IRQNoFlags() {6} + DMA(Compatibility, NotBusMaster, Transfer8, ) {2} + }) + + If(SMC1) + { + // Create pointers to the specific byte. + // + CreateByteField(BUF0,0x02,IO10) + CreateByteField(BUF0,0x03,IO11) + CreateByteField(BUF0,0x04,IO12) + CreateByteField(BUF0,0x05,IO13) + CreateByteField(BUF0,0x0a,IO20) + CreateByteField(BUF0,0x0b,IO21) + CreateByteField(BUF0,0x0c,IO22) + CreateByteField(BUF0,0x0d,IO23) + CreateWordField(BUF0,0x11,IRQW) + CreateByteField(BUF0,0x14,DMA0) + + Store(0,CR55) + + // + // Write the Base Address into the Buffer. + // + ShiftLeft(CR25,2,IO10) // Low Byte. + ShiftRight(And(CR25,0xC0), 6, IO11) + Store(IO10, IO12) + Store(IO11, IO13) + + ShiftLeft(CR2B,3,IO20) // Low Byte. + ShiftRight(And(CR2B,0xE0), 5, IO21) + Store(IO20, IO22) + Store(IO21, IO23) + + // + // Write the IRQ value into the Buffer. + // + Store(0x0,Local1) + And(CR28,0x0F,Local1) + ShiftLeft(1, Local1, IRQW) + + // Write DMA value into buffer + Store(0x0,Local1) + And(CR2C,0x0F,Local1) + + If(LEqual(Local1, 0x0F)){ + Store(0, DMA0) //No DMA + } + Else{ + ShiftLeft(1, Local1, DMA0) + } + Store(0,CRAA) + } + Return(BUF0) + } + + // + // Possible Resource Setting Method for UART 2. + // + + Name(_PRS, ResourceTemplate() { + StartDependentFn(0, 0) { + IO(Decode16,0x2f8,0x2f8,0x01,0x08) + IO(Decode16,0x7E0,0x7E0,0x01,0x08) + IRQNoFlags(){6} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1} + } + StartDependentFnNoPri() { + IO(Decode16, 0x3F8, 0x3F8, 1, 8) + IO(Decode16,0x7E0,0x7E0,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x2F8, 0x3F8, 1, 8) + IO(Decode16,0x7E0,0x7E0,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x3E8, 0x3E8, 1, 8) + IO(Decode16,0x7E0,0x7E0,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x2E8, 0x3E8, 1, 8) + IO(Decode16,0x7E0,0x7E0,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + EndDependentFn() + }) + + + // Set Resource Setting Method for UART 2. + // Set Resource Setting Method for UART 2. + Method(_SRS,1,Serialized) + { + Store(0,CR55) + Store(CR2B, Local0) + Store(0,CRAA) + If(Local0) + { + // Point to the specific information in the passed + // in Buffer. + CreateByteField(Arg0,0x02,IO10) + CreateByteField(Arg0,0x03,IO11) + CreateByteField(Arg0,0x0a,IO20) + CreateByteField(Arg0,0x0b,IO21) + CreateWordField(Arg0,0x11,IRQW) + CreateByteField(Arg0,0x14,DMA0) + + Store(0,CR55) + + // + // Disable the device. + // + And(CR02,0x0F,CR02) + + // + // Set the Base IO Address. + // + Store(ShiftRight(IO10,2),CR25) + Or(CR25,ShiftLeft(IO11,6),CR25) + If(IO20){ + Store(ShiftRight(IO20,3),CR2B) + Or(CR2B,ShiftLeft(IO21,5),CR2B) + } + + // + // Set the IRQ. + // + And(CR28,0xF0,CR28) + Or(CR28,Subtract(FindSetRightBit(IRQW),1),CR28) + + // Set DMA + And(CR2C,0xF0,CR2C) + If(DMA0) + { + Or(CR2C,Subtract(FindSetRightBit(DMA0),1),CR2C) + } + Else + { + Or(CR2C,0x0F,CR2C) // No DMA + } + + // + // Set the Decode Range so UART 2 works with ICH7 and + // future platforms. + // + AND(IOD0,0x8F,IOD0) // Clear all bits. + If(LEqual(IO11,0x03)) // Address = 0x3xx + { + If(LEqual(IO10,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x070,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IO10,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x010,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x050,IOD0) + } + } + + // + // Enable the device. + // + Or(CR02,0x80,CR02) + + Store(0,CRAA) + + } + Else + { + // Point to the specific information in the passed + // in Buffer. + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQR) + + Store(0,CR55) + + // + // Disable the device. + // + And(CR02,0x0F,CR02) + + // + // Set the Base IO Address. + // + Store(ShiftRight(IOLO,2),CR25) + Or(CR25,ShiftLeft(IOHI,6),CR25) + + // + // Set the IRQ. + // + And(CR28,0xF0,CR28) + Or(CR28,Subtract(FindSetRightBit(IRQR),1),CR28) + + // + // Set the Decode Range so UART 2 works with ICH7 and + // future platforms. + // + AND(IOD0,0x8F,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x070,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x010,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x050,IOD0) + } + } + + // + // Enable the device. + // + Or(CR02,0x80,CR02) + + Store(0,CRAA) + } + } + + // + // D0 Method for UART 2. + // + Method(_PS0,0,Serialized) + { + Store(0,CR55) + Store(Or(CR02,0x80),CR02) + Store(0,CRAA) + + } + + // + // D3 Method for UART 2. + // + Method(_PS3,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0x0F),CR02) + Store(0,CRAA) + + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/SMSC1000_LPT.asl b/ReferenceCode/AcpiTables/Dsdt/SMSC1000_LPT.asl new file mode 100644 index 0000000..235a714 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/SMSC1000_LPT.asl @@ -0,0 +1,226 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(LPT1) // Printer, Output Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,5) + + // Status Method for LPT-Output Mode. + + Method(_STA,0,Serialized) + { + If(SMC1) + { + // Check if SIO Device is Present & Display LPT1 and return status. + + Store(0,CR55) + Store(CR01,Local0) + Store(0,CRAA) + + If(And(Local0,0x0C)) + { + Return(0x000F) + } + + Return(0x000D) + } + + Return(0x0000) + } + + + // Disable Method for LPT-Output Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + Store(0,CR55) + Store(And(CR01,0x0FB),CR01) + Store(0,CRAA) + } + + // Current Resource Setting Method for LPT-Output Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x04) + IRQNoFlags(){5} + }) + + If(SMC1) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + Store(0,CR55) + + ShiftLeft(CR23,2,IOL0) // Low Byte. + ShiftLeft(CR23,2,IOL1) + + ShiftRight(CR23,6,IOH0) // High Byte. + ShiftRight(CR23,6,IOH1) + + // Write the length into the Buffer. + + Store(4,LEN0) + + // Write the IRQ value into the Buffer. + + Store(0x0,Local1) + And(CR27,0x0F,Local1) + ShiftLeft(1, Local1, IRQW) + Store(0,CRAA) + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-Output Mode. + // Build a Buffer with all valid LPT Port Resources. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){7} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-Output Mode. + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + // Disable the device. + Store(0,CR55) + Store(And(CR01,0x0FB),CR01) + + // Set the Base IO Address. + Store(ShiftRight(IOL0,2),CR23) + Or(CR23,ShiftLeft(IOH0,6),CR23) + + // Set the IRQ. + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,CR27) + + // Set the Decode Range so POUT works when docked. + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x3xx + { + If(LEqual(IOL0,0x78)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else + { + Or(IOD1,0x02,IOD1) // Address = 0x3BC + } + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Or(CR01,0x04,CR01) + Store(0,CRAA) + } + + // D0 Method for LPT-Output Mode. + + Method(_PS0,0,Serialized) + { + Store(0,CR55) + Store(Or(CR01,0x04),CR01) + Store(0,CRAA) + } + + // D3 Method for LPT-Output Mode. + + Method(_PS3,0,Serialized) + { + Store(0,CR55) + Store(And(CR01,0x0FB),CR01) + Store(0,CRAA) + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/SMSC1000_SIO.asl b/ReferenceCode/AcpiTables/Dsdt/SMSC1000_SIO.asl new file mode 100644 index 0000000..8ba11dc --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/SMSC1000_SIO.asl @@ -0,0 +1,92 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(SM10) +{ + Name(_HID,EISAID("PNP0A05")) + + Name(_UID,4) + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // present on the Docking Board. + + If(SMC1) + { + Return(0x000F) + } + + Return(0x0000) + } + + // Define the SMSC1000 Reduced SIO Index/Data Registers as an ACPI + // Operating Region. These registers will be used communicate + // to the SIO. + + OperationRegion(SM10,SystemIO,\SP2O,0x02) + Field(SM10, ByteAcc, Lock, Preserve) + { + INDX, 8, + DATA, 8 + } + + // Use ACPI Defined IndexField so consecutive Index/Data I/Os are + // assured to be uninterrupted. + + IndexField(INDX,DATA,ByteAcc,Lock,Preserve) + { + CR00,8, + CR01,8, + Offset(0x02), + CR02, 8, // UART Power Management + Offset(0x0C), + CR0C, 8, // UARTMODE + Offset(0x23), + CR23,8, + Offset(0x24), + CR24, 8, // UART 1 Base Address + CR25, 8, // UART 2 Base Address + Offset(0x27), + CR27, 8, + Offset(0x28), + CR28, 8, // UART IRQ Select + Offset(0x2B), + CR2B, 8, //SCE (FIR) Base Address + CR2C, 8, //SCE (FIR) DMA Select + Offset(0x3A), + CR3A, 8, // LPC Docking Activate + CR3B, 8, // LPC Docking Base (High) + CR3C, 8, // LPC Docking Base (Low) + Offset(0x55), + CR55, 8, // Configuration Enable Key + Offset(0xAA), + CRAA, 8 // Configuration Disable Key + } + Include("SMSC1000_COM.ASL") + Include("SMSC1000_LPT.ASL") +}
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Dsdt/SMSC1007_COM.ASL b/ReferenceCode/AcpiTables/Dsdt/SMSC1007_COM.ASL new file mode 100644 index 0000000..c2c820f --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/SMSC1007_COM.ASL @@ -0,0 +1,593 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(UAR1) // SMSC 1007 UART 1. +{ + // Identify UART 2 as a COM Port. + + Name(_HID, EISAID("PNP0501")) + + Name(_UID,0) + + // Enable Wake on Ring through a Serial Modem. + + Method(_PRW, 0) { Return(GPRW(0x08, 3)) } // can wakeup from S3 state + + // Status Method for UART 1. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // not set to Disabled in BIOS Setup. + + If(LAnd(SMSC,CMCP)) + { + // Display UART 1 and return status. + + Store(0,CR55) + Store(CR02,Local0) + Store(0,CRAA) + + If(And(Local0,0x08)) + { + Return(0x000F) + } + + Return(0x000D) + } + + Return(0x0000) + } + + // Disable Method for UART 1. + + Method(_DIS,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0xF0),CR02) + Store(0,CRAA) + } + + // Current Resource Setting Method for UART 1. + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags(){4} + }) + + // Skip this sequence if UART 1 is Disabled + // in BIOS Setup. + + If(LAnd(SMSC,CMCP)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Write the base address into the Buffer. + + Store(0,CR55) + + ShiftLeft(CR24,2,IOL0) // Low Byte. + ShiftLeft(CR24,2,IOL1) + + ShiftRight(CR24,6,IOH0) // High Byte. + ShiftRight(CR24,6,IOH1) + + // Write the length into the Buffer. + + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + ShiftLeft(One,ShiftRight(And(CR28,0xF0),4),IRQW) + + Store(0,CRAA) + } + + Return(BUF0) + } + + // Possible Resource Setting Method for UART 1. + + + Name(_PRS,ResourceTemplate() + { + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for UART 1. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQW) + + // Disable the device. + + Store(0,CR55) + Store(And(CR02,0xF0),CR02) + + // Set the Base IO Address. + + Store(ShiftRight(IOLO,2),CR24) + Or(CR24,ShiftLeft(IOHI,6),CR24) + + // Set the IRQ. + + And(CR28,0x0F,CR28) + Or(CR28,ShiftLeft(Subtract(FindSetRightBit(IRQW),1),4),CR28) + + // Set the Decode Range so UART 1 works with ICH7 and + // future platforms. + + AND(IOD0,0xF8,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x07,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x01,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x05,IOD0) + } + } + + // Enable the device. + + Store(Or(CR02,0x08),CR02) + Store(0,CRAA) + } + + // D0 Method for UART 1. + + Method(_PS0,0,Serialized) + { + Store(0,CR55) + Store(Or(CR02,0x08),CR02) + Store(0,CRAA) + } + + // D3 Method for UART 1. + + Method(_PS3,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0xF0),CR02) + Store(0,CRAA) + } +} + +Device(UAR2) // SMSC 1007 UART 2. +{ + // Identify UART 2 as an IR Device. + + Name(_HID, EISAID("PNP0510")) + + Name(_UID,0) + + // Status Method for UART 2. + + Method(_STA,0,Serialized) + { + // + //Check SIR Base Address, If ADR9 and ADR8 are 0, SIR disabled. + // + If (LAnd(SMSC,CIRP)) + { + Store(0,CR55) + Store(CR02,Local0) + Store(0,CRAA) + If (And(Local0,0x80)) + { + Return (0x000F) + } + Return (0x000D) // Not present + } + Return (0x0000) + } + // Disable Method for UART 2. + + Method(_DIS,0,Serialized) + { + Store(0,CR55) + + Store(And(CR02,0x0F),CR02) + + // + // Disable IR on Logical Device Activate Register + // + Store(And(CR3A,0xFA),CR02) + + Store(0,CRAA) + } + + + // + // Current Resource Setting Method for UART 2. + // + Method(_CRS,0,Serialized) + { + + // Create the FIR Buffer that stores the Resources to + // be returned. + Name(BUF0,ResourceTemplate() + { + IO(Decode16, 0x0000, 0x0000, 0x01, 0x08) + IO(Decode16, 0x0000, 0x0000, 0x01, 0x08) + IRQNoFlags() {7} + DMA(Compatibility, NotBusMaster, Transfer8, ) {2} + }) + + // Skip this sequence if UART 2 is Disabled + // in BIOS Setup. + + If (LAnd(SMSC,CIRP)) + { + // + // Create pointers to the specific byte. + // + CreateByteField(BUF0,0x02,IO10) + CreateByteField(BUF0,0x03,IO11) + CreateByteField(BUF0,0x04,IO12) + CreateByteField(BUF0,0x05,IO13) + CreateByteField(BUF0,0x0a,IO20) + CreateByteField(BUF0,0x0b,IO21) + CreateByteField(BUF0,0x0c,IO22) + CreateByteField(BUF0,0x0d,IO23) + CreateWordField(BUF0,0x11,IRQW) + CreateByteField(BUF0,0x14,DMA0) + + Store(0,CR55) + + // + // Write the Base Address into the Buffer. + // + ShiftLeft(CR25,2,IO10) // Low Byte. + ShiftRight(And(CR25,0xC0), 6, IO11) + Store(IO10, IO12) + Store(IO11, IO13) + + ShiftLeft(CR2B,3,IO20) // Low Byte. + ShiftRight(And(CR2B,0xE0), 5, IO21) + Store(IO20, IO22) + Store(IO21, IO23) + + // + // Write the IRQ value into the Buffer. + // + Store(0x0,Local1) + And(CR28,0x0F,Local1) + ShiftLeft(1, Local1, IRQW) + + // Write DMA value into buffer + Store(0x0,Local1) + And(CR2C,0x0F,Local1) + If(LEqual(Local1, 0x0F)){ + Store(0, DMA0) //No DMA + }Else{ + ShiftLeft(1, Local1, DMA0) + } + + Store(0,CRAA) + } + + Return(BUF0) + } + + // + // Possible Resource Setting Method for UART 2. + // + // Build a Buffer with all valid UART 2 Resources. + + Name(_PRS, ResourceTemplate() { +// IRQ, No DMA +StartDependentFn(0, 0) { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IO(Decode16,0x7E8,0x7E8,0x01,0x08) + IRQNoFlags(){3} + DMA(Compatibility, NotBusMaster, Transfer8_16) {3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x3F8, 0x3F8, 1, 8) + IO(Decode16,0x7E8,0x7E8,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x2F8, 0x3F8, 1, 8) + IO(Decode16,0x7E8,0x7E8,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x3E8, 0x3E8, 1, 8) + IO(Decode16,0x7E8,0x7E8,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x2E8, 0x3E8, 1, 8) + IO(Decode16,0x7E8,0x7E8,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + EndDependentFn() + + }) + + + // Set Resource Setting Method for UART 2. + // Set Resource Setting Method for UART 2. + Method(_SRS,1,Serialized) + { + Store(0,CR55) + Store(CR2B, Local0) + Store(0,CRAA) + If(Local0) + { + // Point to the specific information in the passed + // in Buffer. + CreateByteField(Arg0,0x02,IO10) + CreateByteField(Arg0,0x03,IO11) + CreateByteField(Arg0,0x0a,IO20) + CreateByteField(Arg0,0x0b,IO21) + CreateWordField(Arg0,0x11,IRQW) + CreateByteField(Arg0,0x14,DMA0) + + Store(0,CR55) + + // + // Disable the device. + // + And(CR02,0x0F,CR02) + + // + // If UART2 mode has not already been configured, set it here. + // +// Store(0x0B, CR0C) +// Store(0x40, CR0A) +// Store(0x0C, CR0C) + + // + // Set the Base IO Address. + // + Store(ShiftRight(IO10,2),CR25) + Or(CR25,ShiftLeft(IO11,6),CR25) + If(IO20){ + Store(ShiftRight(IO20,3),CR2B) + Or(CR2B,ShiftLeft(IO21,5),CR2B) + } + + + // + // Set the IRQ. + // + And(CR28,0xF0,CR28) + Or(CR28,Subtract(FindSetRightBit(IRQW),1),CR28) + + // Set DMA + And(CR2C,0xF0,CR2C) + If(DMA0) + { + Or(CR2C,Subtract(FindSetRightBit(DMA0),1),CR2C) + } + Else + { + Or(CR2C,0x0F,CR2C) // No DMA + } + + // + // Set the Decode Range so UART 2 works with ICH7 and + // future platforms. + // + AND(IOD0,0x8F,IOD0) // Clear all bits. + If(LEqual(IO11,0x03)) // Address = 0x3xx + { + If(LEqual(IO10,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x070,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IO10,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x010,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x050,IOD0) + } + } + + // + // Enable the device. + // + Or(CR02,0x80,CR02) + + Store(0,CRAA) + + } + Else + { + // Point to the specific information in the passed + // in Buffer. + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQR) + + Store(0,CR55) + + // + // Disable the device. + // + And(CR02,0x0F,CR02) + + // + // If UART2 mode has not already been configured, set it here. + // +// Store(0x0B, CR0C) +// Store(0x40, CR0A) +// Store(0x0C, CR0C) + + // + // Set the Base IO Address. + // + Store(ShiftRight(IOLO,2),CR25) + Or(CR25,ShiftLeft(IOHI,6),CR25) + + // + // Set the IRQ. + // + And(CR28,0xF0,CR28) + Or(CR28,Subtract(FindSetRightBit(IRQR),1),CR28) + + // + // Set the Decode Range so UART 2 works with ICH7 and + // future platforms. + // + AND(IOD0,0x8F,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x070,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x010,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x050,IOD0) + } + } + + // + // Enable the device. + // + Or(CR02,0x80,CR02) + + Store(0,CRAA) + } + } + + // + // D0 Method for UART 2. + // + Method(_PS0,0,Serialized) + { + Store(0,CR55) + Store(Or(CR02,0x80),CR02) + Store(0,CRAA) + + } + + // + // D3 Method for UART 2. + // + Method(_PS3,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0x0F),CR02) + Store(0,CRAA) + + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/SMSC1007_SIO.ASL b/ReferenceCode/AcpiTables/Dsdt/SMSC1007_SIO.ASL new file mode 100644 index 0000000..6874fe6 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/SMSC1007_SIO.ASL @@ -0,0 +1,149 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + // Define the SMSC Runtime I/O Registers and the LPC Docking I/O Register + // as an ACPI Operating Region. The base address for both can be found + // in the SMSC 1007 Configuration Registers, specfically at CR30 for the + // Runtime I/O Base and CR3B and CR3C for the LPC Docking Base. + // +Scope(\) +{ + OperationRegion(S_IO,SystemIo,\IO2B,0x11) + Field(S_IO, ByteAcc, NoLock, Preserve) + { + PMS0, 8, + PME0, 8, + PMS1, 8, + PMS2, 8, + PMS3, 8, + PME1, 8, + PME2, 8, + PME3, 8, + Offset(0x08), + SS10, 1, + SS11, 1, + SS12, 1, + SS13, 1, + SS14, 1, + SS15, 1, + SS16, 1, + SS17, 1, + SMS2, 8, + Offset(0x0A), + SE10, 1, + SE11, 1, + SE12, 1, + SE13, 1, + SE14, 1, + SE15, 1, + SE16, 1, + SE17, 1, + SME2, 8, + Offset(0x0C), + RT10, 1, // GP10 = 1 = SMSC COM Port On, 0 = Off, in Wake Mode. + RT11, 1, // GP11 + RT12, 1, // GP12 + RT13, 1, // GP13 + RT14, 1, // GP14 + RT15, 1, // GP15 + RT16, 1, // GP16 + RT17, 1, // GP17 + Offset(0x0E), + RT30, 1, // GP30 + RT31, 1, // GP31 + RT32, 1, // GP32 + RT33, 1, // GP33 + RT34, 1, // GP34 + RT35, 1, // GP35 + RT36, 1, // GP36 + RT37, 1, // GP37 + Offset(0x10), + DLPC, 1, // DLPC Switch + CK33, 1, // 33MHz Clock + CK14, 1 // 14MHz Clock + } +} + +Device(SM17) +{ + Name(_HID,EISAID("PNP0A05")) + + Name(_UID,2) + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // present on the Docking Board. + + If(SMSC) + { + Return(0x000F) + } + + Return(0x0000) + } + + // Define the SM17 Reduced SIO Index/Data Registers as an ACPI + // Operating Region. These registers will be used communicate + // to the SIO. + + OperationRegion(SM17,SystemIO,\SP1O,0x02) + Field(SM17, ByteAcc, Lock, Preserve) + { + INDX, 8, + DATA, 8 + } + + // Use ACPI Defined IndexField so consecutive Index/Data I/Os are + // assured to be uninterrupted. + + IndexField(INDX,DATA,ByteAcc,Lock,Preserve) + { + Offset(0x02), + CR02, 8, // UART Power Management + Offset(0x0C), + CR0C, 8, // UARTMODE + Offset(0x24), + CR24, 8, // UART 1 Base Address + CR25, 8, // UART 2 Base Address + Offset(0x28), + CR28, 8, // UART IRQ Select + Offset(0x2B), + CR2B, 8, //SCE (FIR) Base Address + CR2C, 8, //SCE (FIR) DMA Select + Offset(0x3A), + CR3A, 8, // LPC Docking Activate + CR3B, 8, // LPC Docking Base (High) + CR3C, 8, // LPC Docking Base (Low) + Offset(0x55), + CR55, 8, // Configuration Enable Key + Offset(0xAA), + CRAA, 8 // Configuration Disable Key + } + + Include("SMSC1007_COM.ASL") +} diff --git a/ReferenceCode/AcpiTables/Dsdt/THERMAL.ASL b/ReferenceCode/AcpiTables/Dsdt/THERMAL.ASL new file mode 100644 index 0000000..f38392f --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/THERMAL.ASL @@ -0,0 +1,681 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ +External(\_PR.APSV) +External(\_PR.ACRT) +External(\_PR.AAC0) + +// THERMAL.ASL represents a Thermal Zone to be used for testing on the +// Customer Reference Boards. +Scope(\_TZ) +{ + + // Notes: + // 1) WIN2K strictly uses interrupt driven thermal events. + // 2) Temperature values are stored in tenths of Kelvin to + // eliminate the decimal place. + // 3) Kelvin = Celsius + 273.2. + // 4) All temperature must be >= 289K. + + Name(ETMD, 1) + + // Temprature Threshold in Celsius, used to guard against hardware returning bad temprature readings + Name(THLD, 120) + + // + // YBTx -- _ACx Thermal Trip Points for YellowBluff platform + // + // Matrix of Thermal Trip points & Fan Control (YellowBluff Platform) + // T('C) PWM Duty Cycle + Name(YBT4, 55) // 35 + Name(YBT3, 64) // 55 + Name(YBT2, 73) // 75 + Name(YBT1, 80) // 90 + Name(YBT0, 91) // 100 + + // Fan 0 = Package Processor Fan - Maximum speed + PowerResource(FN00, 0, 0) + { + Method(_STA, 0, Serialized) + { + // Return Virtual Fan 0 status. + Return(VFN0) + } + + // This method is called when the temprature goes above _AC0. + // Regardless of other FAN states, set to ACF0 since this is max cooling state: temp > _AC0 + Method(_ON, 0, Serialized) + { + // Set Virtual Fan 0 On. + Store(1,VFN0) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(AC0F, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + + // This method is called when the temprature goes below _AC0. + // If FAN1 is on, use its value (AC1F): _AC0 > temp > _AC1 + // If FAN1 is off, use FAN2 value (AC2F): _AC0 > _AC1 > temp + Method(_OFF, 0, Serialized) + { + // Set Virtual Fan 0 Off. + Store(0,VFN0) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LNotEqual(VFN1,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(AC1F, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC1F + } + Else + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC2F = 0 + } + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // Associate Virtual Fan 0 Power Resource with the FAN0 Device. + Device(FAN0) + { + Name(_HID, EISAID("PNP0C0B")) + Name(_UID, 0) + Name(_PR0, Package(1){FN00}) +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Method(_DEP) // Fan method depends on EC Wrapper Op Region to be available + { + Return(Package() {\_SB.PCI0.LPCB.H_EC}) + } +#endif + } + + // Fan 1 = Package Processor Fan. + PowerResource(FN01,0,0) + { + Method(_STA,0,Serialized) + { + // Return Virtual Fan 1 status. + Return(VFN1) + } + + // This method is called when the temprature goes above _AC1. + // If FAN0 is on, do nothing since we're already at AC0F: temp > _AC0 > _AC1 + // If FAN0 is off, use FAN1 value (AC1F): _AC0 > temp > _AC1 + Method(_ON,0,Serialized) + { + // Set Virtual Fan 1 On. + Store(1,VFN1) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LEqual(VFN0,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(AC1F, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC1F + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // This method is called when the temprature goes below _AC1. + // If FAN2 is on, use its value (AC2F): _AC1 > temp > _AC2 + // If FAN2 is off, use FAN3 value (AC3F): _AC1 > _AC2 > temp + Method(_OFF,0,Serialized) + { + // Set Virtual Fan 1 Off. + Store(0,VFN1) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LNotEqual(VFN2,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC2F = 0 + } + Else + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC3F = 0 + } + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // Associate Virtual Fan 1 Power Resource with the FAN1 Device. + Device(FAN1) + { + Name(_HID, EISAID("PNP0C0B")) + Name(_UID, 1) + Name(_PR0, Package(1){FN01}) +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Method(_DEP) // Fan method depends on EC Wrapper Op Region to be available + { + Return(Package() {\_SB.PCI0.LPCB.H_EC}) + } +#endif + } + + + // Fan 2 = Package Processor Fan. + PowerResource(FN02,0,0) + { + Method(_STA,0,Serialized) + { + // Return Virtual Fan 2 status. + Return(VFN2) + } + + // This method is called when the temprature goes above _AC2. + // If FAN1 is on, do nothing since we're already at AC1F or greater: temp > _AC1 > _AC2 + // If FAN1 is off, use FAN2 value (AC2F): _AC1 > temp > _AC2 + Method(_ON,0,Serialized) + { + // Set Virtual Fan 2 On. + Store(1,VFN2) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LEqual(VFN1,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC2F = 0 + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // This method is called when the temprature goes below _AC2. + // If FAN3 is on, use its value (AC3F): _AC2 > temp > _AC3 + // If FAN3 is off, use FAN4 value (AC4F): _AC2 > _AC3 > temp + Method(_OFF,0,Serialized) + { + // Set Virtual Fan 2 Off. + Store(0,VFN2) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LNotEqual(VFN3,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC3F = 0 + } + Else + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC4F = 0 + } + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // Associate Virtual Fan 2 Power Resource with the FAN0 Device. + Device(FAN2) + { + Name(_HID, EISAID("PNP0C0B")) + Name(_UID, 2) + Name(_PR0, Package(1){FN02}) +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Method(_DEP) // Fan method depends on EC Wrapper Op Region to be available + { + Return(Package() {\_SB.PCI0.LPCB.H_EC}) + } +#endif + } + + // Fan 3 = Package Processor Fan. + PowerResource(FN03,0,0) + { + Method(_STA,0,Serialized) + { + // Return Virtual Fan 3 status. + Return(VFN3) + } + + // This method is called when the temprature goes above _AC3. + // If FAN2 is on, do nothing since we're already at AC2F or greater: temp > _AC2 > _AC3 + // If FAN2 is off, use FAN3 value (AC3F): _AC2 > temp > _AC3 + Method(_ON,0,Serialized) + { + // Set Virtual Fan 3 On. + Store(1,VFN3) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LEqual(VFN2,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC3F = 0 + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // This method is called when the temprature goes below _AC3. + // If FAN4 is on, use its value (AC4F): _AC3 > temp > _AC4 + // If FAN4 is off, use FAN5 value (AC5F): _AC3 > _AC4 > temp + Method(_OFF,0,Serialized) + { + // Set Virtual Fan 3 Off. + Store(0,VFN3) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LNotEqual(VFN4,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC4F = 0 + } + Else + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC5F = 0 + } + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // Associate Virtual Fan 3 Power Resource with the FAN3 Device. + Device(FAN3) + { + Name(_HID, EISAID("PNP0C0B")) + Name(_UID, 3) + Name(_PR0, Package(1){FN03}) +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Method(_DEP) // Fan method depends on EC Wrapper Op Region to be available + { + Return(Package() {\_SB.PCI0.LPCB.H_EC}) + } +#endif + } + + // Fan 4 = Package Processor Fan - Lowest Fan Speed + PowerResource(FN04,0,0) + { + Method(_STA,0,Serialized) + { + // Return Virtual Fan 4 status. + Return(VFN4) + } + + // This method is called when the temprature goes above _AC4. + // If FAN3 is on, do nothing since we're already at AC3F or greater: temp > _AC3 > _AC4 + // If FAN3 is off, use FAN4 value (AC4F): _AC3 > temp > _AC4 + Method(_ON,0,Serialized) + { + // Set Virtual Fan 4 On. + Store(1,VFN4) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LEqual(VFN3,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC4F = 0 + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // This method is called when the temprature goes below _AC4. + // FAN4 is the lowest FAN state defined, so we simply go to AC4F + Method(_OFF,0,Serialized) + { + // Set Virtual Fan 4 Off. + Store(0,VFN4) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC4F = 0 + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // Associate Virtual Fan 4 Power Resource with the FAN4 Device. + Device(FAN4) + { + Name(_HID, EISAID("PNP0C0B")) + Name(_UID, 4) + Name(_PR0, Package(1){FN04}) +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Method(_DEP) // Fan method depends on EC Wrapper Op Region to be available + { + Return(Package() {\_SB.PCI0.LPCB.H_EC}) + } +#endif + } + + // Thermal Zone 0 = Package Thermal Zone. + // Package Thermal Zone is used for Active and Critical Policy Control + // Package Thermal Zone returns the maximum temperature + // of all components within the package + ThermalZone(TZ00) + { + // Temporary variable for holding the current temprature reading + Name(PTMP,3000) + + // Notifies ASL Code the current cooling mode. + // 0 - Active cooling + // 1 - Passive cooling + Method(_SCP, 1, Serialized) + { + Store(Arg0, CTYP) + } + + // Return the temperature at which the OS performs Critical Shutdown + Method(_CRT, 0, Serialized) + { + // Returns automatic thermal reporting temperature for CPU throttling if available and valid. + If(CondRefOf(\_PR.ACRT)) + { + If(LNotEqual(\_PR.ACRT,0)) + { + Return(Add(2732, Multiply(\_PR.ACRT, 10))) + } + } + + Return(Add(2732, Multiply(CRTT, 10))) + } + + // Return the temperature(s) at which the OS initiates Active Cooling. + Method(_AC0, 0, Serialized) + { + // Returns automatic thermal reporting temperature for CPU throttling if available and valid. + If(CondRefOf(\_PR.AAC0)) + { + If(LNotEqual(\_PR.AAC0,0)) + { + Return(Add(2732, Multiply(\_PR.AAC0, 10))) + } + } + Return(Add(2732, Multiply(ACTT, 10))) + + } + + Method(_AC1, 0, Serialized) + { + Return(Add(2732, Multiply(ACT1, 10))) + } + + Method(_AC2, 0, Serialized) + { + Return(Add(2732, Multiply(0, 10))) + + } + + Method(_AC3, 0, Serialized) + { + Return(Add(2732, Multiply(0, 10))) + + } + + Method(_AC4, 0, Serialized) + { + Return(Add(2732, Multiply(0, 10))) + + } + + // Return the device(s) to turn on when _ACx is exceeded. + Name(_AL0, Package(){FAN0}) + Name(_AL1, Package(){FAN1}) + Name(_AL2, Package(){FAN2}) + Name(_AL3, Package(){FAN3}) + Name(_AL4, Package(){FAN4}) + + // Return the Package Temperature. + // Source 1: CPU DTS temperature + // Source 2: Max Platform temprature returned by EC + Method(_TMP, 0, Serialized) + { + + If (LNot(ETMD)) // If Legacy TM is disabled, return static value + { + Return (3000) + } + + If (LEqual(DTSE, 0x3)) //Out Of Spec Condition occurred. Return critical temperature for OS shutdown + { + Return(Add(2832,Multiply(CRTT,10))) + } + + // Source 1: If DTS SMM enabled + // + // If Package Temp MSR is available, then send Package DTS Temp + // otherwise send Core DTS Temp + If(LEqual(DTSE, 0x01)) + { + If(LEqual(PKGA, 0x01)) + { + Store(PDTS, Local0) + Return(Add(2732, Multiply(Local0, 10))) + } + // + // Package DTS not support. Report MAX temperature between all cores to OS. + // + Store(DTS1,Local0) + If(LGreater(DTS2, Local0)) + { + Store(DTS2,Local0) + } + If(LGreater(DTS3, Local0)) + { + Store(DTS3,Local0) + } + If(LGreater(DTS4, Local0)) + { + Store(DTS4,Local0) + } + Return(Add(2732, Multiply(Local0, 10))) + } + + // Source 2: Max Platform temprature returned by EC + // If EC enabled/avaialable + If(ECON) + { + // Store current reading in temporary variable + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PLMX)), Local0) // Max Platform temprature + Add(2732, Multiply(Local0, 10), Local0 ) + Store(Local0, PTMP) + Return(Local0) + } + + + // Return a static value if no source is available. + Return(3010) + } + } + + // Thermal Zone 1 = CPU Thermal Zone. + // CPU Thermal Zone is used for Passive Policy Control + // Since Passive Control implies reducing CPU IA core performance states, + // Only CPU's temperature must be used for that purpose. + ThermalZone(TZ01) + { + + // Temporary variable for holding the current temprature reading + Name(PTMP,3000) + + // Notifies ASL Code the current cooling mode. + // 0 - Active cooling + // 1 - Passive cooling + Method(_SCP, 1, Serialized) + { + Store(Arg0,CTYP) + } + + // Return the temperature at which the OS performs Critical Shutdown + Method(_CRT, 0, Serialized) + { + // Returns automatic thermal reporting temperature for CPU throttling if available and valid. + If(CondRefOf(\_PR.ACRT)) + { + If(LNotEqual(\_PR.ACRT,0)) + { + Return(Add(2732, Multiply(\_PR.ACRT, 10))) + } + } + + Return(Add(2732, Multiply(CRTT, 10))) + } + + // Return the CPU Temperature to the OS. + // CPU Temperature is the maximum temperature of all CPU IA cores + // Source 1: CPU temprature reported by DTS SMM + // Source 2: CPU temprature reported by EC via PECI + Method(_TMP,0,Serialized) + { + + If (LNot(ETMD)) // If Legacy TM is disabled, return static value + { + Return (3020) + } + + If (LEqual(DTSE, 0x3)) //Out Of Spec Condition occurred. Return critical temperature for OS shutdown + { + Return(Add(2832,Multiply(CRTT,10))) + } + + // Source 1: If DTS SMM enabled + // If Package Temp MSR is available, then send Package DTS Temp + // otherwise send Core DTS Temp + If(LEqual(DTSE, 0x01)) + { + If(LEqual(PKGA, 0x01)) + { + Store(PDTS, Local0) + Return(Add(2732, Multiply(Local0, 10))) + } + // + // Package DTS not support. Report MAX temperature between all cores to OS. + // + Store(DTS1,Local0) + If(LGreater(DTS2, Local0)) + { + Store(DTS2,Local0) + } + If(LGreater(DTS3, Local0)) + { + Store(DTS3,Local0) + } + If(LGreater(DTS4, Local0)) + { + Store(DTS4,Local0) + } + Return(Add(2732, Multiply(Local0, 10))) + } + + // If EC avialable/enabled + If(ECON) + { + + // Source 2: CPU temprature reported by EC via PECI + // Store current Integer part of reading in temporary variable + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PECH)), Local0) + Multiply(Local0, 10, Local0) + + // Fractional part of temprature + // Fractional part is in 1/64C, Fractional value = (PECL >> 2 ) * 1/64 + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PECL)), Local1) + ShiftRight(Local1, 2, Local1) + Store(Divide( Multiply(Local1, 10), 64), Local1) + + // Add fractional part to decimal part + Add( Local0, Local1, Local0) + + Add(2732, Local0, Local0 ) + Store(Local0, PTMP) + Return(Local0) + } + + + // Return a static value if no source is available. + Return(3030) + } + + // Return the Processor(s) used for Passive Cooling. + Method(_PSL, 0, Serialized) + { + If(LEqual(TCNT, 8)) + { + // CMP - Throttling controls eight logical CPUs. + Return(Package(){\_PR.CPU0,\_PR.CPU1,\_PR.CPU2,\_PR.CPU3,\_PR.CPU4,\_PR.CPU5,\_PR.CPU6,\_PR.CPU7}) + } + + If(LEqual(TCNT, 4)) + { + // CMP - Throttling controls four logical CPUs. + Return(Package(){\_PR.CPU0,\_PR.CPU1,\_PR.CPU2,\_PR.CPU3}) + } + + If(LEqual(TCNT, 2)) + { + // CMP - Throttling controls both CPUs. + Return(Package(){\_PR.CPU0,\_PR.CPU1}) + } + + Return(Package(){\_PR.CPU0}) + } + + // Returns the temperature at which the OS initiates CPU throttling. + Method(_PSV, 0, Serialized) + { + // Returns automatic thermal reporting temperature for CPU throttling if available and valid. + If(CondRefOf(\_PR.APSV)) + { + If(LNotEqual(\_PR.APSV,0)) + { + Return(Add(2732, Multiply(\_PR.APSV, 10))) + } + } + + Return(Add(2732, Multiply(PSVT, 10))) + } + + // Returns TC1 value used in the passive cooling formula. + Method(_TC1, 0, Serialized) + { + Return(TC1V) + } + + // Returns TC2 value used in the passive cooling formula. + Method(_TC2, 0, Serialized) + { + Return(TC2V) + } + + // Returns the sampling period used in the passive cooling formula. + Method(_TSP, 0, Serialized) + { + Return(TSPV) + } + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/Video.asl b/ReferenceCode/AcpiTables/Dsdt/Video.asl new file mode 100644 index 0000000..41a33b1 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Video.asl @@ -0,0 +1,48 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) +External(DIDX) +#endif + +// Brightness Notification: +// Generate a brightness related notification +// to the LFP if its populated. +// +// Arguments: +// Arg0: Notification value. +// +// Return Value: +// None + +Method(BRTN,1,Serialized) +{ + If(LEqual(And(DIDX,0x0F00),0x400)) + { + Notify(\_SB.PCI0.GFX0.DD1F,Arg0) + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/WPCN381U_COM.asl b/ReferenceCode/AcpiTables/Dsdt/WPCN381U_COM.asl new file mode 100644 index 0000000..494f25e --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/WPCN381U_COM.asl @@ -0,0 +1,775 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(UAR5) // Serial Port UART 5 +{ + Name(_HID, EISAID("PNP0501")) + + Name(_UID,3) + + // Status Method for UART 5. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // not set to Disabled in BIOS Setup. + + If(W381) + { + // Set the SIO to UART 5. + + Store(3,WR07) + + // Display UART 5 and return status. + + If(WR30) + { + Return(0x000F) + } + + Return(0x000D) + } + + Return(0x0000) + } + + // Disable Method for UART 5. + + Method(_DIS,0,Serialized) + { + Store(3,WR07) + Store(0,WR30) + } + + // Current Resource Setting Method for UART 5. + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags(){4} + }) + + // Set SIO to UART 5. + + Store(3,WR07) + + // Skip this sequence if the UART 5 Port is Disabled + // in BIOS Setup. + + If(W381) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Write IO and Length values into the Buffer. + + Store(WR60,IOH0) + Store(WR61,IOL0) + Store(WR60,IOH1) + Store(WR61,IOL1) + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + And(WR70,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for UART 5. + + // Build a Buffer with all valid COM Port Resources. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for UART 5. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQW) + + // Set the SIO to UART 5. + + Store(3,WR07) + + // Disable the device. + + Store(0,WR30) + + // Set the Base IO Address. + + Store(IOLO,WR61) + Store(IOHI,WR60) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If(LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + // Set the Decode Range so UART 5 works on ICH7 and + // future platforms. + + AND(IOD0,0xF8,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x07,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x01,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x05,IOD0) + } + } + + // Enable the device. + + Store(1,WR30) + } + + // D0 Method for COM Port. + + Method(_PS0,0,Serialized) + { + Store(3,WR07) + Store(1,WR30) + } + + // D3 Method for COM Port. + + Method(_PS3,0,Serialized) + { + Store(3,WR07) + Store(0,WR30) + } +} + +Device(UAR8) // Serial Port UART 8 +{ + Name(_HID, EISAID("PNP0501")) + + Name(_UID,4) + + // Status Method for UART 8. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // not set to Disabled in BIOS Setup. + + If(W381) + { + And(WR27,0x0E0,Local0) + If (LEqual (Local0, 0x00)) //SIORevID == 000x xxxxb => 374L(LDC2 card) + { + Store(0x2,WR07) + // Check if Serial port 2 is enabled + If(WR30) + { + Return(0x000F) + } + Return(0x000D) + } + } + Return(Zero) + } + + // Disable Method for UART 8. + + Method(_DIS,0,Serialized) + { + Store(2,WR07) + Store(0,WR30) + } + + // Current Resource Setting Method for UART 8. + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x02F8,0x02F8,0x01,0x08) + IRQNoFlags(){3} + }) + + // Set SIO to UART 8. + + Store(2,WR07) + + // Skip this sequence if the UART 8 Port is Disabled + // in BIOS Setup. + + If(W381) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Write IO and Length values into the Buffer. + + Store(WR60,IOH0) + Store(WR61,IOL0) + Store(WR60,IOH1) + Store(WR61,IOL1) + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + And(WR70,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for UART 8. + + // Build a Buffer with all valid UART 8 Port Resources. + + Name(_PRS,ResourceTemplate() + { + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for UART 8. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQW) + + // Set the SIO to UART 8. + + Store(2,WR07) + + // Disable the device. + + Store(0,WR30) + + // Set the Base IO Address. + + Store(IOLO,WR61) + Store(IOHI,WR60) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If(LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + // Set the Decode Range so UART 8 works on PCH and + // future platforms. + + AND(IOD0,0x8F,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x70,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x10,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x50,IOD0) + } + } + + // Enable the device. + + Store(1,WR30) + } + + // D0 Method for UART 8 Port. + + Method(_PS0,0,Serialized) + { + Store(2,WR07) + Store(1,WR30) + } + + // D3 Method for UART 8 Port. + + Method(_PS3,0,Serialized) + { + Store(2,WR07) + Store(0,WR30) + } +} +//Resource for WPCD376I SP3 Device(LDN 0x16) +Device(LD16) // LDN 0x16 +{ + Name(_HID, EISAID("PNP0501")) + Name(_UID,5) + + // Status Method for LDN 0x16. Keep it Disabled as this LDN is part of Consumer IR device + Method(_STA,0,Serialized) + { + Return(0x0000) + } + + // Possible Resource Setting Method for LDN 0x16. + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){3} + } + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + EndDependentFn() + }) +} +//Resource for WPCD376I CIR Device(LDN 0x15) +Device(LD15) // LDN 0x15 +{ + Name(_HID, EISAID("WEC0001")) + Name(_UID,6) + + // Status Method for LDN 0x15. Keep it Disabled as this LDN is part of Consumer IR device + Method(_STA,0,Serialized) + { + Return(0x0000) + } + + // Possible Resource Setting Method for CIR. + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO (Decode16, 0x07D0, 0x07D0, 0x01, 0x10) + IO (Decode16, 0x07C0, 0x07C0, 0x01, 0x10) + } + EndDependentFn() + }) +} + +//WPCD376I Consumer IR device +Device (ECIR) +{ + Name (_HID, EISAID("WEC1022")) + Name (_UID, One) + + OperationRegion(CIRR,SystemIO,0x7C0,0x20) + Field(CIRR,ByteAcc,NoLock,Preserve) + { + Offset(0x15), //CIR wake up base address offset 5 [0x7D0 + 5] + RXEE, 3, + , 5, + } + + Method (_STA, 0, NotSerialized) + { + If(W381) + { + And(WR27,0x0E0,Local0) + Store(0x15,WR07) + If (LAnd(LEqual (Local0, 0x80), LOr(WR60,WR61))) //SIORevID == 100x xxxxb => 376I and Resource allocated + { + If (WR30) //Check if CIR device is enabled. + { + Return(0x000F) + } + Return(0x000D) + } + } + Return(Zero) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x15, WR07) + Store (Zero, WR30) + Store (0x16, WR07) + Store (Zero, WR30) + } + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO (Decode16, 0x0, 0x0, 0x01, 0x10) + IO (Decode16, 0x0, 0x0, 0x01, 0x10) + IO (Decode16, 0x0, 0x0, 0x08, 0x08) + IRQNoFlags (){0} + }) + + CreateByteField(BUF0,0x02,IO00) + CreateByteField(BUF0,0x03,IO01) + CreateByteField(BUF0,0x04,IO10) + CreateByteField(BUF0,0x05,IO11) + CreateByteField(BUF0,0x0a,IO20) + CreateByteField(BUF0,0x0b,IO21) + CreateByteField(BUF0,0x0c,IO30) + CreateByteField(BUF0,0x0d,IO31) + CreateByteField(BUF0,0x12,IO40) + CreateByteField(BUF0,0x13,IO41) + CreateByteField(BUF0,0x14,IO50) + CreateByteField(BUF0,0x15,IO51) + CreateWordField(BUF0,0x19,IRQW) + + // Set the SIO to SP3. + Store(0x16,WR07) + // Set the Base IO Address. + Store(WR61,IO40) + Store(WR60,IO41) + Store(WR61,IO50) + Store(WR60,IO51) + // Write the IRQ value into the Buffer. + And(WR70,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + + //set resource for CIr device + // Set the SIO to SP3. + Store(0x15,WR07) + // Set the Base IO Address. + Store(WR61,IO00) + Store(WR60,IO01) + Store(WR61,IO10) + Store(WR60,IO11) + + Store(WR63,IO20) + Store(WR62,IO21) + Store(WR63,IO30) + Store(WR62,IO31) + + Return(BUF0) + } + + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO (Decode16, 0x07D0, 0x07D0, 0x01, 0x10) + IO (Decode16, 0x07C0, 0x07C0, 0x01, 0x10) + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags(){3} + } + StartDependentFn(0,2) + { + IO (Decode16, 0x07D0, 0x07D0, 0x01, 0x10) + IO (Decode16, 0x07C0, 0x07C0, 0x01, 0x10) + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + StartDependentFn(0,2) + { + IO (Decode16, 0x07D0, 0x07D0, 0x01, 0x10) + IO (Decode16, 0x07C0, 0x07C0, 0x01, 0x10) + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + StartDependentFn(0,2) + { + IO (Decode16, 0x07D0, 0x07D0, 0x01, 0x10) + IO (Decode16, 0x07C0, 0x07C0, 0x01, 0x10) + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + StartDependentFn(0,2) + { + IO (Decode16, 0x07D0, 0x07D0, 0x01, 0x10) + IO (Decode16, 0x07C0, 0x07C0, 0x01, 0x10) + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + EndDependentFn () + }) + + Method (_SRS, 1, NotSerialized) + { + CreateByteField(Arg0,0x02,IO00) + CreateByteField(Arg0,0x03,IO01) + CreateByteField(Arg0,0x0a,IO20) + CreateByteField(Arg0,0x0b,IO21) + CreateByteField(Arg0,0x12,IO40) + CreateByteField(Arg0,0x13,IO41) + CreateWordField(Arg0,0x19,IRQW) + + // Set the SIO to SP3. + Store(0x16,WR07) + // Set the Base IO Address. + Store(IO40, WR61) + Store(IO41, WR60) + // Set the IRQ. + FindSetRightBit(IRQW,Local0) + If(LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + AND(IOD0,0x8F,IOD0) // Clear all bits. + If(LEqual(IO41,0x03)) // Address = 0x3xx + { + If(LEqual(IO40,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x70,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IO40,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x10,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x50,IOD0) + } + } + + //set resource for CIr device + // Set the SIO to SP3. + Store(0x15,WR07) + // Set the Base IO Address. + Store(IO00, WR61) + Store(IO01, WR60) + Store(IO20, WR63) + Store(IO21, WR62) + Store (0x15, WR07) + Store (One, WR30) + Store (0x16, WR07) + Store (0x82, WRF0) + Store (One, WR30) + } + + Method (_S3D, 0, NotSerialized) + { + Return (0x02) + } + + Method (_S4D, 0, NotSerialized) + { + Return (0x02) + } + + Method (_S3W, 0, NotSerialized) + { + Return (0x02) + } + + Method (_S4W, 0, NotSerialized) + { + Return (0x02) + } + + Name (CPS4, Package (0x02) + { + 0x1D, + 0x04 + }) + Method (_PRW, 0, NotSerialized) + { + Return (CPS4) + } + + Method (_PSW, 1, NotSerialized) + { + If (LEqual (Arg0, Zero)) + { + Store (Zero, RXEE) + } + If (LEqual (Arg0, One)) + { + Store (0x07, RXEE) + } + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/WPCN381U_LPT.ASL b/ReferenceCode/AcpiTables/Dsdt/WPCN381U_LPT.ASL new file mode 100644 index 0000000..2a2cb9e --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/WPCN381U_LPT.ASL @@ -0,0 +1,988 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + +// This ASL file will support the LPT in Output, BiDirectional, EPP, +// & ECP mode. Only 1 of these devices will be shown by the OS at any +// given time, and that one will depend on the BIOS configuration. +Scope(\_SB.PCI0.LPCB.WPCN){ + +Device(LPT2) // Printer, Output Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,2) + + // Status Method for LPT-Output Mode. + + Method(_STA,0,Serialized) + { + // Output mode = 000x xxxxb - check that no bits are set. + + Store(1,WR07) + If(LEqual(And(WRF0,0xE0),0x00)) + { + // LPT is in Output Mode. Only report resources + // to the OS if the SIO Device is not set to + // Disabled in BIOS Setup. + + If(W381) + { + // Set SIO to LPT. + + Store(1,WR07) + + // Display POUT and return Status. + + If(WR30) + { + Return(0x000F) + } + + Return(0x000D) + } + } + + Return(0x0000) + } + + // Disable Method for LPT-Output Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,WR07) + + If(LEqual(And(WRF0,0xE0),0x00)) + { + Store(0,WR30) + } + + } + + // Current Resource Setting Method for LPT-Output Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x04) + IRQNoFlags(){7} + }) + + // Skip this sequence if the LPT Device is not set + // to Output Mode. + + If(LEqual(And(WRF0,0xE0),0x00)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Set SIO to LPT. + Store(1,WR07) + + // Write IO and Length values into the Buffer. + + Store(WR61,IOL0) + Store(WR60,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(4,LEN0) + + // Write the IRQ value into the Buffer. + + If(And(WR70,0x0F)) + { + ShiftLeft(One,And(WR70,0x0F),IRQW) + } + Else + { + Store(Zero,IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-Output Mode. + // Build a Buffer with all valid LPT Port Resources. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){5} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-Output Mode. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,WR07) + + // Disable the LPT. + + Store(0,WR30) + + // Disable the DMA channels. + + Store(4,WR74) + + // Set the Base IO Address. + + Store(IOL0,WR61) + Store(IOH0,WR60) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + // Set the Decode Range so POUT works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x3xx + { + If(LEqual(IOL0,0x78)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else + { + Or(IOD1,0x02,IOD1) // Address = 0x3BC + } + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + Store(1,WR30) + + // Set to Output Mode. + And(WRF0,0x0F,WRF0) + + + + } + + // D0 Method for LPT-Output Mode. + + Method(_PS0,0,Serialized) + { + Store(1,WR07) + Store(1,WR30) + + } + + // D3 Method for LPT-Output Mode. + + Method(_PS3,0,Serialized) + { + Store(1,WR07) + Store(0,WR30) + + } +} + +Device(PBI2) // Printer, BiDirectional Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,2) + + // Status Method for LPT-BiDirectional Mode. + + Method(_STA,0,Serialized) + { + // BiDirectional mode = 001x xxxxb, so check that only + // bit 5 is set. + Store(1,WR07) + + If(LEqual(And(WRF0,0xE0),0x20)) + { + // LPT is in BiDirectional Mode. Only report + // resources to the OS if the SIO Device is not + // set to Disabled in BIOS Setup. + + If(W381) + { + // Display PBID and return Status. + + If(WR30) + { + Return(0x000F) + } + + Return(0x000D) + } + } + + Return(0x0000) + } + + // Disable Method for LPT-BiDirectional Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,WR07) + + If(LEqual(And(WRF0,0xE0),0x20)) + { + Store(0,WR30) + } + } + + // Current Resource Setting Method for LPT-BiDirectional Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x04) + IRQNoFlags(){7} + }) + + // Skip this sequence if the LPT Device is not set + // to BiDirectional Mode. + + If(LEqual(And(WRF0,0xE0),0x20)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,WR07) + + // Write IO and Length values into the Buffer. + + Store(WR61,IOL0) + Store(WR60,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(4,LEN0) + + // Write the IRQ value into the Buffer. + + If(And(WR70,0x0F)) + { + ShiftLeft(One,And(WR70,0x0F),IRQW) + } + Else + { + Store(Zero, IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-BiDirectional Mode. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){5} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-BiDirectional Mode. + + Method(_SRS,1,Serialized) + { + // Arg0 passed into _SRS is the buffer identical to BUF0. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + Store(1,WR07) + + // Disable the LPT. + + Store(0,WR30) + + // Disable the DMA channels. + + Store(4,WR74) + + // Set the Base IO Address. + + Store(IOL0,WR61) + Store(IOH0,WR60) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + // Set the Decode Range so PBID works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x3xx + { + If(LEqual(IOL0,0x78)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else + { + Or(IOD1,0x02,IOD1) // Address = 0x3BC + } + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,WR30) + + // Set to Bi-Directional Mode. + + Or(And(WRF0,0x0F),0x20,WRF0) + + + } + + // D0 Method for LPT-BiDirectional Mode. + + Method(_PS0,0,Serialized) + { + Store(1,WR07) + Store(1,WR30) + + } + + // D3 Method for LPT-BiDirectional Mode. + + Method(_PS3,0,Serialized) + { + Store(1,WR07) + Store(0,WR30) + } +} + +Device(PEP2) // Printer, EPP Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,2) + + // Status Method for LPT-EPP Mode. + + Method(_STA,0,Serialized) + { + // EPP 1.9 mode = 011x xxxxb. + + Store(1,WR07) + If(LOr(LEqual(And(WRF0,0xE0),0x60), LEqual(And(WRF0,0xE0),0x40))) + { + // LPT is in EPP Mode. Only report resources + // to the OS if the SIO Device is not set to + // Disabled in BIOS Setup. + + // Display PEPP and return Status. + + If(WR30) + { + Return(0x000F) + } + Else + { + Return(0x000D) + } + } + + + Return(0x0000) + } + + // Disable Method for LPT-EPP Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,WR07) + + If(LOr(LEqual(And(WRF0,0xE0),0x60), LEqual(And(WRF0,0xE0),0x40))) + { + Store(0,WR30) + } + } + + // Current Resource Setting Method for LPT-EPP Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x08) + IRQNoFlags(){7} + }) + + // Skip this sequence if the LPT Device is not set + // to EPP Mode. + + If(LOr(LEqual(And(WRF0,0xE0),0x60), LEqual(And(WRF0,0xE0),0x40))) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,WR07) + + // Write IO and Length values into the Buffer. + + Store(WR61,IOL0) + Store(WR60,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + If(And(WR70,0x0F)) + { + ShiftLeft(One,And(WR70,0x0F),IRQW) + } + Else + { + Store(Zero, IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-EPP Mode. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IRQNoFlags(){5} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-EPP Mode. + + Method(_SRS,1,Serialized) + { + // Arg0 passed into _SRS is the buffer identical to BUF0. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + Store(1,WR07) + + // Disable the LPT. + + Store(0,WR30) + + // Disable the DMA channels. + + Store(4,WR74) + + // Set the Base IO Address. + + Store(IOL0,WR61) + Store(IOH0,WR60) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + // Set the Decode Range so PEPP works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,WR30) + + // Set to SPP + EPP 1.9 Mode. + + Or(And(WRF0,0x0F),0x60,WRF0) + + } + + // D0 Method for LPT-EPP Mode. + + Method(_PS0,0,Serialized) + { + Store(1,WR07) + Store(1,WR30) + } + + // D3 Method for LPT-EPP Mode. + + Method(_PS3,0,Serialized) + { + Store(1,WR07) + Store(0,WR30) + } +} + +Device(PEC2) // Printer, ECP Mode +{ + Name(_HID,EISAID("PNP0401")) + Name(_UID,2) + + // Status Method for LPT-ECP Mode. + + Method(_STA,0,Serialized) + { + // ECP mode = 111x xxxxb. + + Store(1,WR07) + If(LOr(LEqual(And(WRF0,0xE0),0xE0), LEqual(And(WRF0,0xE0),0x80))) + { + // LPT is in ECP Mode. Only report resources + // to the OS if the SIO Device is not set to + // Disabled in BIOS Setup. + + + + // Display PECP and return Status. + + If(WR30) + { + Return(0x000F) + } + Else + { + Return(0x000D) + } + + } + + Return(0x0000) + } + + // Disable Method for LPT-ECP Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,WR07) + + If(LOr(LEqual(And(WRF0,0xE0),0xE0), LEqual(And(WRF0,0xE0),0x80))) + { + Store(0,WR30) + } + } + + // Current Resource Setting Method for LPT-ECP Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x08) + IO(Decode16,0x0778,0x0778,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16,){1} + }) + + // Skip this sequence if the LPT Device is not set + // to ECP Mode. + + If(LOr(LEqual(And(WRF0,0xE0),0xE0), LEqual(And(WRF0,0xE0),0x80))) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateByteField(BUF0,0x0A,IOL2) + CreateByteField(BUF0,0x0B,IOH2) + CreateByteField(BUF0,0x0C,IOL3) + CreateByteField(BUF0,0x0D,IOH3) + CreateByteField(BUF0,0x0F,LEN1) + CreateWordField(BUF0,0x11,IRQW) + CreateByteField(BUF0,0x14,DMA0) + + // Set SIO to LPT. + + Store(1,WR07) + + // Write IO and Length values into the Buffer. + + Store(WR61,IOL0) + Store(WR60,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(IOL0,IOL2) + Store(Add(0x4,IOH0),IOH2) + Store(IOL0,IOL3) + Store(Add(0x4,IOH0),IOH3) + Store(8,LEN0) + Store(8,LEN1) + + // Write the IRQ value into the Buffer. + + And(WR70,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + + // Write the DMA value into the Buffer. + + Store(WR74,Local0) + If(LEqual(Local0,0x04)) + { + Store(Zero,DMA0) + } + Else + { + ShiftLeft(One,Local0,DMA0) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-ECP Mode. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IO(Decode16,0x778,0x778,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IO(Decode16,0x678,0x678,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IO(Decode16,0x778,0x778,0x01,0x08) + IRQNoFlags(){5} + DMA(Compatibility,NotBusMaster,Transfer8_16){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IO(Decode16,0x678,0x678,0x01,0x08) + IRQNoFlags(){5} + DMA(Compatibility,NotBusMaster,Transfer8_16){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IO(Decode16,0x778,0x778,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16){1} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IO(Decode16,0x678,0x678,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16){1} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IO(Decode16,0x778,0x778,0x01,0x08) + IRQNoFlags(){5} + DMA(Compatibility,NotBusMaster,Transfer8_16){1} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IO(Decode16,0x678,0x678,0x01,0x08) + IRQNoFlags(){5} + DMA(Compatibility,NotBusMaster,Transfer8_16){1} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-ECP Mode. + + Method(_SRS,1,Serialized) + { + // Arg0 passed into _SRS is the buffer identical to BUF0. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x11,IRQW) + CreateByteField(Arg0,0x14,DMA0) + + Store(1,WR07) + + // Disable the LPT. + + Store(0,WR30) + + + // Set the Base I/O Address + + Store(IOL0,WR61) + Store(IOH0,WR60) + + // Set the IRQ + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + // Set the DMA Channel + + FindSetRightBit(DMA0,Local0) + If (LNotEqual(DMA0,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR74) + + // Set the Decode Range so PECP works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,WR30) + + // Set to ECP Mode with EPP Mode 4 support. + + Or(WRF0,0xF0,WRF0) + + } + + // D0 Method for LPT-ECP Mode. + + Method(_PS0,0,Serialized) + { + Store(1,WR07) + Store(1,WR30) + } + + // D3 Method for LPT-ECP Mode. + + Method(_PS3,0,Serialized) + { + Store(1,WR07) + Store(0,WR30) + } +} + +} // End of Scope() diff --git a/ReferenceCode/AcpiTables/Dsdt/WPCN381U_SIO.asl b/ReferenceCode/AcpiTables/Dsdt/WPCN381U_SIO.asl new file mode 100644 index 0000000..9bf40f5 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/WPCN381U_SIO.asl @@ -0,0 +1,98 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(WPCN) +{ + Name(_HID,EISAID("PNP0A05")) + + Name(_UID,3) + + // Status Method for the National SIO. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // present on the Docking Board. + + If(W381) + { + Return(0x000F) + } + + Return(0x0000) + } + + // Define the SIO Index/Data Registers as an ACPI Operating + // Region. These registers will be used communicate to the SIO. + + OperationRegion(WPCN, SystemIO, 0x02E, 0x02) + Field(WPCN, ByteAcc, Lock, Preserve) + { + INDX, 8, + DATA, 8 + } + + // Use ACPI Defined IndexField so consecutive Index/Data I/Os are + // assured to be uninterrupted. + + IndexField(INDX, DATA, ByteAcc, Lock, Preserve) + { + Offset(0x07), // Logical Device Number. + WR07, 8, + Offset(0x20), // SIO Configuration and ID. + WR20, 8, + WR21, 8, + WR22, 8, + WR23, 8, + WR24, 8, + WR25, 8, + WR26, 8, + WR27, 8, + WR28, 8, + WR29, 8, + WR2A, 8, + Offset(0x30), // Logical Device Activate. + WR30, 8, + Offset(0x60), // I/O Space Configuration. + WR60, 8, + WR61, 8, + WR62, 8, + WR63, 8, + Offset(0x70), // Interrupt Configuration. + WR70, 8, + WR71, 8, + Offset(0x74), // DMA Configuration. + WR74, 8, + WR75, 8, + Offset(0xF0), // Special Logical Device Configuration. + WRF0, 8, + WRF1, 8 + } + + Include ("WPCN381U_COM.ASL") + Include ("WPCN381U_LPT.ASL") +} diff --git a/ReferenceCode/AcpiTables/Dsdt/token.asl b/ReferenceCode/AcpiTables/Dsdt/token.asl new file mode 100644 index 0000000..d62a151 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/token.asl @@ -0,0 +1,145 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Name(SP2O, 0x4e) // Super I/O (SMSC 1007) Index/Data configuration port for ASL. +Name(SP1O, 0x164e) // Super I/O (SMSC 1007) Index/Data configuration port for ASL. +Name(IO1B, 0x600) // Super I/O (SMSC 1007) GPIO base address +Name(IO1L, 0x70) // Super I/O (SMSC 1007) GPIO base address length +Name(IO2B, 0x680) // Super I/O (SMSC 1007) PME base address +Name(IO2L, 0x20) // Super I/O (SMSC 1007) PME base address length +Name(IO3B, 0x290) // Super I/O (SMSC 1007) HHM Base Address +Name(IO3L, 0x10) // Super I/O (SMSC 1007) HHM base address length +Name(SP3O, 0x2e) // Super I/O (Winbond 3xx) Index/Data configuration port for ASL. +Name(IO4B, 0xa20) // Super I/O (Winbond 3xx) GPIO base address length +Name(IO4L, 0x20) // Super I/O (Winbond 3xx) GPIO base address length +Name(HSCS, 0x1) // Hitachi H8S2113D Super I/O COM port status. +Name(MCHB, 0xfed10000) // MCH BAR address +Name(MCHL, 0x8000) // MCH BAR length +Name(EGPB, 0xfed19000) // EP BAR address +Name(EGPL, 0x1000) // EP BAR length +Name(DMIB, 0xfed18000) // DMI BAR address +Name(DMIL, 0x1000) // DMI BAR length +Name(IFPB, 0xfed14000) // Base addrerss of 4K MMIO Window any write to which will FLUSH GMCH Global Write Buffer to let software + // guarantee coherency between writes from an isochronous agent and writes from the CPU. +Name(IFPL, 0x1000) // Length of the MMIO region above. +Name(PEBS, EDKII_GLUE_PciExpressBaseAddress) // PCI Express BAR address +Name(PELN, PLATFORM_PCIEXPRESS_LENGTH) // PCI Express BAR length +Name(TTTB, 0xfed20000) // +Name(TTTL, 0x20000) // +Name(SMBS, 0xefa0) // SMBus I/O Registes Base Address +Name(SMBL, 0x10) // SMBus I/O Registes Range +Name(PBLK, 0x1810) // Boot-strap CPU Control Block register address. Use return value of PM_BASE_ADDRESS with proper offset. +Name(PMBS, 0x1800) // ASL alias for ACPI I/O base address. +Name(PMLN, 0x100) // Power Management registers block length +Name(LVL2, 0x1814) // Processor LVL2 register I/O address. +Name(LVL3, 0x1815) // Processor LVL3 register I/O address. +Name(LVL4, 0x1816) // Processor LVL4 register I/O address. +Name(SMIP, 0xb2) // I/O port to triggle SMI +Name(GPBS, 0x800) // GPIO Register Block address +Name(GPLN, 0x400) // GPIO Register Block length +Name(APCB, 0xfec00000) // Default I/O APIC(s) memory start address, 0x0FEC00000 - default, 0 - I/O APIC's disabled +Name(APCL, 0x1000) // I/O APIC(s) memory decoded range, 0x1000 - default, 0 - I/O APIC's not decoded +Name(PM30, 0x1830) // SMI Control Register +Name(SRCB, 0xfed1c000) // RCBA (Root Complex Base Address) +Name(SRCL, 0x4000) // RCBA length +Name(HPTB, 0xfed00000) // Same as HPET_BASE_ADDRESS for ASL use +Name(HPTC, 0xfed1f404) // High Precision Event Timer Configuration Register +Name(ACPH, 0xde) // North Bridge Scratchpad Data Register for patch ACPI. +Name(ASSB, 0x0) // ACPI Sleep State Buffer for BIOS Usage. +Name(AOTB, 0x0) // ACPI OS Type Buffer for BIOS Usage. +Name(AAXB, 0x0) // ACPI Auxiliary Buffer for BIOS Usage. +Name(PEHP, 0x1) // _OSC: Pci Express Native Hot Plug Control +Name(SHPC, 0x1) // _OSC: Standard Hot Plug Controller (SHPC) Native Hot Plug control +Name(PEPM, 0x1) // _OSC: Pci Express Native Power Management Events control +Name(PEER, 0x1) // _OSC: Pci Express Advanced Error Reporting control +Name(PECS, 0x1) // _OSC: Pci Express Capability Structure control +Name(ITKE, 0x0) // This will be overridden by the ITK module. +Name(DSSP, 0x0) // ON - Disable SATA Software Setting Preservation feature so that it will not preserve the state after hardware reset. i.e. After a hardware reset HDD will change security state as power-on. OFF - Do not change it in POST, leave it as default (enabled). +Name(FHPP, 0x0) // Set to 1 to always prompt for HDD password (in AHCI mode). +Name(FMBL, 0x1) // Platform Flavor - Mobile flavor for ASL code. +Name(FDTP, 0x2) // Platform Flavor - Desktop flavor for ASL code. +Name(FUPS, 0x3) // Platform Flavor - UP Server flavor for ASL code. +Name(FEMD, 0x4) // Platform Flavor - Embedded flavor for ASL code. +Name(BGR, 0x1) // Haswell - Grays Reef Board ID for ASL code. +Name(BFR, 0x2) // Haswell - Flathead Rock Board ID for ASL code. +Name(BBR, 0x3) // Haswell - Basking Ridge Board ID for ASL code. +Name(BWC, 0x4) // Haswell - Walnut Canyon Board ID for ASL code. +Name(BGRP, 0x9) // Haswell - Grays Reef PPV Board ID for ASL code. +Name(BGRC, 0xa) // Haswell - Grays Reef CPV Board ID for ASL code. +Name(BFRP, 0xb) // Haswell - Flathead Rock PPV Board ID for ASL code. +Name(BBRP, 0xc) // Haswell - Basking Ridge PPV Board ID for ASL code. +Name(BRPS, 0x10) // Haswell - STHIPPVRSVD1 Board ID for ASL code. +Name(BRCS, 0x11) // Haswell - STHICPVRSVD2 Board ID for ASL code. +Name(BRDS, 0x12) // Haswell - STHIDOERSVD3 Board ID for ASL code. +Name(BR4S, 0x13) // Haswell - STHIPPVRSVD4 Board ID for ASL code. +Name(BR5S, 0x14) // Haswell - STHIPPVRSVD5 Board ID for ASL code. +Name(BWT1, 0x20) // Haswell - WhiteTip Mountain1 Board ID for ASL code. +Name(BW1P, 0x21) // Haswell - WhiteTip Mountain1 PPV Board ID for ASL code. +Name(BW2C, 0x22) // Haswell - WhiteTip Mountain2 Board ID for ASL code. +Name(BW2P, 0x23) // Haswell - WhiteTip Mountain2 PPV Board ID for ASL code. +Name(BSPC, 0x24) // Haswell - Sawtooth Peak Board ID for ASL code. +Name(BSPP, 0x25) // Haswell - Sawtooth Peak PPV Board ID for ASL code. +Name(BTS, 0x26) // Haswell - TopSham Board ID for ASL code. +Name(BICO, 0x27) // Haswell - WhiteTip Mountain2 CDK Open Chasis Board ID for ASL code. +Name(BICC, 0x28) // Haswell - WhiteTip Mountain2 CDK Closed Chasis Board ID for ASL code. +Name(BHB, 0x30) // Haswell - Harris Beach FFRD Board ID for ASL code. +Name(BFS2, 0x31) // Haswell - FFRD SKU2 Board ID for ASL code. +Name(BFS3, 0x32) // Haswell - FFRD SKU3 Board ID for ASL code. +Name(BFS4, 0x33) // Haswell - FFRD SKU4 Board ID for ASL code. +Name(BRH, 0x35) // Haswell - Reed Harbor TDV Board ID for ASL code. + +Name(BFHC, 0x40) // Haswell - Flathead Creek Board ID for ASL code +Name(BFD1, 0x41) // Haswell - Flathead Creek DOE1 Board ID for ASL code. +Name(BFD2, 0x42) // Haswell - Flathead Creek DOE2 Board ID for ASL code. +Name(BFCC, 0x43) // Haswell - Flathead Creek CRB Board ID for ASL code. +Name(BHCP, 0x44) // Haswell - Haddock Creek Board ID for ASL code. +Name(BCOC, 0x45) // Haswell - CRB OC Board ID for ASL code. +Name(BFHP, 0x46) // Haswell - Flathead Creek PPV Board ID for ASL code. +Name(BFCP, 0x47) // Haswell - Flathead Creek CPV Board ID for ASL code. +Name(BTDT, 0x50) // BidwellBar - TumaloFalls DT Board ID for ASL code. +Name(BTMB, 0x51) // BidwellBar - TumaloFalls MB Board ID for ASL code. +Name(BBGB, 0x52) // Big Creek MB Board ID for ASL code. +Name(BHC2, 0x53) // Haswell - Haddock Creek Fab2 Board ID for ASL code. + +Name(TCGM, 0x1) // Flag to check TCG Module support in platform.asl +Name(TRTP, 0x1) // PPM IO Trap flag +Name(WDTE, 0x1) // Flag for WDT enabled/disabled +Name(TRTD, 0x2) // DTS IO Trap flag +Name(TRTI, 0x3) // IGD IO Trap flag +Name(PFTI, 0x4) // PFAT IO Trap flag +Name(GCDD, 0x1) // SW_SMI_GET_CURRENT_DISPLAY_DEVICE +Name(DSTA, 0xa) // SW_SMI_DISPLAY_SWITCH_TOGGLE_ACPI +Name(DSLO, 0xc) // SW_SMI_DISPLAY_SWITCH_LID_OPEN_ACPI +Name(DSLC, 0xe) // SW_SMI_DISPLAY_SWITCH_LID_CLOSE_ACPI +Name(PITS, 0x10) // SW_SMI_POPUP_ICON_TOGGLE +Name(SBCS, 0x12) // SW_SMI_SET_BACKLIGHT_CONTROL +Name(SALS, 0x13) // SW_SMI_SET_ALI_LEVEL +Name(LSSS, 0x2a) // SW_SMI_LID_STATE_SWITCH +Name(SOOT, 0x35) // SW_SMI_SAVE_OSB_OS_TYPE +Name(PDBR, 0x4d) // SW_SMI_PCIE_DOCK_BRIDGE_RESOURCE_PATCH +Name(DPPB, 0xfed98000) // Thermal Solution Resource Base Address +Name(DPPL, 0x8000) // Length of Thermal Solution Resource Base Address diff --git a/ReferenceCode/AcpiTables/Dsdt/wcam.asl b/ReferenceCode/AcpiTables/Dsdt/wcam.asl new file mode 100644 index 0000000..8d75b2d --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/wcam.asl @@ -0,0 +1,21 @@ +Device(WCAM) +{ + Name(_ADR, 0x05) + Method(_UPC, 0, Serialized) { + Name(UPCP, Package() { 0x00,0xFF,0x00,0x00 }) // Not connectable, Proprietary connector + Return(UPCP) + } + + Method(_PLD, 0, Serialized) { + Name(PLDP, Package(1) + { + Buffer(0x14) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Revision 2 + 0x24, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Not visible, Center + 0xC8, 0x00, 0xA0, 0x00 + } + }) + Return (PLDP) + } +}
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