diff options
| author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
|---|---|---|
| committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
| commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
| tree | eebe9b0d0ca03062955223097e57da84dd618b9a /ReferenceCode/AcpiTables/SampleCode | |
| download | zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz | |
Diffstat (limited to 'ReferenceCode/AcpiTables/SampleCode')
19 files changed, 5369 insertions, 0 deletions
diff --git a/ReferenceCode/AcpiTables/SampleCode/Lpit/LowPowerIdleTable.h b/ReferenceCode/AcpiTables/SampleCode/Lpit/LowPowerIdleTable.h new file mode 100644 index 0000000..9ef102b --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/Lpit/LowPowerIdleTable.h @@ -0,0 +1,68 @@ +/** @file + +This file defines the Low Power Idle Table definition, defined by +Intel IA-PC LPIT (Low Power Idle Table) Specification draft. + +@copyright +Copyright (c) 2013, Intel Corporation. All rights reserved.<BR> +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. +This file contains an 'Intel Peripheral Driver' and is +licensed for Intel CPUs and chipsets under the terms of your +license agreement with Intel or your vendor. This file may +be modified by the user, subject to additional terms of the +license agreement + +**/ + +#ifndef _LOW_POWER_IDLE_TABLE_H_ +#define _LOW_POWER_IDLE_TABLE_H_ + +// +// Include files +// +#include "Acpi2_0.h" + +// +// LPIT Definitions +// + +#define EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION 0x1 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +typedef union _EFI_ACPI_LPI_STATE_FLAGS { + struct { + UINT32 Disabled :1; + UINT32 CounterUnavailable :1; + UINT32 Reserved :30; + }; + UINT32 AsUlong; +} EFI_ACPI_LPI_STATE_FLAGS, *PEFI_ACPI_LPI_STATE_FLAGS; + +// Only Mwait LPI here: + +typedef struct _EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR { + UINT32 Type; // offset: 0 + UINT32 Length; // offset: 4 + UINT16 UniqueId; // offset: 8 + UINT8 Reserved[2]; // offset: 10 + EFI_ACPI_LPI_STATE_FLAGS Flags; // offset: 12 + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EntryTrigger; // offset: 16 + UINT32 Residency; // offset: 28 + UINT32 Latency; // offset: 32 + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResidencyCounter; // offset: 36 + UINT64 ResidencyCounterFrequency; //offset: 48 +} EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR; + +#pragma pack() + +#endif //_LOW_POWER_IDLE_TABLE_H_ diff --git a/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.act b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.act new file mode 100644 index 0000000..82849de --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.act @@ -0,0 +1,110 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + --*/ +/*++ + +Copyright (c) 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + +Lpit.act + +Abstract: + +This file contains a structure definition for the ACPI Low Power Idle Table +(LPIT). The contents of this file should only be modified +for bug fixes, no porting is required. The table layout is defined in +LowPowerIdleTable.h and the table contents are defined in Lpit.h. + +--*/ + + // + // Statements that include other files + // + +#include "Lpit.h" + + // + // Low Power Idle Table + // Please modify all values in Lpit.h only. + // + +EFI_ACPI_LOW_POWER_IDLE_TABLE Lpit = { + + // + // Header + // + + + EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE, + sizeof (EFI_ACPI_LOW_POWER_IDLE_TABLE), + EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION , + + // + // Checksum will be updated at runtime + // + 0x00, + + // + // It is expected that these values will be updated at runtime + // + 'A', 'L', 'A', 'S', 'K', 'A', + + 0, + EFI_ACPI_OEM_LPIT_REVISION, + EFI_ACPI_CREATER_ID, + EFI_ACPI_CREATER_REVISION, + + + + // + // Descriptor + // + { + { + EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE, + sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR), + EFI_ACPI_HSW_LPI_AUDIO_ID, + {0,0}, + {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, // Flags + EFI_ACPI_HSW_LPI_TRIGGER, //EntryTrigger + EFI_ACPI_HSW_LPI_MIN_RES, //Residency + EFI_ACPI_HSW_LPI_LATENCY, //Latency + EFI_ACPI_HSW_LPI_RES_COUNTER, //ResidencyCounter + EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_TSC //Residency counter frequency + }, + { + EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE, + sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR), + EFI_ACPI_HSW_LPI_CS_ID, + {0,0}, + {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, // Flags + EFI_ACPI_HSW_LPI_TRIGGER, //EntryTrigger + EFI_ACPI_HSW_LPI_MIN_RES, //Residency + EFI_ACPI_HSW_LPI_LATENCY, //Latency + EFI_ACPI_HSW_LPI_RES_COUNTER, //ResidencyCounter + EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_TSC //Residency counter frequency + } + } + +}; + +VOID +main ( + VOID + ) + +{ +}
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.cif b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.cif new file mode 100644 index 0000000..b9f6d91 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.cif @@ -0,0 +1,12 @@ +<component> + name = "lpit" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\SampleCode\Lpit\" + RefName = "lpit" +[files] +"LowPowerIdleTable.h" +"lpit.act" +"lpit.h" +"lpit.mak" +"lpit.sdl" +<endComponent> diff --git a/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.h b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.h new file mode 100644 index 0000000..17e6eed --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.h @@ -0,0 +1,114 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + --*/ +/*++ + +Copyright (c) 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + +Lpit.h + +Abstract: + +This file describes the contents of the ACPI Low Power Idle Table (LPIT). +All changes to the LPIT contents should be done in this file. + + + +--*/ + +#ifndef _LPIT_H_ +#define _LPIT_H_ + +// +// Statements that include other files +// + +#include "LowPowerIdleTable.h" + +// +// Defines for LPIT table, some are HSW ULT specific +// + + +// signature "LPIT" +#define EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE 0x5449504c + +#define EFI_ACPI_OEM_LPIT_REVISION 0x00000000 +#define EFI_ACPI_CREATER_ID 0x2e494d41 //"AMI." +#define EFI_ACPI_CREATER_REVISION 0x5 +#define EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE 0x0 +#define EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG 0x0 +#define EFI_ACPI_LOW_POWER_IDLE_NO_RES_COUNTER_FLAG 0x2 +#define EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_TSC 0x0 + +// +// LPI state count (only 1 on HSW ULT) +// + +#define EFI_ACPI_HSW_LPI_STATE_COUNT 2 + +// +// LPI TRIGGER (HW C10 on HSW ULT) +// +#define EFI_ACPI_HSW_LPI_TRIGGER {0x7F,0x1,0x2,0x0,0x60} + +// +// LPI residency counter (HW C10 on HSW ULT) +// +#define EFI_ACPI_HSW_LPI_RES_COUNTER {0x7F,64,0x0,0x0,0x632} + +// +// LPI DUMMY COUNTER +// +#define EFI_ACPI_HSW_DUMMY_RES_COUNTER {0x0,0,0x0,0x0,0x0} + + +// +// LPI break-even residency in us (HW C10 on HSW ULT) +// +#define EFI_ACPI_HSW_LPI_MIN_RES 30000 + +// +// LPI latency in us (HW C10 on HSW ULT) +// +#define EFI_ACPI_HSW_LPI_LATENCY 3000 + +// +// LPI ID (HW C10 on HSW ULT) +// +#define EFI_ACPI_HSW_LPI_AUDIO_ID 0 + +// +// LPI ID (HW C10 on HSW ULT) +// +#define EFI_ACPI_HSW_LPI_CS_ID 1 + +// +// LPI ACPI table header +// + +#pragma pack(1) + +typedef struct _EFI_ACPI_LOW_POWER_IDLE_TABLE { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR LpiStates[EFI_ACPI_HSW_LPI_STATE_COUNT]; +} EFI_ACPI_LOW_POWER_IDLE_TABLE; + +#pragma pack() + + +#endif //_LPIT_H_ diff --git a/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.mak b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.mak new file mode 100644 index 0000000..5c78da2 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.mak @@ -0,0 +1,75 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: lpit.mak +# +# Description: MAke file to build Aptio ACPI ASL components +# +# +#<AMI_FHDR_END> +#************************************************************************* +all : Lpit + +Lpit : $(BUILD_DIR)\Lpit.ffS + +Lpit_Includes = \ + $(EDK_INCLUDES)\ + +Lpit_Defines = \ + /D"TIANO_RELEASE_VERSION=0x00080006"\ + +Lpit_ACPIS = \ + $(BUILD_DIR)\Lpit.acpi\ + +$(BUILD_DIR)\Lpit.asl: $(BUILD_DIR)\token.mak $(LPIT_DIR)\lpit.mak + copy << $@ +<< + +$(BUILD_DIR)\Lpit.exe : $(LPIT_DIR)\lpit.act $(LPIT_DIR)\lpit.h + @CL $(CFLAGS) $(Lpit_Defines) /Fo$(BUILD_DIR)\ $(Lpit_Includes) /TC $(LPIT_DIR)\lpit.act + @Link /OUT:$(BUILD_DIR)\Lpit.exe /NODEFAULTLIB /ENTRY:main $(BUILD_DIR)\Lpit.obj + +$(BUILD_DIR)\Lpit.acpi : $(BUILD_DIR)\Lpit.exe + $(GENACPI) $(BUILD_DIR)\Lpit.exe $(BUILD_DIR)\Lpit.acpi + +$(BUILD_DIR)\Lpit.sec : $(Lpit_ACPIS) + $(GENSECTION) -I $** -O $@ -S EFI_SECTION_RAW + +$(BUILD_DIR)\Lpit.ffs: $(BUILD_DIR)\Lpit.sec $(LPIT_DIR)\lpit.mak + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=9DD795EB-41E8-4591-8E63-5EF4AA33B908\ + TYPE=EFI_FV_FILETYPE_FREEFORM \ + FFS_CHECKSUM=1\ + RAWFILE=$(BUILD_DIR)\Lpit.sec FFSFILE=$(BUILD_DIR)\Lpit.ffs COMPRESS=0 NAME=Lpit + + + + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.sdl b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.sdl new file mode 100644 index 0000000..188ddd8 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.sdl @@ -0,0 +1,38 @@ +TOKEN + Name = "LPIT_SUPPORT" + Value = "1" + Help = "Main switch to enable LPIT support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +PATH + Name = "LPIT_DIR" +End + +MODULE + Help = "Includes LPIT.mak to Project" + File = "lpit.mak" +End + +ELINK + Name = "$(BUILD_DIR)\Lpit.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\Lpit.asl" + Parent = "GENERIC_ASL" + InvokeOrder = AfterParent +End + +TOKEN + Name = "LPIT_GUID" + Value = "{0x9dd795eb, 0x41e8, 0x4591, 0x8e, 0x63, 0x5e, 0xf4, 0xaa, 0x33, 0xb9, 0x8}" + Help = "lpit Acpi Package" + TokenType = Expression + TargetH = Yes +End
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/BRRtd3.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/BRRtd3.asl new file mode 100644 index 0000000..fd364d6 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/BRRtd3.asl @@ -0,0 +1,1250 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + +DefinitionBlock ( + "Rtd3.aml", + "SSDT", + 1, + "AcpiRef", + "BR0_Rtd3", + 0x1000 + ) +{ +#define BRRTD3 1 +Include("RTD3Common.asl") +#undef BRRTD3 + +External(BBR, IntObj) // BaskinRidge +External(BWC, IntObj) // Walnut Canyon +External(\_SB.PCI0.EHC2.HUBN.PR01.PR11, DeviceObj) +External(\_SB.PCI0.EHC2.HUBN.PR01.PR12, DeviceObj) +External(\_SB.PCI0.LPCB.GR19) +External(\_SB.PCI0.LPCB.GR0B) +External(\RT14) +External(\RT16) +External(\RT17) +External(\RT32) +External(\RT35) +External(\GL01) +External(\GIV1) +External(\GL00) +External(\GL04) +External(\GL05) +External(\GL06) +External(\GL08) +External(\SS11) +External(\SE11) +External(\SS13) +External(\SE13) +External(PFLV) +External(FDTP) + + +If(LOr(LAnd(LEqual(BID,BBR),LEqual(RTD3,1)),LAnd(LEqual(BID,BWC),LEqual(RTD3,1)))) { + + +// +// PCIe RTD3 - for slot#3 +// + +Scope (\_SB.PCI0.RP03) +{ + Name(WC, 0) +} + +Scope (\_SB.PCI0.RP03) +{ + Name(_PR0, Package(){PXP3}) + Name(_PR3, Package(){PXP3}) + Name(WKEN, 0) + + Method(_S0W, 0) + { // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W + + Method(_DSW, 3) + { + If(Arg1) + { // Entering Sx, need to disable WAKE# from generating runtime PME + Store(0, WKEN) + } Else { // Staying in S0 + If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake + { // Set PME + Store(1, WKEN) + } Else { // Disable runtime PME, either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + } // End _DSW + + + // Define a power resource for PCIe RP3 D0-D3hot + PowerResource(PXP3, 0, 0) + { + Name(OFFC, 0) // _OFF Counter + Name(ONC, 0) // _ON Counter + Name(PWRS, 0xFF) // current power status + + Method(_STA, 0) + { + If(LAnd(NAnd(GL00, 0x40), And(GL06, 0x80))){ + Return (1) + } Else { + Return (0) + } + + } + Method(_ON) // Turn on core power to PCIe Slot3 + { + Increment(ONC) + //Power ON for Slot3 + And(\GL00, 0x0BF, \GL00) + Sleep(PEP0) // Sleep for programmable delay + Store(1, PWRS) + Or(\GL06, 0x80, \GL06) + } + + Method(_OFF) // Turn off core power to PCIe Slot1 + { + Increment(OFFC) + //Power OFF for Slot3 + And(\GL06, 0x7F, \GL06) + Or(\GL00, 0x40, \GL00) + Store(1, \_SB.PCI0.RP03.LDIS) //Not required as power not removed at this time + Store(0, \_SB.PCI0.RP03.LDIS) //toggle link disable + + If(\_SB.PCI0.RP03.WKEN) { + Store(0, PWRS) + } + } + } // End PXP3 +} // End RP03 +/* +Scope(\_SB.PCI0.RP03.PXSX) +{ // PCIe Device beneath RP03 + Method(_S0W, 0) + { // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W +} // End PXSX +*/ +// +// PCIe RTD3 - for slot#4 +// +Scope (\_SB.PCI0.RP04) +{ + Name(_PR0, Package(){PXP4}) + Name(_PR3, Package(){PXP4}) + Name(WKEN, 0) + + Method(_S0W, 0) + { // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W + + Method(_DSW, 3) + { + If(Arg1) + { // Entering Sx, need to disable WAKE# from generating runtime PME + Store(0, WKEN) + } Else { // Staying in S0 + If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake + { // Set PME + Store(1, WKEN) + } Else { // Disable runtime PME, either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + } // End _DSW + + + // Define a power resource for PCIe RP4 D0-D3hot + PowerResource(PXP4, 0, 0) + { + Name(OFFC, 0) // _OFF Counter + Name(ONC, 0) // _ON Counter + Name(PWRS, 0xFF) // current power status + + Method(_STA, 0) + { + If(LAnd(NAnd(RT16, 1), And(RT17, 1))){ + Return (1) // + } else { + Return (0) + } + } + Method(_ON) // Turn on core power to PCIe Slot4 + { + Increment(ONC) + //Power ON for Slot4 + And(\RT16, 0x0, \RT16) //Apply power + Sleep(PEP0) // Sleep for programmable delay + Or(\RT17, 0x1, \RT17) //De-assert PERST# + Store(1, PWRS) + } + + Method(_OFF) // Turn off core power to PCIe Slot1 + { + Increment(OFFC) + //Power OFF for Slot4 + And(\RT17, 0x0, \RT17) + Or(\RT16, 0x1, \RT16) + Store(1, \_SB.PCI0.RP04.LDIS) + Store(0, \_SB.PCI0.RP04.LDIS) //toggle link disable + + If(\_SB.PCI0.RP04.WKEN) { + Store(0, PWRS) + Store(1, \SS11) //Clear SMI status + Store(1, \SE11) //Enable SMI + } + } + } // End PXP4 + +} // End RP04 +/* +Scope(\_SB.PCI0.RP04.PXSX) +{ // PCIe Device beneath RP04 + Method(_S0W, 0) + { // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W +} // End PXSX +*/ + +// +// PCIe RTD3 - for slot#5 +// +Scope (\_SB.PCI0.RP05) +{ + Name(_PR0, Package(){PXP5}) + Name(_PR3, Package(){PXP5}) + Name(WKEN, 0) + + Method(_S0W, 0) + { // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W + + Method(_DSW, 3) + { + If(Arg1) + { // Entering Sx, need to disable WAKE# from generating runtime PME + Store(0, WKEN) + } Else { // Staying in S0 + If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake + { // Set PME + Store(1, WKEN) + } Else { // Disable runtime PME, either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + } // End _DSW + + + // Define a power resource for PCIe RP5 D0-D3hot + PowerResource(PXP5, 0, 0) + { + Name(OFFC, 0) // _OFF Counter + Name(ONC, 0) // _ON Counter + Name(PWRS, 0xFF) // current power status + + Method(_STA, 0) + { + If(LAnd(NAnd(RT32, 1), And(RT35, 1))){ + Return (1) + } else { + Return (0) + } + + } + Method(_ON) // Turn on core power to PCIe Slot1 + { + P8XH(0,0x11) + P8XH(1,0x50) + Increment(ONC) + //Power ON for Slot5 + And(\RT32, 0x0, \RT32) + Store(1, PWRS) + Sleep(PEP0) // Sleep for programmable delay + Or(\RT35, 0x1, \RT35) + } + + Method(_OFF) // Turn off core power to PCIe Slot5 + { + Increment(OFFC) + //Power OFF for Slot5 + And(\RT35, 0x0, \RT35) + Or(\RT32, 0x1, \RT32) + + Store(1, \_SB.PCI0.RP05.LDIS) + Store(0, \_SB.PCI0.RP05.LDIS) //toggle link disable + Store(0, PWRS) + Sleep(PEP3) // user selectable delay + If(\_SB.PCI0.RP05.WKEN) { + Store(1, \SS13) //Clear SMI status + Store(1, \SE13) //Enable SMI + } + } + } // End PXP5 + +} // End RP05 +/* For Debug +Scope(\_SB.PCI0.RP05.PXSX) +{ // PCIe Device beneath RP05 + Method(_S0W, 0) + { // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W +} // End PXSX +*/ + +// +// GPE Event Handler +// + +Scope(\_GPE) { + // + // GPIO19 routed to GPE0b[25] => 32+25 = 57(0x39) = PCIE slot 3 wake event + // + + Method(_L39) { + // PCIe WAKE# + Increment(\_SB.PCI0.RP03.WC) + If(\_SB.PCI0.RP03.WKEN){ + Store(0, \_SB.PCI0.LPCB.GR19) //Mask SCI - to stop SCI flooding + Notify(\_SB.PCI0.RP03, 0x02) // DeviceWake + } + } + + // + // GPI03 = SMSC 1007 nIO_SMI routed to PCH GPIO 3 + // + Method(_L13) { + /* + If(LAnd(\_SB.PCI0.RP04.WKEN, SS11)){ + Store(0, SE11) + Store(1, SS11) + Notify(\_SB.PCI0.RP04, 0x02) // DeviceWake + } + If(LAnd(\_SB.PCI0.RP05.WKEN, SS13)){ + Store(0, SE13) + Store(1, SS13) + Notify(\_SB.PCI0.RP05, 0x02) // DeviceWake + } + */ + } + // + // GPIO11 - ZPODD DA + // + Method(_L1B){ + // + // Do nothing if Desktop platform + // + If(LEqual(PFLV,FDTP)) { + Return () + } + + // + // Toggle GPI invert + // + If(LEqual(And(\GL01, 0x08),0x08)) { // GPI11 is high + Or(\GIV1, 0x08, \GIV1) //GP_INV should be set to trigger low + }Else { + And(\GIV1, 0xF7, \GIV1) //GP_INV should be set to trigger high + } + + // Only do this if ZPODD not under _DSM control + If(LEqual(\_SB.PCI0.SAT0.UDSM, Zero)) { + // + // Notify OSPM + // + //If(WKEN) { // _DSW called to enable ODD to generate a wake event + //send notification for Port 2 + Notify(\_SB.PCI0.SAT0.PRT2, 2) // Device Wake to Device (Windows) + //} + } Else { + + // Drive GPIO68 to High to power on device. + // + Or(\GL08, 0x10, \GL08) + // + // Notify the OSPM + // + Notify(\_SB.PCI0.SAT0, 0x82) + } // \_SB.PCI0.SAT0.UDSM + Return () + } +} + +// +// AHCI RTD3 +// +Scope(\_SB.PCI0.SAT0) { + // + // _DSM Device Specific Method supporting AHCI LPM/DEVSLP + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Name(DRV, 0) // Storage for _DSM Arg3 parameter 0 + Name(PWR, 0) // Storage for _DSM Arg3 parameter 1 + Name(UDSM, 0) // Use _DSM for ZPODD control. 0 = Disabled; 1 = Enabled + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("E4DB149B-FCFE-425b-A6D8-92357D78FC7F"))) { + // + // Switch by function index + // + Switch (Arg2) { + Case (0) { + // Standard query - A bitmask of functions supported + // Supports function 0-3 + Name(RBUF, Buffer(1){0x00}) + CreateByteField (RBUF, 0, SFUN) + Store (0x0F, SFUN) + Return (RBUF) + } + Case (1) { + // Query Device IDs (Addresses) of children where drive power and/or PHYSLP are supported + //Return (Package(){0x0000FFFF, 0x0001FFFF, 0x0002FFFF}) //Debug - All Ports supports Link control + Return (Package(){0x0000FFFF}) //Only Port0 in MintSpring supports Link control + + } + // + // Control power to device. + // + Case (2) { + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Store(ToInteger(DerefOf(Index(Arg3, One))), PWR) + + Switch(DRV){ + Case (0x0000FFFF){ + If(PWR){ // Applying Power + // Turn on drive and link power to drive at Port 0 + Store(1, RT14) // De assert physlp -> Link ON, LED ON + ^PRT0.P0PR._ON() + } Else { // Remove Link Power + Store(0, RT14) // Assert physlp -> Link OFF, LED OFF + } + } + //We don't have Link power control in Mintspring. so the code below can be removed. + Case (0x0001FFFF){ + If(PWR){ // Applying Power + // Turn on drive and link power to drive at Port 1 + \_SB.PCI0.SAT0.PRT1.P1PR._ON() + } Else { // Remove Link Power + NoOp // No link power control on these ports. + } + } + Case (0x0002FFFF){ + // Turn on drive and link power to drive at Port 2 + If(PWR){ // Applying Power + // Turn on drive and link power to drive at Port 2 + //^PRT2.P2PR._ON() + } Else { // Remove Link Power + NoOp // No link power control on these ports + } + } + Case (Ones){ + // Turn on drive and link power to all drives + If(PWR){ // Applying Power + Store(1, RT14) // De assert physlp -> Link ON, LED ON (Link might be disabled) + ^PRT0.P0PR._ON() + \_SB.PCI0.SAT0.PRT1.P1PR._ON() + ^PRT2.P2PR._ON() + } + } + } + Return (0) + } + // + // Current status of Device/Link of Port + // + Case (3){ + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Switch(DRV){ + Case (0x0000FFFF){ + Store(ShiftRight(NAnd(GL04, 0x04), 2), Local0) // Bit0 => Device power state + If(LEqual(RT14,1)){ //If Link ON + Or(Local0, 2, Local0) //Bit1 => Link power state + } + Return (Local0) + } + + Case (0x0001FFFF){ + Store(ShiftRight(NAnd(GL04, 0x08), 2), Local0) // Bit0 => Device power state + Or(Local0, 2, Local0) //Bit1 => Link power state + Return (Local0) + } + + Case (0x0002FFFF){ + Store(ShiftRight(And(GL08, 0x010), 2), Local0) // Bit0 => Device power state + Or(Local0, 2, Local0) //Bit1 => Link power state + Return (Local0) + } + + Default { + Return (Ones) + } + } + } + Default { + Return (0) + } + } //Switch (Arg2) + } Else { + Return (0) + } + } + + // D0 Method for SATA HBA(for debug) + Method(_PS0,0,Serialized) + { + } + + // D3 Method for SATA HBA(for debug) + Method(_PS3,0,Serialized) + { + } + + Scope(PRT0) { + Name(_PR0, Package(){P0PR}) + Name(_PR3, Package(){P0PR}) + + + PowerResource(P0PR, 0, 0){ // SATA_PWR_EN#0 is PCH GPIO34 + Method(_STA){ + If(And(GL04, 0x04)) { + Return(0x00) + } Else { + Return(0x01) + } + } + + Method(_ON, 0) + { // Turn on the PFET + And(GL04, 0xfb, GL04) + // Delay for power ramp + Sleep(16) + } + + Method(_OFF, 0) + { // Turn off the PFET + // TODO: when removing power, need to ensure DEVSLP is either deasserted or reverts to an input + //(safer, no need to keep track if it was asserted before) + Store(1, RT14) // De assert physlp -> Link ON, LED ON + Or(GL04, 0x04, GL04) + } + } // End P0PR + } // End PRT0 + + Scope(PRT1) { + + Name(_PR0, Package(){P1PR}) + Name(_PR3, Package(){P1PR}) + + + PowerResource(P1PR, 0, 0){ // SATA_PWR_EN#0 is PCH GPIO35 on Emerald Lake + Method(_STA){ +// Or(GU04, 8, GU04) // GPIO init code incorrect- make this GPIO non-native + If(And(GL04, 0x08)) { + Return(0x00) + } Else { + Return(0x01) + } + } + + Method(_ON, 0) + { // Turn on the PFET + And(GL04, 0xf7, GL04) + // Delay for power ramp + Sleep(16) + } + + Method(_OFF, 0) + { // Turn off the PFET + Or(GL04, 8, GL04) + } + } // End P1PR + } //End PRT1 + + Scope(PRT2) { // Port 2- Cable Connect power + // + // _DSM Device Specific Method supporting SATA ZPODD function + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Method (_DSM, 4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("bdfaef30-aebb-11de-8a39-0800200c9a66"))) { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) { + // + // Standard query - A bitmask of functions supported + // Supports function 0-5 + // + Case (0) { + switch(ToInteger(Arg1)) { + case(1) { + // + // Return - 0 (No Functions supported) for Desktop Platforms + // + If(LEqual(PFLV,FDTP)) { + Return (Buffer () {0}) + } + Return (Buffer () {0xF}) + } + Default {Return (Buffer () {0})} + } + } + // + // Enable ZPODD feature + // + Case (1) { + // + // Enable Power ON/OFF + // + // Function 1: Enable Power OFF/ON. Enables the Power Off/ON hardware in the system. + // When called, the BIOS is informed that the host software is using this interface. + If(LEqual(\_SB.PCI0.SAT0.UDSM, Zero)){ //if Ownership not acquired + Store (1, \_SB.PCI0.SAT0.UDSM) // Indicate ZPODD _DSM control enabled + } + Store(2, \_SB.PCI0.LPCB.GR0B) // Enable SCI (for ZPODD wake) in LPC register + Return (1) + } + // + // Power Off Device + // + Case (2) { + // + // Drive GPIO68 to low to power off device. + // + And(\GL08, 0xEF, \GL08) + Return (1) + } + // + // Power ON Device + // + Case (3) { + Or(\GL08, 0x10, \GL08) + Sleep(16) // To turn the FET + Return (1) + } + Default { + Return (0) + } + } + } Else { + Return (0) + } + } + Name(_PR0, Package(){P2PR}) + Name(_PR3, Package(){P2PR}) + + Name(WKEN, 0) // Device on this port wake enabled? + + Method(_S0W, 0) + { // PMEs can be generated from D3cold + Store(2, \_SB.PCI0.LPCB.GR0B) // Enable SCI (for ZPODD wake) in LPC register + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W + + Method(_DSW, 3) + { + If(Arg1) + { // Entering Sx, need to disable DA from generating runtime PME + Store(0, WKEN) + } Else { // Staying in S0 + If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake + { // Set WKEN to allow _OFF to enable the wake event + Store(1, WKEN) + } Else { // Clear WKEN to allow _OFF to enable the wake event, + // either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + } // End _DSW + + Method(_PRW, 0) { Return(GPRW(0x13, 4)) } // can wakeup from S4 state + + PowerResource(P2PR, 0, 0){ + Name(_STA, 0x01) + + Method(_ON, 0) + { + Store(0x01, _STA) + Or(GL08, 0x10, GL08) + Sleep(16) // To turn the FET + } + + Method(_OFF, 0) + { + // + // Drive GPIO68 to low to power off device. + // + And(GL08, 0xEF, GL08) + Store(0, _STA) + } + } // End P2PR + } //End PRT2 + + PowerResource(V0PR, 0, 0) + { // Power Resource Aggregate for RAID volume 0 + Name(_STA, 0x01) + Name(PMAP, 0) + + Method(_ON, 0) + { // Turn on the PFET + If(Not(_STA)){ + Store(0x01, _STA) + If(And(PMAP, 0x01)) + { // Turn On Port 0 Power + And(GL04, 0xfb, GL04) + } + If(And(PMAP, 0x02)) + { // Turn On Port 1 Power + And(GL04, 0xf7, GL04) + } + If(And(PMAP, 0x04)) + { // Turn On Port 2 Power + Or(GL08, 0x10, GL08) + } + // Delay for power ramp + Sleep(16) + } + } + + Method(_OFF, 0) + { // Turn off the PFET + If(_STA){ + Store(0x01, _STA) + If(And(PMAP, 1)) + { // Turn Off Port 0 Power + Or(GL04, 0x04, GL04) + } + If(And(PMAP, 2)) + { // Turn Off Port 1 Power + Or(GL04, 0x08, GL04) + } + If(And(PMAP, 4)) + { // Turn Off Port 2 Power + And(GL08, 0xEF, GL08) + } + } + } + } // End V0PR + + PowerResource(V1PR, 0, 0) + { // Power Resource Aggregate for RAID volume 1 + Name(_STA, 0x01) + Name(PMAP, 0) + + Method(_ON, 0) + { // Turn on the PFET + If(Not(_STA)){ + Store(0x01, _STA) + If(And(PMAP, 0x01)) + { // Turn On Port 0 Power + And(GL04, 0xfb, GL04) + } + If(And(PMAP, 0x02)) + { // Turn On Port 1 Power + And(GL04, 0xf7, GL04) + } + If(And(PMAP, 0x04)) + { // Turn On Port 2 Power + Or(GL08, 0x10, GL08) + } + // Delay for power ramp + Sleep(16) + } + } + + Method(_OFF, 0) + { // Turn off the PFET + If(_STA){ + Store(0x01, _STA) + If(And(PMAP, 1)) + { // Turn Off Port 0 Power + Or(GL04, 0x04, GL04) + } + If(And(PMAP, 2)) + { // Turn Off Port 1 Power + Or(GL04, 0x08, GL04) + } + If(And(PMAP, 4)) + { // Turn Off Port 2 Power + And(GL08, 0xEF, GL08) + } + } + } + } // End V1PR + + PowerResource(V2PR, 0, 0) + { // Power Resource Aggregate for RAID volume 2 + Name(_STA, 0x01) + Name(PMAP, 0) + + Method(_ON, 0) + { // Turn on the PFET + If(Not(_STA)){ + Store(0x01, _STA) + If(And(PMAP, 0x01)) + { // Turn On Port 0 Power + And(GL04, 0xfb, GL04) + } + If(And(PMAP, 0x02)) + { // Turn On Port 1 Power + And(GL04, 0xf7, GL04) + } + If(And(PMAP, 0x04)) + { // Turn On Port 2 Power + Or(GL08, 0x10, GL08) + } + // Delay for power ramp + Sleep(16) + } + } + + Method(_OFF, 0) + { // Turn off the PFET + If(_STA){ + Store(0x01, _STA) + If(And(PMAP, 1)) + { // Turn Off Port 0 Power + Or(GL04, 0x04, GL04) + } + If(And(PMAP, 2)) + { // Turn Off Port 1 Power + Or(GL04, 0x08, GL04) + } + If(And(PMAP, 4)) + { // Turn Off Port 2 Power + And(GL08, 0xEF, GL08) + } + } + } + } // End V2PR + + Device(VOL0) { + Name(_ADR,0x0080FFFF) // RAID Volume 0 + + Name(_PR0, Package(){V0PR}) + Name(_PR3, Package(){V0PR}) + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("E03E3431-E510-4fa2-ABC0-2D7E901245FE"))) { + // + // Switch by function index + // + Switch (Arg2) { + + Case (0) { + // Standard query - A bitmask of functions supported + // Supports function 0-3 + Name(RBUF, Buffer(1){0x00}) + CreateByteField (RBUF, 0, SFUN) + Store (0x03, SFUN) + Return (RBUF) + } + + Case (1) {// Assign ports to this RAID volume + Store(DeRefOf(Index(Arg3,0)), ^^V0PR.PMAP) // Assign port mapping to the volume's power resource + Return(Package(0){}) + } + Default { + Return (0) + } + } //Switch (Arg2) + } Else { + Return (0) + } + } + } + + Device(VOL1) { + Name(_ADR,0x0081FFFF) // RAID Volume 1 + + Name(_PR0, Package(){V1PR}) + Name(_PR3, Package(){V1PR}) + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("E03E3431-E510-4fa2-ABC0-2D7E901245FE"))) { + // + // Switch by function index + // + Switch (Arg2) { + + Case (0) { + // Standard query - A bitmask of functions supported + // Supports function 0-3 + Name(RBUF, Buffer(1){0x00}) + CreateByteField (RBUF, 0, SFUN) + Store (0x03, SFUN) + Return (RBUF) + } + + Case (1) {// Assign ports to this RAID volume + Store(DeRefOf(Index(Arg3,0)), ^^V1PR.PMAP) // Assign port mapping to the volume's power resource + Return(Package(0){}) + } + Default { + Return (0) + } + } //Switch (Arg2) + } Else { + Return (0) + } + } + } + + Device(VOL2) { + Name(_ADR,0x0082FFFF) // RAID Volume 2 + + Name(_PR0, Package(){V2PR}) + Name(_PR3, Package(){V2PR}) + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("E03E3431-E510-4fa2-ABC0-2D7E901245FE"))) { + // + // Switch by function index + // + Switch (Arg2) { + + Case (0) { + // Standard query - A bitmask of functions supported + // Supports function 0-3 + Name(RBUF, Buffer(1){0x00}) + CreateByteField (RBUF, 0, SFUN) + Store (0x03, SFUN) + Return (RBUF) + } + + Case (1) {// Assign ports to this RAID volume + Store(DeRefOf(Index(Arg3,0)), ^^V2PR.PMAP) // Assign port mapping to the volume's power resource + Return(Package(0){}) + } + Default { + Return (0) + } + } //Switch (Arg2) + } Else { + Return (0) + } + } + } +} + + Scope(\_SB.PCI0.EHC2){ + Method(_S0W, 0) + { // PMEs can be generated from D3(hot) + Return(3) + } // End _S0W + + // D0 Method for EHCI2 Host Controller + Method(_PS0,0,Serialized) + { + } + + // D3 Method for EHCI2 Host Controller + Method(_PS3,0,Serialized) + { + Store(1, \_SB.PCI0.EHC2.PMES) //Clear PME status + Store(1, \_SB.PCI0.EHC2.PMEE) //Enable PME + } + } + + Scope(\_SB.PCI0.XHC){ + Method(_S0W, 0) + { // PMEs can be generated from D3(hot) + Return(3) + } // End _S0W + + // D0 Method for xHCI Host Controller + Method(_PS0,0,Serialized) + { + } + + // D3 Method for xHCI Host Controller + Method(_PS3,0,Serialized) + { + Store(1, \_SB.PCI0.XHC.PMES) //Clear PME status + Store(1, \_SB.PCI0.XHC.PMEE) //Enable PME + } + } + + Scope(\_SB.PCI0.XHC.RHUB.HS01){ + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF),0x01)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } // End of Method _PR0 + Method(_PR2, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF),0x01)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } // End of Method _PR2 + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF),0x01)) + { + Return(Package(){\PX01}) + } + Else + { + Return (Package() {}) + } + } // End of Method _PR3 + } + + Scope(\_SB.PCI0.XHC.RHUB.HS02){ + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF0),0x10)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } // End of Method _PR0 + Method(_PR2, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF0),0x10)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } // End of Method _PR2 + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF0),0x10)) + { + Return(Package(){\PX01}) + } + Else + { + Return (Package() {}) + } + } // End of Method _PR3 + + } + + Scope(\_SB.PCI0.XHC.RHUB.SSP1){ + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF),0x02)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } + Method(_PR2, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF),0x02)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF),0x02)) + { + Return(Package(){\PX01}) + } + Else + { + Return (Package() {}) + } + }// End of method _PR3 + } // End of Scope(\_SB.PCI0.XHC.RHUB.SSP1) + + Scope(\_SB.PCI0.XHC.RHUB.SSP2){ + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF0),0x20)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } + Method(_PR2, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF0),0x20)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF0),0x20)) + { + Return(Package(){\PX01}) + } + Else + { + Return (Package() {}) + } + }// End of method _PR3 + }//Scope(\_SB.PCI0.XHC.RHUB.SSP2) + + Scope(\_SB.PCI0.EHC2.HUBN.PR01.PR11){ + Name(_PR0, Package(){\PX89}) + Name(_PR2, Package(){\PX89}) + Name(_PR3, Package(){\PX89}) + + } + + Scope(\_SB.PCI0.EHC2.HUBN.PR01.PR12){ + Name(_PR0, Package(){\PX89}) + Name(_PR2, Package(){\PX89}) + Name(_PR3, Package(){\PX89}) + + } + + Scope(\) { + PowerResource(PX01, 0, 0){ //Common power rail for USB2.0 ports 0,1 /USB3.0 ports 1,2 - GPIO 40 + Method(_STA){ + If(And(GL05, 0x02)) { //GPIO41 => GL05 BIT0 + Return(0x01) + } Else { + Return(0x00) + } + } + + Method(_ON, 0) + { // Turn on + Or(GL05, 2, GL05) + // Delay for power ramp + Sleep(16) + } + + Method(_OFF, 0) + { // Turn off + And(GL05, 0xfd, GL05) + } + } // End PX01 + + PowerResource(PX89, 0, 0){ //Common power rail for USB2.0 ports 8, 9 (stacked with LAN conn; EHCI) - GPIO 14 + Method(_STA){ + If(And(GL01, 0x40)) { //GPI14 => GL01 BIT6 + Return(0x01) + } Else { + Return(0x00) + } + } + + Method(_ON, 0) + { // Turn on + Or(GL01, 0x40, GL01) + // Delay for power ramp + Sleep(16) + } + + Method(_OFF, 0) + { // Turn off + And(GL01, 0x0bf, GL01) + } + } // End PX89 + +} //Scope(\) + +} //If(LAnd(LEqual(BID,BBR),LEqual(RTD3,1))) + +} // End SSDT
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Common.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Common.asl new file mode 100644 index 0000000..9f8857e --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Common.asl @@ -0,0 +1,178 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + +External(\_SB.OSCO) +External(\_SB.PCI0,DeviceObj) +External(\_SB.PCI0.SAT0, DeviceObj) +External(\_SB.PCI0.SAT0.PRT0, DeviceObj) +External(\_SB.PCI0.SAT0.PRT1, DeviceObj) +External(\_SB.PCI0.SAT0.PRT2, DeviceObj) + +External(\_SB.PCI0.RP01, DeviceObj) +External(\_SB.PCI0.RP03, DeviceObj) +External(\_SB.PCI0.RP04, DeviceObj) +External(\_SB.PCI0.RP05, DeviceObj) +External(\_SB.PCI0.RP06, DeviceObj) +External(\_SB.PCI0.RP01.LDIS) +External(\_SB.PCI0.RP03.LDIS) +External(\_SB.PCI0.RP04.LDIS) +External(\_SB.PCI0.RP05.LDIS) +External(\_SB.PCI0.RP06.LDIS) +External(\_SB.PCI0.RP01.L23E) +External(\_SB.PCI0.RP03.L23E) +External(\_SB.PCI0.RP04.L23E) +External(\_SB.PCI0.RP05.L23E) +External(\_SB.PCI0.RP06.L23E) +External(\_SB.PCI0.RP01.L23R) +External(\_SB.PCI0.RP03.L23R) +External(\_SB.PCI0.RP04.L23R) +External(\_SB.PCI0.RP05.L23R) +External(\_SB.PCI0.RP06.L23R) +External(\_SB.PCI0.RP01.LEDM) +External(\_SB.PCI0.RP03.LEDM) +External(\_SB.PCI0.RP04.LEDM) +External(\_SB.PCI0.RP05.LEDM) +External(\_SB.PCI0.RP06.LEDM) +External(\_SB.PCI0.RP01.LASX) +External(\_SB.PCI0.RP03.LASX) +External(\_SB.PCI0.RP04.LASX) +External(\_SB.PCI0.RP05.LASX) +External(\_SB.PCI0.RP06.LASX) +External(\CKEN) +External(\PMFS) + +External(\_SB.PCI0.XHC, DeviceObj) +External(\_SB.PCI0.XHC.PMES) +External(\_SB.PCI0.XHC.PMEE) +External(\_SB.PCI0.XHC.MEMB) +External(\_SB.PCI0.EHC2, DeviceObj) +External(\_SB.PCI0.EHC2.PMES) +External(\_SB.PCI0.EHC2.PMEE) +External(\_SB.PCI0.XHC.RHUB, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.SSP1, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.SSP2, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.HS01, DeviceObj) //xHCI HSP port 1 +External(\_SB.PCI0.XHC.RHUB.HS02, DeviceObj) //xHCI HSP port 2 +External(\_SB.PCI0.I2C0, DeviceObj) //I2C Controller +External(\_SB.PCI0.I2C0.SHUB, DeviceObj) // Sensor hub + +External(PEP0) +External(PEP3) +External(XHPR) +External(RCG0, IntObj) // RTD3 Config Setting(BIT0:ZPODD,BIT1:USB Camera Port4, BIT2/3:SATA Port3) +External(\GPRW, MethodObj) +External(P8XH, MethodObj) +External(BID, IntObj) // BoardId +External(RTD3, IntObj) +//AMI_OVERRIDE --- Change name from XDST to XHDS to fix that the system has BsOD issue. It is due to the name(XDST) is conflict with AMI Aptio definition name. >> +//External(XHDS, IntObj) +//External(XDST, IntObj) +//AMI_OVERRIDE --- << +// +// Externs common to ULT0RTD3.asl and FFRDRTD3.asl and exclude for BRRTD3.asl +// +#ifndef BRRTD3 +External(\_SB.GP2A, MethodObj) +External(\_SB.GP2B, MethodObj) +External(\_SB.GP2N, MethodObj) +External(\_SB.RDGP, MethodObj) +External(\_SB.WTGP, MethodObj) +External(\_SB.WTIN, MethodObj) +External(\_SB.RDGI, MethodObj) + +External(\_SB.PCI0.HDEF, DeviceObj) +External(\_SB.PCI0.ADSP, DeviceObj) +External(\_SB.PCI0.I2C1, DeviceObj) //I2C1 Controller +External(\_SB.PCI0.I2C1.TPD1, DeviceObj) // Touch pad +External(\_SB.PCI0.I2C1.TPL0, DeviceObj) // Touch panel +External(\_SB.PCI0.I2C1.TPD0, DeviceObj) // Touch pad +External(\_SB.PCI0.LPCB.H_EC.SPT2) // SATA_CABLE_PWR_EN bit in EC +External(\_SB.PCI0.LPCB.H_EC.ECMD, MethodObj) // EC Command method +External(\_SB.PCI0.LPCB.H_EC.ECAV, IntObj) // EC Driver loaded flag +External(\_SB.PCI0.LPCB.H_EC.ECRD, MethodObj) // EC Read Method +External(\_SB.PCI0.LPCB.H_EC.ECWT, MethodObj) // EC Write Method +External(\_SB.PCI0.SAT0.PRT3, DeviceObj) + +External(\UAMS) +External(RIC0,FieldUnitObj) +External(SDS0,FieldUnitObj) +External(SDS1,FieldUnitObj) +External(IC1D,FieldUnitObj) +External(IC1S,FieldUnitObj) +External(IC0D,FieldUnitObj) +External(I20D,FieldUnitObj) +External(I21D,FieldUnitObj) +External(AUDD,FieldUnitObj) +External(HDAD,FieldUnitObj) +External(SHSB,FieldUnitObj) +External(VRSD,FieldUnitObj) +External(VRRD,FieldUnitObj) + +External(\GO08) +External(\GO45) +External(\GO51) +External(\GS08) +External(\GS45) +External(\GS51) + +Name(LONT, 0) // Last ON Timestamp: The time stamp of the last RTDpower resource _ON method evaluation + +// +// SGON - Staggering ON Method with VR Staggering delay +// Staggering ON Method with VR Staggering (VRSD) delay. Sleep the extra remaining amount of time if necessary. +// Update the global running timer of LONT (Last ON mehtod timestamp) +// +// Arguments: +// Arg0 - GPIO Pin number to toggle power on +// Arg1 - GPIO Value, 0: Active Low, 1: Active High +// +// Return Value: +// Zero - VR staggering is skipped +// One - VR staggering is performed +// +Method(SGON, 2, Serialized) +{ + // Check if device is already driven to power on + If(LNotEqual(\_SB.RDGP(Arg0), Arg1)) { + // Check for VR staggering + Divide(Subtract(Timer(), \LONT), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + If(LLess(Local0, \VRSD)) { //Do not sleep if already past the delay requirement + // Delay for power ramp using Timer Based Sleep + Sleep(Subtract(\VRSD, Local0)) + } + + \_SB.WTGP(Arg0, Arg1) // Drive GPIO to power on device + + Store(Timer(), \LONT) // Update the global Last ON Method Timer + + Return(One) // VR staggering is performed + } Else { + Return(Zero) // VR staggering is skipped + } +} + +#endif + diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Pcie.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Pcie.asl new file mode 100644 index 0000000..d560c2c --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Pcie.asl @@ -0,0 +1,165 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + Name(WKEN, 0) + + Method(_S0W, 0) + { // PMEs can be generated from D3hot + Return(3) //For ULT + } // End _S0W + + Method(_DSW, 3) + { + If(Arg1) + { // Entering Sx, need to disable WAKE# from generating runtime PME + Store(0, WKEN) + } Else { // Staying in S0 + If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake + { // Set PME + Store(1, WKEN) + } Else { // Disable runtime PME, either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + } // End _DSW + + // Define a power resource for PCIe RP D0-D3hot + PowerResource(PXP, 0, 0) + { + Method(_STA, 0) + { + if(LAND(LEqual(\_SB.RDGP(PWRG),PONP), LEqual(\_SB.RDGP(RSTG),RONP))){ + Return (1) + } Else { + Return (0) + } + } + Method(_ON) // Turn on core power to PCIe Slot + { + + // Power ON for Slot + // Dont enable power for NGFF because NGFF only has AUX power + If(LNot(NGFF)) { + \_SB.WTGP(PWRG,PONP) + Sleep(PEP0) // Sleep for programmable delay + } + + // Enable PCIe Src Clock + While(LEqual(PMFS,1)){ // PMC message serviced? + Stall(10) + } + Store(Or(ShiftLeft(SCLK, 24), ShiftLeft(SCLK, 16)), Local1) // Set Bit and Mask + Or(Local1, 4, Local1) // OCKEN command + Store(Local1, \CKEN) // Enable Source Clock + While(LEqual(PMFS,1)){ // PMC message serviced? + Stall(10) + } + + \_SB.WTGP(RSTG,RONP) // De-Assert Reset Pin + Store(1, L23R) // Set L23_Rdy to Detect Transition (L23R2DT) + Sleep(16) + Store(0, Local0) + // Wait up to 12 ms for transition to Detect + While(L23R) { + If(Lgreater(Local0, 4)) // Debug - Wait for 5 ms + { + Break + } + Sleep(16) + Increment(Local0) + } + // Once in Detect, wait up to 124 ms for Link Active (typically happens in under 70ms) + // Worst case per PCIe spec from Detect to Link Active is: + // 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config (24+2+2+2+2) + Store(0, Local0) + While(LEqual(LASX,0)) { + If(Lgreater(Local0, 123)) + { + Break + } + Sleep(16) + Increment(Local0) + } + // ADBG(Local0) // uncomment to print the timeout value for debugging + Store(0, LEDM) // PCIEDBG.DMIL1EDM (324[3]) = 0 + } + Method(_OFF) // Turn off core power to PCIe Slot + { + // Set L23_Rdy Entry Request (L23ER) + Store(1, L23E) + Sleep(16) + Store(0, Local0) + While(L23E) { + If(Lgreater(Local0, 4)){ // Debug - Wait for 5 ms + Break + } + Sleep(16) + Increment(Local0) + } + Store(1, LEDM) // PCIEDBG.DMIL1EDM (324[3]) = 1 + + While(LEqual(PMFS,1)){ // PMC message serviced? + Stall(10) + } + // Disable PCIe Src Clock + Store(Or(ShiftLeft(SCLK, 24), 4), Local1) // Set Mask, OCKEN command + Store(Local1, \CKEN) // Disable Source Clock + While(LEqual(PMFS,1)){ // PMC message serviced? + Stall(10) + } + + \_SB.WTGP(RSTG,Not(RONP)) // Assert Reset Pin + + If(LNot(NGFF)) { // Dont disable power for NGFF because NGFF only has AUX power + \_SB.WTGP(PWRG,Not(PONP)) //Power OFF for Slot + } + + Store(1, LDIS) + Store(0, LDIS) //toggle link disable + + If(WKEN) { + Switch(SLOT){ + Case(0x3){ // Root Port 3 + Store(1, \GS08) //Clear GPE STATUS + Store(0, \GO08) //GPIO_OWN to ACPI Driver + } + Case(0x4){ // Root Port 4 + Store(1, \GS45) //Clear GPE STATUS + Store(0, \GO45) //GPIO_OWN to ACPI Driver + } + Case(0x5){ // Root Port 5 + Store(1, \GS51) //Clear GPE STATUS + Store(0, \GO51) //GPIO_OWN to ACPI Driver + } + Default{ + } + } + } + } // End of Method_OFF + } // End PXP + + Name(_PR0, Package(){PXP}) + diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/Rtd3FFRD.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/Rtd3FFRD.asl new file mode 100644 index 0000000..a00d8e0 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/Rtd3FFRD.asl @@ -0,0 +1,1049 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + +DefinitionBlock ( + "Rtd3.aml", + "SSDT", + 1, + "AcpiRef", + "HSW-FFRD", + 0x1000 + ) +{ +#define FFRDRTD3 1 +Include ("RTD3Common.asl") +#undef FFRDRTD3 + +External(PEBS, IntObj) // PCI Express BAR address +External(BHB, IntObj) // Harris Beach FFRD Board +External(\_SB.PCI0.XHC.RHUB.HS05, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.HS06, DeviceObj) +External(\_SB.PCI0.SDHC, DeviceObj) //SDIO +External(\_SB.PCI0.SDHC.WI01, DeviceObj) //SDIO Wifi +External(\_SB.PCI0.I2C1.TPD7, DeviceObj) // Precision Elantech touchpad +External(\_SB.PCI0.I2C1.TPD8, DeviceObj) // Precision Synaptics touchpad + +If(LAnd(LEqual(BID,BHB),LEqual(RTD3,1))) { +// +// PCIe RTD3 - for slot#1 +// +Scope(\_SB.PCI0.RP01) +{ + Name(SLOT, 1) + Name(RSTG, 77) // reset GPIO NGFF_WIFI_RST_N + Name(PWRG, 83) // power GPIO + Name(RONP, 1) // reset on polarity (DE-ASSERT) + Name(PONP, 1) // power on polarity + Name(NGFF, 1) // Is Slot NGFF form factor 1- Yes 0- No + Name(SCLK, 0x1) // Source Clock Enable Bit Location(BIT0) + Include("Rtd3Pcie.asl") +} + +//SATA - START + Scope(\_SB.PCI0.SAT0) { + + // D0 Method for SATA HBA + Method(_PS0,0,Serialized) + { + } + + // D3 Method for SATA HBA + Method(_PS3,0,Serialized) + { + } + + OperationRegion(SMIO,PCI_Config,0x24,4) + Field(SMIO,AnyAcc, NoLock, Preserve) { + Offset(0x00), // SATA MABR6 + MBR6, 32, // SATA ABAR + } + + OperationRegion(ST93,PCI_Config,0x93,1) + Field(ST93,AnyAcc, NoLock, Preserve) { + Offset(0x00), + P0P, 1, // Port 0 Present + P1P, 1, // Port 1 Present + P2P, 1, // Port 2 Present + P3P, 1, // Port 3 Present + } + + Scope(PRT1) { + // Store boot drive connection status + // Initialize to drive connected, value updated in _INI + Name(CONN, 1) + + Method (_INI, 0) + { + // If no drive connected on boot, update connection status and power gate the port + If(LEqual(P1P, 0)) + { + Store (0, CONN) + \_SB.WTGP (90, 1) + } + } + + PowerResource(P1PR, 0, 0){ + Name(OFTM, Zero) // Time returned by Timer() when the Power resource was turned OFF + + Method(_STA){ + If(LEqual(\_SB.RDGP(90),1)) { //GPIO90 + Return(0x00) + } Else { + Return(0x01) + } + } + Method(_ON, 0) + { + if(And(RCG0,0x10)) // RTD3Config0/RCG0 BIT 4 - Setup option to powergate Port 1 + { + // If there was a device present on boot, power on device + If(LEqual(CONN, 1)) + { + If(LNotEqual(^OFTM, Zero)) { // if OFTM != 0 => Disk as turned OFF by asl + Divide(Subtract(Timer(), ^OFTM), 10000, , Local0) //Store Elapsed time in ms + Store(Zero, ^OFTM) // Reset OFTM to zero to indicate minimum 50ms requirement does not apply when _ON called next time + If(LLess(Local0, 50)) // Do not sleep if already past the delay requirement + { + Sleep(Subtract(50, Local0)) // Sleep 100ms - time elapsed + } + } + + SGON(90, Zero) // VR stagger GPIO90 to low to power on device + } + } // if(And(RCG0,0x10)) + } // End of ON Method + Method(_OFF, 0) + { + if(And(RCG0,0x10)) // RTD3Config0/RCG0 BIT 4 - Setup option to powergate Port 1 + { + Add(\_SB.PCI0.SAT0.MBR6,0x198 ,Local0) + OperationRegion(PSTS, SystemMemory, Local0, 0x18) + Field(PSTS, DWordAcc, NoLock, Preserve) { + Offset(0x0), + CMST, 1, //PxCMD.ST + CSUD, 1, //PxCMD.SUD + , 2, + CFRE, 1, //PxCMD.FRE + Offset(0x10), + SDET, 4, //PxSSTS.DET + Offset(0x14), + CDET, 4 //PxSCTL.DET + } + If(LOr(LEqual(SDET, 1), LEqual(SDET, 3))){ //Offline flow only if Device detected and Phy not offline + //Clear ST (PxCMD.ST) 198[0] + Store(0, CMST) + //Clear FRE 198[4] + Store(0, CFRE) + //Clear SUD (PxCMD.SUD) 198[1] + Store(0, CSUD) + //Set DET to 4 (PxSCTL.DET) 1ac[3:0] + Store(4, CDET) + Sleep(16) + //Wait until PxSSTS.DET == 4 + While(LNotEqual(SDET, 4)){ + Sleep(16) + } + } + // Drive GPIO90 to High to power off device + \_SB.WTGP(90,1) + Store(Timer(), ^OFTM) // Store time when Disk turned OFF(non-zero OFTM indicate minimum 50ms requirement does apply when _ON called next time) + } // if(And(RCG0,0x10)) + } // End of OFF method + } // End P1PR + + Name(_PR0, Package(){P1PR}) + Name(_PR3, Package(){P1PR}) + + } //End PRT1 + + // PRT2 . Controlled by EC pin (PF6/PWMU4A/ExCTS). + Scope(PRT2) { + // Store boot drive connection status + // Initialize to drive connected, value updated in _INI + Name(CONN, 1) + + Method (_INI, 0) + { + // If no drive connected on boot, update connection status and power gate the port + If(LEqual(P2P, 0)) + { + Store (0, CONN) + \_SB.WTGP (86, 1) + } + } + + PowerResource(P2PR, 0, 0){ + Name(OFTM, Zero) // Time returned by Timer() when the Power resource was turned OFF + + Method(_STA){ + If(LEqual(\_SB.RDGP(86),1)) { // GPIO86 + Return(0x00) + } Else { + Return(0x01) + } + + } + Method(_ON, 0) + { + if(And(RCG0,0x20)) // RTD3Config0/RCG0 BIT 5 - Setup option to powergate Port 2 + { + // If there was a device present on boot, power on device + If(LEqual(CONN, 1)) + { + If(LNotEqual(^OFTM, Zero)) { // if OFTM != 0 => Disk as turned OFF by asl + Divide(Subtract(Timer(), ^OFTM), 10000, , Local0) // Store Elapsed time in ms + Store(Zero, ^OFTM) // Reset OFTM to zero to indicate minimum 50ms requirement does not apply when _ON called next time + If(LLess(Local0, 50)) // Do not sleep if already past the delay requirement + { + Sleep(Subtract(50, Local0)) //Sleep 100ms - time elapsed + } + } + + SGON(86, Zero) // VR stagger GPIO86 to low to power on device + } + } // if(And(RCG0,0x20)) + } // End of ON Method + Method(_OFF, 0) + { + if(And(RCG0,0x20)) // RTD3Config0/RCG0 BIT 5 - Setup option to powergate Port 2 + { + Add(\_SB.PCI0.SAT0.MBR6,0x218 ,Local0) + OperationRegion(PSTS, SystemMemory, Local0, 0x18) + Field(PSTS, DWordAcc, NoLock, Preserve) { + Offset(0x0), + CMST, 1, //PxCMD.ST + CSUD, 1, //PxCMD.SUD + , 2, + CFRE, 1, //PxCMD.FRE + Offset(0x10), + SDET, 4, + Offset(0x14), + CDET, 4 //PxSCTL.DET + } + If(LOr(LEqual(SDET, 1), LEqual(SDET, 3))){ //Offline flow only if Device detected and Phy not offline + //Clear ST (PxCMD.ST) + Store(0, CMST) + //Clear FRE + Store(0, CFRE) + //Clear SUD (PxCMD.SUD) + Store(0, CSUD) + //Set DET to 4 (PxSCTL.DET) + Store(4, CDET) + Sleep(16) + //Wait until PxSSTS.DET == 4 + While(LNotEqual(SDET, 4)){ + Sleep(16) + } + } + // Drive GPIO86 to High to power off device + \_SB.WTGP(86,1) + Store(Timer(), ^OFTM) // Store time when Disk turned OFF(non-zero OFTM indicate minimum 50ms requirement does apply when _ON called next time) + } // if(And(RCG0,0x20)) + } // End of OFF method + } // End P2PR + + Name(_PR0, Package(){P2PR}) + Name(_PR3, Package(){P2PR}) + + } //End PRT2 + + + // + // _DSM Device Specific Method supporting AHCI DEVSLP + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Name(DRV, 0) // Storage for _DSM Arg3 parameter 0 + Name(PWR, 0) // Storage for _DSM Arg3 parameter 1 + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("E4DB149B-FCFE-425b-A6D8-92357D78FC7F"))) { + // + // Switch by function index + // + Switch (Arg2) { + Case (0) { + // Standard query - A bitmask of functions supported + // Supports function 0-3 + Return(0x0f) + } + Case (1) { + // Query Device IDs (Addresses) of children where drive power and/or DevSleep are supported. + // LPT-LP SATA HBA provides autonomous link (DevSleep) support, return a package of 0 elements + Return( Package(){}) // SATA HBA provides native DevSleep + } + // + // Control power to device. + // + Case (2) { + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Store(ToInteger(DerefOf(Index(Arg3, One))), PWR) + + Switch(DRV){ + Case (Ones){ + // Turn on drive and link power to all drives. Note that even though + If(PWR){ // Applying Power + //^PRT0.P0PR._ON() // apply power to port 0 + \_SB.PCI0.SAT0.PRT1.P1PR._ON() // apply power to port 1 + \_SB.PCI0.SAT0.PRT2.P2PR._ON() // apply power to port 2 + } + } + } //Switch(DRV) + Return (0) + } //Case (2) + // + // Current status of Device/Link of Port + // + Case (3){ + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Switch(DRV){ + Case (0x0000FFFF){ // SATA Port 0 + // Bit0 => Device power state + Store(1, Local0) // always ON + Return (Local0) + } + Case (0x0001FFFF){ // SATA Port 1 + // Bit0 => Device power state + If(LEqual(\_SB.PCI0.SAT0.PRT1.P1PR._STA(), 0)){ + Store(0, Local0) + }Else{ + Store(1, Local0) + } + Return (Local0) + } + Case (0x0002FFFF){ // SATA Port 2 + // Bit0 => Device power state + If(LEqual(\_SB.PCI0.SAT0.PRT2.P2PR._STA(), 0)){ + Store(0, Local0) + }Else{ + Store(1, Local0) + } + Return (Local0) + } + Default { // Invalid SATA Port - error + Return (Ones) + } + } + } + Default { + Return (0) + } + } + } Else { // UUID does not match + Return (0) + } + } //Method(_DSM) + + } //Scope(\_SB.PCI0.SAT0) + +// SATA - END + +//USB - START + Scope(\_SB.PCI0.XHC){ + Name(_S0W, 3) + } + + Scope(\_SB.PCI0.XHC.RHUB){ //USB XHCI RHUB + Method(_PS0,0,Serialized) + { + Store(0x00,USPP) + } + Method(_PS2,0,Serialized) + { + + OperationRegion (XHCM, SystemMemory, And(\_SB.PCI0.XHC.MEMB,0xFFFF0000), 0x600) + Field (XHCM, DWordAcc, NoLock, Preserve) + { + Offset(0x2), + XHCV,16, + Offset(0x480), + HP01, 1, // HS port 1 + Offset(0x490), + HP02, 1, // HS port 2 + Offset(0x4F0), + HP08, 1, // HS port 8 + Offset(0x510), + SP00, 1, // SS port 0 + Offset(0x520), + SP01, 1, // SS port 1 + Offset(0x540), + SP03 , 1, // SS port 3 + } + If(LEqual(XHCV,0xFFFF)) // Controller in D3Hot(MEM_BASE not decoded) + { + Return() + } + If(LAnd(LEqual(HP08,0x00),LEqual(SP03,0x00))) // SD Card reader + { + Or(USPP,0x01, USPP) + } + If(LAnd(LEqual(HP01,0x00),LEqual(SP00,0x00))) // USB(HS1 : 0x480 /SS0 : 0x510) + { + Or(USPP,0x02, USPP) + } + If(LAnd(LEqual(HP02,0x00),LEqual(SP01,0x00))) // USB(HS2 : 0x490 / SS1 : 0x520) + { + Or(USPP,0x04, USPP) + } + } // End of PS2 method + Method(_PS3,0,Serialized) + { + } // End of _PS3 method + } + +Scope(\_SB.PCI0.XHC.RHUB.HS06){ + + PowerResource(PX06, 0, 0){ // power rail for USB3.0 ports 6 - GPIO 84 + Method(_STA){ + If(LEqual(\_SB.RDGP(84),1)) { //GPIO84 + Return(0x01) + } Else { + Return(0x00) + } + } + Method(_ON, 0) + { // Turn on + SGON(84, One) // VR stagger GPIO84 to high to power on device + } + + Method(_OFF, 0) + { // Turn off + \_SB.WTGP(84,0) + } + } // End PX06 + Name(_S0W,2) // Indicate WWAN can wake from D2 while in S0 using selective suspend + Name(_PR0,Package(){\_SB.PCI0.XHC.RHUB.HS06.PX06}) // Power Resource required to support D0 + Name(_PR2,Package(){\_SB.PCI0.XHC.RHUB.HS06.PX06}) // Power Resource required to support D2 + Name(_PR3,Package(){\_SB.PCI0.XHC.RHUB.HS06.PX06}) // Power Resource required to support D3 +} + + Scope(\_SB.PCI0.XHC.RHUB.HS05){ + PowerResource(PX05, 0, 0){ // power rail for USB2.0 ports 5 - GPIO 25 + Method(_STA){ + If(LEqual(\_SB.RDGP(25),1)) { //GPIO25 + Return(0x01) + } Else { + Return(0x00) + } + } + Method(_ON, 0) + { // Turn on + SGON(25, One) // VR stagger GPIO25 to high to power on device + } + + Method(_OFF, 0) + { // Turn off + \_SB.WTGP(25,0) + } + } // End PX05 + Name(_PR0,Package(){\_SB.PCI0.XHC.RHUB.HS05.PX05}) // Power Resource required to support D0 + Name(_PR2,Package(){\_SB.PCI0.XHC.RHUB.HS05.PX05}) // Power Resource required to support D2 + Name(_PR3,Package(){\_SB.PCI0.XHC.RHUB.HS05.PX05}) // Power Resource required to support D3 + } + Scope(\_SB.PCI0.XHC){ //USB XHCI + + Name(UPWR,0) + Name(USPP,0) + // Bit 0 : USB SD Card Reader + // Bit 1 : USB(HS1 : 0x480 /SS0 : 0x510) + // BIT 2 : USB(HS2 : 0x490 / SS1 : 0x520) + + + Method(DUAM,0,Serialized) + { + + OperationRegion (XHCM, SystemMemory, And(\_SB.PCI0.XHC.MEMB,0xFFFF0000), 0x600) + Field (XHCM, DWordAcc, NoLock, Preserve) + { + Offset(0x2), + XHCV,16, + Offset(0x480), + HP01, 1, // HS port 1 + Offset(0x490), + HP02, 1, // HS port 2 + Offset(0x4F0), + HP08, 1, // HS port 8 + Offset(0x510), + SP00, 1, // SS port 0 + Offset(0x520), + SP01, 1, // SS port 1 + Offset(0x540), + SP03 , 1, // SS port 3 + } + + if(LNotEqual(\UAMS,0x00)) // User not present + { + Store(0x00,UPWR) + // Enterng CS, Remove power if SD card not present + + If(LEqual(XHCV,0xFFFF)) // Controller in D3Hot(MEM_BASE not decoded) + { + If(And(USPP,0x01)) // SD Card reader + { + \_SB.WTGP(60,0) + Or(UPWR,0x01, UPWR) + } + If(And(USPP,0x06)) // USB(HS1 : 0x480 /SS0 : 0x510) & USB(HS2 : 0x490 / SS1 : 0x520) + { + \_SB.GP2N(40,1) // Mask OC#(Switch to GPIO mode) + \_SB.WTGP(13,0) // Power gate GPIO13/43 at same time + \_SB.WTGP(43,0) + Or(UPWR,0x02, UPWR) + Or(UPWR,0x04, UPWR) + } + }Else{ // If(Lequal(XHCV,0xFFFF)) + If(LAnd(LEqual(HP08,0x00),LEqual(SP03,0x00))) // SD Card reader + { + \_SB.WTGP(60,0) + Or(UPWR,0x01, UPWR) + } + If(LAnd(LAnd(LEqual(HP01,0x00),LEqual(SP00,0x00)), LAnd(LEqual(HP02,0x00),LEqual(SP01,0x00)))) // USB(HS1 : 0x480 /SS0 : 0x510) &USB(HS2 : 0x490 / SS1 : 0x520) + { + \_SB.GP2N(40,1) // Mask OC#(switch to GPIO mode) + \_SB.WTGP(13,0) // Power gate GPIO13/43 at same time + \_SB.WTGP(43,0) + Or(UPWR,0x02, UPWR) + Or(UPWR,0x04, UPWR) + } + }// If(Lequal(XHCV,0xFFFF)) + }Else{ //if(LNotEqual(\UAMS,0x00)) + + // Exiting CS , Apply power if power removed + if(And(UPWR,0x01)) // SD Card reader + { + \_SB.WTGP(60,1) + } + if(And(UPWR,0x02)) // USB(HS1 : 0x480 /SS0 : 0x510) + { + \_SB.GP2N(40,0) // Un-mask OC# + \_SB.WTGP(13,1) + } + if(And(UPWR,0x04)) // USB(HS2 : 0x490 / SS1 : 0x520) + { + \_SB.GP2N(40,0) // Un-mask OC# + \_SB.WTGP(43,1) + } + } //if(LNotEqual(\UAMS,0x00)) // User not present + } // End of DUAM + } + +//USB - END + + + +// Serial IO Start + + //Power Resource for Audio Codec +Scope(\_SB.PCI0) +{ + PowerResource(PAUD, 0, 0) { + + Name(PSTA, One) // Physical Power Status of Codec 0 - OFF; 1-ON + Name(ONTM, Zero) // 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON + + Name(_STA, One) // PowerResource Logical Status 0 - OFF; 1-ON + + Method(_ON, 0){ + Store(One, _STA) // Set Logocal power state + PUAM() // Tansition Physical state to match current logical state + } // End _ON + + Method(_OFF, 0){ + Store(Zero, _STA) // Set the current power state + PUAM() // Tansition Physical state to match current logical state + } // End _OFF + + // PUAM - Power Resource User Absent Mode for onboard Audio CODEC + // Arguments: + // + // Uses: + // _STA - Variable updated by Power Resource _ON/_OFF methods + // \UAMS - Variable updated by GUAM method to show User absent/Present + // ONTM - Local variable to store ON time during Speculative ON + // ______________________________ + // | Inputs | Outputs | + // ______________________________ + // | _STA | \UAMS | GPIO | ONTM | + // ______________________________ + // | 1 | 0 | ON | !0 | + // | 1 | !0 | ON | !0 | + // | 0 | 0 | ON | !0 | + // | 0 | !0 | OFF | 0 | + // ______________________________ + + Method(PUAM, 0, Serialized) + { + If (LAnd(LEqual(^_STA, Zero), LNotEqual(\UAMS, Zero))) { //New state = OFF (_STA ==0 && \UAMS != 0) + If(LEqual(\_SB.RDGP(76), One)) { //skip if Power Resource is already in OFF + //Device OFF + // Drive GPIO 76 to Low + \_SB.WTGP(76, Zero) // Remove CODEC Power + Store(Zero, ^PSTA) + Store(Zero, ^ONTM) + } + } Else { // New state = ON (_STA=1) or (_STA=0 and \UAMS=0) + If(LNotEqual(^PSTA, One)) { //skip if Power Resource is already in ON + SGON(76, One) // VR stagger GPIO76 to high to power on device + Store(One, ^PSTA) + Store(Timer(), ^ONTM) // Start the timer for this PR + } + } // Turn power on + } //PUAM + } //PAUD +} //Scope(\_SB.PCI0) + +If(LNot(HDAD)) { // Check Funtion disable register that gets updated depending on setup option + Scope(\_SB.PCI0.HDEF) { + + Method(_PS0,0,Serialized) // D0 Method for HD-A Controller + { + If(LEqual(\_SB.PCI0.PAUD.ONTM, Zero)){ + Return() + } + + // + // Make sure "D0 delay" (AUDD) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // AUDD: Time required for device to be ready after power on + // Local1 = AUDD + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.PAUD.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(AUDD, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) { //Do not sleep if already past the delay requirement audio + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (AUDD + VRRD - time elapsed) + } + } + Method(_PS3,0,Serialized) // D3 Method for HD-A Controller(Dummy routine to support D3 state) + { + } + + Name(_PR0, Package(){\_SB.PCI0.PAUD}) + } +}// IF(HDAD) + +// I2C0 +Scope(\_SB.PCI0.I2C0) { // I2C0 + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + Store(0, Local0) // BIT0 : ADSP Disabled BIT1 : SHUB Disabled + If(LEqual(And(SDS0,0x01), 0x00)) { // Update Local0 BIT1 if SHUB disabled in setup + Or(0x02,Local0,Local0) + } + + If(LEqual(Local0,0x01)){ // Only SHUB enabled + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,\_SB.PCI0.I2C1.PXTC}) + } + Return(Package(){}) // Both SHUB and ADSP codec disabled + } + // D0 Method for I2C0 Controller(Called by _PS0) + Method(PS0X,0,Serialized) + { + Sleep(I20D) // If required add delay in controller to gurantee longest delaying device have time + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + // Drive GIO49 High - routed to Sensor HUB STOP mode + \_SB.WTGP(49,1) + Sleep(16) + } + } + + // D3 Method for I2C0 Controller(Called by _PS3) + Method(PS3X,0,Serialized) + { + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + // Drive GIO49 Low - routed to Sensor HUB STOP mode + \_SB.WTGP(49,0) + Sleep(16) + } + } +} // \_SB.PCI0.I2C0 +Scope(\_SB.PCI0.I2C0.SHUB) +{ + // D0 Method Hook for I2C1 Controller(Called by _PS0) + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C0.SHUB.PSEN.ONTM,Zero)){ + Return() + } + + // + // Make sure "D0 delay" (IC0D) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC0D: Time required for device to be ready after power on + // Local1 = IC0D + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C0.SHUB.PSEN.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC0D, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for SensorHub + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC0D + VRRD - time elapsed) + } + } + Method(_PS3,0,Serialized) + { + } + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + Return(Package(){PSEN,\_SB.PCI0.I2C1.PXTC}) + } Else { + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + Return(Package(){PSEN,\_SB.PCI0.I2C1.PXTC}) + } Else { + Return(Package(){}) + } + } + + PowerResource(PSEN, 0, 0) { + Name(ONTM, Zero) // On Timer + + Method(_STA){ + If(LEqual(SHSB, 0)){ + If(LEqual(\_SB.RDGP(46),1)) { //GPIO46 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } + }Else{ + If(LEqual(\_SB.RDGP(70),1)) { //GPIO70 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } + } + Return(0x00) + } + + Method(_ON, 0){ + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + // Drive GPIO 46 High + If(LEqual(SHSB, 0)){ + If(LEqual(SGON(46, One), One)) { // VR stagger GPIO46 to high to power on device + Store(Timer(), ^ONTM) // Start the timer + \_SB.GP2B(14, One) // Enable int line from sensor hub. GPIO14 is PIRQM(IOAPIC ln28) + } + }Else{ + If(LEqual(SGON(70, One), One)) { // VR stagger GPIO70 to high to power on device + Store(Timer(), ^ONTM) // Start the timer + \_SB.GP2B(14, One) // Enable int line from sensor hub. GPIO14 is PIRQM(IOAPIC ln28) + } + } + } // End if - Enabled in Setup and not in DFU mode + } // End _ON + + Method(_OFF, 0){ + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + // Mask interrupt from Sensorhub GPIPIRQ2IOXAPIC: GPI PIRQ[X:I] to IOxAPIC[39:24] Enable + \_SB.GP2B(14, Zero) // GPIO14 is PIRQM(IOAPIC ln28) + If(LEqual(SHSB, 0)){ + \_SB.WTGP(46, Zero) // Remove Device Power + }Else{ + \_SB.WTGP(70, Zero) + } + Store(Zero, ^ONTM) + Store(Zero , ^ONTM) + }// End if - Enabled in Setup and not in DFU mode + } // End _OFF + } //PSEN +} // Scope(SHUB) + + //Merge TouchPanel/Touch Pad Power control - I2C Sensors Need to Turn ON/OFF at same time + Scope(\_SB.PCI0.I2C1){ + + Method(PS0X,0,Serialized) + { + // If required add delay in controller to gurantee longest delaying device have time + Sleep(I21D) + } + + Method(PS3X,0,Serialized) + { + } + + PowerResource(PXTC, 0, 0){ // power rail for Touch Panel and Touchpad GPIO 89 + + Name(ONTM, 0) // 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON + Method(_STA){ + If(LEqual(\_SB.RDGP(89),1)) { //GPIO89 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } Else { + Return(0x00) + } + } + Method(_ON, 0) + { + If(LOr(LEqual(\_SB.RDGP(89),0), LEqual(\_SB.RDGP(52),0))) { //GPIO89 NOTE: 1=> ON; 0=> OFF + \_SB.WTGP(52,1) //DeAssert GPIO RST + SGON(89, One) // VR stagger GPIO89 to high to power on device + Store(Timer(), ^ONTM) + //Enable int line from touch screen and Touch pad + \_SB.GP2A(50, One) //TPL0 + If(LAnd(LNotEqual(And(SDS1,0x0800), 0x0800),LNotEqual(And(SDS1,0x1000), 0x1000))) { //Precision Enabled + \_SB.GP2A(55, One) //TPD0/1 + } + } + }// End _ON + + Method(_OFF, 0) + { + //mask interrupt from Touch Screen and Touch Pad GPIPIRQ2IOXAPIC: GPI PIRQ[X:I] to IOxAPIC[39:24] Enable + \_SB.GP2A(50, Zero) //TPL0 + If(LAnd(LNotEqual(And(SDS1,0x0800), 0x0800),LNotEqual(And(SDS1,0x1000), 0x1000))) { //Precision Enabled + \_SB.GP2A(55, Zero) //TPD0/1 + } + \_SB.WTGP(89,0) // Drive GPIO89 to remove power for Touchpad and TouchPanel + \_SB.WTGP(52,0) //GPIO RST to Touch Panel + Store(Zero , ^ONTM) + }// End _OFF + } // End PXTC + + Scope(TPL0){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + + // + // Make sure "D0 delay" (IC1D) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1D: Time required for device to be ready after power on + // Local1 = IC1D + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1D, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1D + VRRD - time elapsed) + } + } + Method(_PS3,0,Serialized) + { + } + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x01), 0x01)) + { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + } Else { + Return(Package() {}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x01), 0x01)) + { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + } Else { + Return(Package() {}) + } + } + } // End of Scope(TPL0) + Scope(TPD1){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + Method(_PS3,0,Serialized) + { + } + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x08), 0x08)) { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + } Else { + Return(Package() {}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x08), 0x08)) { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + } Else { + Return(Package() {}) + } + } + }// End of Scope(TPD1) + + //------------------------ + // Elantech Precision touchpad + //------------------------ + Scope(TPD7){ + + // + // Delay for Touchpanel & TouchPad - Both share same I2C bus + // + Method(PS0X,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0800), 0x0800)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0800), 0x0800)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPD7) + + //------------------------ + // Synaptics Precision touchpad + //------------------------ + Scope(TPD8){ + + // + // Delay for Touchpanel & TouchPad - Both share same I2C bus + // + Method(PS0X,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x1000), 0x1000)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x1000), 0x1000)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPD8) + }// Scope(\_SB.PCI0.I2C1) + +//Serial IO End + + //SDIO Reset support + Scope(\_SB.PCI0.SDHC) + { + // D0 Method for SDHC + Method(PS0X,0,Serialized) + { + // Drive GPIO77 High - 1: No GPIO RST to on board mPCIe/NGFF_WIFI + \_SB.WTGP(77,1) + } + } + + Scope(\_SB.PCI0.SDHC.WI01) + { + // D0 Method for WiFi + Method(PS0X,0,Serialized) + { + // Drive GPIO77 High - 1: No GPIO RST to on board mPCIe/NGFF_WIFI + \_SB.WTGP(77,1) + } + + // D3 Method for WiFi + Method(PS3X,0,Serialized) + { + // Drive GPIO77 Low - 0: GPIO RST to on board mPCIe/NGFF_WIFI + \_SB.WTGP(77,0) + } + } //\_SB.PCI0.SDHC.WI01 + +} //If(LAnd(LEqual(BID,BHB),LEqual(RTD3,1))) +} // End SSDT diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.cif b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.cif new file mode 100644 index 0000000..841f0f9 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.cif @@ -0,0 +1,14 @@ +<component> + name = "SsdtRtd3" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\SampleCode\SsdtRtd3\" + RefName = "SsdtRtd3" +[files] +"SsdtRtd3.sdl" +"SsdtRtd3.mak" +"Ult0Rtd3.asl" +"BRRtd3.asl" +"Rtd3FFRD.asl" +"RTD3Common.asl" +"RTD3Pcie.asl" +<endComponent> diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.mak b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.mak new file mode 100644 index 0000000..aaa91eb --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.mak @@ -0,0 +1,82 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SsdtRtd3.mak +# +# Description: MAke file to build Aptio ACPI ASL components +# +# +#<AMI_FHDR_END> +#************************************************************************* +all : BuildRTD3 + +BuildRTD3 : $(BUILD_DIR)\Ult0Rtd3.ffs + +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +!IF "$(ACPIPLATFORM_ASL_COMPILER)"=="" +!ERROR It is an invalid path, please check your ASL compiler path. +!ENDIF + +IASL = $(ACPIPLATFORM_ASL_COMPILER) +#----------------------------------------------------------------------- +$(BUILD_DIR)\Ult0Rtd3.aml : $(INTEL_RTD3_ASL_FILE) + @cl /C /EP $(INTEL_RTD3_ASL_FILE) > $(BUILD_DIR)\Ult0Rtd3.asl + @cl /C /EP $(INTEL_RTD3_COMMON_ASL_FILE) > $(BUILD_DIR)\RTD3Common.asl + @cl /C /EP $(INTEL_RTD3_PCIE_ASL_FILE) > $(BUILD_DIR)\RTD3Pcie.asl + $(IASL) -p $(BUILD_DIR)\Ult0Rtd3.aml $(BUILD_DIR)\Ult0Rtd3.asl + +$(BUILD_DIR)\Ult0Rtd3.sec: $(BUILD_DIR)\Ult0Rtd3.aml + $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW + +#Note. Expand the package with RTD3 tables. +# DXE phase will load the tables +# and update Aml contents if provided in Acpiplatform.c + +$(BUILD_DIR)\Ult0Rtd3.ffs: $(BUILD_DIR)\Ult0Rtd3.sec + $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\Ult0Rtd3.pkg + +PACKAGE.INF +[.] +BASE_NAME = Ult0Rtd3 +FFS_FILEGUID = 7FFC3536-0A8A-448B-95F4-39F5B9F09ADD +FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM +FFS_ATTRIB_CHECKSUM = TRUE + +IMAGE_SCRIPT = +{ + Compress (dummy) { + $(PROJECT_DIR)\$(BUILD_DIR)\Ult0Rtd3.sec + } +} +<<KEEP + + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.sdl b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.sdl new file mode 100644 index 0000000..db8df2a --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.sdl @@ -0,0 +1,93 @@ +TOKEN + Name = "RTD3_SUPPORT" + Value = "1" + Help = "Main switch to enable RTD3 support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +TOKEN + Name = "ULT0RTD3_SUPPORT" + Value = "1" + Help = "Main switch to enable RTD3 support for Whitetip Mountain or Sawtooth Peak CRB" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "RTD3_SUPPORT" "=" "1" +End + +TOKEN + Name = "BRRTD3_SUPPORT" + Value = "0" + Help = "Main switch to enable RTD3 support for Basking Ridge CRB" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "RTD3_SUPPORT" "=" "1" +End + +TOKEN + Name = "RTD3FFRD_SUPPORT" + Value = "0" + Help = "Main switch to enable RTD3 support for FFRD SKU CRB" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "RTD3_SUPPORT" "=" "1" +End + +PATH + Name = "INTEL_SSDTRTD3_DIR" +End + +TOKEN + Name = "INTEL_RTD3_ASL_FILE" + Value = "$(INTEL_SSDTRTD3_DIR)\Ult0Rtd3.asl" + TokenType = Expression + TargetMAK = Yes + Token = "ULT0RTD3_SUPPORT" "=" "1" +End + +TOKEN + Name = "INTEL_RTD3_ASL_FILE" + Value = "$(INTEL_SSDTRTD3_DIR)\BRRtd3.asl" + TokenType = Expression + TargetMAK = Yes + Token = "BRRTD3_SUPPORT" "=" "1" +End + +TOKEN + Name = "INTEL_RTD3_ASL_FILE" + Value = "$(INTEL_SSDTRTD3_DIR)\Rtd3FFRD.asl" + TokenType = Expression + TargetMAK = Yes + Token = "RTD3FFRD_SUPPORT" "=" "1" +End + +TOKEN + Name = "INTEL_RTD3_COMMON_ASL_FILE" + Value = "$(INTEL_SSDTRTD3_DIR)\RTD3Common.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_RTD3_PCIE_ASL_FILE" + Value = "$(INTEL_SSDTRTD3_DIR)\RTD3Pcie.asl" + TokenType = Expression + TargetMAK = Yes +End + +MODULE + Help = "Includes SsdtRtd3.mak to Project" + File = "SsdtRtd3.mak" +End + +ELINK + Name = "$(BUILD_DIR)\Ult0Rtd3.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent + Token = "RTD3_SUPPORT" "=" "1" +End diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/Ult0Rtd3.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/Ult0Rtd3.asl new file mode 100644 index 0000000..e55ac2f --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/Ult0Rtd3.asl @@ -0,0 +1,1718 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + +DefinitionBlock ( + "Rtd3.aml", + "SSDT", + 1, + "AcpiRef", + "Ult0Rtd3", + 0x1000 + ) +{ +#define ULT0RTD3 1 +Include ("RTD3Common.asl") +#undef ULT0RTD3 + +External(PEBS, IntObj) // PCI Express BAR address +External(BWT1, IntObj) // WhitTipMountain1 +External(BSPC, IntObj) // SawToothPeak + +External(\_SB.PCI0.I2C0.ACD0, DeviceObj) +External(\_SB.PCI0.I2C0.ACD1, DeviceObj) +External(\_SB.PCI0.I2C0.ACD2, DeviceObj) +External(\_SB.PCI0.I2C1.TPL1, DeviceObj) // Touch panel +External(\_SB.PCI0.I2C1.TPL2, DeviceObj) // NTRIG Digitizer Touch Panel +External(\_SB.PCI0.I2C1.TPD2, DeviceObj) // Alps touchpad +External(\_SB.PCI0.I2C1.TPL3, DeviceObj) // EETI Touch Panel +External(\_SB.PCI0.I2C1.TPD3, DeviceObj) // Cypress touchpad +External(\_SB.PCI0.I2C1.TPD7, DeviceObj) // Precision Elantech touchpad +External(\_SB.PCI0.I2C1.TPD8, DeviceObj) // Precision Synaptics touchpad +External(\_SB.PCI0.SDHC, DeviceObj) //SDIO +External(\_SB.PCI0.SDHC.WI01, DeviceObj) //SDIO Wifi +External(\_SB.PCI0.XHC.RHUB.HS10, DeviceObj) //xHCI SSP port 1 +External(S0ID) +External(\_SB.PCI0.XHC.RHUB.HS11, DeviceObj) //xHCI SSP port 2 +External(\_SB.PCI0.XHC.RHUB.HS04, DeviceObj) //EHCI HSP port 4 + +External(ADSD, FieldUnitObj) +External(CODS, IntObj) +External(\GO17) + + +External(DSPD) +External(RWAG, IntObj) + +If(LAnd(LOr(LEqual(BID,BWT1), LEqual(BID,BSPC)),LEqual(RTD3,1))) { + +If(LEqual(RWAG,1)) { // this enables board W/A for RTD3 on slot 1 + // + // PCIe RTD3 - for slot#1 + // + Scope(\_SB.PCI0.RP01) + { + Name(SLOT, 1) + Name(RSTG, 77) // reset GPIO + Name(PWRG, 83) // power GPIO + Name(RONP, 1) // reset on polarity + Name(PONP, 0) // power on polarity + Name(NGFF, 1) // Is Slot NGFF form factor 1- Yes 0- No + Name(SCLK, 0x1) // Source Clock Enable Bit Location(BIT0) + Include("Rtd3Pcie.asl") + } +} + +If(LEqual(RWAG,6)) { // this enables board W/A for RTD3 on slot 6 + // + // PCIe RTD3 - for slot#6 + // + Scope(\_SB.PCI0.RP06) + { + Name(SLOT, 6) + Name(RSTG, 77) // reset GPIO + Name(PWRG, 83) // power GPIO + Name(RONP, 1) // reset on polarity + Name(PONP, 0) // power on polarity + Name(NGFF, 0) // Is Slot NGFF form factor 1- Yes 0- No + Name(SCLK, 0x2) // Source Clock Enable Bit Location(BIT1) + Include("Rtd3Pcie.asl") + } +} + + // + // PCIe RTD3 - for slot#3 + // + Scope(\_SB.PCI0.RP03) + { + Name(SLOT, 3) + Name(RSTG, 59) // reset GPIO + Name(PWRG, 60) // power GPIO + Name(RONP, 1) // reset on polarity + Name(PONP, 0) // power on polarity + Name(NGFF, 0) // Is Slot NGFF form factor 1- Yes 0- No + Name(SCLK, 0x4) // Source Clock Enable Bit Location(BIT2) + Include("Rtd3Pcie.asl") + } + + // + // PCIe RTD3 - for slot#4 + // + Scope(\_SB.PCI0.RP04) + { + Name(SLOT, 4) + Name(RSTG, 56) // reset GPIO + Name(PWRG, 57) // power GPIO + Name(RONP, 1) // reset on polarity + Name(PONP, 0) // power on polarity + Name(NGFF, 0) // Is Slot NGFF form factor 1- Yes 0- No + Name(SCLK, 0x8) // Source Clock Enable Bit Location(BIT3) + Include("Rtd3Pcie.asl") + } + + // + // PCIe RTD3 - for slot#5 + // + Scope(\_SB.PCI0.RP05) + { + Name(SLOT, 5) + Name(RSTG, 48) // reset GPIO + Name(PWRG, 84) // power GPIO + Name(RONP, 1) // reset on polarity + Name(PONP, 0) // power on polarity + Name(NGFF, 0) // Is Slot NGFF form factor 1- Yes 0- No + Name(SCLK, 0x10) // Source Clock Enable Bit Location(BIT4) + Include("Rtd3Pcie.asl") + } + +//SATA - START + Scope(\_SB.PCI0.SAT0) { + + // D0 Method for SATA HBA + Method(_PS0,0,Serialized) + { + } + + // D3 Method for SATA HBA + Method(_PS3,0,Serialized) + { + } + + OperationRegion(SMIO,PCI_Config,0x24,4) + Field(SMIO,AnyAcc, NoLock, Preserve) { + Offset(0x00), // SATA MABR6 + MBR6, 32, // SATA ABAR + } + + Scope(PRT1) { + Name(UDSM, 0) // Use _DSM for ZPODD control. 0 = Disabled; 1 = Enabled + + // + // _DSM Device Specific Method supporting SATA ZPODD function + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Method (_DSM, 4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + if(LNot(And(RCG0,1))){ + Return(0) // HDD do nothing + } + If (LEqual(Arg0, ToUUID ("bdfaef30-aebb-11de-8a39-0800200c9a66"))) { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) { + // + // Standard query - A bitmask of functions supported + // Supports function 0-5 + // + Case (0) { + if(LEqual(ToInteger(Arg1),1)){ // Check Revision + Return (Buffer () {0xF}) + } + } + Case (1) { // Enable ZPODD feature + // Function 1: Enable Power OFF/ON. Enables the Power Off/ON hardware in the system. + // When called, the BIOS is informed that the host software is using this interface. + If(LEqual(\_SB.PCI0.SAT0.PRT1.UDSM, Zero)){ //if Ownership not acquired + Store (1, \_SB.PCI0.SAT0.PRT1.UDSM) // Indicate ZPODD _DSM control enabled + } + Return (1) // Enable Power ON/OFF + } + Case (2) { + \_SB.WTGP(86,1) // Power Off the device + Store(0,\GO17) // Enable GPIO86 + Return (1) + } + Case (3) { + \_SB.WTGP(86,0) // Power ON Device + Sleep(16) // To turn the FET + + Return (1) + } + Default { + Return (0) + } + } + } Else { + Return (0) + } + } + + Name(_PR0, Package(){P1PR}) + Name(_PR3, Package(){P1PR}) + + Name(WKEN, 0) // Device on this port wake enabled? + + Method(_S0W, 0) + { + if(LNot(And(RCG0,1))){ + }Else{ + // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { + Return(4) // OS comprehends D3cold, as described via \_SB._OSC + }Else{ + Return(3) + } + } + } // End _S0W + + Method(_DSW, 3) + { + if(LNot(And(RCG0,1))){ + Return() + } + If(Arg1) + { + Store(1,\GO17) + Store(0, WKEN) + }Else{ // Staying in S0 + If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake + { // Set WKEN to allow _OFF to enable the wake event + Store(1, WKEN) + } Else { // Clear WKEN to allow _OFF to enable the wake event, + // either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + } // End _DSW + + + PowerResource(P1PR, 0, 0) + { + Name(OFTM, Zero) // Time returned by Timer() when the Power resource was turned OFF + + Method(_STA) + { + if(LNot(And(RCG0,1))){ + If(LEqual(\_SB.RDGP(90),1)) { //GPIO90 + Return(0x00) + } Else { + Return(0x01) + } + }Else{ + // Read ZPODD Status + if(LEqual(RDGP(86),0)){ + Return(0x01) + }Else{ + Return(0x00) + } + } + } + + Method(_ON, 0) + { + If(LNotEqual(^OFTM, Zero)) { // if OFTM != 0 => Disk was turned OFF by asl + Divide(Subtract(Timer(), ^OFTM), 10000, , Local0) //Store Elapsed time in ms + Store(Zero, ^OFTM) // Reset OFTM to zero to indicate minimum 50ms requirement does not apply when _ON called next time + If(LLess(Local0, 50)) // Do not sleep if already past the delay requirement + { + Sleep(Subtract(50, Local0)) // Sleep 50ms - time elapsed + } + } + + if(LNot(And(RCG0,1))){ + SGON(90, Zero) // VR stagger GPIO90 to low to power on device + }Else{ + + SGON(86, Zero) // VR stagger GPIO86 to low to power on device + } + } + + + Method(_OFF, 0) + { + If(LNot(And(RCG0,1))){ + Add(\_SB.PCI0.SAT0.MBR6,0x198 ,Local0) + OperationRegion(PSTS, SystemMemory, Local0, 0x18) + Field(PSTS, DWordAcc, NoLock, Preserve) + { + Offset(0x0), + CMST, 1, //PxCMD.ST + CSUD, 1, //PxCMD.SUD + , 2, + CFRE, 1, //PxCMD.FRE + Offset(0x10), + SDET, 4, //PxSSTS.DET + Offset(0x14), + CDET, 4 //PxSCTL.DET + } + // if S0Ix enabled + If(LEqual(S0ID, 1)) + { + If(LOr(LEqual(SDET, 1), LEqual(SDET, 3))) //Offline flow only if Device detected and Phy not offline + { + //Clear ST (PxCMD.ST) 198[0] + Store(0, CMST) + //Clear FRE 198[4] + Store(0, CFRE) + //Clear SUD (PxCMD.SUD) 198[1] + Store(0, CSUD) + //Set DET to 4 (PxSCTL.DET) 1ac[3:0] + Store(4, CDET) + Sleep(16) + //Wait until PxSSTS.DET == 4 + While(LNotEqual(SDET, 4)){ + Sleep(16) + } + } + // Drive GPIO90 to High to power off device + \_SB.WTGP(90,1) + } // if S0Ix enabled + }Else{ + + \_SB.WTGP(86,1) // Drive GPIO86 to low to power off device. + Store(0,\GO17) // Enable ZPODD SATA_ODD_DA_N to generate SCI + } + + Store(Timer(), ^OFTM) // Store time when Disk turned OFF(non-zero OFTM indicate minimum 50ms requirement does apply when _ON called next time) + } + } // End P1PR + } //End PRT1 + + // PRT2 . Controlled by EC pin (PF6/PWMU4A/ExCTS). + Scope(PRT2) { // Port 2- Cable Connect power + + PowerResource(P2PR, 0, 0){ + Name(OFTM, Zero) // Time returned by Timer() when the Power resource was turned OFF + + Method(_STA){ + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) { // Read SATA_CABLE_PWR_EN from EC + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.SPT2)), Local0) + } Else { + Store(1, Local0) //This FET is ON during POST. It cannot be turned OFF until EC driver is loaded + } + If(LEqual(Local0,0)) { // Read SATA_CABLE_PWR_EN from EC + Return(0x00) + } Else { + Return(0x01) + } + + Return(0x01) + } + Method(_ON, 0) + { + If(LNotEqual(^OFTM, Zero)) { // if OFTM != 0 => Disk as turned OFF by asl + Divide(Subtract(Timer(), ^OFTM), 10000, , Local0) //Store Elapsed time in ms + Store(Zero, ^OFTM) // Reset OFTM to zero to indicate minimum 50ms requirement does not apply when _ON called next time + If(LLess(Local0, 50)) // Do not sleep if already past the delay requirement + { + Sleep(Subtract(50, Local0)) // Sleep 50ms - time elapsed + } + } + + //SET SATA_CABLE_PWR_EN and Send EC UpdateDevPwr - 0x2C + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) { // Check If EC driver loaded + // + // Special case for EC driven device power on using VR staggering (SGON is for GPIO driven device power on) + // Marked with "//VR Staggering" at the end of line. + // //VR Staggering + // Check for VR staggering //VR Staggering + // //VR Staggering + Divide(Subtract(Timer(), \LONT), 10000, , Local0) //Store Elapsed time in ms, ignore remainder //VR Staggering + If(LLess(Local0, \VRSD)) { //Do not sleep if already past the delay requirement //VR Staggering + // Delay for power ramp using Timer Based Sleep //VR Staggering + Sleep(Subtract(\VRSD, Local0)) //VR Staggering + } //VR Staggering + + \_SB.PCI0.LPCB.H_EC.ECWT(One, RefOf(\_SB.PCI0.LPCB.H_EC.SPT2)) + \_SB.PCI0.LPCB.H_EC.ECMD (0x2E) + + Store(Timer(), \LONT) // Update the global Last ON Method Timer //VR Staggering + } + } + Method(_OFF, 0) + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) { // Check If EC driver loaded + Add(\_SB.PCI0.SAT0.MBR6,0x218 ,Local0) + OperationRegion(PSTS, SystemMemory, Local0, 0x18) + Field(PSTS, DWordAcc, NoLock, Preserve) { + Offset(0x0), + CMST, 1, //PxCMD.ST + CSUD, 1, //PxCMD.SUD + , 2, + CFRE, 1, //PxCMD.FRE + Offset(0x10), + SDET, 4, + Offset(0x14), + CDET, 4 //PxSCTL.DET + } + If(LOr(LEqual(SDET, 1), LEqual(SDET, 3))){ //Offline flow only if Device detected and Phy not offline + //Clear ST (PxCMD.ST) + Store(0, CMST) + //Clear FRE + Store(0, CFRE) + //Clear SUD (PxCMD.SUD) + Store(0, CSUD) + //Set DET to 4 (PxSCTL.DET) + Store(4, CDET) + Sleep(16) + //Wait until PxSSTS.DET == 4 + While(LNotEqual(SDET, 4)){ + Sleep(16) + } + } + //Clear SATA_CABLE_PWR_EN and Send EC UpdateDevPwr - 0x2C + \_SB.PCI0.LPCB.H_EC.ECWT(Zero, RefOf(\_SB.PCI0.LPCB.H_EC.SPT2)) + \_SB.PCI0.LPCB.H_EC.ECMD (0x2E) + } + Store(Timer(), ^OFTM) // Store time when Disk turned OFF(non-zero OFTM indicate minimum 50ms requirement does apply when _ON called next time) + } + } // End P2PR + + Name(_PR0, Package(){P2PR}) + Name(_PR3, Package(){P2PR}) + + } //End PRT2 + + // PRT3 + Scope(PRT3) { + +// RCG0 : BIT2BIT3 : 00 - Disabled 01 - 1.5Minicard(GPIO83) 10:3.3Minicard(GPIO85) + PowerResource(P3PR, 0, 0){ + Method(_STA){ + if(LEqual(And(RCG0,0xC),0x04)){ // 1.5Minicard GPIO83 + Return(\_SB.RDGP(83)) + } + if(LEqual(And(RCG0,0xC),0x08)){ // 3.3Minicard GPIO85 + Return(\_SB.RDGP(85)) + } + Return(0x00) // Disabled + } + Method(_ON, 0) + { + if(LEqual(And(RCG0,0xC),0x04)){ // 1.5Minicard GPIO83 + SGON(83, One) // VR stagger GPIO83 to high to power on device + } + if(LEqual(And(RCG0,0xC),0x08)){ // 3.3Minicard GPIO85 + SGON(85, One) // VR stagger GPIO85 to high to power on device + } + } + Method(_OFF, 0) + { + Add(\_SB.PCI0.SAT0.MBR6,0x298 ,Local0) + OperationRegion(PSTS, SystemMemory, Local0, 0x18) + Field(PSTS, DWordAcc, NoLock, Preserve) { + Offset(0x0), + CMST, 1, //PxCMD.ST + CSUD, 1, //PxCMD.SUD + , 2, + CFRE, 1, //PxCMD.FRE + Offset(0x10), + SDET, 4, + Offset(0x14), + CDET, 4 //PxSCTL.DET + } + If(LOr(LEqual(SDET, 1), LEqual(SDET, 3))){ //Offline flow only if Device detected and Phy not offline + //Clear ST (PxCMD.ST) + Store(0, CMST) + //Clear FRE + Store(0, CFRE) + //Clear SUD (PxCMD.SUD) + Store(0, CSUD) + //Set DET to 4 (PxSCTL.DET) + Store(4, CDET) + Sleep(16) + //Wait until PxSSTS.DET == 4 + While(LNotEqual(SDET, 4)){ + Sleep(16) + } + } + + if(LEqual(And(RCG0,0xC),0x04)){ // 1.5Minicard GPIO83 + \_SB.WTGP(83,0) + Sleep(16) // Delay for power ramp + } + if(LEqual(And(RCG0,0xC),0x08)){ // 3.3Minicard GPIO85 + \_SB.WTGP(85,0) + Sleep(16) // Delay for power ramp + } + } + } // End P2PR + + Name(_PR0, Package(){P3PR}) + Name(_PR3, Package(){P3PR}) + + } //End PRT3 + + + // + // _DSM Device Specific Method supporting AHCI DEVSLP + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Name(DRV, 0) // Storage for _DSM Arg3 parameter 0 + Name(PWR, 0) // Storage for _DSM Arg3 parameter 1 + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("E4DB149B-FCFE-425b-A6D8-92357D78FC7F"))) { + // + // Switch by function index + // + Switch (Arg2) { + Case (0) { + // Standard query - A bitmask of functions supported + // Supports function 0-3 + Return(0x0f) + } + Case (1) { + // Query Device IDs (Addresses) of children where drive power and/or DevSleep are supported. + // LPT-LP SATA HBA provides autonomous link (DevSleep) support, return a package of 0 elements + Return( Package(){}) // SATA HBA provides native DevSleep + } + // + // Control power to device. + // + Case (2) { + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Store(ToInteger(DerefOf(Index(Arg3, One))), PWR) + + Switch(DRV){ + Case (Ones){ + // Turn on drive and link power to all drives. Note that even though + If(PWR){ // Applying Power + //^PRT0.P0PR._ON() // apply power to port 0 + \_SB.PCI0.SAT0.PRT1.P1PR._ON() // apply power to port 1 + \_SB.PCI0.SAT0.PRT2.P2PR._ON() // apply power to port 2 + } + } + } //Switch(DRV) + Return (0) + } //Case (2) + // + // Current status of Device/Link of Port + // + Case (3){ + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Switch(DRV){ + Case (0x0000FFFF){ // SATA Port 0 + // Bit0 => Device power state + Store(1, Local0) // always ON + Return (Local0) + } + Case (0x0001FFFF){ // SATA Port 1 + // Bit0 => Device power state + If(LEqual(\_SB.PCI0.SAT0.PRT1.P1PR._STA(), 0)){ + Store(0, Local0) + }Else{ + Store(1, Local0) + } + Return (Local0) + } + Case (0x0002FFFF){ // SATA Port 2 + // Bit0 => Device power state + If(LEqual(\_SB.PCI0.SAT0.PRT2.P2PR._STA(), 0)){ + Store(0, Local0) + }Else{ + Store(1, Local0) + } + Return (Local0) + } + Default { // Invalid SATA Port - error + Return (Ones) + } + } + } + Default { + Return (0) + } + } + } Else { // UUID does not match + Return (0) + } + } //Method(_DSM) + + } //Scope(\_SB.PCI0.SAT0) + +// SATA - END + +//USB - START + Scope(\_SB.PCI0.XHC){ + + Method(_S0W, 0) + { // PMEs can be generated from D3(hot) + Return(3) + } // End _S0W + } + + Scope(\_SB.PCI0.XHC.RHUB){ //USB XHCI RHUB + Method(_PS0,0,Serialized) + { + Store(0x00,USPP) + } + Method(_PS2,0,Serialized) + { + + OperationRegion (XHCM, SystemMemory, And(MEMB,0xFFFF0000), 0x600) + Field (XHCM, DWordAcc, NoLock, Preserve) + { + Offset(0x2), + XHCV,16, + Offset(0x480), + HP01, 1, // HS port 1 + Offset(0x490), + HP02, 1, // HS port 2 + Offset(0x510), + SP00, 1, // SS port 0 + Offset(0x520), + SP01, 1, // SS port 1 + } + If(LEqual(XHCV,0xFFFF)) // Controller in D3Hot(MEM_BASE not decoded) + { + Return() + } + If(LAnd(LEqual(HP01,0x00),LEqual(SP00,0x00))) // USB(HS1 : 0x480 /SS0 : 0x510) + { + Or(USPP,0x02, USPP) + } + If(LAnd(LEqual(HP02,0x00),LEqual(SP01,0x00))) // USB(HS2 : 0x490 / SS1 : 0x520) + { + Or(USPP,0x04, USPP) + } + } // End of PS2 method + Method(_PS3,0,Serialized) + { + } // End of PS3 method + } + +If(LNotEqual(And(XHPR,0xF),0x0)){ + Scope(\) { + PowerResource(PX01, 0, 0){ // power rail for USB3.0 ports 1 - GPIO 13 + Method(_STA){ + If(LEqual(\_SB.RDGP(13),1)) { //GPIO13 + Return(0x01) + } Else { + Return(0x00) + } + } + Method(_ON, 0) + { // Turn on + SGON(13, One) // VR stagger GPIO13 to high to power on device + } + + Method(_OFF, 0) + { // Turn off + \_SB.WTGP(13,0) + } + } // End PX01 + } +} +If(LNotEqual(And(XHPR,0xF0),0x0)){ + Scope(\) { + PowerResource(PX02, 0, 0){ // power rail for USB3.0 ports 2 - GPIO 43 + Method(_STA){ + If(LEqual(\_SB.RDGP(43),1)) { //GPIO43 + Return(0x01) + } Else { + Return(0x00) + } + } + Method(_ON, 0) + { // Turn on + SGON(43, One) // VR stagger GPIO43 to high to power on device + } + + Method(_OFF, 0) + { // Turn off + \_SB.WTGP(43,0) + } + } // End PX02 + + } +} + +if(LEqual(And(RCG0,2),2)) +{ + // USB Camera RTD3 support is enabled + Scope(\_SB.PCI0.XHC.RHUB.HS04){ + PowerResource(PX04, 0, 0){ // power rail for USB2.0 Port 4 - GPIO 25 + Method(_STA){ + If(LEqual(\_SB.RDGP(25),1)) { //GPIO25 + Return(0x01) + } Else { + Return(0x00) + } + } + Method(_ON, 0) + { // Turn on + SGON(25, One) // VR stagger GPIO25 to high to power on device + } + + Method(_OFF, 0) + { // Turn off + \_SB.WTGP(25,0) + } + } // End PX04 + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + Return(Package(){\_SB.PCI0.XHC.RHUB.HS04.PX04}) + } // End of Method _PR0 + Method(_PR2, Zero, NotSerialized, 0, PkgObj) + { + Return(Package(){\_SB.PCI0.XHC.RHUB.HS04.PX04}) + } // End of Method _PR2 + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + Return(Package(){\_SB.PCI0.XHC.RHUB.HS04.PX04}) + } // End of Method _PR3 + } // Scope(\_SB.PCI0.XHC.RHUB.HS04) +} + +If(LEqual(And(XHPR,0xF),0x01)) +{ + Scope(\_SB.PCI0.XHC.RHUB.HS01){ + Name(_PR0, Package(){\PX01}) + Name(_PR2, Package(){\PX01}) + Name(_PR3, Package(){\PX01}) + } +} + +If(LEqual(And(XHPR,0xF0),0x10)){ + Scope(\_SB.PCI0.XHC.RHUB.HS02){ + Name(_PR0, Package(){\PX02}) + Name(_PR2, Package(){\PX02}) + Name(_PR3, Package(){\PX02}) + } +} + +If(LEqual(And(XHPR,0xF),0x02)){ + Scope(\_SB.PCI0.XHC.RHUB.SSP1){ + Name(_PR0, Package(){\PX01}) + Name(_PR2, Package(){\PX01}) + Name(_PR3, Package(){\PX01}) + } // End of Scope(\_SB.PCI0.XHC.RHUB.SSP1) +} + +If(LEqual(And(XHPR,0xF0),0x20)){ + Scope(\_SB.PCI0.XHC.RHUB.SSP2){ + Name(_PR0, Package(){\PX02}) + Name(_PR2, Package(){\PX02}) + Name(_PR3, Package(){\PX02}) + } // End of Scope(\_SB.PCI0.XHC.RHUB.SSP2) +} +//USB - END +// Serial IO Start + +//Power Resource for Audio Codec +Scope(\_SB.PCI0) +{ + PowerResource(PAUD, 0, 0) { + + Name(PSTA, One) // Physical Power Status of Codec 0 - OFF; 1-ON + Name(ONTM, Zero) // 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON + + Name(_STA, One) // PowerResource Logical Status 0 - OFF; 1-ON + + Method(_ON, 0){ + Store(One, _STA) // Set Logocal power state + PUAM() // Tansition Physical state to match current logical state + } // End _ON + + Method(_OFF, 0){ + Store(Zero, _STA) // Set the current power state + PUAM() // Tansition Physical state to match current logical state + } // End _OFF + + // PUAM - Power Resource User Absent Mode for onboard Audio CODEC + // Arguments: + // + // Uses: + // _STA - Variable updated by Power Resource _ON/_OFF methods + // \UAMS - Variable updated by GUAM method to show User absent/Present + // ONTM - Local variable to store ON time during Speculative ON + // ______________________________ + // | Inputs | Outputs | + // ______________________________ + // | _STA | \UAMS | GPIO | ONTM | + // ______________________________ + // | 1 | 0 | ON | !0 | + // | 1 | !0 | ON | !0 | + // | 0 | 0 | ON | !0 | + // | 0 | !0 | OFF | 0 | + // ______________________________ + + Method(PUAM, 0, Serialized) + { + If (LAnd(LEqual(^_STA, Zero), LNotEqual(\UAMS, Zero))) { //New state = OFF (_STA ==0 && \UAMS != 0) + If(LEqual(\_SB.RDGP(76), One)) { //skip if Power Resource is already in OFF + //Device OFF + // Drive GPIO 76 to Low + \_SB.WTGP(76, Zero) // Remove CODEC Power + Store(Zero, ^PSTA) + Store(Zero, ^ONTM) + } + } Else { // New state = ON (_STA=1) or (_STA=0 and \UAMS=0) + If(LNotEqual(^PSTA, One)) { //skip if Power Resource is already in ON + SGON(76, One) // VR stagger GPIO76 to High to power on device + Store(One, ^PSTA) + Store(Timer(), ^ONTM) // Start the timer for this PR + } + } // Turn power on + } //PUAM + } //PAUD +} //Scope(\_SB.PCI0) + +If(LNot(HDAD)) { // Check Funtion disable register that gets updated depending on setup option + Scope(\_SB.PCI0.HDEF) { + + Method(_PS0,0,Serialized) // D0 Method for HD-A Controller + { + If(LEqual(\_SB.PCI0.PAUD.ONTM, Zero)){ + Return() + } + + // + // Make sure "D0 delay" (AUDD) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // AUDD: Time required for device to be ready after power on + // Local1 = AUDD + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.PAUD.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(AUDD, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) { //Do not sleep if already past the delay requirement audio + // Delay for device init + Sleep(Subtract(Local1, Local0)) //Sleep (AUDD + VRRD - time elapsed) + } + } + Method(_PS3,0,Serialized) // D3 Method for HD-A Controller(Dummy routine to support D3 state) + { + } + + Name(_PR0, Package(){\_SB.PCI0.PAUD}) + } + }// IF(HDAD) + +// ADSP device +if(LNot(ADSD)){ // Check Funtion disable register that gets updated depending on setup option + Scope(\_SB.PCI0.ADSP) { + + // D0 Method for ADSP Controller + Method(_PS0,0,Serialized) // D0 Method for ADSP Controller + { + + If(LEqual(\_SB.PCI0.PAUD.ONTM, Zero)) { + Return() + } + + // + // Make sure "D0 delay" (DSPD) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // DSPD: Time required for device to be ready after power on + // Local1 = DSPD + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.PAUD.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(DSPD, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) { //Do not sleep if already past the delay requirement audio + // Delay for device init + Sleep(Subtract(Local1, Local0)) //Sleep (DSPD + VRRD - time elapsed) + } + } + Method(_PS3,0,Serialized) // D3 Method for ADSP Controller(Dummy routine to support D3 state) + { + } + + Name(_PR0, Package(){\_SB.PCI0.PAUD}) + } +}// if(ADSD) + +// I2C0 +Scope(\_SB.PCI0.I2C0) { // I2C0 + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + Store(0, Local0) // BIT0 : ADSP Disabled BIT1 : SHUB Disabled + If (LEqual(ADSD,1)){ // Update Local0 BIT0 if ADSP disabled in RCBA function disable register(implies disabled in setup) + Or(0x01,Local0,Local0) + } + If(LEqual(And(SDS0,0x01), 0x00)) { // Update Local0 BIT1 if SHUB disabled in setup + Or(0x02,Local0,Local0) + } + + If(LEqual(Local0,0x0)){ // Both SHUB and ADSP enabled + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,\_SB.PCI0.I2C1.PXTC,\_SB.PCI0.PAUD}) + } + If(LEqual(Local0,0x01)){ // Only SHUB enabled + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,\_SB.PCI0.I2C1.PXTC}) + } + If(LEqual(Local0,0x02)){ // Only ADSP codec enabled + Return(Package(){\_SB.PCI0.PAUD}) + } + Return(Package(){}) // Both SHUB and ADSP codec disabled + } + // D0 Method for I2C0 Controller(Called by _PS0) + Method(PS0X,0,Serialized) + { + Sleep(I20D) // If required add delay in controller to gurantee longest delaying device have time + // Drive GIO49 High - routed to Sensor HUB STOP mode + \_SB.WTGP(49,1) + Sleep(16) + } + + // D3 Method for I2C0 Controller(Called by _PS3) + Method(PS3X,0,Serialized) + { + + // Drive GIO49 Low - routed to Sensor HUB STOP mode + \_SB.WTGP(49,0) + Sleep(16) + } +} // \_SB.PCI0.I2C0 + +If (AND(LEqual(CODS, 0),LNot(ADSD))){ // CODEC 0 : RealTek + Scope(\_SB.PCI0.I2C0.ACD0) + { + Name(_PR0,Package(){\_SB.PCI0.PAUD}) + } +} + +If (AND(LEqual(CODS, 1),LNot(ADSD))){ // CODEC 1 : Cirrus + Scope(\_SB.PCI0.I2C0.ACD1) + { + Name(_PR0,Package(){\_SB.PCI0.PAUD}) + } +} + +If (AND(LEqual(CODS, 2),LNot(ADSD))){ // CODEC 2 : Idt + Scope(\_SB.PCI0.I2C0.ACD2) + { + Name(_PR0,Package(){\_SB.PCI0.PAUD}) + } +} + +Scope(\_SB.PCI0.I2C0.SHUB) +{ + // D0 Method Hook for I2C1 Controller(Called by _PS0) + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C0.SHUB.PSEN.ONTM,Zero)) { + Return() + } + + // Make sure "D0 delay" (IC0D) delay is elapsed before returning _PS0 + Divide(Subtract(Timer(), \_SB.PCI0.I2C0.SHUB.PSEN.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + If(LLess(Local0, IC0D)) //Do not sleep if already past the delay requirement 100ms for SensorHub + { + // Delay for power ramp + Sleep(Subtract(IC0D, Local0)) //Sleep (100 - time elapsed) + } + } + Method(_PS3,0,Serialized) + { + } + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + Return(Package(){PSEN,\_SB.PCI0.I2C1.PXTC}) + } Else { + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + Return(Package(){PSEN,\_SB.PCI0.I2C1.PXTC}) + } Else { + Return(Package(){}) + } + } + + PowerResource(PSEN, 0, 0) { + Name(ONTM, Zero) // On Timer + + Method(_STA){ + If(LEqual(SHSB, 0)){ + If(LEqual(\_SB.RDGP(46),1)) { //GPIO89 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } + }Else{ + If(LEqual(\_SB.RDGP(70),1)) { //GPIO89 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } + } + Return(0x00) + } + + Method(_ON, 0){ + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + // Drive GPIO 46 High + If(LEqual(SHSB, 0)){ + If(LEqual(SGON(46, One), One)) { // VR stagger GPIO46 to high to power on device + Store(Timer(), ^ONTM) // Start the timer + \_SB.GP2B(14, One) // Enable int line from sensor hub. GPIO14 is PIRQM(IOAPIC ln28) + } + }Else{ + If(LEqual(SGON(70, One), One)) { // VR stagger GPIO70 to high to power on device + Store(Timer(), ^ONTM) // Start the timer + \_SB.GP2B(14, One) // Enable int line from sensor hub. GPIO14 is PIRQM(IOAPIC ln28) + } + } + } // End if - Enabled in Setup and not in DFU mode + } // End _ON + + Method(_OFF, 0){ + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + // Mask interrupt from Sensorhub GPIPIRQ2IOXAPIC: GPI PIRQ[X:I] to IOxAPIC[39:24] Enable + \_SB.GP2B(14, Zero) // GPIO14 is PIRQM(IOAPIC ln28) + If(LEqual(SHSB, 0)){ + \_SB.WTGP(46, Zero) // Remove Device Power + }Else{ + \_SB.WTGP(70, Zero) + } + Store(Zero, ^ONTM) + Store(Zero , ^ONTM) + } // End if - Enabled in Setup and not in DFU mode + } // End _OFF + } //PSEN +} // Scope(SHUB) + + //Merge TouchPanel/Touch Pad Power control - I2C Sensors Need to Turn ON/OFF at same time + Scope(\_SB.PCI0.I2C1){ + + Method(PS0X,0,Serialized) + { + // If required add delay in controller to gurantee longest delaying device have time + Sleep(I21D) + } + + Method(PS3X,0,Serialized) + { + } + + PowerResource(PXTC, 0, 0){ // power rail for Touch Panel and Touchpad GPIO 89 + + Name(ONTM, 0) // 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON + + Method(_STA){ + If(LOr(LEqual(And(SDS1,0x0800), 0x0800),LEqual(And(SDS1,0x1000), 0x1000))){ //Precision Enabled + If(LEqual(\_SB.RDGP(89),1)) { //GPIO89 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } Else { + Return(0x00) + } + } Else{ + If(LAnd(LEqual(\_SB.RDGP(88),1), LEqual(\_SB.RDGP(89),1))) { //GPIO88/89 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } Else { + Return(0x00) + } + } + } + Method(_ON, 0) + { // Turn on + If(LOr(LEqual(And(SDS1,0x0800), 0x0800),LEqual(And(SDS1,0x1000), 0x1000))){ //Precision Enabled + If(LOr(LEqual(\_SB.RDGP(89),0), LEqual(\_SB.RDGP(52),0))) { //GPIO88 NOTE: 1=> ON; 0=> OFF + \_SB.WTGP(52,1) //DeAssert GPIO RST + SGON(89, One) // VR stagger GPIO89 to high to power on device + Store(Timer(), ONTM) + //Enable int line from touch screen + \_SB.GP2A(50, One) //TPL0 + } + }Else { + If(LOr(LOr(LEqual(\_SB.RDGP(88),0), LEqual(\_SB.RDGP(89),0)), LEqual(\_SB.RDGP(52),0))) { //GPIO88/89 NOTE: 1=> ON; 0=> OFF + \_SB.WTGP(52,1) //DeAssert GPIO RST + SGON(88, One) // VR stagger GPIO88 to high to power on device + SGON(89, One) // VR stagger GPIO89 to high to power on device + Store(Timer(), ONTM) + //Enable int line from touch screen and Touch pad + \_SB.GP2A(50, One) //TPL0 + \_SB.GP2A(55, One) //TPD0/1 + } + } + } + + Method(_OFF, 0) + { // Turn off + If(LOr(LEqual(And(SDS1,0x0800), 0x0800),LEqual(And(SDS1,0x1000), 0x1000))){ //Precision Enabled + //mask interrupt from Touch Screen GPIPIRQ2IOXAPIC: GPI PIRQ[X:I] to IOxAPIC[39:24] Enable + \_SB.GP2A(50, Zero) //TPL0 + \_SB.WTGP(89,0) + \_SB.WTGP(52,0) //GPIO RST to Touch Panel + Store(Zero , ^ONTM) + } + Else{ + //mask interrupt from Touch Screen and Touch Pad GPIPIRQ2IOXAPIC: GPI PIRQ[X:I] to IOxAPIC[39:24] Enable + \_SB.GP2A(50, Zero) //TPL0 + \_SB.GP2A(55, Zero) //TPD0/1 + \_SB.WTGP(88,0) + \_SB.WTGP(89,0) + \_SB.WTGP(52,0) //GPIO RST to Touch Panel + Store(Zero , ^ONTM) + } + } + } // End PXTC + + Scope(TPL0){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + + // + // Make sure "D0 delay" (IC1D) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1D: Time required for device to be ready after power on + // Local1 = IC1D + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1D, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1D + VRRD - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x01), 0x01)) + { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + } Else { + Return(Package() {}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x01), 0x01)) + { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + } Else { + Return(Package() {}) + } + } + } // End of Scope(TPL0) + + Scope(TPD0){ + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x04), 0x04)) + { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0004), 0x0004)) + { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + } + + Scope(TPL1){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // Make sure "D0 delay" (IC1D) delay is elapsed before returning _PS0 + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + If(LLess(Local0, IC1D)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(IC1D, Local0)) //Sleep (IC1D - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0002), 0x0002)) + { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0002), 0x0002)) + { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + }Else{ + Return(Package(){}) + } + } + } + + Scope(TPD1){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x08), 0x08)) { + Return(Package(){PXTC}) + } Else { + Return(Package() {}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x08), 0x08)) { + Return(Package(){PXTC}) + } Else { + Return(Package() {}) + } + } + }// End of Scope(TPD1) + + //------------------------------ + // NTRIG Digitizer Touch Panel + //------------------------------ + Scope(TPL2){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1D) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1D: Time required for device to be ready after power on + // Local1 = IC1D + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1D, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1D + VRRD - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0020), 0x0020)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0020), 0x0020)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPL2) + + //------------------------ + // EETI Touch Panel + //------------------------ + Scope(TPL3){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // Make sure "D0 delay" (IC1D) delay is elapsed before returning _PS0 + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + If(LLess(Local0, IC1D)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(IC1D, Local0)) //Sleep (IC1D - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0040), 0x0040)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0040), 0x0040)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPL3) + + + //------------------------ + // Alps touchpad + //------------------------ + Scope(TPD2){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0080), 0x0080)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0080), 0x0080)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPD2) + + //------------------------ + // Cypress touchpad + //------------------------ + Scope(TPD3){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0100), 0x0100)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0100), 0x0100)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPD3) + + //------------------------ + // Elantech Precision touchpad + //------------------------ + Scope(TPD7){ + + // + // Delay for Touchpanel & TouchPad - Both share same I2C bus + // + Method(PS0X,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0800), 0x0800)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0800), 0x0800)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPD7) + + //------------------------ + // Synaptics Precision touchpad + //------------------------ + Scope(TPD8){ + + // + // Delay for Touchpanel & TouchPad - Both share same I2C bus + // + Method(PS0X,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x1000), 0x1000)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x1000), 0x1000)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPD8) + }// Scope(\_SB.PCI0.I2C1) + +//Serial IO End + //GPE Event handling - Start + Scope(\_GPE) { + + Method(_L11) { // Zpodd GPIO handler + Store(1,\GO17) // Clear GPI ownership to stop SCI flooding + If(LEqual(\_SB.PCI0.SAT0.PRT1.UDSM, Zero)) { + Notify(\_SB.PCI0.SAT0.PRT1, 2) // Device Wake to Device (Windows) + }Else{ + Notify(\_SB.PCI0.SAT0, 0x81) //Notify Port 1 to wake from DSM method + } // \_SB.PCI0.SAT0.UDSM + } + // + // GPIO8 PCIE slot 3 wake event + // + Method(_L08) { + // PCIe WAKE# + If(\_SB.PCI0.RP03.WKEN){ + //GPIO_OWN to GPIO Driver to stop SCI flooding + Store(1, \GO08) + Notify(\_SB.PCI0.RP03, 0x02) // DeviceWake + } + } + // + // GPIO45(0x2D) PCIE slot 4 wake event + // + Method(_L2D) { + // PCIe WAKE# + If(\_SB.PCI0.RP04.WKEN){ + //GPIO_OWN to GPIO Driver to stop SCI flooding + Store(1, \GO45) + Notify(\_SB.PCI0.RP04, 0x02) // DeviceWake + } + } + + // + // GPIO51(0x33) PCIE slot 5 wake event + // + Method(_L33) { + // PCIe WAKE# + If(\_SB.PCI0.RP05.WKEN){ + //GPIO_OWN to GPIO Driver to stop SCI flooding + Store(1, \GO51) + Notify(\_SB.PCI0.RP05, 0x02) // DeviceWake + } + } + } //Scope(\_GPE) + +If(LEqual(RWAG,0)) {// standard board configuration, no W/A bue wires for slot 1 or 6 + //SDIO Reset support + Scope(\_SB.PCI0.SDHC) { + // D0 Method for SDHC + Method(PS0X,0,Serialized) + { + // Drive GPIO77 High - 1: No GPIO RST to on board mPCIe/NGFF_WIFI + \_SB.WTGP(77,1) + } + } + + Scope(\_SB.PCI0.SDHC.WI01) { + // D0 Method for WiFi + Method(PS0X,0,Serialized) + { + // Drive GPIO77 High - 1: No GPIO RST to on board mPCIe/NGFF_WIFI + \_SB.WTGP(77,1) + } + // D3 Method for WiFi + Method(PS3X,0,Serialized) + { + // Drive GPIO77 Low - 0: GPIO RST to on board mPCIe/NGFF_WIFI + \_SB.WTGP(77,0) + } + } //\_SB.PCI0.SDHC.WI01 +} + + Scope(\_SB.PCI0.XHC){ //USB XHCI + + Name(UPWR,0) + Name(USPP,0) + // Bit 0 : USB SD Card Reader + // Bit 1 : USB(HS1 : 0x480 /SS0 : 0x510) + // BIT 2 : USB(HS2 : 0x490 / SS1 : 0x520) + + + Method(DUAM,0,Serialized) + { + + OperationRegion (XHCM, SystemMemory, And(MEMB,0xFFFF0000), 0x600) + Field (XHCM, DWordAcc, NoLock, Preserve) + { + Offset(0x2), + XHCV,16, + Offset(0x480), + HP01, 1, // HS port 1 + Offset(0x490), + HP02, 1, // HS port 2 + Offset(0x510), + SP00, 1, // SS port 0 + Offset(0x520), + SP01, 1, // SS port 1 + } + + if(LNotEqual(\UAMS,0x00)) // User not present + { + Store(0x00,UPWR) + // Enterng CS, Remove power if SD card not present + + If(LEqual(XHCV,0xFFFF)) // Controller in D3Hot(MEM_BASE not decoded) + { + If(And(USPP,0x02)) // USB(HS1 : 0x480 /SS0 : 0x510) + { + \_SB.WTGP(13,0) + Or(UPWR,0x02, UPWR) + } + If(And(USPP,0x04)) // USB(HS2 : 0x490 / SS1 : 0x520) + { + \_SB.WTGP(43,0) + Or(UPWR,0x04, UPWR) + } + }Else{ // If(Lequal(XHCV,0xFFFF)) + If(LAnd(LEqual(HP01,0x00),LEqual(SP00,0x00))) // USB(HS1 : 0x480 /SS0 : 0x510) + { + \_SB.WTGP(13,0) + Or(UPWR,0x02, UPWR) + } + If(LAnd(LEqual(HP02,0x00),LEqual(SP01,0x00))) // USB(HS2 : 0x490 / SS1 : 0x520) + { + \_SB.WTGP(43,0) + Or(UPWR,0x04, UPWR) + } + }// If(Lequal(XHCV,0xFFFF)) + }Else{ //if(LNotEqual(\UAMS,0x00)) + + // Exiting CS , Apply power if power removed + if(And(UPWR,0x02)) // USB(HS1 : 0x480 /SS0 : 0x510) + { + \_SB.WTGP(13,1) + } + if(And(UPWR,0x04)) // USB(HS2 : 0x490 / SS1 : 0x520) + { + \_SB.WTGP(43,1) + } + } //if(LNotEqual(\UAMS,0x00)) // User not present + } // End of DUAM + } +} //If(LAnd(LEqual(BID,BWT1),LEqual(RTD3,1))) +} // End SSDT + diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.asl new file mode 100644 index 0000000..bd69431 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.asl @@ -0,0 +1,134 @@ + +DefinitionBlock ( + "SsdtZpOdd.aml", + "SSDT", + 1, + "Intel", + "zpodd", + 0x1000 + ) +{ +External(PFLV) +External(FDTP) +External(GPE3) +External(\GL00) +External(\GL08) +External(GPS3) +External(\_SB.PCI0.SAT0.PRT2, DeviceObj) +External(\GIV0) +External(RTD3, IntObj) + + If(LEqual(RTD3, Zero)) + { + Scope(\_SB.PCI0.SAT0.PRT2) + { + + // + // _DSM Device Specific Method supporting SATA ZPODD function + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Method (_DSM, 4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("bdfaef30-aebb-11de-8a39-0800200c9a66"))) { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) { + // + // Standard query - A bitmask of functions supported + // Supports function 0-5 + // + Case (0) { + switch(ToInteger(Arg1)) { + case(1) { + // + // Return - 0 (No Functions supported) for Desktop Platforms + // + If(LEqual(PFLV,FDTP)) { + Return (Buffer () {0}) + } + Return (Buffer () {0xF}) + } + Default {Return (Buffer () {0})} + } + } // Case (0) + // + // Enable ZPODD feature + // + Case (1) { + Return (1) + } // Case (1) + // + // Power Off Device + // + Case (2) { + // + // Drive GPIO to low to power off device. + // + Store(0,GPE3) + If(LEqual(And(\GL00, 0x08), 0x08)) + { + Or(\GIV0, 0x08, \GIV0) + } Else { + And(\GIV0, 0xF7, \GIV0) + } + And(\GL08, 0xEF, \GL08) + Sleep(0xC8) + Store(1,GPS3) + Store(1,GPE3) + Return (1) + } // Case (2) + // + // Power ON Device + // + Case (3) { + Store(0,GPE3) + Store(1,GPS3) + Or(\GL08, 0x10, \GL08) + Return (1) + } // Case (3) + + Default { + Return (0) + } + } // Switch (ToInteger(Arg2)) + } Else { + Return (0) + } // bdfaef30-aebb-11de-8a39-0800200c9a66 + } // _DSM + } // (\_SB.PCI0.SAT0) +// +// GPE Event Handler +// +Scope(\_GPE) { + // + // SATA_ODD_DA + // + Method(_L13) { + // + // Do nothing if Desktop platform + // + If(LEqual(PFLV,FDTP)) { + Return () + } + // + // Power on drive, disable SCI on GPI + // Disable SCI on GPIO3 (PMBASE+0x28 - BIT19) + // + Store(0,GPE3) + // + // Drive GPIO68 to High to power on device. + // + Or(\GL08, 0x10, \GL08) + // + // Notify the OSPM + // + Notify(\_SB.PCI0.SAT0, 0x82) + Return () + } +} // \_GPE +} // If(LEqual(RTD3, Zero)) +} // End SSDT diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.cif b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.cif new file mode 100644 index 0000000..02be8d2 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.cif @@ -0,0 +1,11 @@ +<component> + name = "SsdtZpOdd" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\SampleCode\SsdtZpOdd\" + RefName = "SsdtZpOdd" +[files] +"SsdtZpOdd.sdl" +"SsdtZpOdd.mak" +"SsdtZpOdd.asl" +"SsdtZpOddULT.asl" +<endComponent> diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.mak b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.mak new file mode 100644 index 0000000..81eb0d1 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.mak @@ -0,0 +1,89 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SsdtZpOdd.mak +# +# Description: MAke file to build Aptio ACPI ASL components +# +# +#<AMI_FHDR_END> +#************************************************************************* +all : BuildZPODD + +BuildZPODD : $(BUILD_DIR)\SsdtZpOdd.ffs + +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +!IF "$(ACPIPLATFORM_ASL_COMPILER)"=="" +!ERROR It is an invalid path, please check your ASL compiler path. +!ENDIF + +IASL = $(ACPIPLATFORM_ASL_COMPILER) +#----------------------------------------------------------------------- +$(BUILD_DIR)\SsdtZpOdd.aml $(BUILD_DIR)\SsdtZpOddult.aml: $(BUILD_DIR)\SsdtZpOdd.asl $(BUILD_DIR)\SsdtZpOddult.asl + $(SILENT)$(IASL) -p $@ $*.asl + +$(BUILD_DIR)\SsdtZpOdd.sec $(BUILD_DIR)\SsdtZpOddult.sec: $(BUILD_DIR)\SsdtZpOdd.aml $(BUILD_DIR)\SsdtZpOddult.aml + $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW + +#Note. Expand the package with ZpOdd tables. +# DXE phase will load the tables +# and update Aml contents if provided in Acpiplatform.c + +$(BUILD_DIR)\SsdtZpOdd.ffs: $(BUILD_DIR)\SsdtZpOdd.sec $(BUILD_DIR)\SsdtZpOddult.sec + $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\SsdtZpOdd.pkg + +PACKAGE.INF +[.] +BASE_NAME = ZpOdd +FFS_FILEGUID = E42A76A1-D4B3-4c26-A1BB-84A3502A779F + FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM +FFS_ATTRIB_CHECKSUM = TRUE + +IMAGE_SCRIPT = +{ + Compress (dummy) { + $(PROJECT_DIR)\$(BUILD_DIR)\SsdtZpOdd.sec + $(PROJECT_DIR)\$(BUILD_DIR)\SsdtZpOddult.sec + } +} +<<KEEP + +#-----------------------------------------------------------------------# +# Process SG asl files +#-----------------------------------------------------------------------# +$(BUILD_DIR)\SsdtZpOdd.asl : $(INTEL_ZPODD_ASL_FILE) + $(CP) /I$(INTEL_SSDTZPODD_DIR) /FItoken.h /C $(INTEL_ZPODD_ASL_FILE) > $(BUILD_DIR)\SsdtZpOdd.asl + +$(BUILD_DIR)\SsdtZpOddult.asl : $(INTEL_ZPODDULT_ASL_FILE) + $(CP) /I$(INTEL_SSDTZPODD_DIR) /FItoken.h /C $(INTEL_ZPODDULT_ASL_FILE) > $(BUILD_DIR)\SsdtZpOddult.asl + + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.sdl b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.sdl new file mode 100644 index 0000000..98dbe92 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.sdl @@ -0,0 +1,59 @@ +TOKEN + Name = "ZPODD_SUPPORT" + Value = "1" + Help = "Main switch to enable ZpODD support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes + Token = "PCH_SKU" "=" "1" +End + +TOKEN + Name = "STD_ZPODD_SUPPORT" + Value = "1" + Help = "Main switch to enable Stand ZpODD support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "ZPODD_SUPPORT" "=" "1" +End + +TOKEN + Name = "ULT_ZPODD_SUPPORT" + Value = "1" + Help = "Main switch to enable ULT ZpODD support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "ZPODD_SUPPORT" "=" "1" +End + +PATH + Name = "INTEL_SSDTZPODD_DIR" +End + +TOKEN + Name = "INTEL_ZPODD_ASL_FILE" + Value = "$(INTEL_SSDTZPODD_DIR)\SsdtZpOdd.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_ZPODDULT_ASL_FILE" + Value = "$(INTEL_SSDTZPODD_DIR)\SsdtZpOddult.asl" + TokenType = Expression + TargetMAK = Yes +End + +MODULE + Help = "Includes SsdtZpOdd.mak to Project" + File = "SsdtZpOdd.mak" +End + +ELINK + Name = "$(BUILD_DIR)\SsdtZpOdd.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOddULT.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOddULT.asl new file mode 100644 index 0000000..dd393d4 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOddULT.asl @@ -0,0 +1,110 @@ + +DefinitionBlock ( + "SsdtZpOddult.aml", + "SSDT", + 1, + "Intel", + "zpoddult", + 0x1000 + ) +{ +External(\GO17) +External(\_SB.PCI0.SAT0.PRT1, DeviceObj) +External(RTD3, IntObj) +External(ECON, IntObj) +External(\_SB.WTGP, MethodObj) + + + If(LEqual(RTD3, Zero)) + { + Scope(\_SB.PCI0.SAT0.PRT1) + { + + // + // _DSM Device Specific Method supporting SATA ZPODD function + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Method (_DSM, 4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("bdfaef30-aebb-11de-8a39-0800200c9a66"))) { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) { + // + // Standard query - A bitmask of functions supported + // Supports function 0-5 + // + Case (0) { + switch(ToInteger(Arg1)) { + case(1) { + // + // Return - 0 (No Functions supported) for Desktop Platforms + // + If(LEqual(ECON, Zero)) { + Return (Buffer () {0}) + } + Return (Buffer () {0xF}) + } + Default {Return (Buffer () {0})} + } + } // Case (0) + // + // Enable ZPODD feature + // + Case (1) { + Return (1) + } // Case (1) + // + // Power Off Device + // + Case (2) { + // + // Drive GPIO to low to power off device. + // + \_SB.WTGP(86,1) // Power Off the device + Store(0,\GO17) // Enable GPIO86 + Return (1) + } // Case (2) + // + // Power ON Device + // + Case (3) { + \_SB.WTGP(86,0) // Power ON Device + Store(1,\GO17) // Enable GPIO86 + Sleep(0x0A) // To turn the FET + Return (1) + } // Case (3) + + Default { + Return (0) + } + } // Switch (ToInteger(Arg2)) + } Else { + Return (0) + } // bdfaef30-aebb-11de-8a39-0800200c9a66 + } // _DSM + } // (\_SB.PCI0.SAT0) + +// +// GPE Event Handler +// +Scope(\_GPE) { + // + // GPI03 = SATA_ODD_DA + // + Method(_L11) { + If(LEqual(ECON, Zero)) { + Return () + } + + Store(1,\GO17) // Enable GPIO86 + Notify(\_SB.PCI0.SAT0, 0x81) + Return () + } +} // \_GPE +} // If(LEqual(RTD3, Zero)) +} // End SSDT |