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author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
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committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
tree | eebe9b0d0ca03062955223097e57da84dd618b9a /ReferenceCode/Chipset/LynxPoint/LynxPoint.cif | |
download | zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz |
Diffstat (limited to 'ReferenceCode/Chipset/LynxPoint/LynxPoint.cif')
-rw-r--r-- | ReferenceCode/Chipset/LynxPoint/LynxPoint.cif | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/LynxPoint/LynxPoint.cif b/ReferenceCode/Chipset/LynxPoint/LynxPoint.cif new file mode 100644 index 0000000..1722234 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/LynxPoint.cif @@ -0,0 +1,47 @@ +<component> + name = "Intel Pch SB Refcode" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\LynxPoint" + RefName = "Intel Pch SB Refcode" +[files] +"Pch.sdl" +[parts] +"PchAcpiTables" +"ActiveBios" +"IntelPchInclude" +"IoTrap" +"IntelLegacyInterrupt" +"PchLib" +"PchInitDxe" +"PchInitPeim" +"PchSmiDispatcher" +"PchPcieSmm" +"IntelPchPpiLib" +"IntelPchProtocolLib" +"PchReset" +"PchResetPeim" +"PchResetCommonLib" +"PchSampleCode" +"SataController" +"PchSerialGpio" +"SmartTimer" +"PchSmbusCommonLib" +"PchSmbusDxe" +"PchSmbusArpDisabled" +"PeiSmmControl" +"SmmControl" +"PchSpiCommonLib" +"PchSpiPeim" +"PchSpiSmm" +"PchSpiRuntime" +"PchSmbusSmm" +"PchSmbusArpEnabled" +"PchUsbCommonLib" +"PchUsb" +"Wdt" +"PchGuidLib" +"PchLateInitSmm" +"PchS3Support" +"PchS3Peim" +"S3SupportSmm" +<endComponent>
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