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| author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
|---|---|---|
| committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
| commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
| tree | eebe9b0d0ca03062955223097e57da84dd618b9a /ReferenceCode/Haswell/Include | |
| download | zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz | |
Diffstat (limited to 'ReferenceCode/Haswell/Include')
20 files changed, 3007 insertions, 0 deletions
diff --git a/ReferenceCode/Haswell/Include/CommonIncludes.h b/ReferenceCode/Haswell/Include/CommonIncludes.h new file mode 100644 index 0000000..4fe8b54 --- /dev/null +++ b/ReferenceCode/Haswell/Include/CommonIncludes.h @@ -0,0 +1,120 @@ +/** @file + This file defines common equates. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Mobile Silicon Support Module" and is + licensed for Intel Mobile CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _COMMON_INCLUDES_H_ +#define _COMMON_INCLUDES_H_ + +#define V_INTEL_VID 0x8086 + +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_MILLI_SECOND +#define STALL_ONE_MILLI_SECOND 1000 +#endif +// +// Min Max +// +#define V_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define V_MAX(a, b) (((a) > (b)) ? (a) : (b)) + +/// +/// Bit map macro +/// +#ifndef BIT0 + +#define BIT63 0x8000000000000000ULL +#define BIT62 0x4000000000000000ULL +#define BIT61 0x2000000000000000ULL +#define BIT60 0x1000000000000000ULL +#define BIT59 0x0800000000000000ULL +#define BIT58 0x0400000000000000ULL +#define BIT57 0x0200000000000000ULL +#define BIT56 0x0100000000000000ULL +#define BIT55 0x0080000000000000ULL +#define BIT54 0x0040000000000000ULL +#define BIT53 0x0020000000000000ULL +#define BIT52 0x0010000000000000ULL +#define BIT51 0x0008000000000000ULL +#define BIT50 0x0004000000000000ULL +#define BIT49 0x0002000000000000ULL +#define BIT48 0x0001000000000000ULL +#define BIT47 0x0000800000000000ULL +#define BIT46 0x0000400000000000ULL +#define BIT45 0x0000200000000000ULL +#define BIT44 0x0000100000000000ULL +#define BIT43 0x0000080000000000ULL +#define BIT42 0x0000040000000000ULL +#define BIT41 0x0000020000000000ULL +#define BIT40 0x0000010000000000ULL +#define BIT39 0x0000008000000000ULL +#define BIT38 0x0000004000000000ULL +#define BIT37 0x0000002000000000ULL +#define BIT36 0x0000001000000000ULL +#define BIT35 0x0000000800000000ULL +#define BIT34 0x0000000400000000ULL +#define BIT33 0x0000000200000000ULL +#define BIT32 0x0000000100000000ULL + +#define BIT31 0x80000000 +#define BIT30 0x40000000 +#define BIT29 0x20000000 +#define BIT28 0x10000000 +#define BIT27 0x08000000 +#define BIT26 0x04000000 +#define BIT25 0x02000000 +#define BIT24 0x01000000 +#define BIT23 0x00800000 +#define BIT22 0x00400000 +#define BIT21 0x00200000 +#define BIT20 0x00100000 +#define BIT19 0x00080000 +#define BIT18 0x00040000 +#define BIT17 0x00020000 +#define BIT16 0x00010000 +#define BIT15 0x00008000 +#define BIT14 0x00004000 +#define BIT13 0x00002000 +#define BIT12 0x00001000 +#define BIT11 0x00000800 +#define BIT10 0x00000400 +#define BIT9 0x00000200 +#define BIT8 0x00000100 +#define BIT7 0x00000080 +#define BIT6 0x00000040 +#define BIT5 0x00000020 +#define BIT4 0x00000010 +#define BIT3 0x00000008 +#define BIT2 0x00000004 +#define BIT1 0x00000002 +#define BIT0 0x00000001 +#endif + +#define BITS(x) (1 << (x)) + +/* +Notes : + 1. Bit position always starts at 0. + 2. Following macros are applicable only for Word alligned integers. +*/ +#define BIT(Pos, Value) (1 << (Pos) & (Value)) +#define BITRANGE(From, Width, Value) (((Value) >> (From)) & ((1 << (Width)) - 1)) + +#endif diff --git a/ReferenceCode/Haswell/Include/CpuAccess.h b/ReferenceCode/Haswell/Include/CpuAccess.h new file mode 100644 index 0000000..e3dd024 --- /dev/null +++ b/ReferenceCode/Haswell/Include/CpuAccess.h @@ -0,0 +1,28 @@ +/** @file + Macros to simplify and abstract the interface to CPU configuration. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _CPUACCESS_H_ +#define _CPUACCESS_H_ + +#include "CpuRegs.h" +#include "CpuDataStruct.h" +#include "CpuBaseLib.h" + +#endif diff --git a/ReferenceCode/Haswell/Include/CpuBaseLib.h b/ReferenceCode/Haswell/Include/CpuBaseLib.h new file mode 100644 index 0000000..87c8363 --- /dev/null +++ b/ReferenceCode/Haswell/Include/CpuBaseLib.h @@ -0,0 +1,193 @@ +/** @file + +@copyright + Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _CPU_BASE_LIB_H +#define _CPU_BASE_LIB_H + +/// +/// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number +/// +#define EfiMakeCpuVersion(f, m, s) (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s))) + +#if defined (__GNUC__) +#define IA32API _EFIAPI +#else +#define IA32API __cdecl +#endif + +/** + Halt the Cpu +**/ +VOID +IA32API +EfiHalt ( + VOID + ); + +/** + Write back and invalidate the Cpu cache +**/ +VOID +IA32API +EfiWbinvd ( + VOID + ); + +/** + Invalidate the Cpu cache +**/ +VOID +IA32API +EfiInvd ( + VOID + ); + +/** + Get the Cpu info by excute the CPUID instruction + + @param[in] RegisterInEax -The input value to put into register EAX + @param[in] Regs -The Output value +**/ +VOID +IA32API +EfiCpuid ( + IN UINT32 RegisterInEax, + OUT EFI_CPUID_REGISTER *Regs + ); + +/** + When RegisterInEax != 4, the functionality is the same as EfiCpuid. + When RegisterInEax == 4, the function return the deterministic cache + parameters by excuting the CPUID instruction + + @param[in] RegisterInEax - The input value to put into register EAX + @param[in] CacheLevel - The deterministic cache level + @param[in] Regs - The Output value +**/ +VOID +IA32API +EfiCpuidExt ( + IN UINT32 RegisterInEax, + IN UINT32 CacheLevel, + OUT EFI_CPUID_REGISTER *Regs + ); + +/** + Read Cpu MSR + + @param[in] Index - The index value to select the register + + @retval UINT64 - the read data +**/ +UINT64 +IA32API +EfiReadMsr ( + IN UINT32 Index + ); + +/** + Write Cpu MSR + + @param[in] Index - The index value to select the register + @param[in] Value - The value to write to the selected register +**/ +VOID +IA32API +EfiWriteMsr ( + IN UINT32 Index, + IN UINT64 Value + ); + +/** + Read Time stamp + + @retval Return the read data +**/ +UINT64 +IA32API +EfiReadTsc ( + VOID + ); + +/** + Writing back and invalidate the cache,then diable it +**/ +VOID +IA32API +EfiDisableCache ( + VOID + ); + +/** + Invalidate the cache,then Enable it +**/ +VOID +IA32API +EfiEnableCache ( + VOID + ); + +/** + Get Eflags + + @retval Return the Eflags value +**/ +UINT32 +IA32API +EfiGetEflags ( + VOID + ); + +/** + Disable interrupt +**/ +VOID +IA32API +EfiDisableInterrupts ( + VOID + ); +/** + Enable interrupt +**/ +VOID +IA32API +EfiEnableInterrupts ( + VOID + ); + +/** + Extract CPU detail version infomation + + @param[in] FamilyId - FamilyId, including ExtendedFamilyId + @param[in] Model - Model, including ExtendedModel + @param[in] SteppingId - SteppingId + @param[in] Processor - Processor +**/ +VOID +IA32API +EfiCpuVersion ( + IN UINT16 *FamilyId, + OPTIONAL + IN UINT8 *Model, + OPTIONAL + IN UINT8 *SteppingId, + OPTIONAL + IN UINT8 *Processor OPTIONAL + ); + +#endif diff --git a/ReferenceCode/Haswell/Include/CpuDataStruct.h b/ReferenceCode/Haswell/Include/CpuDataStruct.h new file mode 100644 index 0000000..bb2aee4 --- /dev/null +++ b/ReferenceCode/Haswell/Include/CpuDataStruct.h @@ -0,0 +1,142 @@ +/** @file + CPU data structure + +@copyright + Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _CPU_DATA_STRUCT_H +#define _CPU_DATA_STRUCT_H + +#include EFI_GUID_DEFINITION (SmramCpuDataVariable) +#include EFI_GUID_DEFINITION (SmramCpuDataHeader) + +#pragma pack(1) +typedef struct { + UINT16 Limit; + UINTN Base; +} PSEUDO_DESCRIPTOR; +#pragma pack() + +typedef struct { + BOOLEAN APState; + BOOLEAN S3BootPath; + EFI_PHYSICAL_ADDRESS WakeUpBuffer; + EFI_PHYSICAL_ADDRESS GdtrProfile; + EFI_PHYSICAL_ADDRESS IdtrProfile; + EFI_PHYSICAL_ADDRESS CpuPrivateData; + EFI_PHYSICAL_ADDRESS StackAddress; + EFI_PHYSICAL_ADDRESS MicrocodePointerBuffer; + EFI_PHYSICAL_ADDRESS SmramBase; + EFI_PHYSICAL_ADDRESS SmmStartImageBase; + UINT32 SmmStartImageSize; + UINT32 NumberOfCpus; +} ACPI_CPU_DATA; + +typedef struct { + // + // Guid as Signature. + // + EFI_GUID HeaderGuid; + EFI_PHYSICAL_ADDRESS AcpiCpuPointer; + ACPI_CPU_DATA AcpiCpuData; + + // + // It points the data defined below. + // + EFI_PHYSICAL_ADDRESS GdtrProfileOffset; + EFI_PHYSICAL_ADDRESS GdtOffset; + EFI_PHYSICAL_ADDRESS IdtrProfileOffset; + EFI_PHYSICAL_ADDRESS IdtOffset; + EFI_PHYSICAL_ADDRESS CpuPrivateDataOffset; + EFI_PHYSICAL_ADDRESS S3BootScriptTableOffset; + EFI_PHYSICAL_ADDRESS S3BspMtrrTableOffset; + EFI_PHYSICAL_ADDRESS MicrocodePointerBufferOffset; ///< It is pointer to pointer array. + EFI_PHYSICAL_ADDRESS MicrocodeDataBufferOffset; ///< It is pointer to the data. + /// + /// We need put all the data buffer here as well. + /// These data will be copied to original location in S3. + /// + // + // DataBuffer size + // + UINT32 GdtrProfileSize; + UINT32 GdtSize; + UINT32 IdtrProfileSize; + UINT32 IdtSize; + UINT32 CpuPrivateDataSize; + UINT32 S3BootScriptTableSize; + UINT32 S3BspMtrrTableSize; + UINT32 MicrocodePointerBufferSize; + UINT32 MicrocodeDataBufferSize; + + // + // UINT8 WakeUpBufferData[WakeUpBufferSize]; + // UINT8 GdtrProfileData[GdtrProfileSize]; + // UINT8 GdtData[GdtSize]; + // UINT8 IdtrProfileData[IdtrProfileSize]; + // UINT8 IdtData[IdtSize]; + // UINT8 CpuPrivateData[CpuPrivateDataSize]; + // UINT8 S3BootScriptTable[S3BootScriptTableSize]; + // UINT8 S3BspMtrrTable[S3BspMtrrTableSize]; + // UINT32 MicrocodePointerBufferData[NumberOfCpus + 1]; + // UINT8 MicrocodeDataBufferData[MicrocodeDataBufferSize * NumberOfCpus]; + // +} SMRAM_CPU_DATA; + +typedef struct { + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; +} EFI_CPUID_REGISTER; + +typedef struct { + UINT32 HeaderVersion; + UINT32 UpdateRevision; + UINT32 Date; + UINT32 ProcessorId; + UINT32 Checksum; + UINT32 LoaderRevision; + UINT32 ProcessorFlags; + UINT32 DataSize; + UINT32 TotalSize; + UINT8 Reserved[12]; +} EFI_CPU_MICROCODE_HEADER; + +typedef struct { + UINT32 ExtendedSignatureCount; + UINT32 ExtendedTableChecksum; + UINT8 Reserved[12]; +} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER; + +typedef struct { + UINT32 ProcessorSignature; + UINT32 ProcessorFlag; + UINT32 ProcessorChecksum; +} EFI_CPU_MICROCODE_EXTENDED_TABLE; + +typedef struct { + UINT32 Stepping : 4; + UINT32 Model : 4; + UINT32 Family : 4; + UINT32 Type : 2; + UINT32 Reserved1 : 2; + UINT32 ExtendedModel : 4; + UINT32 ExtendedFamily : 8; + UINT32 Reserved2 : 4; +} EFI_CPU_VERSION; + +#endif diff --git a/ReferenceCode/Haswell/Include/CpuPowerMgmt.dsc b/ReferenceCode/Haswell/Include/CpuPowerMgmt.dsc new file mode 100644 index 0000000..1acb64f --- /dev/null +++ b/ReferenceCode/Haswell/Include/CpuPowerMgmt.dsc @@ -0,0 +1,145 @@ +## @file +# Build description file for building the power management ACPI tables +# +#@copyright +# Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + +[=============================================================================] +# +# Instructions for building the power management ACPI table storage file +# +[=============================================================================] +[Build.Ia32.ACPITABLE,Build.x64.ACPITABLE] +# +# Check if we have any source to work with. +# +!IFNDEF SECTIONS +!IFNDEF ASL_FILES +!ERROR No ASL source files to build were defined in the INF file +!ENDIF +!ENDIF + +# +# Define some macros to simplify changes +# +TARGET_FFS_FILE = $(BIN_DIR)\$(FILE_GUID)-$(BASE_NAME).ffs + +# +# Build CST SSDT sections for processor 0 +# +$(DEST_DIR)\SsdtCpu0Cst.sec : $(ASL_SOURCE_FILES) $(ASL_FILES) + $(ASL) $(ASL_FLAGS) $(DEST_DIR)\Ssdt\Cpu0Cst.asl + -copy $(DEST_DIR)\Ssdt\Cpu0Cst.aml $(DEST_DIR)\SsdtCpu0Cst.acpi + $(GENSECTION) -I $(DEST_DIR)\SsdtCpu0Cst.acpi -O $(DEST_DIR)\SsdtCpu0Cst.sec -S EFI_SECTION_RAW + +# +# Build IST SSDT sections for processor 0 +# +$(DEST_DIR)\SsdtCpu0Ist.sec : $(ASL_SOURCE_FILES) $(ASL_FILES) + $(ASL) $(ASL_FLAGS) $(DEST_DIR)\Ssdt\Cpu0Ist.asl + -copy $(DEST_DIR)\Ssdt\Cpu0Ist.aml $(DEST_DIR)\SsdtCpu0Ist.acpi + $(GENSECTION) -I $(DEST_DIR)\SsdtCpu0Ist.acpi -O $(DEST_DIR)\SsdtCpu0Ist.sec -S EFI_SECTION_RAW + +# +# Build TST SSDT sections for processor 0 +# +$(DEST_DIR)\SsdtCpu0Tst.sec : $(ASL_SOURCE_FILES) $(ASL_FILES) + $(ASL) $(ASL_FLAGS) $(DEST_DIR)\Ssdt\Cpu0Tst.asl + -copy $(DEST_DIR)\Ssdt\Cpu0Tst.aml $(DEST_DIR)\SsdtCpu0Tst.acpi + $(GENSECTION) -I $(DEST_DIR)\SsdtCpu0Tst.acpi -O $(DEST_DIR)\SsdtCpu0Tst.sec -S EFI_SECTION_RAW + + +# +# Build CST SSDT sections for processor 1 +# +$(DEST_DIR)\SsdtApCst.sec : $(ASL_SOURCE_FILES) $(ASL_FILES) + $(ASL) $(ASL_FLAGS) $(DEST_DIR)\Ssdt\ApCst.asl + -copy $(DEST_DIR)\Ssdt\ApCst.aml $(DEST_DIR)\SsdtApCst.acpi + $(GENSECTION) -I $(DEST_DIR)\SsdtApCst.acpi -O $(DEST_DIR)\SsdtApCst.sec -S EFI_SECTION_RAW + +# +# Build IST SSDT sections for processor 1 +# +$(DEST_DIR)\SsdtApIst.sec : $(ASL_SOURCE_FILES) $(ASL_FILES) + $(ASL) $(ASL_FLAGS) $(DEST_DIR)\Ssdt\ApIst.asl + -copy $(DEST_DIR)\Ssdt\ApIst.aml $(DEST_DIR)\SsdtApIst.acpi + $(GENSECTION) -I $(DEST_DIR)\SsdtApIst.acpi -O $(DEST_DIR)\SsdtApIst.sec -S EFI_SECTION_RAW + +# +# Build TST SSDT sections for processor 1 +# +$(DEST_DIR)\SsdtApTst.sec : $(ASL_SOURCE_FILES) $(ASL_FILES) + $(ASL) $(ASL_FLAGS) $(DEST_DIR)\Ssdt\ApTst.asl + -copy $(DEST_DIR)\Ssdt\ApTst.aml $(DEST_DIR)\SsdtApTst.acpi + $(GENSECTION) -I $(DEST_DIR)\SsdtApTst.acpi -O $(DEST_DIR)\SsdtApTst.sec -S EFI_SECTION_RAW + +# +# Build SSDT sections for processor power management +# +$(DEST_DIR)\SsdtCpuPm.sec : $(ASL_SOURCE_FILES) $(ASL_FILES) + $(ASL) $(ASL_FLAGS) $(DEST_DIR)\Ssdt\CpuPm.asl + -copy $(DEST_DIR)\Ssdt\CpuPm.aml $(DEST_DIR)\SsdtCpuPm.acpi + $(GENSECTION) -I $(DEST_DIR)\SsdtCpuPm.acpi -O $(DEST_DIR)\SsdtCpuPm.sec -S EFI_SECTION_RAW + +# +# Build SSDT sections for processor power management +# +$(DEST_DIR)\SsdtCtdp.sec : $(ASL_SOURCE_FILES) $(ASL_FILES) + $(ASL) $(ASL_FLAGS) $(DEST_DIR)\Ssdt\Ctdp.asl + -copy $(DEST_DIR)\Ssdt\Ctdp.aml $(DEST_DIR)\SsdtCtdp.acpi + $(GENSECTION) -I $(DEST_DIR)\SsdtCtdp.acpi -O $(DEST_DIR)\SsdtCtdp.sec -S EFI_SECTION_RAW + +# +# Build LakeTiny SSDT sections for processor power management +# +$(DEST_DIR)\SsdtLakeTiny.sec : $(ASL_SOURCE_FILES) $(ASL_FILES) + $(ASL) $(ASL_FLAGS) $(DEST_DIR)\Ssdt\LakeTiny.asl + -copy $(DEST_DIR)\Ssdt\LakeTiny.aml $(DEST_DIR)\SsdtLakeTiny.acpi + $(GENSECTION) -I $(DEST_DIR)\SsdtLakeTiny.acpi -O $(DEST_DIR)\SsdtLakeTiny.sec -S EFI_SECTION_RAW + +# +# Build FFS file +# +$(TARGET_FFS_FILE) : $(SECTIONS) $(DEST_DIR)\SsdtCpu0Cst.sec $(DEST_DIR)\SsdtCpu0Ist.sec $(DEST_DIR)\SsdtCpu0Tst.sec $(DEST_DIR)\SsdtApCst.sec $(DEST_DIR)\SsdtApIst.sec $(DEST_DIR)\SsdtApTst.sec $(DEST_DIR)\SsdtCpuPm.sec $(DEST_DIR)\SsdtCtdp.sec $(DEST_DIR)\SsdtLakeTiny.sec + $(GENFFSFILE) -B $(DEST_DIR) -P1 $(DEST_DIR)\$(BASE_NAME).pkg -V + +all : $(TARGET_FFS_FILE) + +[=============================================================================] +[Package.ACPITABLE.Default] +PACKAGE.INF +\[.] +BASE_NAME = $(BASE_NAME) +FFS_FILEGUID = $(FILE_GUID) +FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM +FFS_ATTRIB_CHECKSUM = TRUE + +IMAGE_SCRIPT = +{ + Compress (Dummy) { + $(DEST_DIR)\SsdtCpu0Cst.sec + $(DEST_DIR)\SsdtCpu0Ist.sec + $(DEST_DIR)\SsdtCpu0Tst.sec + $(DEST_DIR)\SsdtApCst.sec + $(DEST_DIR)\SsdtApIst.sec + $(DEST_DIR)\SsdtApTst.sec + $(DEST_DIR)\SsdtCpuPm.sec + $(DEST_DIR)\SsdtCtdp.sec + $(DEST_DIR)\SsdtLakeTiny.sec + } +} diff --git a/ReferenceCode/Haswell/Include/CpuRcInclude.cif b/ReferenceCode/Haswell/Include/CpuRcInclude.cif new file mode 100644 index 0000000..88aff67 --- /dev/null +++ b/ReferenceCode/Haswell/Include/CpuRcInclude.cif @@ -0,0 +1,27 @@ +<component> + name = "CpuRcInclude" + category = ModulePart + LocalRoot = "ReferenceCode\Haswell\Include\" + RefName = "CpuRcInclude" +[files] +"CommonIncludes.h" +"CpuAccess.h" +"CpuBaseLib.h" +"CpuDataStruct.h" +"CpuPowerMgmt.dsc" +"CpuRegs.h" +"IntelCpuDxe.dsc" +"IntelCpuDxeLib.dsc" +"IntelCpuPei.dsc" +"IntelCpuPeiLib.dsc" +"PfatDefinitions.h" +"PowerMgmtDefinitions.h" +"ThunkLib.h" +"TisPc.h" +"Txt.h" +"Txt.inc" +"Library\CpuPlatformLib.h" +"Library\BootGuardLibrary.h" +"Library\TxtLibrary.h" + +<endComponent> diff --git a/ReferenceCode/Haswell/Include/CpuRegs.h b/ReferenceCode/Haswell/Include/CpuRegs.h new file mode 100644 index 0000000..ed92b70 --- /dev/null +++ b/ReferenceCode/Haswell/Include/CpuRegs.h @@ -0,0 +1,582 @@ +/** @file + Conventions: + - Prefixes: + Definitions beginning with "MSR_" are MSRs + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + +@copyright + Copyright (c) 2004 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _CPU_REGS_H_ +#define _CPU_REGS_H_ + +#include "CommonIncludes.h" + +// +// Local APIC defines +// +#define APIC_REGISTER_LOCAL_ID_OFFSET 0x00000020 +#define APIC_REGISTER_APIC_VERSION_OFFSET 0x00000030 +#define APIC_REGISTER_SPURIOUS_VECTOR_OFFSET 0x000000F0 +#define APIC_REGISTER_ICR_LOW_OFFSET 0x00000300 +#define APIC_REGISTER_ICR_HIGH_OFFSET 0x00000310 +#define APIC_REGISTER_LINT0_VECTOR_OFFSET 0x00000350 +#define APIC_REGISTER_LINT1_VECTOR_OFFSET 0x00000360 + +#define BROADCAST_MODE_SPECIFY_CPU 0x00 +#define BROADCAST_MODE_ALL_INCLUDING_SELF 0x01 +#define BROADCAST_MODE_ALL_EXCLUDING_SELF 0x02 + +#ifndef DELIVERY_MODE_REMOTE_READ + +#define DELIVERY_MODE_FIXED 0x00 +#define DELIVERY_MODE_LOWEST_PRIORITY 0x01 +#define DELIVERY_MODE_SMI 0x02 +#define DELIVERY_MODE_REMOTE_READ 0x03 +#define DELIVERY_MODE_NMI 0x04 +#define DELIVERY_MODE_INIT 0x05 +#define DELIVERY_MODE_SIPI 0x06 +#define DELIVERY_MODE_MAX 0x07 + +#define TRIGGER_MODE_EDGE 0x00 +#define TRIGGER_MODE_LEVEL 0x01 + +#endif + +#define CACHE_UNCACHEABLE 0 +#define CACHE_WRITECOMBINING 1 +#define CACHE_WRITETHROUGH 4 +#define CACHE_WRITEPROTECTED 5 +#define CACHE_WRITEBACK 6 + +#define CPUID_SIGNATURE 0x0 +#define CPUID_VERSION_INFO 0x1 +#define CPUID_FUNCTION_4 0x4 +#define CPU_CACHE_TYPE_MASK 0x1F +#define CPU_CACHE_LEVEL_MASK 0x07 +#define CPU_CACHE_ASSOCIATIVITY_MASK 0x03FF +#define CPU_CACHE_PARTITION_MASK 0x03FF +#define CPU_CACHE_LINE_SIZE_MASK 0x0FFF +#define B_CPUID_VERSION_INFO_ECX_MWAIT BIT3 +#define B_CPUID_VERSION_INFO_ECX_VME BIT5 +#define B_CPUID_VERSION_INFO_ECX_SME BIT6 +#define B_CPUID_VERSION_INFO_ECX_EIST BIT7 +#define B_CPUID_VERSION_INFO_ECX_TM2 BIT8 +#define B_CPUID_VERSION_INFO_ECX_DCA BIT18 +#define B_CPUID_VERSION_INFO_ECX_AES BIT25 +#define B_CPUID_VERSION_INFO_ECX_XAPIC BIT21 +#define B_CPUID_VERSION_INFO_EDX_XD BIT20 +#define B_CPUID_VERSION_INFO_EDX_HT BIT28 +#define B_CPUID_VERSION_INFO_EDX_TM1 BIT29 + +#define CPUID_CACHE_INFO 0x2 +#define CPUID_SERIAL_NUMBER 0x3 +#define CPUID_CACHE_PARAMS 0x4 + +// +// CPU ID Instruction defines +// +#define V_CPUID_CACHE_TYPE_MASK 0x1F +#define B_CPUID_CACHE_TYPE_DATA 0x1 +#define B_CPUID_CACHE_TYPE_INSTRUCTION 0x2 +#define B_CPUID_CACHE_TYPE_UNIFIED 0x3 +#define V_CPUID_CACHE_LEVEL_MASK 0xE0 +#define B_CPUID_CACHE_LEVEL_SHIFT 5 +#define B_CPUID_CACHE_PARAMS_WAYS_SHIFT 22 +#define B_CPUID_CACHE_PARAMS_PARTITIONS_SHIFT 12 +#define CPUID_MONITOR_MWAIT_PARAMS 0x5 +#define B_CPUID_MONITOR_MWAIT_ECX_EXTENSIONS BIT0 +#define B_CPUID_MONITOR_MWAIT_EDX_CSTATE BIT0 +#define V_CPUID_MONITOR_MWAIT_EDX_ENHANCED_CSTATE 0x2 +#define CPUID_POWER_MANAGEMENT_PARAMS 0x6 +#define B_CPUID_POWER_MANAGEMENT_EAX_TURBO BIT1 +#define B_CPUID_POWER_MANAGEMENT_EAX_FINE_GRAINED_CLOCK_MODULATION BIT5 +#define B_CPUID_POWER_MANAGEMENT_ECX_ENERGY_EFFICIENT_POLICY_SUPPORT BIT3 +#define CPUID_REV7 0x7 +#define CPUID_REV8 0x8 +#define CPUID_DCA_PARAMS 0x9 +#define CPUID_REVA 0xA +#define CPUID_CORE_TOPOLOGY 0xB +#define CPUID_EXTENDED_FUNCTION 0x80000000 +#define CPUID_EXTENDED_CPU_SIG 0x80000001 +#define CPUID_BRAND_STRING1 0x80000002 +#define CPUID_BRAND_STRING2 0x80000003 +#define CPUID_BRAND_STRING3 0x80000004 +#define CPUID_L2_CACHE_FEATURE 0x80000006 +#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008 + +// +// MSR defines +// +#define MSR_IA32_PLATFORM_ID 0x00000017 +#define MSR_IA32_APIC_BASE 0x0000001B +#define B_MSR_IA32_APIC_BASE_G_XAPIC BIT11 +#define B_MSR_IA32_APIC_BASE_M_XAPIC BIT10 +#define B_MSR_IA32_APIC_BASE_BSP BIT8 +#define PIC_THREAD_CONTROL 0x0000002E +#define B_PIC_THREAD_CONTROL_TPR_DIS BIT10 +#define MSR_CORE_THREAD_COUNT 0x00000035 +#define N_CORE_COUNT_OFFSET 16 +#define B_THREAD_COUNT_MASK 0xFFFF +#define MSR_SOCKET_ID_MSR 0x00000039 +#define MSR_IA32_FEATURE_CONTROL 0x0000003A +#define B_MSR_IA32_FEATURE_CONTROL_LOCK BIT0 +#define B_MSR_IA32_FEATURE_CONTROL_ELT BIT1 +#define B_MSR_IA32_FEATURE_CONTROL_EVT BIT2 +#define B_MSR_IA32_FEATURE_CONTROL_SLFE (BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT14) +#define B_MSR_IA32_FEATURE_CONTROL_SGE BIT15 +#define MSR_IA32_SMM_SAVE_CONTROL 0x0000003E +#define B_MSR_IA32_SMM_SAVE_CONTROL_SFPPE BIT0 +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 +#define MSR_IA32_BIOS_SIGN_ID 0x0000008B +#define MSR_IA32_SMM_MONITOR_CONTROL 0x0000009B +#define MSR_IA32_PMC0_MSR 0x000000C1 +#define MSR_IA32_PMC1_MSR 0x000000C2 +#define MSR_IA32_PMC2_MSR 0x000000C3 +#define MSR_IA32_PMC3_MSR 0x000000C4 +#define MSR_IA32_PMC4_MSR 0x000000C5 +#define MSR_IA32_PMC5_MSR 0x000000C6 +#define MSR_IA32_PMC6_MSR 0x000000C7 +#define MSR_IA32_PMC7_MSR 0x000000C8 +#define MSR_PLATFORM_INFO 0x000000CE +#define N_PLATFORM_INFO_MIN_RATIO 40 +#define B_PLATFORM_INFO_RATIO_MASK 0xFF +#define N_PLATFORM_INFO_MAX_RATIO 8 +#define B_MSR_PLATFORM_INFO_PFAT_AVAIL BIT35 +#define N_MSR_PLATFORM_INFO_CONFIG_TDP_NUM_LEVELS_OFFSET 33 +#define V_CONFIG_TDP_NUM_LEVELS_MASK (BIT34 | BIT33) +#define B_PLATFORM_INFO_TDC_TDP_LIMIT BIT29 +#define N_PLATFORM_INFO_RATIO_LIMIT 28 +#define B_PLATFORM_INFO_RATIO_LIMIT BIT28 +#define B_FIVR_RFI_TUNING_AVAIL BIT25 +#define B_PLATFORM_INFO_SMM_SAVE_CONTROL BIT16 +#define N_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET 30 +#define B_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET BIT30 +#define B_PLATFORM_INFO_TIMED_MWAIT_SUPPORTED BIT37 +#define MSR_PMG_CST_CONFIG 0x000000E2 +#define B_CST_CONTROL_LOCK BIT15 +#define B_IO_MWAIT_REDIRECTION_ENABLE BIT10 +#define B_TIMED_MWAIT_ENABLE BIT31 +#define B_PACKAGE_C_STATE_LIMIT (BIT3 | BIT2 | BIT1 | BIT0) +#define V_CSTATE_LIMIT_C1 0x01 +#define V_CSTATE_LIMIT_C3 0x02 +#define V_CSTATE_LIMIT_C6 0x03 +#define V_CSTATE_LIMIT_C7 0x04 +#define V_CSTATE_LIMIT_C7S 0x05 +#define V_CSTATE_LIMIT_C8 0x06 +#define V_CSTATE_LIMIT_C9 0x07 +#define V_CSTATE_LIMIT_C10 0x08 +#define B_C3_AUTO_DEMOTION_ENABLE BIT25 +#define B_C1_AUTO_DEMOTION_ENABLE BIT26 +#define B_C3_AUTO_UNDEMOTION_ENABLE BIT27 +#define B_C1_AUTO_UNDEMOTION_ENABLE BIT28 +#define B_PKG_CSTATE_DEMOTION_ENABLE BIT29 +#define B_PKG_CSTATE_UNDEMOTION_ENABLE BIT30 +#define MSR_RFI_TUNNING 0x000000E3 +#define V_FREQ_TUNNING_MASK 0xFFFF +#define MSR_PMG_IO_CAPTURE_BASE 0x000000E4 +#define B_MSR_PMG_CST_RANGE (BIT18 | BIT17 | BIT16) +#define V_IO_CAPT_LVL2 (0x0 << 16) ///< C3 +#define V_IO_CAPT_LVL3 (0x1 << 16) ///< C6 +#define V_IO_CAPT_LVL4 (0x2 << 16) ///< C7 +#define V_IO_CAPT_LVL5 (0x3 << 16) ///< C8 +#define V_IO_CAPT_LVL6 (0x4 << 16) ///< C9 +#define V_IO_CAPT_LVL7 (0x5 << 16) ///< C10 +#define V_IO_CAPT_LVL2_BASE_ADDR_MASK 0xFFFF +#define IA32_MTRR_CAP 0x000000FE +#define B_IA32_MTRR_VARIABLE_SUPPORT 0xFF +#define B_IA32_MTRR_CAP_FIXED_SUPPORT BIT8 +#define B_IA32_MTRR_CAP_SMRR_SUPPORT BIT11 +#define B_IA32_MTRR_CAP_EMRR_SUPPORT BIT12 +#define MSR_PLAT_FRMW_PROT_CTRL 0x00000110 +#define B_MSR_PLAT_FRMW_PROT_CTRL_LK BIT0 +#define B_MSR_PLAT_FRMW_PROT_CTRL_EN BIT1 +#define B_MSR_PLAT_FRMW_PROT_CTRL_S1 BIT2 +#define MSR_PLAT_FRMW_PROT_HASH_0 0x00000111 +#define MSR_PLAT_FRMW_PROT_HASH_1 0x00000112 +#define MSR_PLAT_FRMW_PROT_HASH_2 0x00000113 +#define MSR_PLAT_FRMW_PROT_HASH_3 0x00000114 +#define MSR_PLAT_FRMW_PROT_TRIG_PARAM 0x00000115 +#define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_STATUS_OFFSET 0 +#define V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_STATUS_MASK 0x000000000000FFFF +#define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_DATA_OFFSET 16 +#define V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_DATA_MASK 0x000000000000FFFF +#define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_TERMINAL_OFFSET 32 +#define V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_TERMINAL_MASK 0x000000000000FFFF +#define B_MSR_PLAT_FRMW_PROT_TRIG_PARAM_SE BIT62 +#define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_SE_OFFSET 62 +#define MSR_PLAT_FRMW_PROT_TRIGGER 0x00000116 +#define MSR_PLAT_FRMW_PROT_PASSWD 0x00000117 +#define MSR_SPCL_CHIPSET_USAGE_ADDR 0x000001FE +#define MSR_IA32_FEATURE_CONFIG 0x0000013C +#define B_IA32_FEATURE_CONFIG_AES_DIS BIT1 +#define B_IA32_FEATURE_CONFIG_LOCK BIT0 +#define IA32_MCG_CAP 0x00000179 +#define IA32_MCG_STATUS 0x0000017A +#define MSR_FLEX_RATIO 0x00000194 +#define N_FLEX_RATIO 8 +#define B_FLEX_RATIO (0xFF << 8) +#define B_FLEX_EN BIT16 +#define B_MAX_EXTRA_VOLTAGE 0xFF +#define N_OVERCLOCKING_BINS 17 +#define B_OVERCLOCKING_BINS (0x7 << 17) +#define B_OVERCLOCKING_LOCK BIT20 +#define RATIO_FLEX_CLEAR_MASK 0xFFFFFFFFFFFF00FFULL +#define MSR_IA32_PERF_STS 0x00000198 +#define N_IA32_PERF_STSP_STATE_TARGET 8 +#define B_IA32_PERF_STSP_STATE_MASK 0xFF +#define MSR_IA32_PERF_CTRL 0x00000199 +#define N_IA32_PERF_CTRLP_STATE_TARGET 8 +#define B_IA32_PERF_CTRLP_STATE_TARGET (0x7F << 8) +#define B_IA32_PERF_CTRL_TURBO_DIS BIT32 +#define MSR_IA32_CLOCK_MODULATION 0x0000019A +#define IA32_THERM_INTERRUPT 0x0000019B +#define B_IA32_THERM_INTERRUPT_VIE BIT4 +#define MSR_IA32_THERM_STATUS 0x0000019C +#define MSR_IA32_MISC_ENABLE 0x000001A0 +#define B_MSR_IA32_MISC_ENABLE_FSE BIT0 +#define B_MSR_IA32_MISC_ENABLE_TME BIT3 +#define N_MSR_IA32_MISC_ENABLE_EIST_OFFSET 16 +#define B_MSR_IA32_MISC_ENABLE_EIST BIT16 +#define B_MSR_IA32_MISC_ENABLE_MONITOR BIT18 +#define B_MSR_IA32_MISC_ENABLE_CPUID_MAX BIT22 +#define B_MSR_IA32_MISC_ENABLE_TPR_DIS BIT23 +#define B_MSR_IA32_MISC_ENABLE_XD BIT34 +#define B_MSR_IA32_MISC_DISABLE_TURBO BIT38 +#define MSR_TEMPERATURE_TARGET 0x000001A2 +#define N_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LIMIT 24 +#define N_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_OFFSET (16) +#define B_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_MASK (0xFF << 16) +#define N_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET 8 +#define B_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET (0xFF << 8) +#define MISC_FEATURE_CONTROL 0x000001A4 +#define B_MISC_FEATURE_CONTROL_MLC_STRP BIT0 +#define B_MISC_FEATURE_CONTROL_MLC_SPAP BIT1 +#define B_MISC_FEATURE_CONTROL_DCU_STRP BIT2 +#define B_MISC_FEATURE_CONTROL_DCU_IPP BIT3 +#define MSR_MISC_PWR_MGMT 0x000001AA +#define B_MSR_MISC_PWR_MGMT_EIST_HW BIT0 +#define B_MSR_MISC_PWR_MGMT_LTMI BIT22 +#define MSR_TURBO_POWER_CURRENT_LIMIT 0x000001AC +#define B_MSR_TURBO_POWER_CURRENT_LIMIT_TDC_EN BIT31 +#define N_MSR_TURBO_POWER_CURRENT_LIMIT_TDC_LIMIT 16 +#define B_MSR_TURBO_POWER_CURRENT_LIMIT_TDC_LIMIT (0x7F << 16) +#define B_MSR_TURBO_POWER_CURRENT_LIMIT_TDP_EN BIT15 +#define N_MSR_TURBO_POWER_CURRENT_LIMIT_TDP_LIMIT 0 +#define B_MSR_TURBO_POWER_CURRENT_LIMIT_TDP_LIMIT (0x7F << 0) +#define MSR_TURBO_RATIO_LIMIT 0x000001AD +#define N_MSR_TURBO_RATIO_LIMIT_1C 0 +#define B_MSR_TURBO_RATIO_LIMIT_1C (0xFF << 0) +#define N_MSR_TURBO_RATIO_LIMIT_2C 8 +#define B_MSR_TURBO_RATIO_LIMIT_2C (0xFF << 8) +#define N_MSR_TURBO_RATIO_LIMIT_3C 16 +#define B_MSR_TURBO_RATIO_LIMIT_3C (0xFF << 16) +#define N_MSR_TURBO_RATIO_LIMIT_4C 24 +#define B_MSR_TURBO_RATIO_LIMIT_4C (0xFF << 24) +#define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1B0 +#define B_ENERGY_POLICY_MASK 0xF +#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8 +#define B_MSR_IA32_PLATFORM_DCA_CAP_TYPE0_EN BIT0 +#define MSR_IA32_CPU_DCA_CAP 0x000001F9 +#define B_MSR_IA32_CPU_DCA_CAP_TYPE0_SUP BIT0 +#define MSR_IA32_DCA_0_CAP 0x000001FA +#define B_MSR_IA32_CPU_DCA_CAP_ENDID BIT11 +#define N_MSR_IA32_CPU_DCA_CAP_DELAY 13 +#define B_MSR_IA32_CPU_DCA_CAP_DELAY (BIT13 | BIT14 | BIT15 | BIT16) +#define B_MSR_IA32_CPU_DCA_CAP_SW_LOCK BIT24 +#define B_MSR_IA32_CPU_DCA_CAP_SW_FLUSH BIT25 +#define B_MSR_IA32_CPU_DCA_CAP_HW_LOCK BIT26 +#define MSR_POWER_CTL 0x000001FC +#define B_MSR_POWER_CTL_BROCHOT BIT0 +#define B_MSR_POWER_CTL_C1E BIT1 +#define B_ENERGY_EFFICIENT_P_STATE_FEATURE_ENABLE BIT18 +#define B_MSR_POWER_CTL_DISABLE_PHOT_OUT BIT21 +#define B_MSR_POWER_CTL_PROC_HOT_RESPONSE BIT22 +#define B_MSR_POWER_CTL_PROC_HOT_LOCK BIT23 +#define B_MSR_POWER_CTL_DISABLE_VR_THERMAL_ALERT BIT24 +#define B_MSR_POWER_CTL_CSTATE_PRE_WAKE_DISABLE BIT30 +#define MSR_FERR_CAPABILITIES 0x000001F1 +#define B_MSR_FERR_ENABLE BIT0 +#define MSR_VR_CURRENT_CONFIG 0x00000601 +#define B_CURRENT_LIMIT_LOCK BIT31 +#define B_CURRENT_LIMIT_MASK 0x1FFF +#define MSR_VR_MISC_CONFIG 0x603 +#define N_MSR_VR_MISC_CONFIG_MIN_VID_OFFSET 24 +#define B_MSR_VR_MISC_CONFIG_MIN_VID_MASK 0xFF +#define V_MSR_VR_MISC_CONFIG_MIN_VID_DEFAULT 0 +#define N_MSR_VR_MISC_CONFIG_IDLE_EXIT_RAMP_RATE_OFFSET 50 +#define B_MSR_VR_MISC_CONFIG_IDLE_EXIT_RAMP_RATE BIT50 +#define N_MSR_VR_MISC_CONFIG_IDLE_ENTRY_RAMP_RATE_OFFSET 51 +#define B_MSR_VR_MISC_CONFIG_IDLE_ENTRY_RAMP_RATE BIT51 +#define N_MSR_VR_MISC_CONFIG_IDLE_ENTRY_DECAY_ENABLE_OFFSET 52 +#define B_MSR_VR_MISC_CONFIG_IDLE_ENTRY_DECAY_ENABLE BIT52 +#define N_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_OFFSET 53 +#define B_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_MASK (BIT54 | BIT53) +#define V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_DEFAULT 1 +#define V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_2 0 +#define V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_4 BIT53 +#define V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_8 BIT54 +#define V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_16 (BIT54 | BIT53) +#define MSR_VR_MISC_CONFIG2 0x636 +#define N_MSR_VR_MISC_CONFIG2_FAST_RAMP_VOLTAGE_OFFSET 0 +#define B_MSR_VR_MISC_CONFIG2_FAST_RAMP_VOLTAGE_MASK 0xFF +#define V_MSR_VR_MISC_CONFIG2_FAST_RAMP_VOLTAGE_DEFAULT 0x6F +#define N_MSR_VR_MISC_CONFIG2_MIN_C8_VOLTAGE_OFFSET 8 +#define B_MSR_VR_MISC_CONFIG2_MIN_C8_VOLTAGE_MASK 0xFF +#define V_MSR_VR_MISC_CONFIG2_MIN_C8_VOLTAGE_DEFAULT 0 +#define MSR_PACKAGE_POWER_SKU_UNIT 0x606 +#define PACKAGE_POWER_UNIT_MASK 0xF +#define PACKAGE_TIME_UNIT_MASK 0xF0000 +#define MSR_C_STATE_LATENCY_CONTROL_0 0x60A +#define MSR_C_STATE_LATENCY_CONTROL_1 0x60B +#define MSR_C_STATE_LATENCY_CONTROL_2 0x60C +#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 +#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 +#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 +#define B_PKG_IRTL_VALID BIT15 +#define B_INTERRUPT_RESPONSE_TIME_LIMIT_MASK 0x3FF +#define B_TIME_UNIT_MASK (0x7 << 10) +#define N_TIME_UNIT_OFFSET 10 +#define MSR_PACKAGE_POWER_LIMIT 0x610 +#define MSR_PACKAGE_POWER_SKU 0x614 +#define B_POWER_LIMIT_ENABLE BIT15 +#define B_CRITICAL_POWER_CLAMP_ENABLE BIT16 +#define B_POWER_LIMIT_LOCK BIT31 +#define POWER_LIMIT_MASK (0x7FFF) +#define POWER_LIMIT_1_TIME_MASK (0xFE0000) +#define PACKAGE_TDP_POWER_MASK (0x7FFF) +#define PACKAGE_MIN_POWER_MASK (0x7FFF0000) +#define PACKAGE_MAX_POWER_MASK (0x7FFF) +#define MSR_PLATFORM_POWER_LIMIT 0x615 +#define POWER_LIMIT_3_TIME_MASK (0xFE0000) +#define POWER_LIMIT_3_DUTY_CYCLE_MASK (0x7F000000) +#define MSR_DDR_RAPL_LIMIT 0x618 +#define MSR_RING_RATIO_LIMIT 0x620 +#define MSR_MAX_RING_RATIO_LIMIT_MASK 0x7F +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define CONFIG_TDP_NOMINAL_RATIO_MASK 0xFF +#define MSR_CONFIG_TDP_LVL1 0x649 +#define CONFIG_TDP_LVL1_RATIO_OFFSET 16 +#define CONFIG_TDP_LVL1_RATIO_MASK (0xFF << 16) +#define CONFIG_TDP_LVL1_PKG_TDP_MASK (0x7FFF) +#define MSR_CONFIG_TDP_LVL2 0x64A +#define CONFIG_TDP_LVL2_RATIO_OFFSET 16 +#define CONFIG_TDP_LVL2_RATIO_MASK (0xFF << 16) +#define CONFIG_TDP_LVL2_PKG_TDP_MASK (0x7FFF) +#define MSR_CONFIG_TDP_CONTROL 0x64B +#define CONFIG_TDP_CONTROL_LOCK (1 << 31) +#define CONFIG_TDP_CONTROL_LVL_MASK 0x3 +#define CONFIG_TDP_NOMINAL 0 +#define CONFIG_TDP_LEVEL1 1 +#define CONFIG_TDP_LEVEL2 2 +#define MSR_TURBO_ACTIVATION_RATIO 0x64C +#define MSR_TURBO_ACTIVATION_RATIO_LOCK (1 << 31) +#define MSR_TURBO_ACTIVATION_RATIO_MASK 0xFF +#define SMRR_PHYS_BASE 0x000001F2 +#define SMRR_PHYS_MASK 0x000001F3 +#define EMRR_PHYS_BASE 0x000001F4 +#define EMRR_PHYS_MASK 0x000001F5 +#define B_MSR_EMRR_PHYS_MASK_EN BIT11 +#define B_MSR_EMRR_PHYS_MASK_LOCK BIT10 +#define V_MAXIMUM_VARIABLE_MTRR_NUMBER 10 +#define CACHE_VARIABLE_MTRR_BASE 0x00000200 +#define V_FIXED_MTRR_NUMBER 11 +#define IA32_MTRR_FIX64K_00000 0x00000250 +#define IA32_MTRR_FIX16K_80000 0x00000258 +#define IA32_MTRR_FIX16K_A0000 0x00000259 +#define IA32_MTRR_FIX4K_C0000 0x00000268 +#define IA32_MTRR_FIX4K_C8000 0x00000269 +#define IA32_MTRR_FIX4K_D0000 0x0000026A +#define IA32_MTRR_FIX4K_D8000 0x0000026B +#define IA32_MTRR_FIX4K_E0000 0x0000026C +#define IA32_MTRR_FIX4K_E8000 0x0000026D +#define IA32_MTRR_FIX4K_F0000 0x0000026E +#define IA32_MTRR_FIX4K_F8000 0x0000026F +#define MSR_IA32_CR_PAT 0x00000277 +#define CACHE_IA32_MTRR_DEF_TYPE 0x000002FF +#define B_CACHE_MTRR_VALID BIT11 +#define B_CACHE_FIXED_MTRR_VALID BIT10 +#define NO_EVICT_MODE 0x000002E0 +#define B_NO_EVICT_MODE_SETUP BIT0 +#define B_NO_EVICT_MODE_RUN BIT1 +#define UNCORE_CR_MEMLOCK_COMMANDS 0x000002E2 +#define B_LOCK_MEM_CFG BIT1 +#define EFI_PCIEXBAR 0x00000300 +#define B_PCIEXBAR_EN BIT0 +#define B_PCIEXBAR_SIZE (BIT1 | BIT2 | BIT3) +#define N_PCIEXBAR_SIZE 1 +#define IA32_MC0_CTL 0x00000400 +#define IA32_MC0_STATUS 0x00000401 +#define IA32_MC0_ADDR 0x00000402 +#define IA32_MC0_MISC 0x00000403 +#define IA32_MC8_CTL (IA32_MC0_CTL + (8 * 4)) +#define IA32_MC5_STATUS (IA32_MC0_STATUS + (5 * 4)) +#define IA32_MC6_STATUS (IA32_MC0_STATUS + (6 * 4)) +#define IA32_MC7_STATUS (IA32_MC0_STATUS + (7 * 4)) +#define IA32_MC8_STATUS (IA32_MC0_STATUS + (8 * 4)) +#define MSR_IA32_VMX_BASIC 0x00000480 +#define MSR_IA32_VMX_MISC 0x00000485 +#define APIC_GLOBAL_ENABLE 0x00000800 +#define EXT_XAPIC_LOGICAL_APIC_ID 0x00000802 +#define EXT_XAPIC_VERSION 0x00000803 +#define EXT_XAPIC_SVR 0x0000080F +#define EXT_XAPIC_ICR 0x00000830 +#define MSR_EXT_XAPIC_LVT_THERM 0x00000833 +#define EXT_XAPIC_LVT_LINT0 0x00000835 +#define EXT_XAPIC_LVT_LINT1 0x00000836 +#define MSR_IA32_DEBUG_INTERFACE 0x00000C80 +#define B_DEBUG_INTERFACE_ENABLE BIT0 +#define B_DEBUG_INTERFACE_LOCK BIT30 +#define B_DEBUG_INTERFACE_DEBUG_STATUS BIT31 +#define NUM_TENTHS_TO_PERCENTAGE 1000 +#define FIVR_SSC_LOCK_BIT BIT31 +#define MAX_FIVR_SSC_PERCENT 70 +// +// MSRs for SMM State Save Register +// +#define MSR_SMM_MCA_CAP 0x17D +#define B_TARGETED_SMI BIT56 +#define N_TARGETED_SMI 56 +#define B_SMM_CPU_SVRSTR BIT57 +#define N_SMM_CPU_SVRSTR 57 +#define B_SMM_CODE_ACCESS_CHK BIT58 +#define N_SMM_CODE_ACCESS_CHK 58 +#define B_LONG_FLOW_INDICATION BIT59 +#define N_LONG_FLOW_INDICATION 59 +#define MSR_SMM_FEATURE_CONTROL 0x4E0 +#define B_SMM_FEATURE_CONTROL_LOCK BIT0 +#define B_SMM_CPU_SAVE_EN BIT1 +#define B_SMM_CODE_CHK_EN BIT2 +#define MSR_SMM_ENABLE 0x4E1 +#define MSR_SMM_DELAYED 0x4E2 +#define MSR_SMM_BLOCKED 0x4E3 +#define MSR_CR0 0xC00 +#define MSR_CR3 0xC01 +#define MSR_EFLAGS 0xC02 +#define MSR_RIP 0xC04 +#define MSR_DR6 0xC05 +#define MSR_DR7 0xC06 +#define MSR_TR_LDTR 0xC07 +#define MSR_GS_FS 0xC08 +#define MSR_DS_SS 0xC09 +#define MSR_CS_ES 0xC0A +#define MSR_IO_MISC_INFO 0xC0B +#define MSR_IO_MEM_ADDR 0xC0C +#define MSR_RDI 0xC0D +#define MSR_RSI 0xC0E +#define MSR_RBP 0xC0F +#define MSR_RSP 0xC10 +#define MSR_RBX 0xC11 +#define MSR_RDX 0xC12 +#define MSR_RCX 0xC13 +#define MSR_RAX 0xC14 +#define MSR_R8 0xC15 +#define MSR_R9 0xC16 +#define MSR_R10 0xC17 +#define MSR_R11 0xC18 +#define MSR_R12 0xC19 +#define MSR_R13 0xC1A +#define MSR_R14 0xC1B +#define MSR_R15 0xC1C +#define MSR_EVENT_CTL_HLT_IO 0xC1F +#define MSR_SMBASE 0xC20 +#define MSR_SMM_REVID 0xC21 +#define MSR_IEDBASE 0xC22 +#define MSR_EPTP_ENABLE 0xC23 +#define MSR_EPTP 0xC24 +#define MSR_LDTR_BASE 0xC2C +#define MSR_IDTR_BASE 0xC2D +#define MSR_GDTR_BASE 0xC2E +#define MSR_CR4 0xC37 +#define MSR_IO_RSI 0xC40 +#define MSR_IO_RCX 0xC41 +#define MSR_IO_RIP 0xC42 +#define MSR_IO_RDI 0xC43 +#define MSR_BC_PBEC 0x139 +#define B_STOP_PBET BIT0 + +#define MSR_BOOT_GUARD_SACM_INFO 0x13A +#define B_NEM_INIT BIT0 +#define V_TPM_PRESENT_MASK 0x06 +#define V_TPM_PRESENT_NO_TPM 0 +#define V_TPM_PRESENT_DTPM_12 1 +#define V_TPM_PRESENT_DTPM_20 2 +#define V_TPM_PRESENT_PTT 3 +#define B_TPM_SUCCESS BIT3 +#define B_MEASURED BIT5 +#define B_VERIFIED BIT6 +#define TXT_PUBLIC_BASE 0xFED30000 +#define R_CPU_BOOT_GUARD_ERRORCODE 0x30 +#define R_CPU_BOOT_GUARD_BOOTSTATUS 0xA0 +#define R_CPU_BOOT_GUARD_ACM_STATUS 0x328 +#define V_CPU_BOOT_GUARD_LOAD_ACM_SUCCESS 0x8000000000000000 +#define B_BOOT_GUARD_ACM_ERRORCODE_MASK 0x00007FF0 + +// +// Processor Definitions +// +#define CPUID_FULL_STEPPING 0x0000000F +#define CPUID_FULL_FAMILY_MODEL 0x0FFF0FF0 +#define CPUID_FULL_FAMILY_MODEL_STEPPING 0x0FFF0FFF +#define CPUID_FULL_FAMILY_MODEL_HASWELL 0x000306C0 +#define CPUID_FULL_FAMILY_MODEL_HASWELL_ULT 0x00040650 +#define CPUID_FULL_FAMILY_MODEL_CRYSTALWELL 0x00040660 + +#define CPUID_PROCESSOR_TOPOLOGY 0xB + +typedef enum { + EnumCpuHsw = CPUID_FULL_FAMILY_MODEL_HASWELL, + EnumCpuHswUlt = CPUID_FULL_FAMILY_MODEL_HASWELL_ULT, + EnumCpuCrw = CPUID_FULL_FAMILY_MODEL_CRYSTALWELL, + EnumCpuMax = CPUID_FULL_FAMILY_MODEL +} CPU_FAMILY; + +typedef enum { + /// + /// Haswell Family Stepping + /// + EnumHswA0 = 1, + EnumHswB0, + EnumHswC0, + EnumHswD0, + /// + /// Haswell ULT Family Stepping + /// + EnumHswUltB0 = 0, + EnumHswUltC0, + /// + /// Crystalwell Family Stepping + /// + EnumCrwB0 = 0, + EnumCrwC0, + EnumCrwD0, + /// + /// Max Stepping + /// + EnumCpuSteppingMax = CPUID_FULL_STEPPING +} CPU_STEPPING; + +typedef enum { + EnumCpuUlt = 0, + EnumCpuTrad, + EnumCpuUnknown +} CPU_SKU; + +#endif diff --git a/ReferenceCode/Haswell/Include/IntelCpuDxe.dsc b/ReferenceCode/Haswell/Include/IntelCpuDxe.dsc new file mode 100644 index 0000000..29cd9a0 --- /dev/null +++ b/ReferenceCode/Haswell/Include/IntelCpuDxe.dsc @@ -0,0 +1,53 @@ +## @file +# Build description file for building the Intel CPU DXE drivers +# +#@copyright +# Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +# +# CpuInit DXE drivers +# +$(PROJECT_CPU_ROOT)\CpuInit\Dxe\CpuInitDxe.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints + +# +# DTS SMM drivers +# +$(PROJECT_CPU_ROOT)\Dts\Smm\DigitalThermalSensorSmm.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints + +# +# PFAT SMM drivers +# +$(PROJECT_CPU_ROOT)\Pfat\Smm\PfatServices.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints + +# +# Power Management Drivers +# +$(PROJECT_CPU_ROOT)\PowerManagement\Dxe\PowerMgmtDxe.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints +$(PROJECT_CPU_ROOT)\PowerManagement\Smm\PowerMgmtS3.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints +$(PROJECT_CPU_ROOT)\PowerManagement\AcpiTables\PowerMgmtAcpiTables.inf + +# +# TxT drivers +# +$(PROJECT_CPU_ROOT)\Txt\TxtInit\Dxe\TxtDxe.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints + +# +# Sample drivers +# +$(PROJECT_CPU_ROOT)\SampleCode\SmramSaveInfoHandlerSmm\SmramSaveInfoHandlerSmm.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints +$(PROJECT_CPU_ROOT)\SampleCode\TxtOneTouch\Dxe\TxtOneTouchDxe.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints +$(PROJECT_CPU_ROOT)\SampleCode\SmmThunk\Smm\SmmThunk.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints + diff --git a/ReferenceCode/Haswell/Include/IntelCpuDxeLib.dsc b/ReferenceCode/Haswell/Include/IntelCpuDxeLib.dsc new file mode 100644 index 0000000..3f3faba --- /dev/null +++ b/ReferenceCode/Haswell/Include/IntelCpuDxeLib.dsc @@ -0,0 +1,41 @@ +## @file +# Build description file for building the CPU DXE libraries +# +#@copyright +# Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +# +# CPU DXE Libraries +# +$(PROJECT_CPU_ROOT)\Protocol\CpuProtocolLib.inf +$(PROJECT_CPU_ROOT)\Guid\CpuGuidLib.inf +$(PROJECT_CPU_ROOT)\Library\Thunklib\Thunklib.inf +$(PROJECT_CPU_ROOT)\Library\CpuPlatformLib\CpuPlatformLib.inf +$(PROJECT_CPU_ROOT)\Library\BootGuardLib\BootGuardLib.inf + +# +# DTS DXE Libraries +# +$(PROJECT_CPU_ROOT)\SampleCode\Library\SmmIo\SmmIoLib.inf +$(PROJECT_CPU_ROOT)\SampleCode\Library\AslUpdate\Dxe\DxeAslUpdateLib.inf +$(PROJECT_CPU_ROOT)\SampleCode\Library\DTSHookLib\Smm\DTSHookLib.inf +$(PROJECT_CPU_ROOT)\SampleCode\Library\Ksc\Smm\SmmKscLib.inf + +# +# Sample Code +# +$(PROJECT_CPU_ROOT)\SampleCode\Protocol\CpuSampleProtocolLib.inf +$(PROJECT_CPU_ROOT)\SampleCode\Library\BootGuardRevocationLib\Dxe\BootGuardRevocationLib.inf
\ No newline at end of file diff --git a/ReferenceCode/Haswell/Include/IntelCpuPei.dsc b/ReferenceCode/Haswell/Include/IntelCpuPei.dsc new file mode 100644 index 0000000..98e0c7e --- /dev/null +++ b/ReferenceCode/Haswell/Include/IntelCpuPei.dsc @@ -0,0 +1,35 @@ +## @file +# Build description file for building the CPU PEI modules +# +#@copyright +# Copyright (c) 2008 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +# +# PEI module produce CPU PPI +# +$(PROJECT_CPU_ROOT)\CpuInit\Pei\CpuInitPeim.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints +$(PROJECT_CPU_ROOT)\CpuS3\Pei\CpuS3Peim.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints + +# +# TxT Drivers +# +$(PROJECT_CPU_ROOT)\Txt\TxtInit\Pei\TxtPei.inf SOURCE_OVERRIDE_PATH = $(EDK_SOURCE)\Foundation\Library\EdkIIGlueLib\EntryPoints +$(PROJECT_CPU_ROOT)\Txt\TxtInit\Pei\Ia32\TxtPeiApV7.inf +# $(PROJECT_CPU_ROOT)\Txt\BiosAcm\TxtBiosAcm.inf + +# +# Sample drivers +# diff --git a/ReferenceCode/Haswell/Include/IntelCpuPeiLib.dsc b/ReferenceCode/Haswell/Include/IntelCpuPeiLib.dsc new file mode 100644 index 0000000..a5475e9 --- /dev/null +++ b/ReferenceCode/Haswell/Include/IntelCpuPeiLib.dsc @@ -0,0 +1,30 @@ +## @file +# Build description file for building the CPU PEI Libraries +# +#@copyright +# Copyright (c) 2011 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +# +# CPU PEI libraries +# +$(PROJECT_CPU_ROOT)\Ppi\CpuPpiLib.inf +$(PROJECT_CPU_ROOT)\Guid\CpuGuidLib.inf +$(PROJECT_CPU_ROOT)\Library\Thunklib\Thunklib.inf +$(PROJECT_CPU_ROOT)\Library\CpuPlatformLib\CpuPlatformLib.inf +$(PROJECT_CPU_ROOT)\Library\OverclockingLib\OverClockingLib.inf +$(PROJECT_CPU_ROOT)\Library\TxtLib\TxtLib.inf +$(PROJECT_CPU_ROOT)\SampleCode\Library\Ksc\Pei\PeiKscLib.inf +$(PROJECT_CPU_ROOT)\Library\BootGuardLib\BootGuardLib.inf
\ No newline at end of file diff --git a/ReferenceCode/Haswell/Include/Library/BootGuardLibrary.h b/ReferenceCode/Haswell/Include/Library/BootGuardLibrary.h new file mode 100644 index 0000000..e6bfbcc --- /dev/null +++ b/ReferenceCode/Haswell/Include/Library/BootGuardLibrary.h @@ -0,0 +1,46 @@ +/** @file + Header file for Boot Guard Lib implementation. + +@copyright + Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _BOOT_GUARD_LIBRARY_H_ +#define _BOOT_GUARD_LIBRARY_H_ + +/** + Determine if Boot Guard is supported + + @retval TRUE - Processor is Boot Guard capable. + @retval FALSE - Processor is not Boot Guard capable. + +**/ +BOOLEAN +IsBootGuardSupported ( + VOID + ); + +/** + Stop PBE timer if system is in Boot Guard boot + + @retval EFI_SUCCESS - Stop PBE timer + @retval EFI_UNSUPPORTED - Not in Boot GuardSupport mode. +**/ +EFI_STATUS +StopPbeTimer ( + VOID + ); +#endif diff --git a/ReferenceCode/Haswell/Include/Library/CpuPlatformLib.h b/ReferenceCode/Haswell/Include/Library/CpuPlatformLib.h new file mode 100644 index 0000000..99b349f --- /dev/null +++ b/ReferenceCode/Haswell/Include/Library/CpuPlatformLib.h @@ -0,0 +1,221 @@ +/** @file + Header file for CpuPlatform Lib. + +@copyright + Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _CPU_PLATFORM_LIB_H_ +#define _CPU_PLATFORM_LIB_H_ + +/** + Check CPU Type of the platform + + @retval CPU_FAMILY CPU type +**/ +CPU_FAMILY +EFIAPI +GetCpuFamily ( + VOID + ); + +/** + Return Cpu stepping type + + @retval CPU_STEPPING Cpu stepping type +**/ +CPU_STEPPING +EFIAPI +GetCpuStepping ( + VOID + ); + +/** + Determine if CPU is supported + + @retval TRUE CPU is supported + @retval FALSE CPU is not supported +**/ +BOOLEAN +IsCpuSupported ( + VOID + ); + +/** + Return CPU Sku + + @retval UINT8 CPU Sku +**/ +UINT8 +EFIAPI +GetCpuSku ( + VOID + ); + +// +// Mailbox Related Definitions +// +#define MAILBOX_TYPE_PCODE 0x00000001 +#define MAILBOX_TYPE_OC 0x00000002 +#define PCODE_MAILBOX_INTERFACE_OFFSET 0x5DA4 +#define PCODE_MAILBOX_DATA_OFFSET 0x5DA0 +#define OC_MAILBOX_MSR 0x00000150 +#define MCHBAR_OFFSET 0x48 + +// +// Mailbox commands +// +#define READ_ICC_MAX_CMD 0x80002A03 +#define SAMPLE_TSC_24AND100_CMD 0x80000009 +#define READ_TSC24_LOWER_CMD 0x80000109 +#define READ_TSC24_UPPER_CMD 0x80000209 +#define READ_TSC100_LOWER_CMD 0x80000309 +#define READ_TSC100_UPPER_CMD 0x80000409 +#define READ_PCODE_CALIBRATED_CMD 0x80000509 +#define WRITE_CONVERTION_RATIO_CMD 0x80000609 +#define WRITE_PREVENT_BCLKOFF_CMD 0x80000709 +#define WRITE_MEASURE_INTERVAL_CMD 0x80000809 +#define WRITE_FSM_MEASURE_INTVL_CMD 0x80000909 +#define START_CAL_VALUE 0x85000000 +#define READ_PL1_DUTY_CYCLE_CLAMP_ENABLE 0x00000015 +#define WRITE_PL1_DUTY_CYCLE_CLAMP_ENABLE 0x00000016 +#define READ_DDR_FORCE_2X_REFRESH 0x00000017 +#define WRITE_DDR_FORCE_2X_REFRESH 0x00000018 + +#ifndef MAILBOX_WAIT_TIMEOUT +#define MAILBOX_WAIT_TIMEOUT 1000 ///< 1 millisecond +#endif +#ifndef MAILBOX_WAIT_STALL +#define MAILBOX_WAIT_STALL 1 ///< 1 microsecond +#endif +#ifndef MAILBOX_READ_TIMEOUT +#define MAILBOX_READ_TIMEOUT 10 ///< 10 microseconds +#endif + +// +// OC Mailbox Structures +// +typedef union _OC_MAILBOX_INTERFACE { + UINT32 InterfaceData; + struct { + UINT8 CommandCompletion : 8; + UINT8 Param1 : 8; + UINT8 Param2 : 8; + UINT8 Reserved : 7; + UINT8 RunBusy : 1; + } Fields; +} OC_MAILBOX_INTERFACE; + +typedef struct _OC_MAILBOX_FULL { + UINT32 Data; + OC_MAILBOX_INTERFACE Interface; +} OC_MAILBOX_FULL; + +// +// OC Mailbox completion codes +// +#define OC_MAILBOX_CC_SUCCESS 0 +#define OC_MAILBOX_CC_OC_LOCKED 1 +#define OC_MAILBOX_CC_INVALID_DOMAIN 2 +#define OC_MAILBOX_CC_MAX_RATIO_EXCEEDED 3 +#define OC_MAILBOX_CC_MAX_VOLTAGE_EXCEEDED 4 +#define OC_MAILBOX_CC_OC_NOT_SUPPORTED 5 + +// +// PCODE Mailbox Structures +// +typedef union _PCODE_MAILBOX_INTERFACE { + UINT32 InterfaceData; + struct { + UINT32 Command : 8; + UINT32 Address : 21; + UINT32 Reserved : 2; + UINT32 RunBusy : 1; + } Fields; +} PCODE_MAILBOX_INTERFACE; + +typedef struct _PCODE_MAILBOX_FULL { + PCODE_MAILBOX_INTERFACE Interface; + UINT32 Data; +} PCODE_MAILBOX_FULL; + +// +// Pcode Mailbox completion codes +// +#define PCODE_MAILBOX_CC_SUCCESS 0 +#define PCODE_MAILBOX_CC_ILLEGAL_CMD 1 +#define PCODE_MAILBOX_CC_TIMEOUT 2 +#define PCODE_MAILBOX_CC_ILLEGAL_DATA 3 +#define PCODE_MAILBOX_CC_RESERVED 4 +#define PCODE_MAILBOX_CC_ILLEGAL_VR_ID 5 +#define PCODE_MAILBOX_CC_VR_INTERFACE_LOCKED 6 +#define PCODE_MAILBOX_CC_VR_ERROR 7 + +#define READ_PCH_POWER_LEVELS_CMD 0x8000000A +#define READ_EXT_PCH_POWER_LEVELS_CMD 0x8000000B + +EFI_STATUS +EFIAPI MailboxWrite ( + IN UINT32 MailboxType, + IN UINT32 MailboxCommand, + IN UINT32 MailboxData, + OUT UINT32 *MailboxStatus + ) +/** + Generic Mailbox function for mailbox write commands. This function will + poll the mailbox interface for control, issue the write request, poll + for completion, and verify the write was succussful. + + @param[IN] MailboxType, + @param[IN] MailboxCommand, + @param[IN] MailboxData, + @param[OUT] *MailboxStatus + + @retval EFI_STATUS +**/ +; + +EFI_STATUS +EFIAPI MailboxRead ( + IN UINT32 MailboxType, + IN UINT32 MailboxCommand, + OUT UINT32 *MailboxDataPtr, + OUT UINT32 *MailboxStatus + ) +/** + Generic Mailbox function for mailbox read commands. This function will write + the read request, and populate the read results in the output data. + + @param[IN] MailboxType, + @param[IN] MailboxCommand, + @param[OUT] *MailboxDataPtr, + @param[OUT] *MailboxStatus + + @retval EFI_STATUS +**/ +; + +EFI_STATUS +EFIAPI PollMailboxReady ( + IN UINT32 MailboxType + ) +/** + Poll the run/busy bit of the mailbox until available or timeout expires. + + @param[IN] MailboxType, + + @retval EFI_STATUS +**/ +; +#endif diff --git a/ReferenceCode/Haswell/Include/Library/TxtLibrary.h b/ReferenceCode/Haswell/Include/Library/TxtLibrary.h new file mode 100644 index 0000000..b3f70de --- /dev/null +++ b/ReferenceCode/Haswell/Include/Library/TxtLibrary.h @@ -0,0 +1,44 @@ +/** + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + +@file + TxtLibrary.h + +@brief + Header file for TXT Lib implementation. + +**/ +#ifndef _TXT_LIBRARY_H_ +#define _TXT_LIBRARY_H_ + +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueBase.h" +#endif + +UINT32 +CheckSmxCapabilities ( + VOID + ) +/** + + Execute GETSEC[CAPABILITIES] to report the SMX capabilities + +**/ +; + +#endif diff --git a/ReferenceCode/Haswell/Include/PfatDefinitions.h b/ReferenceCode/Haswell/Include/PfatDefinitions.h new file mode 100644 index 0000000..ff1ec9d --- /dev/null +++ b/ReferenceCode/Haswell/Include/PfatDefinitions.h @@ -0,0 +1,328 @@ +/** @file + Describes the functions visible to the rest of the PFAT. + +@copyright + Copyright (c) 2011 - 2014 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PFAT_DEFINITIONS_H_ +#define _PFAT_DEFINITIONS_H_ + +#ifndef ALIGN_256KB +#define ALIGN_256KB 0x00040000 +#endif +#ifndef EFI_PAGE_SIZE +#define EFI_PAGE_SIZE 0x00001000 +#endif + +/// +/// PFAT Module Commands +/// +#define PFAT_COMMAND_NOP 0x00 ///< NOP +#define PFAT_COMMAND_BEGIN 0x01 ///< PFAT Begin +#define PFAT_COMMAND_WRITE_INDEX 0x10 ///< PFAT Write Index +#define PFAT_COMMAND_WRITE_IMM 0x11 ///< PFAT Write Immediate +#define PFAT_COMMAND_READ_INDEX 0x12 ///< PFAT Read Index +#define PFAT_COMMAND_READ_IMM 0x13 ///< PFAT Read Immediate +#define PFAT_COMMAND_ERASE_BLK 0x14 ///< PFAT Erase Block +#define PFAT_COMMAND_EC_CMD_WR_INDEX 0x20 ///< EC_CMD Write Index +#define PFAT_COMMAND_EC_CMD_WR_IMM 0x21 ///< EC_CMD Write Immediate +#define PFAT_COMMAND_EC_STS_RD 0x22 ///< EC_CMD Read Status +#define PFAT_COMMAND_EC_DATA_WR_INDEX 0x23 ///< EC_DATA Write Index +#define PFAT_COMMAND_EC_DATA_WR_IMM 0x24 ///< EC_DATA Write Immediate +#define PFAT_COMMAND_EC_DATA_RD 0x25 ///< EC_DATA Read +#define PFAT_COMMAND_SET_BUFFER_INDEX 0x53 ///< PFAT Set Buffer Index +#define PFAT_COMMAND_SET_FLASH_INDEX 0x55 ///< PFAT Set Flash Index +#define PFAT_COMMAND_END 0xFF ///< PFAT End + +/// +/// PFAT Module Error Codes +/// +#define ERR_OK 0x0000 ///< Operation completed without error +#define ERR_UNSUPPORTED_CPU 0x0001 ///< PFAT module detected an incompatibility with the installed CPU +#define ERR_BAD_DIRECTORY 0x0002 ///< PFAT_DIRECTORY check failed +#define ERR_BAD_PPDT 0x0003 ///< A pre-execution check of the PPDT failed +#define ERR_BAD_PUP 0x0004 ///< An inconsistency was found in the update package +#define ERR_SCRIPT_SYNTAX 0x0005 ///< Unknown operator or name, or invalid syntax found in script +#define ERR_UNDEFINED_FLASH_OBJECT 0x0006 ///< An unimplemented flash object was referenced +#define ERR_INVALID_LINE 0x0007 ///< A JMP, JE, JNE, JG, JGE, JL, or JLE operator has a target that is not within the script buffer (between BEGIN and END inclusive) +#define ERR_BAD_PUPC 0x0008 ///< PUPC inconsistency found +#define ERR_BAD_SVN 0x0009 ///< PFAT module SVN is lower than required by PPDT +#define ERR_UNEXPECTED_OPCODE 0x000A ///< An EC related opcode found in a script when the PPDT indicates there is no EC in the system +#define ERR_RANGE_VIOLATION 0x8001 ///< Buffer or flash operation exceeded object bounds +#define ERR_SFAM_VIOLATION 0x8002 ///< An unsigned script attempted to write or erase a bock of flash that overlaps with the SFAM +#define ERR_OVERFLOW 0x8003 ///< An integer overflow occurred +#define ERR_EXEC_LIMIT 0x8004 ///< Total number of script opcodes retired exceeds either platform limit, or global limit +#define ERR_INTERNAL_ERROR 0x8005 ///< An internal consistency check failed within the PFAT module +#define ERR_LAUNCH_FAIL 0xFFFF ///< CPU detected an error and did not execute the PFAT module + +#define PFAT_F0_INDEX 0 +#define PFAT_B0_INDEX 0 + +#define EC_PRESENT BIT1 +#define EC_PFAT_PROTECTED BIT2 +#define PEG_DMI_FIX BIT24; + +#define MAX_SPI_COMPONENTS 8 +#define PFAT_MEMORY_PAGES 64 ///< PFAT Module needs 256KB of reserved memory (64 pages of 4KB each one) +#define ALIGNMENT_IN_PAGES 64 ///< PFAT requires 256KB alignment (64 pages of 4KB each one) + +#define PPDT_MAJOR_VERSION 1 +#define PPDT_MINOR_VERSION 0 +#define PFAT_SVN 0x10001 +#define PUP_HDR_VERSION 1 +#define PSL_MAJOR_VERSION 1 +#define PSL_MINOR_VERSION 0 + +#define PFAT_LOG_VERSION 1 +#define PFAT_LOG_OPT_STEP_TRACE BIT0 +#define PFAT_LOG_OPT_BRANCH_TRACE BIT1 +#define PFAT_LOG_OPT_FLASH_WRITE BIT2 +#define PFAT_LOG_OPT_FLASH_ERASE BIT3 +#define PFAT_LOG_OPT_FLASH_ERROR BIT4 +#define PFAT_LOG_OPT_DEBUG BIT5 + +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +/// +/// GUID to locate PFAT Module +/// +#define PFAT_MODULE_GUID \ + { \ + 0x7934156D, 0xCFCE, 0x460E, 0x92, 0xF5, 0xA0, 0x79, 0x09, 0xA5, 0x9E, 0xCA \ + } +/// +/// GUID to locate PFAT HOB +/// +#define PFAT_HOB_GUID \ + { \ + 0x66F0C42D, 0x0D0E, 0x4C23, 0x93, 0xC0, 0x2D, 0x52, 0x95, 0xDC, 0x5E, 0x21 \ + } +#else +/// +/// GUID to locate PFAT Module +/// +#define PFAT_MODULE_GUID \ + { \ + 0x7934156D, 0xCFCE, 0x460E, \ + { \ + 0x92, 0xF5, 0xA0, 0x79, 0x09, 0xA5, 0x9E, 0xCA \ + } \ + } +/// +/// GUID to locate PFAT HOB +/// +#define PFAT_HOB_GUID \ + { \ + 0x66F0C42D, 0x0D0E, 0x4C23, \ + { \ + 0x93, 0xC0, 0x2D, 0x52, 0x95, 0xDC, 0x5E, 0x21 \ + } \ + } +#endif + +#define SPI_SIZE_BASE_512KB 0x80000 + +typedef enum { + EnumSpiCompSize512KB = 0, + EnumSpiCompSize1MB, + EnumSpiCompSize2MB, + EnumSpiCompSize4MB, + EnumSpiCompSize8MB, + EnumSpiCompSize16MB, + EnumSpiCompSize32MB, + EnumSpiCompSize64MB, + EnumSpiCompSize128MB +} SPI_COMPONENT_SIZE; + +#define MIN_SFAM_COUNT 1 +#define MAX_SFAM_COUNT 64 + +typedef struct { + UINT32 FirstByte; ///< Linear flash address of the first byte of the signed range, must be aligned to be first byte in the block. Ordering is little-endian + UINT32 LastByte; ///< Linear flash address of the last byte of the signed range, must be aligned to be last byte in the block. Ordering is little-endian +} SFAM_DATA; + +/// +/// PFAT Platform Data Table (PPDT) +/// Provides platform specific data required by PFAT Module +/// +typedef struct { + UINT32 PpdtSize; ///< Size in bytes of PPDT including SFAM + UINT16 PpdtMajVer; ///< Indicates major version of PPDT + UINT16 PpdtMinVer; ///< Indicates minor version of PPDT + UINT8 PlatId[16]; ///< PLAT_ID used to be compared against the one found in the PUP Header to prevent cross platform flashing + UINT8 PkeySlot0[32]; ///< SHA256 hash for PUP verification key 0 + UINT8 PkeySlot1[32]; ///< SHA256 hash for PUP verification key 1 + UINT8 PkeySlot2[32]; ///< SHA256 hash for PUP verification key 2 + UINT32 PfatModSvn; ///< PFAT Module SVN + UINT32 BiosSvn; ///< BIOS_SVN to prevent back-flashing + UINT32 ExecLim; ///< Limit the number of opcodes that can be executed on any invocation of PFAT + /// + /// Bitmap of platform policy attributes + /// BIT[0]: Reserved. Must be 0 + /// BIT[2:1] (EC_PRESENT) + /// 00b = There is not an EC is the system + /// 01b = There exists an EC in the system, PFAT does not extend any protection to the EC + /// 11b = There exist an EC in the system, PFAT extends protection to the EC + /// 10b = Reserved. Must not be used + /// BIT[3]: (DESCRIPTOR_OVERRIDE_POLICY) + /// 0b = Do not override PFAT security policy + /// 1b = Override PFAT security policy + /// BIT[23:4]: Reserved, must be 0 + /// BIT[24]: + /// 0b = indicates PFAT module will not take additional steps. + /// 1b = indicates PFAT module should take additional steps to mitigate potential interference from installed PEG device. + /// BIT[31:25] Reserved, must be 0 + /// + UINT32 PlatAttr; + /// + /// BIT[9:0] - 8 bit IO port used for sending EC commands (writes), and reading EC status (reads) + /// This field must be populated if PLAT_ATTR.EC_PRESENT != 0 + /// This field must be zero if PLAT_ATTR.EC_PRESENT == 0 + /// BIT[31:10] - Reserved. Must be 0 + /// + UINT32 EcCmd; + /// + /// BIT[9:0] - 8 bit IO port used for reading and writing data to the EC based on a command issued to EC_CMD + /// This field must be populated if PLAT_ATTR.EC_PRESENT != 0 + /// This field must be zero if PLAT_ATTR.EC_PRESENT == 0 + /// BIT[31:10] - Reserved. Must be 0 + /// + UINT32 EcData; + /// + /// BIT[7:0] - EC command indicating a read of the current EC firmware SVN + /// This field must be populated if PLAT_ATTR.EC_PRESENT != 0 + /// This field must be zero if PLAT_ATTR.EC_PRESENT == 0 + /// BIT[31:8] - Reserved. Must be 0 + /// + UINT32 EcCmdGetSvn; + /// + /// BIT[7:0] - EC command indicating flash begin of flash update session + /// This field must be populated if PLAT_ATTR.EC_PRESENT != 0 + /// This field must be zero if PLAT_ATTR.EC_PRESENT == 0 + /// BIT[31:8] - Reserved. Must be 0 + /// + UINT32 EcCmdOpen; + /// + /// BIT[7:0] - EC command indicating the termination of PFAT protected session + /// This field must be populated if PLAT_ATTR.EC_PRESENT != 0 + /// This field must be zero if PLAT_ATTR.EC_PRESENT == 0 + /// BIT[31:8] - Reserved. Must be 0 + /// + UINT32 EcCmdClose; + /// + /// BIT[7:0] - EC command used to verify connectivity between PFAT and EC + /// This field must be populated if PLAT_ATTR.EC_PRESENT != 0 + /// This field must be zero if PLAT_ATTR.EC_PRESENT == 0 + /// BIT[31:8] - Reserved. Must be 0 + /// + UINT32 EcCmdPortTest; + UINT8 Reserved1[4]; + /// + /// Defines number of elements in SFAM array + /// BIT[5..0]: Index of the last SFAM element + /// BIT[7..6]: Reserved for future use. Must be 0 + /// + UINT8 LastSfam; + UINT8 Reserved2[3]; + SFAM_DATA SfamData[MAX_SFAM_COUNT]; ///< Array of flash address map descriptors. sizeof (SFAM_DESC) == 8 +} PPDT; + +/// +/// PFAT Update Package Header +/// +typedef struct { + UINT16 Version; ///< Version of the update package header. Must be 0x0001 + UINT8 Reserved3[2]; + UINT8 PlatId[16]; ///< PLAT_ID used to be compared against the one found in the PPDT to prevent cross platform flashing + /// + /// If any bit set in this field then PUP must be signed and valid PUPC must be provided for PUP to be processed + /// BIT[0] - Indicates write/erase operations will be executed on protected flash area indicated in the PPDT SFAM + /// BIT[1] - Indicates protected EC operations included + /// + UINT16 PkgAttributes; + UINT8 Reserved4[2]; + UINT16 PslMajorVer; ///< Indicates the PSL major version. Must be 1 + UINT16 PslMinorVer; ///< Indicates the PSL minor version. Must be 0 + UINT32 ScriptSectionSize; ///< Size in bytes of the script + UINT32 DataSectionSize; ///< Size of the data region in bytes + UINT32 BiosSvn; ///< BIOS SVN + UINT32 EcSvn; ///< EC SVN + UINT32 VendorSpecific; + } PUP_HEADER; + + /// + /// Memory location for PUP, PUPC and PFAT LOG inside PFAT DPR allocated memory for Tool interface + /// +#define PUP_BUFFER_SIZE 0x00014000 ///< 16KB Script + 64KB Flash Block +#define PUPC_MEMORY_SIZE 0x00008000 ///< 32KB +#define PFAT_LOG_MEMORY_SIZE 0x00020000 ///< 128KB +#define PUPC_MEMORY_OFFSET (PUPC_MEMORY_SIZE + PFAT_LOG_MEMORY_SIZE) ///< PfatMemAddress + PfatMemSize - PFAT_LOG_MEMORY_SIZE - 32KB +#define PFAT_LOG_MEMORY_OFFSET PFAT_LOG_MEMORY_SIZE ///< PfatMemAddress + PfatMemSize - 128KB +#define MAX_PFAT_LOG_PAGE ((PFAT_LOG_MEMORY_SIZE / EFI_PAGE_SIZE) - 2) ///< 30 4KB Pages + + /// + /// PFAT update package definition for BIOS SMM Initiated runtime calls + /// + typedef struct { + PUP_HEADER PupHeader; + UINT64 PupBuffer[PUP_BUFFER_SIZE / 8]; + } PUP; + +/// +/// PFAT Log +/// The logging facility is used to communicate detailed information regarding the execution of a PFAT script +/// from the SMI handler which invoked the PFAT module itself +/// +typedef struct { + UINT16 Version; ///< Indicates the version of the log. Must be 0x0001 + UINT16 LastPage; ///< Last valid page index for the log + /// + /// Bitmap indicating what events to log + /// BIT[0] - Step trace - this indicates a full execution trace. Each line is entered into the log with an EXECUTION_TRACE entry + /// BIT[1] - Branch trace - All taken jumps are logged with a BRANCH_TRACE entry + /// BIT[2] - Flash write - All flash write operations are logged with a FLASH_WRITE entry + /// BIT[3] - Flash erase - All flash erase operations are logged with a FLASH_ERASE entry + /// BIT[4] - Flash error - All error conditions from flash operations are logged with FLASH_ERROR entry + /// BIT[5] - Debug - Log Debug opcode execution + /// BIT[6] - PFAT module debug message - Log implementation specific debug messages from debug module + /// BIT[31:7] - Reserved. Must be 0. If any reserved bits are set in Header.LoggingOptions, the PFAT module must disable the logging feature + /// + UINT32 LoggingOptions; + UINT8 Reserved5[8]; + UINT32 PfatModSvn; ///< Indicates a version number of the PFAT module + UINT32 NumOfEntriesInLog; ///< Total number of log entries that have been written to the log +} PFAT_LOG; + +/// +/// HOB used to pass data through every phase of PFAT Bios +/// PFAT Bios code is executed in PEI, DXE and SMM and HOB is the only method to properly pass data +/// between every phase +/// +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + PPDT Ppdt; ///< PFAT Platform Data Table + /// + /// PFAT update package header, this header will be appended to all flash updates along with PSL script + /// + PUP_HEADER PupHeader; + UINT8 NumSpiComponents; ///< Number of physical SPI flash components on platform + UINT8 ComponentSize[MAX_SPI_COMPONENTS]; ///< Array containing size of each flash component + UINT64 PfatToolsIntIoTrapAdd; ///< IO Trap address required to Initialize PFAT Tools Interface + PFAT_LOG PfatLog; ///< Header for PFAT Log Buffer +} PFAT_HOB; + +#endif diff --git a/ReferenceCode/Haswell/Include/PowerMgmtDefinitions.h b/ReferenceCode/Haswell/Include/PowerMgmtDefinitions.h new file mode 100644 index 0000000..5f95a72 --- /dev/null +++ b/ReferenceCode/Haswell/Include/PowerMgmtDefinitions.h @@ -0,0 +1,145 @@ +/** @file + This file contains define definitions specific to Haswell processor + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _POWER_MGMT_DEFINITIONS_H_ +#define _POWER_MGMT_DEFINITIONS_H_ + +#define PPM_ENABLE 1 +#define PPM_DISABLE 0 + +#define CSTATE_SUPPORTED 0x1 +#define ENHANCED_CSTATE_SUPPORTED 0x2 +#define C6_C7_SHORT_LATENCY_SUPPORTED 0x01 +#define C6_C7_LONG_LATENCY_SUPPORTED 0x02 +#define C7s_SHORT_LATENCY_SUPPORTED 0x03 +#define C7s_LONG_LATENCY_SUPPORTED 0x04 +// +// Platform Power Management Flags Bit Definitions: +// These defines are also used in CPU0CST.ASL to check platform configuration +// and build C-state table accordingly. +// +#define PPM_EIST 0x1 ///< BIT 0 : Enhanced Intel Speed Step Technology. +#define PPM_C1 0x2 ///< BIT 1 : C1 enabled, supported. +#define PPM_C1E 0x4 ///< BIT 2 : C1E enabled. +#define PPM_C3 0x8 ///< BIT 3 : C3 enabled, supported. +#define PPM_C6 0x10 ///< BIT 4 : C6 enabled, supported. +#define PPM_C7 0x20 ///< BIT 5 : C7 enabled, supported. +#define PPM_C7S 0x40 ///< BIT 6 : C7S enabled, supported +#define PPM_TM 0x80 ///< BIT 7 : Adaptive Thermal Monitor. +#define PPM_TURBO 0x100 ///< BIT 8 : Long duration turbo mode +#define PPM_CMP 0x200 ///< BIT 9 : CMP. +#define PPM_TSTATES 0x400 ///< BIT 10: CPU throttling states +#define PPM_MWAIT_EXT 0x800 ///< BIT 11: MONITIOR/MWAIT Extensions supported. +#define PPM_EEPST 0x1000 ///< BIT 12: Energy efficient P-State Feature enabled +#define PPM_TSTATE_FINE_GRAINED 0x2000 ///< BIT 13: Fine grained CPU Throttling states +#define PPM_CD 0x4000 ///< BIT 14: Deep Cstate - C8/C9/C10 +#define PPM_TIMED_MWAIT 0x8000 ///< BIT 15: Timed Mwait support +#define C6_LONG_LATENCY_ENABLE 0x10000 ///< BIT 16: 1=C6 Long and Short,0=C6 Short only +#define C7_LONG_LATENCY_ENABLE 0x20000 ///< BIT 17: 1=C7 Long and Short,0=C7 Short only +#define C7s_LONG_LATENCY_ENABLE 0x40000 ///< BIT 18: 1=C7s Long and Short,0=C7s Short only +#define PPM_C8 0x80000 ///< Bit 19: 1= C8 enabled/supported +#define PPM_C9 0x100000 ///< Bit 20: 1= C9 enabled/supported +#define PPM_C10 0x200000 ///< Bit 21: 1= C10 enabled/supported + +#define PPM_C_STATES 0x7A ///< PPM_C1 + PPM_C3 + PPM_C6 + PPM_C7 + PPM_C7S +#define C3_LATENCY 0x42 +#define C6_C7_SHORT_LATENCY 0x73 +#define C6_C7_LONG_LATENCY 0x91 +#define C8_LATENCY 0xE4 +#define C9_LATENCY 0x145 +#define C10_LATENCY 0x1EF + +#define CPUID_FUNCTION_6 0x00000006 +// +// The following definitions are based on assumed location for the ACPI +// Base Address. Modify as necessary base on platform-specific requirements. +// +#define PCH_ACPI_PBLK 0x1810 +#define PCH_ACPI_LV2 0x1814 +#define PCH_ACPI_LV3 0x1815 +#define PCH_ACPI_LV4 0x1816 +#define PCH_ACPI_LV6 0x1818 +#define PCH_ACPI_LV5 0x1817 +#define PCH_ACPI_LV7 0x1819 + +// +// C-State Latency (us) and Power (mW) for C1 +// +#define C1_LATENCY 1 +#define C1_POWER 0x3E8 +#define C3_POWER 0x1F4 +#define C6_POWER 0x15E +#define C7_POWER 0xC8 +#define C8_POWER 0xC8 +#define C9_POWER 0xC8 +#define C10_POWER 0xC8 + +#define MAX_POWER_LIMIT_1_TIME_IN_SECONDS 32767 +#define AUTO 0 +#define END_OF_TABLE 0xFF + +#define CONFIG_TDP_DOWN 1 +#define CONFIG_TDP_UP 2 +#define CONFIG_TDP_DEACTIVATE 0xFF +// +// MMIO definitions +// +#define MMIO_DDR_RAPL_LIMIT 0x58e0 +#define MMIO_TURBO_POWER_LIMIT 0x59A0 + +#define MAX_OVERCLOCKING_BINS 0x7 + +/// +/// For Mobile, default PL1 time window value is 28 seconds +/// +#define MB_POWER_LIMIT1_TIME_DEFAULT 28 +/// +/// For Desktop, default PL1 time window value is 8 second +/// +#define DT_POWER_LIMIT1_TIME_DEFAULT 8 + +#define PROCESSOR_FLAVOR_MOBILE 0x04 +#define PROCESSOR_FLAVOR_DESKTOP 0x00 +#define PROCESSOR_FLAVOR_MASK (BIT3 | BIT2) + +// +// Power definitions (Based on EMTS V1.0 for standard voltage 2.4-2.6 GHz dual-core parts.) +// +#define FVID_MAX_POWER 35000 +#define FVID_TURBO_POWER 35000 +#define FVID_SUPERLFM_POWER 12000 +// +// Power definitions for LFM and Turbo mode TBD. +// +#define FVID_MIN_POWER 15000 +/// +/// S3- MSR restore SW SMI +/// +#ifndef SW_SMI_S3_RESTORE_MSR +#define SW_SMI_S3_RESTORE_MSR 0x48 +#endif +/// +/// VR Current Limit Default +/// +#define VR_CURRENT_DEFAULT 0 +#define PSI1_THRESHOLD_DEFAULT 0x14 +#define PSI2_THRESHOLD_DEFAULT 0x05 +#define PSI3_THRESHOLD_DEFAULT 0x01 +#endif diff --git a/ReferenceCode/Haswell/Include/ThunkLib.h b/ReferenceCode/Haswell/Include/ThunkLib.h new file mode 100644 index 0000000..8d7146a --- /dev/null +++ b/ReferenceCode/Haswell/Include/ThunkLib.h @@ -0,0 +1,154 @@ +/** @file + Real Mode Thunk Functions for IA32 and X64 + +@copyright + Copyright (c) 2006 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef __THUNK_LIB__ +#define __THUNK_LIB__ + +/// +/// Byte packed structure for an 16-bit real mode thunks +/// +typedef struct { + UINT32 RealModeBuffer; + UINT32 DefaultStack; +} THUNK16_CONTEXT; + +// +// 16-bit thunking services +// +#define THUNK_SAVE_FP_STATE 0x1 +#define THUNK_USER_STACK 0x2 +#define THUNK_INTERRUPT 0x10000 + +// +// Function Prototypes +// +/** + Returns the properties of this real mode thunk implementation. Currently + there are 2 properties has been defined, the minimum real mode buffer size + and the minimum stack size. + + @param[in] MinimumStackSize - The minimum size required for a 16-bit stack. + + @retval The minimum size of the real mode buffer needed by this thunk implementation + @retval is returned. +**/ +UINTN +EFIAPI +R8AsmThunk16GetProperties ( + OUT UINTN *MinimumStackSize OPTIONAL + ); + +/** + Tell this real mode thunk implementation the address and size of the real + mode buffer needed. + + @param[in] ThunkContext - The thunk context whose properties to set. + @param[in] RealModeBuffer - The address of the buffer allocated by caller. It should be + aligned on a 16-byte boundary. + This buffer must be in identity mapped pages. + @param[in] BufferSize - The size of RealModeBuffer. Must be larger than the minimum + size required as returned by R8AsmThunk16GetProperties(). +**/ +THUNK16_CONTEXT * +EFIAPI +R8AsmThunk16SetProperties ( + OUT THUNK16_CONTEXT *ThunkContext, + IN VOID *RealModeBuffer, + IN UINTN BufferSize + ); + +/** + Reset all internal states to their initial values. The caller should not + release the real mode buffer until after a call to this function. + + @param[in] ThunkContext - The thunk context to destroy. +**/ +VOID +EFIAPI +R8AsmThunk16Destroy ( + IN OUT THUNK16_CONTEXT *ThunkContext + ); + +/** + Make a far call to 16-bit code. + + NOTE: This function must be called on TPL_HIGH_LEVEL or with interrupts + disabled because of GDTR and IDTR manipulations. + This function must be placed in identity mapped pages. + + @param[in] ThunkContext - Thunk context to use. + @param[in] RegisterSet - CPU registers would be set to the values contained in this + structure before making the far call. Then CPU registers are + copied back to this structure. + CS:EIP points to the real mode code being called on input. + SS:ESP points to the real mode stack if THUNK_USER_STACK is + set on input, otherwise ignored. + EFlages is ignored on input. + On output, values of CS, EIP, SS and ESP should be ignored. + @param[in] ThunkFlags - 2 flags have currently been defined, THUNK_SAVE_FP_STATE and + THUNK_USER_STACK. + THUNK_SAVE_FP_STATE - FPU state would be saved/restored + before/after calling real mode code. + THUNK_USER_STACK - The stack specified by SS:ESP would be + used instead of the default stack. + + @retval RegisterSet is returned. +**/ +IA32_REGISTER_SET * +EFIAPI +R8AsmThunk16FarCall86 ( + IN THUNK16_CONTEXT *ThunkContext, + IN OUT IA32_REGISTER_SET *RegisterSet, + IN UINT32 ThunkFlags + ); + +/** + Invoke a 16-bit interrupt handler. + + NOTE: This function must be called on TPL_HIGH_LEVEL or with interrupts + disabled because of GDTR and IDTR manipulations. + This function must be placed in identity mapped pages. + + @param[in] ThunkContext - Thunk context to use. + @param[in] IntNumber - The ordinal of the interrupt handler ranging from 0 to 255. + @param[in] RegisterSet - CPU registers would be set to the values contained in this + structure before making the far call. Then CPU registers are + copied back to this structure. + SS:ESP points to the real mode stack if THUNK_USER_STACK is + set on input, otherwise ignored. + EFlages is ignored on input. + On output, values of CS, EIP, SS and ESP should be ignored. + @param[in] ThunkFlags - 2 flags have currently been defined, THUNK_SAVE_FP_STATE and + THUNK_USER_STACK. + THUNK_SAVE_FP_STATE - FPU state would be saved/restored + before/after calling real mode code. + THUNK_USER_STACK - The stack specified by SS:ESP would be + used instead of the default stack. + + @retval RegisterSet is returned. +**/ +IA32_REGISTER_SET * +EFIAPI +R8AsmThunk16Int86 ( + IN THUNK16_CONTEXT *ThunkContext, + IN UINT8 IntNumber, + IN OUT IA32_REGISTER_SET *RegisterSet, + IN UINT32 ThunkFlags + ); + +#endif diff --git a/ReferenceCode/Haswell/Include/TisPc.h b/ReferenceCode/Haswell/Include/TisPc.h new file mode 100644 index 0000000..e11434b --- /dev/null +++ b/ReferenceCode/Haswell/Include/TisPc.h @@ -0,0 +1,71 @@ +/** + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + +@file + TisPc.h + +@brief + Definitions and function prototypes shared by all TPM components + +**/ +#ifndef _TIS_PC_H_ +#define _TIS_PC_H_ + +/// +/// Set structure alignment to 1-byte +/// +#pragma pack(push) +#pragma pack(1) +/// +/// TPM Base Address Definitions +/// +#define TPM_BASE_ADDRESS 0xFED40000 +/// +/// Register set map as specified in TIS Chapter 10 +/// +typedef struct tdTIS_PC_REGISTERS { + INT8 access; ///< 0 + UINT8 reserved1[7]; ///< 1 + UINT32 intEnable; ///< 8 + UINT8 intVector; ///< 0ch + UINT8 reserved2[3]; ///< 0dh + UINT32 intSts; ///< 10h + UINT32 intfCapability; ///< 14h + INT8 status; ///< 18h + UINT16 burstCount; ///< 19h + UINT8 reserved3[9]; + UINT32 dataFifo; ///< 24 + UINT8 reserved4[0xed8]; ///< 28h + UINT16 vid; ///< 0f00h + UINT16 did; ///< 0f02h + UINT8 rid; ///< 0f04h + UINT8 tcgDefined[0x7b]; ///< 0f05h + UINT32 legacyAddress1; ///< 0f80h + UINT32 legacyAddress1Ex; ///< 0f84h + UINT32 legacyAddress2; ///< 0f88h + UINT32 legacyAddress2Ex; ///< 0f8ch + UINT8 vendorDefined[0x70]; ///< 0f90h +} TIS_PC_REGISTERS; + +/// +/// Define pointer types used to access TIS registers on PC +/// +typedef VOLATILE TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR; + +#pragma pack(pop) +#endif diff --git a/ReferenceCode/Haswell/Include/Txt.h b/ReferenceCode/Haswell/Include/Txt.h new file mode 100644 index 0000000..5db5155 --- /dev/null +++ b/ReferenceCode/Haswell/Include/Txt.h @@ -0,0 +1,160 @@ +/** @file + This file contains definitions required to use the TXT BIOS + Authenticated Code Module Library. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _TXT_BIOS_ACM_LIB_H_ +#define _TXT_BIOS_ACM_LIB_H_ + +#define TPM_TIME_OUT 750 + +#define TXT_RLP_INIT 1 + +/// +/// MMIO definition +/// +#ifndef MmPciAddress +//#define MmPciAddress(Segment, Bus, Device, Function, Register) \ +// ((UINTN) (PciRead32 (PCI_LIB_ADDRESS (0,0,0,0x60)) & 0xFC000000) + \ +// (UINTN) (Bus << 20) + \ +// (UINTN) (Device << 15) + \ +// (UINTN) (Function << 12) + \ +// (UINTN) (Register) \ +// ) +#define MmPciAddress(Segment, Bus, Device, Function, Register) \ + ((UINTN) PlatformPciExpressBaseAddress + \ + (UINTN) (Bus << 20) + \ + (UINTN) (Device << 15) + \ + (UINTN) (Function << 12) + \ + (UINTN) (Register) \ + ) +#endif +// +// TxT BIOS Spec version +// +#define TXT_BIOS_SPEC_VER_MAJOR 2 +#define TXT_BIOS_SPEC_VER_MINOR 1 +#define TXT_BIOS_SPEC_VER_REVISION 0 + +// +// The following are values that are placed in the esi register when +// calling the BIOS ACM. These constants are used as parameters to the +// TxtSetupandLaunchBiosAcm function. +// +#define TXT_LAUNCH_SCLEAN 0x00 +#define TXT_RESET_EST_BIT 0x01 +#define TXT_RESET_AUX 0x02 +#define TXT_LAUNCH_SCHECK 0x04 + +#define TPM_STATUS_REG_ADDRESS 0xFED40000 +#define TXT_PUBLIC_BASE 0xFED30000 +#define TXT_PRIVATE_BASE 0xFED20000 +#define TXT_CONFIG_SPACE_LENGTH 0x60000 + +#define TXT_ERROR_STATUS_REG_OFF 0x8 +#define TXT_SINIT_BASE_REG_OFF 0x270 +#define TXT_SINIT_SIZE_REG_OFF 0x278 +#define TXT_SINIT_SIZE_REG_OFF2 0x27C +#define TXT_SVMM_JOIN_REG_OFF 0x290 +#define TXT_SVMM_JOIN_REG_OFF2 0x294 +#define TXT_HEAP_BASE_REG_OFF 0x300 +#define TXT_HEAP_SIZE_REG_OFF 0x308 +#define TXT_SCRATCHPAD 0x320 +#define TXT_SCRATCHPAD2 0x324 +#define TXT_SCRATCHPAD3 0x328 +#define TXT_SCRATCHPAD4 0x32C +#define TXT_DPR_SIZE_REG_OFF 0x330 + +#define TXT_E2STS_REG_OFF 0x8F0 +#define TXT_BLOCK_MEM_STS BIT2 +#define TXT_SECRETS_STS BIT1 +#define TXT_SLP_ENTRY_ERROR_STS BIT0 + +#define MCU_BASE_ADDR TXT_SINIT_SIZE_REG_OFF +#define BIOACM_ADDR TXT_SINIT_SIZE_REG_OFF2 +#define APINIT_ADDR TXT_SVMM_JOIN_REG_OFF +#define SEMAPHORE TXT_SVMM_JOIN_REG_OFF2 + +/// +/// GUIDs used by TXT drivers +/// +#define PEI_BIOS_ACM_FILE_GUID \ + { \ + 0x2D27C618, 0x7DCD, 0x41F5, 0xBB, 0x10, 0x21, 0x16, 0x6B, 0xE7, 0xE1, 0x43 \ + } + +#define PEI_AP_STARTUP_FILE_GUID \ + { \ + 0xD1E59F50, 0xE8C3, 0x4545, 0xBF, 0x61, 0x11, 0xF0, 0x02, 0x23, 0x3C, 0x97 \ + } + +#define CPU_MICROCODE_FILE_GUID \ + { \ + 0x17088572, 0x377F, 0x44ef, 0x8F, 0x4E, 0xB0, 0x9F, 0xFF, 0x46, 0xA0, 0x70 \ + } + +#pragma pack(push, 1) +/// +/// BIOS OS Data region definitions +/// +#define BIOS_OS_DATAREGION_VERSION 4 + +typedef struct { + UINT32 Type; + UINT32 Size; +} HEAP_EXT_DATA_ELEMENT; + +/// +/// BIOS spec version element +/// +#define HEAP_EXTDATA_TYPE_BIOS_SPEC_VER 1 + +typedef struct { + HEAP_EXT_DATA_ELEMENT Header; + UINT16 SpecVerMajor; + UINT16 SpecVerMinor; + UINT16 SpecVerRevision; +} HEAP_BIOS_SPEC_VER_ELEMENT; + +/// +/// BIOS ACM element +/// +#define HEAP_EXTDATA_TYPE_BIOSACM 2 +typedef struct { + HEAP_EXT_DATA_ELEMENT Header; + UINT32 NumAcms; +} HEAP_BIOSACM_ELEMENT; + +/// +/// END type +/// +#define HEAP_EXTDATA_TYPE_END 0 + +typedef struct { + UINT32 Version; + UINT32 BiosSinitSize; + EFI_PHYSICAL_ADDRESS LcpPdBase; + UINT64 LcpPdSize; + UINT32 NumOfLogicalProcessors; + UINT64 Flags; + HEAP_EXT_DATA_ELEMENT ExtData; +} BIOS_OS_DATA_REGION; + +#pragma pack(pop) +#endif diff --git a/ReferenceCode/Haswell/Include/Txt.inc b/ReferenceCode/Haswell/Include/Txt.inc new file mode 100644 index 0000000..4cd76fe --- /dev/null +++ b/ReferenceCode/Haswell/Include/Txt.inc @@ -0,0 +1,442 @@ +;@file +; This file contains definitions used in Txtpeibsp and txtpeiap.asm +; +;@copyright +; Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +; This software and associated documentation (if any) is furnished +; under a license and may only be used or copied in accordance +; with the terms of the license. Except as permitted by such +; license, no part of this software or documentation may be +; reproduced, stored in a retrieval system, or transmitted in any +; form or by any means without the express written consent of +; Intel Corporation. +; +; This file contains an 'Intel Peripheral Driver' and uniquely +; identified as "Intel Reference Module" and is +; licensed for Intel CPUs and chipsets under the terms of your +; license agreement with Intel or your vendor. This file may +; be modified by the user, subject to additional terms of the +; license agreement +; + +;----------------------------------------------------------------------------- +; Common equates +; + +UINT32 TYPEDEF DWORD +UINT64 TYPEDEF QWORD + +;----------------------------------------------------------------------------- +; Bit definitions +; +BIT31 EQU (1 SHL 31) +BIT30 EQU (1 SHL 30) +BIT29 EQU (1 SHL 29) +BIT28 EQU (1 SHL 28) +BIT27 EQU (1 SHL 27) +BIT26 EQU (1 SHL 26) +BIT25 EQU (1 SHL 25) +BIT24 EQU (1 SHL 24) +BIT23 EQU (1 SHL 23) +BIT22 EQU (1 SHL 22) +BIT21 EQU (1 SHL 21) +BIT20 EQU (1 SHL 20) +BIT19 EQU (1 SHL 19) +BIT18 EQU (1 SHL 18) +BIT17 EQU (1 SHL 17) +BIT16 EQU (1 SHL 16) +BIT15 EQU (1 SHL 15) +BIT14 EQU (1 SHL 14) +BIT13 EQU (1 SHL 13) +BIT12 EQU (1 SHL 12) +BIT11 EQU (1 SHL 11) +BIT10 EQU (1 SHL 10) +BIT9 EQU (1 SHL 9) +BIT8 EQU (1 SHL 8) +BIT7 EQU (1 SHL 7) +BIT6 EQU (1 SHL 6) +BIT5 EQU (1 SHL 5) +BIT4 EQU (1 SHL 4) +BIT3 EQU (1 SHL 3) +BIT2 EQU (1 SHL 2) +BIT1 EQU (1 SHL 1) +BIT0 EQU (1 SHL 0) + +PORTB EQU 061h +PORTBMASK EQU (1 shl 4) +; +; BIOS ACM functions +; +TXT_LAUNCH_SCLEAN EQU 00h +TXT_RESET_EST_BIT EQU 01h +TXT_RESET_AUX EQU 02h +TXT_LAUNCH_SCHECK EQU 04h + +PORT80_CODE_PREFIX EQU 0A0h + +; +; EDI parameter sent to SCHECK function +; +COLD_BOOT_PATH EQU 0 +S3_RESUME_PATH EQU BIT1 +;---------------------------------------------------------------------------- +; Common stackless calling macros +; +CALL_NS MACRO lbl + local retaddr + if @WordSize EQ 2 + mov sp, retaddr + else + mov esp, retaddr + endif + + pslldq xmm4, 4 + pinsrw xmm4, esp, 0 + rol esp, 10h + pinsrw xmm4, esp, 1 + + jmp lbl + +retaddr: +ENDM + +RET_NS MACRO + movd esp, xmm4 + psrldq xmm4, 4 + + if @WordSize EQ 2 + jmp sp + else + jmp esp + endif +ENDM + +;----------------------------------------------------------------------------- +; AC Module header +; +ACM_HEADER STRUCT + ORG 24 + AcmSize dd ? ; // 24 4 Module size (in multiples of four bytes) +ACM_HEADER ENDS + +;----------------------------------------------------------------------------- +; TXT enabling and execution +; + +CAPABILITIES EQU 00h +ENTERACCS EQU 02h + +CR0_NE_MASK EQU (1 SHL 5) +CR0_NW_MASK EQU (1 SHL 29) +CR0_CD_MASK EQU (1 SHL 30) +CR0_PG_MASK EQU (1 SHL 31) + +CR4_VME EQU (1 SHL 0) +CR4_PVI EQU (1 SHL 1) +CR4_TSD EQU (1 SHL 2) +CR4_DE EQU (1 SHL 3) +CR4_PSE EQU (1 SHL 4) +CR4_PAE EQU (1 SHL 5) +CR4_MSE EQU (1 SHL 6) +CR4_PGE EQU (1 SHL 7) +CR4_PCE EQU (1 SHL 8) +CR4_OSFXSR EQU (1 SHL 9) +CR4_VMXE EQU (1 SHL 13) +CR4_SMXE EQU (1 SHL 14) + +_GETSEC EQU db 0fh, 37h + +;---------------------------------------------------------------------------- +; DescriptorAccess Rights Definitions +; +PAGEGRANULARITY EQU 01H ; Page Granularity +BYTEGRANULARITY EQU 00H ; Byte Granularity +BIGSEGMENT EQU 01H ; Big Segment 32 bit +SMALLSEGMENT EQU 00H ; Small Segment 16 bit +SEG_PRESENT EQU 01H ; Segment Present +SEG_NOTPRESENT EQU 00H ; Segment Not Present +APPLSEGMENT EQU 01H ; Application Segment +SYSTEMSEGMENT EQU 00H ; System Segment + +DATATYPE EQU 03H ; Read, Write, accessed +STACKTYPE EQU 03H ; Read, Write, accessed +CODETYPE EQU 0BH ; Execute, Read, accessed + +;---------------------------------------------------------------------------- +;Descritor table structures and records +; + +R_AR0_7 RECORD P:1=0, DPL:2=0, D_T:1=0, sType:4=0 + +; P - Segment present +; 0=NOTPRESENT +; 1=PRESENT +; DPL - Descriptor priviledge level +; D_T - Descriptor type +; 0=SYSTEMSEGMENT +; 1=APPLSEGMENT +; sType - Segment Type +; For Application segment: +; 03h - DATATYPE (Read/Write/Accessed) +; 07h - STACKTYPE (Expand Down/Read/Write/Accessed) +; 0Fh - CODETYPE (Execute/Conforming/Read/Accessed) +; +; For System segment: +; 01h - Available 16 bit TSS +; 02h - LDT +; 03h - Active 16 bit TSS +; 04h - 16 bit call gate +; 05h - 16 + 32 bit task gate +; 06h - 16 bit interrupt gate +; 07h - 16 bit trap gate +; 09h - Available 32 bit TSS +; 0Bh - Active 32 bit TSS +; 0Ch - 32 bit call gate +; 0Eh - 32 bit interrupt gate +; 0Fh - 32 bit trap gate + +R_LAR16_23 RECORD G:1=0, D_B:1=0, L:1=0, Avl:1=0, Lim:4=0 + +; G - Granularity +; 0=BYTEGRANULARITY +; 1=PAGEGRANULARITY +; D_B - Segment size +; 0=SMALLSEGMENT +; 1=BIGSEGMENT +; Res - Reserved +; Avl - Available for OS (Not used) +; Lim - Limit bits 16-19 + +SEG_DESCRIPTOR STRUCT 4 + Limit0_15 DW 0000 ; Limit Bits 0-15 + Base0_15 DW 0000 ; Base address Bits 0-15 + Base16_23 DB 00 ; Base address Bits 16-23 + AR0_7 R_AR0_7 <> ; Access Rights 0-7 + LAR16_23 R_LAR16_23 <> ; Limit Bits 16-19 and Access Bits 8-11 + Base24_31 DB 00 ; Base address Bits 24-31 +SEG_DESCRIPTOR ENDS + +;----------------------------------------------------------------------------- +; Machine Check register definitions +; +MCG_CAP EQU 179h + +MC0_STATUS EQU 401h + +;----------------------------------------------------------------------------- +; TXT register space definitiions +; +TXT_PRIVATE_BASE EQU 0FED20000h +TXT_PUBLIC_BASE EQU 0FED30000h +TXT_REGISTER_SPACE_LENGTH EQU 070000h + +TXT_STS EQU 0000h + TXT_STS_SENTER_DONE_MASK EQU BIT0 + TXT_STS_SEXIT_DONE_MASK EQU BIT1 + TXT_STS_MEM_UNLOCK_STS_MASK EQU BIT4 + TXT_STS_NODMAEN_MASK EQU BIT5 + TXT_STS_MEMCONFIGLOCK_STS_MASK EQU BIT6 + TXT_STS_PRIVATEOPEN_STS_MASK EQU BIT7 + TXT_STS_BLOCKMAP_STS_MASK EQU BIT8 + TXT_STS_NODMACACHE_STS_MASK EQU BIT9 + TXT_STS_NODMATABLEPROTECT_STS_MASK EQU BIT10 + TXT_ESTS EQU 0008h + TXT_WAKE_ERROR_STS EQU BIT6 + +TXT_THREADS_EXIST EQU 0010h +TXT_THREADS_JOIN EQU 0020h +TXT_CRASH EQU 0030h +TXT_CMD_SYS_RESET EQU 0038h +TXT_CMD_OPEN_PRIVATE EQU 0040h +TXT_CMD_CLOSE_PRIVATE EQU 0048h +TXT_POISON EQU 00B0h +TXT_VER_DID EQU 0110h +TXT_VER_EID EQU 0118h +TXT_VER_MIF EQU 0200h +TXT_CMD_LOCK_MEM_CONFIG EQU 0210h +TXT_CMD_UNLOCK_MEM_CONFIG EQU 0218h +TXT_CMD_UNLOCK_MEMORY EQU 0220h +TXT_CMD_NODMA_EN EQU 0230h +TXT_CMD_NODMA_DIS EQU 0238h +TXT_SINIT_BASE EQU 0270h +TXT_SINIT_SIZE EQU 0278h +TXT_SINIT_SIZE2 EQU 027Ch +TXT_SVMM_JOIN EQU 0290h +TXT_SVMM_JOIN2 EQU 0294h +TXT_HEAP_BASE EQU 0300h +TXT_HEAP_SIZE EQU 0308h +TXT_MSEG_BASE EQU 0310h +TXT_MSEG_SIZE EQU 0318h +TXT_SCRATCHPAD EQU 0320h +TXT_SCRATCHPAD2 EQU 0324h +TXT_SCRATCHPAD3 EQU 0328h +TXT_SCRATCHPAD4 EQU 032Ch +TXT_DPR EQU 0330h +TXT_CMD_OPEN_LOCALITY1 EQU 0380h +TXT_CMD_CLOSE_LOCALITY1 EQU 0388h +TXT_CMD_OPEN_LOCALITY3 EQU 03a0h +TXT_CMD_CLOSE_LOCALITY3 EQU 03a8h +TXT_PUBLIC_KEY EQU 0400h +TXT_TGFX_CMD EQU 0504h +TXT_TGA_BASE EQU 0510h +TXT_TGR_BASE EQU 0518h +TXT_TGTT_BASE EQU 0520h +TXT_TMSAC EQU 0540h + TGTT_128MB EQU BIT0 + TGTT_256MB EQU BIT1 + TGTT_512MB EQU BIT1+BIT0 +TXT_VER_FTIF EQU 0800h +TXT_PCH_DIDVID EQU 0810h +TXT_CMD_SECRETS EQU 08E0h +TXT_CMD_NO_SECRETS EQU 08E8h +TXT_E2STS EQU 08F0h + TXT_BLOCK_MEM_STS EQU BIT2 + TXT_SECRETS_STS EQU BIT1 + TXT_SLP_ENTRY_ERROR_STS EQU BIT0 + +MCU_MAX_SIZE EQU 10000h ; 64KB max size per MCU +MCU_SLOT_SZ_BITS EQU 11 ; 2KB MCU slot size +MCU_SLOT_SZ EQU 1 SHL MCU_SLOT_SZ_BITS + +;----------------------------------------------------------------------------- +; +; MCU Constants +; +MCU_HEADER_VER EQU 1 +MCU_LOADER_REV EQU 1 +; +; ProcessorMSR Equates +; +PLAT_ID_MSR EQU 17h ; Platform ID +MCU_LOAD_MSR EQU 79h ; Trigger to load MCU +MCU_REV_MSR EQU 8Bh ; MCU Revision register +; +PLAT_ID_BIT EQU 50 ; Bits 52:50 has the Platform ID +PLAT_ID_BITMASK EQU 07h ; Bits 52:50 has the Platform ID + +EFI_MSR_IA32_THERM_INTERRUPT EQU 019Bh +; +; Microcode Update (MCU) Header +; +MCU STRUCT + headerVer DD ? ; MCU Header Version ( = 00000001h ) + revision DD ? ; MCU Revision + date DD ? ; MCU Date + signature DD ? ; MCU Processor Signature + checksum DD ? ; MCU Main checksum + loaderRev DD ? ; MCU Loader Revision + procFlags DD ? ; MCU Processor Flags (Platform ID) + dataSize DD ? ; MCU Data Size + totalSize DD ? ; MCU Total Size + reserved DD 3 dup(?) +MCU ENDS +; +; Extended Signature Table (EST) +; +EST STRUCT + count DD ? ; EST Count + checksum DD ? ; EST Checksum + reserved DD 3 dup(?) +EST ENDS +; +; Processor Signature Structure (PSS) +; +PSS STRUCT + signature DD ? ; PSS Processor Signature + procFlags DD ? ; PSS Processor Flags (Platform ID) + checksum DD ? ; PSS Checksum +PSS ENDS + +;---------------------------------------------------------------------------- +; APIC definitions +; +IA32_APIC_BASE EQU 001Bh ; APIC base MSR + BASE_ADDR_MASK EQU 0FFFFF000h + EFI_MSR_EXT_XAPIC_LVT_THERM EQU 0833h +APIC_ID EQU 20h + APIC_ID_SHIFT EQU 24 +ICR_LOW EQU 300h +ICR_HIGH EQU 310h +SPURIOUS_VECTOR_1 EQU 0F0h +LOCAL_APIC_THERMAL_DEF EQU 330h + B_INTERRUPT_MASK EQU (1 SHL 16) + B_DELIVERY_MODE EQU (07h SHL 8) + V_MODE_SMI EQU (02h SHL 8) + B_VECTOR EQU (0FFh SHL 0) + + +;----------------------------------------------------------------------------- +; MTRRs +; +IA32_MTRR_CAP EQU 0FEh +IA32_MTRR_PHYSBASE0 EQU 200h +IA32_MTRR_PHYSMASK0 EQU 201h +IA32_MTRR_PHYSBASE1 EQU 202h +IA32_MTRR_PHYSMASK1 EQU 203h +IA32_MTRR_PHYSBASE2 EQU 204h +IA32_MTRR_PHYSMASK2 EQU 205h +IA32_MTRR_PHYSBASE3 EQU 206h +IA32_MTRR_PHYSMASK3 EQU 207h +IA32_MTRR_PHYSBASE4 EQU 208h +IA32_MTRR_PHYSMASK4 EQU 209h +IA32_MTRR_PHYSBASE5 EQU 20Ah +IA32_MTRR_PHYSMASK5 EQU 20Bh +IA32_MTRR_PHYSBASE6 EQU 20Ch +IA32_MTRR_PHYSMASK6 EQU 20Dh +IA32_MTRR_PHYSBASE7 EQU 20Eh +IA32_MTRR_PHYSMASK7 EQU 20Fh +IA32_MTRR_PHYSBASE8 EQU 210h +IA32_MTRR_PHYSMASK8 EQU 211h +IA32_MTRR_PHYSBASE9 EQU 212h +IA32_MTRR_PHYSMASK9 EQU 213h +IA32_MTRR_FIX64K_00000 EQU 250h +IA32_MTRR_FIX16K_80000 EQU 258h +IA32_MTRR_FIX16K_A0000 EQU 259h +IA32_MTRR_FIX4K_C0000 EQU 268h +IA32_MTRR_FIX4K_C8000 EQU 269h +IA32_MTRR_FIX4K_D0000 EQU 26Ah +IA32_MTRR_FIX4K_D8000 EQU 26Bh +IA32_MTRR_FIX4K_E0000 EQU 26Ch +IA32_MTRR_FIX4K_E8000 EQU 26Dh +IA32_MTRR_FIX4K_F0000 EQU 26Eh +IA32_MTRR_FIX4K_F8000 EQU 26Fh +IA32_CR_PAT EQU 277h +IA32_MTRR_DEF_TYPE EQU 2FFh +NO_EVICT_MODE EQU 2E0h + +; +; Only low order bits are assumed +; +MTRR_MASK EQU 0FFFFF000h + +MTRR_ENABLE EQU (1 SHL 11) +MTRR_FIXED_ENABLE EQU (1 SHL 10) +MTRR_VALID EQU (1 SHL 11) +UC EQU 00h +WB EQU 06h + +MTRR_VCNT EQU 8 + +;----------------------------------------------------------------------------- +; +; CPU generic definition +; +IA32_CPUID_SMX_B EQU 6 + +;----------------------------------------------------------------------------- +; +; AP communication area +; + +MCU_BASE_ADDR EQU TXT_SINIT_SIZE +BIOACM_ADDR EQU TXT_SINIT_SIZE2 +APINIT_ADDR EQU TXT_SVMM_JOIN +SEMAPHORE EQU TXT_SVMM_JOIN2 + +IA32_MISC_ENABLE_MSR EQU 1A0h +IA32_EFER_MSR EQU 0C0000080h +LME EQU BIT8 + +IFNDEF MKF_TXT_RLP_INIT +MKF_TXT_RLP_INIT EQU 01h +ENDIF |