init. 1AQQW051HEADmaster

6 files changed, 1813 insertions, 0 deletions

diff --git a/ReferenceCode/ME/Library/MeKernel/include/CoreBiosMsg.h b/ReferenceCode/ME/Library/MeKernel/include/CoreBiosMsg.h
new file mode 100644
index 0000000..bda1bc4
--- /dev/null
+++ b/ReferenceCode/ME/Library/MeKernel/include/CoreBiosMsg.h
@@ -0,0 +1,625 @@
+/** @file
+  Core BIOS Messages
+
+@copyright
+  Copyright (c) 2008 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef CORE_BIOS_MSG_H
+#define CORE_BIOS_MSG_H
+
+#include "MkhiMsgs.h"
+
+#pragma pack(1)
+
+#define CBM_RESET_REQ_CMD         0x0B
+#define CBM_RESET_REQ_CMD_ACK     0x8B
+#define CBM_END_OF_POST_CMD       0x0C
+#define CBM_END_OF_POST_CMD_ACK   0x8C
+#define GEN_SET_DEBUG_MEMORY_CMD  0x11
+
+//
+// HECI Client Address - Core Messages
+//    Core messages to coordinate memory initialization and UMA allocation with ME
+//    as well as to inform ME of the end of POST event
+//
+#define HECI_CLIENT_CORE_MSG_DISPATCHER 0x07
+#define HOST_FIXED_ADDRESS              0x00
+
+typedef union _HECI_MESSAGE_HEADER {
+  UINT32  Data;
+  struct {
+    UINT32  MeAddress : 8;
+    UINT32  HostAddress : 8;
+    UINT32  Length : 9;
+    UINT32  Reserved : 6;
+    UINT32  MessageComplete : 1;
+  } Fields;
+} HECI_MESSAGE_HEADER;
+
+///
+/// Reset request message
+///
+typedef struct _CBM_RESET_REQ_DATA {
+  UINT8 RequestOrigin;
+  UINT8 ResetType;
+} CBM_RESET_REQ_DATA;
+
+typedef struct _CBM_RESET_REQ {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  CBM_RESET_REQ_DATA  Data;
+} CBM_RESET_REQ;
+
+typedef struct _MKHI_CBM_RESET_REQ {
+  HECI_MESSAGE_HEADER Header;
+  CBM_RESET_REQ       Msg;
+} MKHI_CBM_RESET_REQ;
+
+///
+/// Reset request ack message
+///
+typedef struct _CBM_RESET_ACK {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+} CBM_RESET_ACK;
+
+typedef struct _MKHI_CBM_RESET_ACK {
+  HECI_MESSAGE_HEADER Header;
+  CBM_RESET_ACK       Msg;
+} MKHI_CBM_RESET_ACK;
+
+//
+// ASF Watch Dog Timer
+//
+#define ASF_MANAGEMENT_CONTROL    0x02
+#define ASF_SUB_COMMAND_START_WDT 0x13
+#define ASF_SUB_COMMAND_STOP_WDT  0x14
+
+///
+/// ASF Start Watch Dog
+///
+typedef struct _ASF_START_WDT {
+  UINT8 Command;
+  UINT8 ByteCount;
+  UINT8 SubCommand;
+  UINT8 VersionNumber;
+  UINT8 TimeoutLow;
+  UINT8 TimeoutHigh;
+  UINT8 EventSensorType;
+  UINT8 EventType;
+  UINT8 EventOffset;
+  UINT8 EventSourceType;
+  UINT8 EventSeverity;
+  UINT8 SensorDevice;
+  UINT8 SensorNumber;
+  UINT8 Entity;
+  UINT8 EntityInstance;
+  UINT8 EventData[5];
+} ASF_START_WDT;
+
+#define ASF_START_WDT_LENGTH  0x14
+
+///
+/// ASF Stop Watch Dog
+///
+typedef struct _ASF_STOP_WDT {
+  UINT8 Command;
+  UINT8 ByteCount;
+  UINT8 SubCommand;
+  UINT8 VersionNumber;
+} ASF_STOP_WDT;
+
+#define ASF_STOP_WDT_LENGTH 0x04
+
+//
+// HECI Header Definitions for Core BIOS Messages
+//
+#define CBM_END_OF_POST_HECI_HDR          0x80080001
+#define CBM_END_OF_POST_RESPONSE_HECI_HDR 0x80010001
+#define CBM_RESET_REQUEST_HECI_HDR        0x80030001
+#define CBM_RESET_RESPONSE_HECI_HDR       0x80020001
+
+//
+// Enumerations used in Core BIOS Messages
+//
+// End Of Post Codes.
+//
+#define CBM_EOP_EXITING_G3  0x01
+#define CBM_EOP_RESERVED    0x02
+#define CBM_EOP_EXITING_S3  0x03
+#define CBM_EOP_EXITING_S4  0x04
+#define CBM_EOP_EXITING_S5  0x05
+
+//
+// Reset Request Origin Codes.
+//
+#define CBM_RR_REQ_ORIGIN_BIOS_MEMORY_INIT  0x01
+#define CBM_RR_REQ_ORIGIN_BIOS_POST         0x02
+#define CBM_RR_REQ_ORIGIN_MEBX              0x03
+
+//
+// Reset Type Codes.
+//
+#define CBM_HRR_GLOBAL_RESET  0x01
+
+//
+// Reset Response Codes.
+//
+#define CBM_HRR_RES_REQ_NOT_ACCEPTED  0x01
+
+//
+// definitions for ICC MEI Messages
+//
+#define IBEX_PEAK_PLATFORM    0x00010000
+#define COUGAR_POINT_PLATFORM 0x00020000
+#define LYNX_POINT_PLATFORM   0x00030000
+
+typedef enum {
+  ICC_STATUS_SUCCESS                        = 0,
+  ICC_STATUS_SUCCESS_WAITING_FOR_RESET,
+  ICC_STATUS_INCORRECT_API_VERSION,
+  ICC_STATUS_INVALID_FUNCTION,
+  ICC_STATUS_INVALID_BUFFER_LENGTH,
+  ICC_STATUS_INVALID_PARAMETERS,
+  ICC_STATUS_FLASH_WEAR_OUT_VIOLATION,
+  ICC_STATUS_CLOCK_REQ_ENTRY_VIOLATION,
+  ICC_STATUS_STATIC_REGISTER_MASK_VIOLATION,
+  ICC_STATUS_DYNAMIC_REGISTER_MASK_VIOLATION,
+  ICC_STATUS_IMMEDIATE_REQUIRES_POWER_CYCLE,
+  ICC_STATUS_ILLEGAL_RECORD_ID,
+  ICC_STATUS_ENABLED_CLOCK_MASK_VIOLATION,
+  ICC_STATUS_INVALID                        = 0xFFFFFFFF
+} ICC_MEI_CMD_STATUS;
+
+typedef union _ICC_CLOCK_ENABLES_CONTROL_MASK {
+  UINT32  Dword;
+  struct {
+    UINT32  Flex0 : 1;
+    UINT32  Flex1 : 1;
+    UINT32  Flex2 : 1;
+    UINT32  Flex3 : 1;
+    UINT32  Reserved1 : 3;
+    UINT32  PCI_Clock0 : 1;
+    UINT32  PCI_Clock1 : 1;
+    UINT32  PCI_Clock2 : 1;
+    UINT32  PCI_Clock3 : 1;
+    UINT32  PCI_Clock4 : 1;
+    UINT32  Reserved2 : 4;
+    UINT32  SRC0 : 1;
+    UINT32  SRC1 : 1;
+    UINT32  SRC2 : 1;
+    UINT32  SRC3 : 1;
+    UINT32  SRC4 : 1;
+    UINT32  SRC5 : 1;
+    UINT32  SRC6 : 1;
+    UINT32  SRC7 : 1;
+    UINT32  CSI_SRC8 : 1;
+    UINT32  CSI_DP : 1;
+    UINT32  PEG_A : 1;
+    UINT32  PEG_B : 1;
+    UINT32  DMI : 1;
+    UINT32  Reserved3 : 3;
+  } Fields;
+} ICC_CLOCK_ENABLES_CONTROL_MASK;
+
+typedef enum {
+  LOCK_ICC_REGISTERS                        = 0x2,
+  SET_CLOCK_ENABLES                         = 0x3,
+  GET_ICC_PROFILE                           = 0x4,
+  SET_ICC_PROFILE                           = 0x5,
+  GET_ICC_CLOCKS_CAPABILITIES               = 0x6,
+  GET_OEM_CLOCK_RANGE_DEFINITION_RECORD     = 0x7,
+  GET_ICC_RECORD                            = 0x8,
+  READ_ICC_REGISTER                         = 0x9,
+  WRITE_ICC_REGISTER                        = 0xa,
+  WRITE_UOB_RECORD                          = 0xb,
+  READ_MPHY_SETTINGS                        = 0xe,
+  WRITE_MPHY_SETTINGS                       = 0xf
+} ICC_MEI_COMMAND_ID;
+
+typedef struct {
+  UINT32              ApiVersion;
+  ICC_MEI_COMMAND_ID  IccCommand;
+  ICC_MEI_CMD_STATUS  IccResponse;
+  UINT32              BufferLength;
+  UINT32              Reserved;
+} ICC_HEADER;
+
+typedef struct {
+  ICC_HEADER  Header;
+} ICC_GET_PROFILE_MESSAGE;
+
+typedef struct {
+  ICC_HEADER  Header;
+  UINT8       SupportedProfilesNumber;
+  UINT8       IccProfileSoftStrap;
+  UINT8       IccProfileIndex;
+  UINT8       Padding;
+} ICC_GET_PROFILE_RESPONSE;
+
+typedef union {
+  ICC_GET_PROFILE_MESSAGE   message;
+  ICC_GET_PROFILE_RESPONSE  response;
+} ICC_GET_PROFILE_BUFFER;
+
+typedef struct {
+  ICC_HEADER  Header;
+  UINT8       ProfileBIOS;
+  UINT8       PaddingA;
+  UINT16      PaddingB;
+} ICC_SET_PROFILE_MESSAGE;
+
+typedef struct {
+  ICC_HEADER  Header;
+} ICC_SET_PROFILE_RESPONSE;
+
+typedef union {
+  ICC_SET_PROFILE_MESSAGE   message;
+  ICC_SET_PROFILE_RESPONSE  response;
+} ICC_SET_PROFILE_BUFFER;
+
+typedef struct {
+  ICC_HEADER  Header;
+  UINT32      ClockEnables;
+  UINT32      ClockEnablesMask;
+  UINT32      Params;
+} ICC_SET_CLK_ENABLES_MESSAGE;
+
+typedef struct {
+  ICC_HEADER  Header;
+} ICC_SET_CLK_ENABLES_RESPONSE;
+
+typedef union {
+  ICC_SET_CLK_ENABLES_MESSAGE   message;
+  ICC_SET_CLK_ENABLES_RESPONSE  response;
+} ICC_SET_CLK_ENABLES_BUFFER;
+
+typedef struct {
+  ICC_HEADER  Header;
+} ICC_GET_CLK_CAPABILITIES_MESSAGE;
+
+typedef struct {
+  ICC_HEADER  Header;
+  UINT32      VersionNumber;
+  UINT8       IccHwSku;
+  UINT8       Reserved;
+  UINT16      MaxSusramRecordSize;
+  UINT64      IccSkuEnforcementTable;
+  UINT32      IccBootStatusReport;
+} ICC_GET_CLK_CAPABILITIES_RESPONSE;
+
+typedef union {
+  ICC_GET_CLK_CAPABILITIES_MESSAGE  message;
+  ICC_GET_CLK_CAPABILITIES_RESPONSE response;
+} ICC_GET_CLK_CAPABILITIES_BUFFER;
+
+#define ICC_RESPONSE_MODE_WAIT    0
+#define ICC_RESPONSE_MODE_SKIP    1
+#define ICC_LOCK_ACCESS_MODE_SET  0
+#define ICC_LOCK_ACCESS_MODE_GET  1
+#define ICC_LOCK_MASK_COUNT       255
+#define WRITE_ICC_REG_BUNDLE_COUNT  1           ///< 1 bundle for 1 DWORD register write
+#define ADDRESS_MASK_FIXED_DATA     0x00017F01  ///< Target ID = 7F (Aux), MWM = 1(16 bits)
+#define WRITE_ICC_RECORD_FLAGS      0x00012010  ///< 16 byte record length, No param section, valid bit
+
+typedef struct _ICC_REG_BUNDLES
+{
+  UINT32 BundlesCnt :16; ///< Bundles Count - number of Address Mask entries
+  UINT32 AU         :1;  ///< AU=1 -> All regisaters are Unlocked
+  UINT32 Reserved   :15;
+} ICC_REG_BUNDLES;
+
+typedef struct {
+  ICC_REG_BUNDLES RegBundles;
+  UINT32          RegMask[ICC_LOCK_MASK_COUNT];
+} ICC_LOCK_REGS_INFO;
+
+typedef struct {
+  ICC_HEADER          Header;
+  UINT8               AccessMode;
+  UINT8               Parameters;
+  UINT8               Reserved[2];
+  ICC_LOCK_REGS_INFO  LockRegInfo;
+} ICC_LOCK_REGISTERS_MESSAGE;
+
+typedef struct {
+  ICC_HEADER          Header;
+  UINT32              Reserved;
+  ICC_LOCK_REGS_INFO  LockRegInfo;
+} ICC_LOCK_REGISTERS_RESPONSE;
+
+typedef union {
+  ICC_LOCK_REGISTERS_MESSAGE  message;
+  ICC_LOCK_REGISTERS_RESPONSE response;
+} ICC_LOCK_REGISTERS_BUFFER;
+
+typedef union _ICC_ADDRESS_MASK
+{
+  UINT32 AddressMaskData;
+  struct
+  {
+    UINT32 MaskWidthModifier :2;
+    UINT32 Offset            :6;
+    UINT32 TargetId          :7;
+    UINT32 Reserved          :1;
+  }Fields;
+} ICC_ADDRESS_MASK;
+
+typedef struct _ICC_DWORD_RECORD
+{
+  UINT32            RecordFlags;
+  ICC_REG_BUNDLES   BundleCount;
+  ICC_ADDRESS_MASK  AddressMask;
+  UINT32            RegValue;
+} ICC_RECORD_DWORD;
+
+typedef struct {
+  ICC_HEADER        Header;
+  UINT16            Reserved;
+  UINT8             Params;
+  UINT8             Reserved1;
+  ICC_RECORD_DWORD  RecordDword;
+} ICC_WRITE_ICC_REG_DWORD_MESSAGE;
+
+typedef struct {
+  ICC_HEADER  Header;
+  UINT16      BytesProcessed;
+  UINT16      Reserved;
+} ICC_WRITE_ICC_REG_DWORD_RESPONSE;
+
+typedef union {
+  ICC_WRITE_ICC_REG_DWORD_MESSAGE   message;
+  ICC_WRITE_ICC_REG_DWORD_RESPONSE  response;
+} ICC_WRITE_ICC_REG_BUFFER;
+
+//
+// SPI MEI Messages
+//
+#define HMRFPO_ENABLE_CMD_ID      0x01
+#define HMRFPO_LOCK_CMD_ID        0x02
+#define HMRFPO_GET_STATUS_CMD_ID  0x03
+
+typedef enum {
+  HMRFPO_ENABLE_SUCCESS                     = 0,
+  HMRFPO_ENABLE_LOCKED,
+  HMRFPO_NVAR_FAILURE,
+  HMRFOP_ATP_POLICY,
+  HMRFPO_ENABLE_UNKNOWN_FAILURE
+} HMRFPO_ENABLE_STATUS;
+
+typedef struct _MKHI_HMRFPO_ENABLE {
+  MKHI_MESSAGE_HEADER MkhiHeader;
+  UINT64              Nonce;
+} MKHI_HMRFPO_ENABLE;
+
+typedef struct _HMRFPO_ENABLE {
+  HECI_MESSAGE_HEADER Header;
+  MKHI_HMRFPO_ENABLE  Msg;
+} HMRFPO_ENABLE;
+
+typedef struct _MKHI_HMRFPO_ENABLE_RESPONSE {
+  MKHI_MESSAGE_HEADER MkhiHeader;
+  UINT32              FactoryDefaultBase;
+  UINT32              FactoryDefaultLimit;
+  UINT8               Status;
+  UINT8               Rsvd[3];
+} MKHI_HMRFPO_ENABLE_RESPONSE;
+
+typedef struct _HMRFPO_ENABLE_RESPONSE {
+  HECI_MESSAGE_HEADER         Header;
+  MKHI_HMRFPO_ENABLE_RESPONSE Msg;
+} HMRFPO_ENABLE_RESPONSE;
+
+typedef enum {
+  HMRFPO_LOCK_SUCCESS                       = 0,
+  HMRFPO_LOCK_FAILURE
+} HMRFPO_LOCK_STATUS;
+
+typedef struct _MKHI_HMRFPO_LOCK {
+  MKHI_MESSAGE_HEADER MkhiHeader;
+} MKHI_HMRFPO_LOCK;
+
+typedef struct _HMRFPO_LOCK {
+  HECI_MESSAGE_HEADER Header;
+  MKHI_HMRFPO_LOCK    Msg;
+} HMRFPO_LOCK;
+
+typedef struct _MKHI_HMRFPO_LOCK_RESPONSE {
+  MKHI_MESSAGE_HEADER MkhiHeader;
+  UINT64              Nonce;
+  UINT32              FactoryDefaultBase;
+  UINT32              FactoryDefaultLimit;
+  UINT8               Status;
+  UINT8               Reserved[3];
+} MKHI_HMRFPO_LOCK_RESPONSE;
+
+typedef struct _HMRFPO_LOCK_RESPONSE {
+  HECI_MESSAGE_HEADER       Header;
+  MKHI_HMRFPO_LOCK_RESPONSE Data;
+} HMRFPO_LOCK_RESPONSE;
+
+typedef struct _MKHI_HMRFPO_GET_STATUS {
+  MKHI_MESSAGE_HEADER MkhiHeader;
+} MKHI_HMRFPO_GET_STATUS;
+
+typedef struct _HMRFPO_GET_STATUS {
+  HECI_MESSAGE_HEADER     Header;
+  MKHI_HMRFPO_GET_STATUS  Msg;
+} HMRFPO_GET_STATUS;
+
+typedef struct _MKHI_HMRFPO_GET_STATUS_RESPONSE {
+  MKHI_MESSAGE_HEADER MkhiHeader;
+  UINT8               Status;
+  UINT8               Reserved[3];
+} MKHI_HMRFPO_GET_STATUS_RESPONSE;
+
+typedef struct _HMRFPO_GET_STATUS_RESPONSE {
+  HECI_MESSAGE_HEADER             Header;
+  MKHI_HMRFPO_GET_STATUS_RESPONSE Data;
+} HMRFPO_GET_STATUS_RESPONSE;
+
+#define HMRFPO_LOCKED   1
+#define HMRFPO_ENABLED  2
+
+//
+// ME State Control
+//
+#define EFI_ME_STATE_STALL_1_SECOND 1000000
+#define EFI_ME_STATE_MAX_TIMEOUT    20
+//
+// KVM support
+//
+#define EFI_KVM_MESSAGE_COMMAND 0x08
+#define EFI_KVM_BYTE_COUNT      0x06
+#define EFI_KVM_QUERY_REQUES    0x01
+#define EFI_KVM_QUERY_RESPONSE  0x02
+#define EFI_KVM_VERSION         0x10
+
+#define EFI_KVM_STALL_1_SECOND  1000000   ///< Stall 1 second
+#define EFI_KVM_MAX_WAIT_TIME   (60 * 8)  ///< 8 Mins
+typedef enum {
+  QUERY_REQUEST                             = 0,
+  CANCEL_REQUEST
+} QUERY_TYPE;
+
+typedef struct _AMT_QUERY_KVM_REQUEST {
+  UINT8   Command;
+  UINT8   ByteCount;
+  UINT8   SubCommand;
+  UINT8   VersionNumber;
+  UINT32  QueryType;
+} AMT_QUERY_KVM_REQUEST;
+
+typedef enum {
+  KVM_SESSION_ESTABLISHED                   = 1,
+  KVM_SESSION_CANCELLED
+} RESPONSE_CODE;
+
+typedef struct _AMT_QUERY_KVM_RESPONSE {
+  UINT8   Command;
+  UINT8   ByteCount;
+  UINT8   SubCommand;
+  UINT8   VersionNumber;
+  UINT32  ResponseCode;
+} AMT_QUERY_KVM_RESPONSE;
+
+///
+/// ME Memory Debug support
+///
+typedef struct _SET_DEBUG_MEMORY_DATA {
+  UINT32  BiosDebugMemoryAddress;
+  UINT32  BiosDebugMemorySize;
+  UINT32  MeVeDebugMemoryAddress;
+  UINT32  MeVeDebugMemorySize;
+} SET_DEBUG_MEMORY_DATA;
+
+typedef struct _GEN_SET_DEBUG_MEMORY {
+  MKHI_MESSAGE_HEADER   MKHIHeader;
+  SET_DEBUG_MEMORY_DATA Data;
+} GEN_SET_DEBUG_MEMORY;
+
+typedef struct _GEN_SET_DEBUG_MEMORY_ACK {
+  MKHI_MESSAGE_HEADER Header;
+} GEN_SET_DEBUG_MEMORY_ACK;
+
+//
+// BIOS MDES messaging
+//
+#define MDES_BIOS_MSG_LOG_REQ_CMD     0x0B
+#define MDES_BIOS_MSG_GET_CONFIG_CMD  0x0C
+
+typedef struct _MDES_ATTR {
+  UINT16  Severity : 2;
+  UINT16  PayLoadType : 6;
+  UINT16  Reserved : 8;
+} MDES_ATTR;
+
+typedef struct _BIOS_ATTR {
+  UINT16  CallerIdData : 1;
+  UINT16  ExtendedDataHeader : 1;
+  UINT16  Reserved : 14;
+} BIOS_ATTR;
+
+typedef struct {
+  UINT16    HeaderSize;
+  UINT16    Size;
+  EFI_GUID  Type;
+} MDES_EXTENDED_DATA_HEADER;
+
+#define SIZE_OF_MDES_EXTENDED_DATA  (2048 - \
+                                      ( \
+                                      16 + sizeof (MDES_ATTR) + sizeof (BIOS_ATTR) + sizeof (EFI_GUID) + sizeof (MDES_EXTENDED_DATA_HEADER) + \
+                                    sizeof (MKHI_MESSAGE_HEADER) \
+                                ) \
+          )
+
+typedef struct _CBM_BIOS_MDES_MSG_DATA {
+  MDES_ATTR                 MdesAttr;
+  BIOS_ATTR                 BiosAttr;
+  UINT32                    Serial;
+  UINT32                    StatusType;
+  UINT32                    StatusCode;
+  UINT32                    Instance;
+  EFI_GUID                  CallerId;
+  MDES_EXTENDED_DATA_HEADER ExtendedDataHeader;
+  UINT8                     ExtendedData[SIZE_OF_MDES_EXTENDED_DATA];
+} CBM_BIOS_MDES_MSG_DATA;
+
+typedef struct _CBM_BIOS_MDES_MSG_REQ {
+  MKHI_MESSAGE_HEADER     MKHIHeader;
+  CBM_BIOS_MDES_MSG_DATA  Data;
+} CBM_BIOS_MDES_MSG_REQ;
+
+typedef struct _MKHI_CBM_BIOS_MDES_MSG_REQ {
+  HECI_MESSAGE_HEADER   Header;
+  CBM_BIOS_MDES_MSG_REQ Msg;
+} MKHI_CBM_BIOS_MDES_MSG_REQ;
+
+typedef struct _MKHI_CBM_BIOS_MDES_MSG_GET_CONFIG_REQ {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+} MKHI_CBM_BIOS_MDES_MSG_GET_CONFIG_REQ;
+
+typedef union _MDES_BIOS_FLAGS {
+  volatile UINT32 ul;
+  struct {
+    UINT32  MdesEnabled : 1;            ///< High level indication if MDES is enabled
+    UINT32  MdesLogPaused : 1;          ///< A caller paused MDES logging as part of the log retrieval process
+    UINT32  LanInterfaceEnabled : 1;    ///< The user configuration has enabled the LAN debug interface
+    UINT32  SmbusInterfaceEnabled : 1;  ///< The user configuration has enabled the SMBus debug interface
+    UINT32  PramLogEnabled : 1;         ///< The user configuration has enabled the PRAM debug log
+    UINT32  FlashLogEnabled : 1;        ///< The user configuration has enabled the flash error log
+    UINT32  MdesBlockingModeEn : 1;     ///< Set to 0 when operating in buffered mode, set to 1 when MDES blocks the caller until the event is dispatched.
+    UINT32  Reserved7 : 2;
+    UINT32  SensitiveMsgEnabled : 1;    ///< Set to 1 to indicate Sensitive messages are enabled
+    UINT32  DescriptorUnlocked : 1;     ///< Set when FW reads all regions are unlocked.  Enables 'none' sensitivity messages.
+    UINT32  MdesPolicyEnabled : 1;      ///< Set to 1 to indicate MDES is enabled due to BIOS sending the enable message (on current or previous boot)
+    UINT32  MdesEnableRcvdFromBios : 1; ///< BIOS has sent the MDES policy to 'enabled' via a MKHI message on this current boot
+    UINT32  Reserved13 : 19;
+  } fl;
+} MDES_BIOS_FLAGS;
+
+typedef struct _CBM_BIOS_MDES_MSG_GET_CONFIG_DATA {
+  MDES_BIOS_FLAGS Flags;
+  UINT32          BiosEventFilters;
+} CBM_BIOS_MDES_MSG_GET_CONFIG_DATA;
+
+typedef struct _MKHI_CBM_BIOS_MDES_MSG_GET_CONFIG_ACK {
+  MKHI_MESSAGE_HEADER               Header;
+  CBM_BIOS_MDES_MSG_GET_CONFIG_DATA Data;
+} MKHI_CBM_BIOS_MDES_MSG_GET_CONFIG_ACK;
+
+#pragma pack()
+
+#endif
diff --git a/ReferenceCode/ME/Library/MeKernel/include/MeAccess.h b/ReferenceCode/ME/Library/MeKernel/include/MeAccess.h
new file mode 100644
index 0000000..6a7c16d
--- /dev/null
+++ b/ReferenceCode/ME/Library/MeKernel/include/MeAccess.h
@@ -0,0 +1,338 @@
+/** @file
+  Macros to simplify and abstract the interface to PCI configuration.
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _ME_ACCESS_H_
+#define _ME_ACCESS_H_
+
+#include "MeChipset.h"
+#include "PchAccess.h"
+
+///
+/// HECI PCI Access Macro
+///
+#define HeciPciRead32(Register) PciRead32 (PCI_LIB_ADDRESS (ME_BUS, ME_DEVICE_NUMBER, HECI_FUNCTION_NUMBER, Register))
+
+#define HeciPciWrite32(Register, Data) \
+  PciWrite32 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI_FUNCTION_NUMBER, \
+  Register), \
+  (UINT32) Data \
+  )
+
+#define HeciPciOr32(Register, Data) \
+  PciOr32 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI_FUNCTION_NUMBER, \
+  Register), \
+  (UINT32) Data \
+  )
+
+#define HeciPciAnd32(Register, Data) \
+  PciAnd32 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI_FUNCTION_NUMBER, \
+  Register), \
+  (UINT32) Data \
+  )
+
+#define HeciPciAndThenOr32(Register, AndData, OrData) \
+  PciAndThenOr32 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI_FUNCTION_NUMBER, \
+  Register), \
+  (UINT32) AndData, \
+  (UINT32) OrData \
+  )
+
+#define HeciPciRead16(Register) PciRead16 (PCI_LIB_ADDRESS (ME_BUS, ME_DEVICE_NUMBER, HECI_FUNCTION_NUMBER, Register))
+
+#define HeciPciWrite16(Register, Data) \
+  PciWrite16 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI_FUNCTION_NUMBER, \
+  Register), \
+  (UINT16) Data \
+  )
+
+#define HeciPciOr16(Register, Data) \
+  PciOr16 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI_FUNCTION_NUMBER, \
+  Register), \
+  (UINT16) Data \
+  )
+
+#define HeciPciAnd16(Register, Data) \
+  PciAnd16 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI_FUNCTION_NUMBER, \
+  Register), \
+  (UINT16) Data \
+  )
+
+#define HeciPciAndThenOr16(Register, AndData, OrData) \
+  PciAndThenOr16 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI_FUNCTION_NUMBER, \
+  Register), \
+  (UINT16) AndData, \
+  (UINT16) OrData \
+  )
+
+#define HeciPciRead8(Register)  PciRead8 (PCI_LIB_ADDRESS (ME_BUS, ME_DEVICE_NUMBER, HECI_FUNCTION_NUMBER, Register))
+
+#define HeciPciWrite8(Register, Data) \
+  PciWrite8 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI_FUNCTION_NUMBER, \
+  Register), \
+  (UINT8) Data \
+  )
+
+#define HeciPciOr8(Register, Data) \
+  PciOr8 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI_FUNCTION_NUMBER, \
+  Register), \
+  (UINT8) Data \
+  )
+
+#define HeciPciAnd8(Register, Data) \
+  PciAnd8 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI_FUNCTION_NUMBER, \
+  Register), \
+  (UINT8) Data \
+  )
+
+#define HeciPciAndThenOr8(Register, AndData, OrData) \
+  PciAndThenOr8 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI_FUNCTION_NUMBER, \
+  Register), \
+  (UINT8) AndData, \
+  (UINT8) OrData \
+  )
+
+///
+/// HECI2 PCI Access Macro
+///
+#define Heci2PciRead32(Register)  PciRead32 (PCI_LIB_ADDRESS (ME_BUS, ME_DEVICE_NUMBER, HECI2_FUNCTION_NUMBER, Register))
+
+#define Heci2PciWrite32(Register, Data) \
+  PciWrite32 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI2_FUNCTION_NUMBER, \
+  Register), \
+  (UINT32) Data \
+  )
+
+#define Heci2PciOr32(Register, Data) \
+  PciOr32 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI2_FUNCTION_NUMBER, \
+  Register), \
+  (UINT32) Data \
+  )
+
+#define Heci2PciAnd32(Register, Data) \
+  PciAnd32 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI2_FUNCTION_NUMBER, \
+  Register), \
+  (UINT32) Data \
+  )
+
+#define Heci2PciAndThenOr32(Register, AndData, OrData) \
+  PciAndThenOr32 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI2_FUNCTION_NUMBER, \
+  Register), \
+  (UINT32) AndData, \
+  (UINT32) OrData \
+  )
+
+#define Heci2PciRead16(Register)  PciRead16 (PCI_LIB_ADDRESS (ME_BUS, ME_DEVICE_NUMBER, HECI2_FUNCTION_NUMBER, Register))
+
+#define Heci2PciWrite16(Register, Data) \
+  PciWrite16 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI2_FUNCTION_NUMBER, \
+  Register), \
+  (UINT16) Data \
+  )
+
+#define Heci2PciOr16(Register, Data) \
+  PciOr16 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI2_FUNCTION_NUMBER, \
+  Register), \
+  (UINT16) Data \
+  )
+
+#define Heci2PciAnd16(Register, Data) \
+  PciAnd16 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI2_FUNCTION_NUMBER, \
+  Register), \
+  (UINT16) Data \
+  )
+
+#define Heci2PciAndThenOr16(Register, AndData, OrData) \
+  PciAndThenOr16 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI2_FUNCTION_NUMBER, \
+  Register), \
+  (UINT16) AndData, \
+  (UINT16) OrData \
+  )
+
+#define Heci2PciRead8(Register) PciRead8 (PCI_LIB_ADDRESS (ME_BUS, ME_DEVICE_NUMBER, HECI2_FUNCTION_NUMBER, Register))
+
+#define Heci2PciWrite8(Register, Data) \
+  PciWrite8 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI2_FUNCTION_NUMBER, \
+  Register), \
+  (UINT8) Data \
+  )
+
+#define Heci2PciOr8(Register, Data) \
+  PciOr8 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI2_FUNCTION_NUMBER, \
+  Register), \
+  (UINT8) Data \
+  )
+
+#define Heci2PciAnd8(Register, Data) \
+  PciAnd8 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI2_FUNCTION_NUMBER, \
+  Register), \
+  (UINT8) Data \
+  )
+
+#define Heci2PciAndThenOr8(Register, AndData, OrData) \
+  PciAndThenOr8 ( \
+  PCI_LIB_ADDRESS (ME_BUS, \
+  ME_DEVICE_NUMBER, \
+  HECI2_FUNCTION_NUMBER, \
+  Register), \
+  (UINT8) AndData, \
+  (UINT8) OrData \
+  )
+
+#ifndef MmPciAddress
+#define MmPciAddress(Segment, Bus, Device, Function, Register) \
+    ( \
+      (UINTN) (PciRead32 (PCI_LIB_ADDRESS (0,0,0,0x60)) & 0xFC000000) + \
+      (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \
+      (Function << 12) + (UINTN) (Register) \
+    )
+#endif
+///
+/// ME Macro Setting
+///
+#define McD0PciCfg64(Register)              MmPci64 (0, SA_MC_BUS, 0, 0, Register)
+#define McD0PciCfg32And(Register, AndData)  PciAnd32 (PCI_LIB_ADDRESS (SA_MC_BUS, 0, 0, Register), (UINT32) AndData)
+#define McD0PciCfg16And(Register, AndData)  PciAnd16 (PCI_LIB_ADDRESS (SA_MC_BUS, 0, 0, Register), (UINT16) AndData)
+
+///
+///  MMIO access macros
+///
+#define MmioAddress(BaseAddr, Register) ((UINTN) BaseAddr + (UINTN) (Register))
+
+///
+/// 16 bit MMIO access
+///
+#define Mmio16Ptr(BaseAddr, Register) ((volatile UINT16 *) MmioAddress (BaseAddr, Register))
+
+#define Mmio16(BaseAddr, Register)    *Mmio16Ptr (BaseAddr, Register)
+
+#define Mmio16Or(BaseAddr, Register, OrData) \
+  Mmio16 (BaseAddr, Register) = (UINT16) \
+    (Mmio16 (BaseAddr, Register) | (UINT16) (OrData))
+
+#define Mmio16And(BaseAddr, Register, AndData) \
+  Mmio16 (BaseAddr, Register) = (UINT16) \
+    (Mmio16 (BaseAddr, Register) & (UINT16) (AndData))
+
+#define Mmio16AndThenOr(BaseAddr, Register, AndData, OrData) \
+  Mmio16 (BaseAddr, Register) = (UINT16) \
+    ((Mmio16 (BaseAddr, Register) & (UINT16) (AndData)) | (UINT16) (OrData))
+
+///
+/// 32 bit MMIO access
+///
+#define Mmio32Ptr(BaseAddr, Register) ((volatile UINT32 *) MmioAddress (BaseAddr, Register))
+
+#define Mmio32(BaseAddr, Register)    *Mmio32Ptr (BaseAddr, Register)
+
+#define Mmio32Or(BaseAddr, Register, OrData) \
+  Mmio32 (BaseAddr, Register) = (UINT32) \
+    (Mmio32 (BaseAddr, Register) | (UINT32) (OrData))
+
+#define Mmio32And(BaseAddr, Register, AndData) \
+  Mmio32 (BaseAddr, Register) = (UINT32) \
+    (Mmio32 (BaseAddr, Register) & (UINT32) (AndData))
+
+#define Mmio32AndThenOr(BaseAddr, Register, AndData, OrData) \
+  Mmio32 (BaseAddr, Register) = (UINT32) \
+    ((Mmio32 (BaseAddr, Register) & (UINT32) (AndData)) | (UINT32) (OrData))
+
+///
+/// Memory Controller PCI access macros
+///
+#define MCH_REGION_BASE               (McD0PciCfg64 (MC_MCHBAR_OFFSET) &~BIT0)
+#define McMmioAddress(Register)       ((UINTN) MCH_REGION_BASE + (UINTN) (Register))
+
+#define McMmio8Ptr(Register)          ((volatile UINT8 *) McMmioAddress (Register))
+#define McMmio8(Register)             *McMmio8Ptr (Register)
+#define McMmio8Or(Register, OrData)   (McMmio8 (Register) |= (UINT8) (OrData))
+#define McMmio8And(Register, AndData) (McMmio8 (Register) &= (UINT8) (AndData))
+#define McMmio8AndThenOr(Register, AndData, OrData) \
+    (McMmio8 (Register) = (McMmio8 (Register) & (UINT8) (AndData)) | (UINT8) (OrData))
+
+#endif
diff --git a/ReferenceCode/ME/Library/MeKernel/include/MeChipset.h b/ReferenceCode/ME/Library/MeKernel/include/MeChipset.h
new file mode 100644
index 0000000..f18ac61
--- /dev/null
+++ b/ReferenceCode/ME/Library/MeKernel/include/MeChipset.h
@@ -0,0 +1,196 @@
+/** @file
+  Chipset definition for ME Devices.
+
+  Conventions:
+
+  - Prefixes:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values of bits within the registers
+    Definitions beginning with "S_" are register sizes
+    Definitions beginning with "N_" are the bit position
+  - In general, ME registers are denoted by "_ME_" in register names
+  - Registers / bits that are different between ME generations are denoted by
+    "_ME_<generation_name>_" in register/bit names. e.g., "_ME_CPT_"
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+    at the end of the register/bit names
+  - Registers / bits of new devices introduced in a ME generation will be just named
+    as "_ME_" without <generation_name> inserted.
+
+@copyright
+  Copyright (c) 2011 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _ME_CHIPSET_H_
+#define _ME_CHIPSET_H_
+
+#include "MeChipsetLib.h"
+
+#define ME_BUS                0
+#define ME_DEVICE_NUMBER      22
+
+#define HECI_FUNCTION_NUMBER  0x00
+#define HECI2_FUNCTION_NUMBER 0x01
+#define IDER_FUNCTION_NUMBER  0x02
+#define SOL_FUNCTION_NUMBER   0x03
+
+#define IDER_BUS_NUMBER       ME_BUS
+#define IDER_DEVICE_NUMBER    ME_DEVICE_NUMBER
+#define SOL_BUS_NUMBER        ME_BUS
+#define SOL_DEVICE_NUMBER     ME_DEVICE_NUMBER
+#define HECI_DEV_FCN          ((ME_DEVICE_NUMBER) << 3 | (HECI_FUNCTION_NUMBER))
+#define HECI2_DEV_FCN         ((ME_DEVICE_NUMBER) << 3 | (HECI2_FUNCTION_NUMBER))
+
+///
+/// Default Vendor ID and Device ID
+///
+#define V_INTEL_VENDOR_ID   0x8086
+
+#define V_ME_HECI_VENDOR_ID V_INTEL_VENDOR_ID
+#define V_ME_IDER_VENDOR_ID V_INTEL_VENDOR_ID
+#define V_ME_SOL_VENDOR_ID  V_INTEL_VENDOR_ID
+
+#define V_ME_HECI_DEVICE_ID   0x8C3A
+#define V_ME_HECI2_DEVICE_ID  0x8C3B
+#define V_ME_IDER_DEVICE_ID   0x8C3C
+#define V_ME_SOL_DEVICE_ID    0x8C3D
+
+#define V_ME_LPTLP_HECI_DEVICE_ID   0x9C3A
+#define V_ME_LPTLP_HECI2_DEVICE_ID  0x9C3B
+#define V_ME_LPTLP_IDER_DEVICE_ID   0x9C3C
+#define V_ME_LPTLP_SOL_DEVICE_ID    0x9C3D
+
+#define R_ME_HFS                  0x40
+#define R_ME_MISC_SHDW            0x44
+#define R_ME_GS_SHDW              0x48
+#define R_ME_HFS_4                0x64
+#define R_ME_HFS_5                0x68
+#define R_ME_HFS_6                0x6C
+#define B_BOOT_GUARD_ENF_MASK     0x0200
+#define B_TPM_DISCONNECT          0x1000
+#define B_TPM1_2_DEACTIVATED      0x0100
+
+#define R_ME_H_GS                 0x4C
+#define B_ME_DID_RAPID_START_BIT  BIT23
+#define B_ME_DID_TYPE_MASK        BIT28
+#define R_ME_H_GS2                0x70
+#define B_ME_MBP_GIVE_UP          BIT0
+#define R_ME_HERS                 0xBC
+#define B_ME_EXTEND_REG_VALID     BIT31
+#define B_ME_EXTEND_REG_ALGORITHM (BIT0 | BIT1 | BIT2 | BIT3)
+#define V_ME_SHA_1                0x00
+#define V_ME_SHA_256              0x02
+#define R_ME_HER1                 0xC0
+#define R_ME_HER2                 0xC4
+#define R_ME_HER3                 0xC8
+#define R_ME_HER4                 0xCC
+#define R_ME_HER5                 0xD0
+#define R_ME_HER6                 0xD4
+#define R_ME_HER7                 0xD8
+#define R_ME_HER8                 0xDC
+
+///
+/// ME-related Chipset Definition
+///
+#define HeciEnable()    MeDeviceControl (HECI1, Enabled);
+#define Heci2Enable()   MeDeviceControl (HECI2, Enabled);
+#define IderEnable()    MeDeviceControl (IDER, Enabled);
+#define SolEnable()     MeDeviceControl (SOL, Enabled);
+#define Usbr1Enable()   MeDeviceControl (USBR1, Enabled);
+#define Usbr2Enable()   MeDeviceControl (USBR2, Enabled);
+
+#define HeciDisable()   MeDeviceControl (HECI1, Disabled);
+#define Heci2Disable()  MeDeviceControl (HECI2, Disabled);
+#define IderDisable()   MeDeviceControl (IDER, Disabled);
+#define SolDisable()    MeDeviceControl (SOL, Disabled);
+#define Usbr1Disable()  MeDeviceControl (USBR1, Disabled);
+#define Usbr2Disable()  MeDeviceControl (USBR2, Disabled);
+#define DisableAllMEDevices() \
+  HeciDisable (); \
+  Heci2Disable (); \
+  IderDisable (); \
+  SolDisable ();
+
+#define IS_PCH_LPTH_HECI_DEVICE_ID(DeviceId) \
+    (  \
+      (DeviceId == V_ME_HECI_DEVICE_ID) \
+    )
+
+#define IS_PCH_LPTLP_HECI_DEVICE_ID(DeviceId) \
+    (  \
+      (DeviceId == V_ME_LPTLP_HECI_DEVICE_ID) \
+    )
+
+#define IS_PCH_LPT_HECI_DEVICE_ID(DeviceId) \
+    ( \
+      IS_PCH_LPTH_HECI_DEVICE_ID(DeviceId) || \
+      IS_PCH_LPTLP_HECI_DEVICE_ID(DeviceId) \
+    )
+
+#define IS_PCH_LPTH_HECI2_DEVICE_ID(DeviceId) \
+    (  \
+      (DeviceId == V_ME_HECI2_DEVICE_ID) \
+    )
+
+#define IS_PCH_LPTLP_HECI2_DEVICE_ID(DeviceId) \
+    (  \
+      (DeviceId == V_ME_LPTLP_HECI2_DEVICE_ID) \
+    )
+
+#define IS_PCH_LPT_HECI2_DEVICE_ID(DeviceId) \
+    ( \
+      IS_PCH_LPTH_HECI2_DEVICE_ID(DeviceId) || \
+      IS_PCH_LPTLP_HECI2_DEVICE_ID(DeviceId) \
+    )
+
+#define IS_PCH_LPTH_IDER_DEVICE_ID(DeviceId) \
+    (  \
+      (DeviceId == V_ME_IDER_DEVICE_ID) \
+    )
+
+#define IS_PCH_LPTLP_IDER_DEVICE_ID(DeviceId) \
+    (  \
+      (DeviceId == V_ME_LPTLP_IDER_DEVICE_ID) \
+    )
+
+#define IS_PCH_LPT_IDER_DEVICE_ID(DeviceId) \
+    ( \
+      IS_PCH_LPTH_IDER_DEVICE_ID(DeviceId) || \
+      IS_PCH_LPTLP_IDER_DEVICE_ID(DeviceId) \
+    )
+
+#define IS_PCH_LPTH_SOL_DEVICE_ID(DeviceId) \
+    (  \
+      (DeviceId == V_ME_SOL_DEVICE_ID) \
+    )
+
+#define IS_PCH_LPTLP_SOL_DEVICE_ID(DeviceId) \
+    (  \
+      (DeviceId == V_ME_LPTLP_SOL_DEVICE_ID) \
+    )
+
+#define IS_PCH_LPT_SOL_DEVICE_ID(DeviceId) \
+    ( \
+      IS_PCH_LPTH_SOL_DEVICE_ID(DeviceId) || \
+      IS_PCH_LPTLP_SOL_DEVICE_ID(DeviceId) \
+    )
+
+///
+/// Function Disable SUS well lockdown
+///
+#define FunctionDisableWellLockdown() MeDeviceControl (FDSWL, Enabled);
+
+#endif
diff --git a/ReferenceCode/ME/Library/MeKernel/include/MeChipsetLib.h b/ReferenceCode/ME/Library/MeKernel/include/MeChipsetLib.h
new file mode 100644
index 0000000..dfa9417
--- /dev/null
+++ b/ReferenceCode/ME/Library/MeKernel/include/MeChipsetLib.h
@@ -0,0 +1,54 @@
+/** @file
+  Header file for Me Chipset Lib
+
+@copyright
+  Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _ME_CHIPSET_LIB_H_
+#define _ME_CHIPSET_LIB_H_
+
+typedef enum {
+  HECI1 = 1,
+  HECI2,
+  IDER,
+  SOL,
+  USBR1,
+  USBR2,
+  FDSWL,
+} ME_DEVICE;
+
+typedef enum {
+  Disabled= 0,
+  Enabled,
+} ME_DEVICE_FUNC_CTRL;
+
+/**
+  Enable/Disable Me devices
+
+  @param[in] WhichDevice          Select of Me device
+  @param[in] DeviceFuncCtrl       Function control
+
+  @retval None
+**/
+VOID
+MeDeviceControl (
+  IN  ME_DEVICE                   WhichDevice,
+  IN  ME_DEVICE_FUNC_CTRL         DeviceFuncCtrl
+  )
+;
+
+#endif
diff --git a/ReferenceCode/ME/Library/MeKernel/include/MeState.h b/ReferenceCode/ME/Library/MeKernel/include/MeState.h
new file mode 100644
index 0000000..55bb7bd
--- /dev/null
+++ b/ReferenceCode/ME/Library/MeKernel/include/MeState.h
@@ -0,0 +1,67 @@
+/** @file
+  Register Definitions for Me States
+
+@copyright
+  Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _ME_STATE_H
+#define _ME_STATE_H
+///
+/// Ignore ME_FW_INIT_COMPLETE status Macro
+///
+#define ME_STATUS_ME_STATE_ONLY(a)  ((a) & (~(ME_FW_INIT_COMPLETE | ME_FW_BOOT_OPTIONS_PRESENT)))
+
+///
+/// Macro to check if ME FW INIT is completed
+///
+#define ME_STATUS_IS_ME_FW_INIT_COMPLETE(a) (((a) & ME_FW_INIT_COMPLETE) == ME_FW_INIT_COMPLETE)
+
+///
+/// Marco to combind the complete bit to status
+///
+#define ME_STATUS_WITH_ME_INIT_COMPLETE(a)  ((a) | ME_FW_INIT_COMPLETE)
+
+///
+/// Macro to check ME Boot Option Present
+///
+#define ME_STATUS_IS_ME_FW_BOOT_OPTIONS_PRESENT(a)  (((a) & ME_FW_BOOT_OPTIONS_PRESENT) == ME_FW_BOOT_OPTIONS_PRESENT)
+
+//
+// Abstract ME Mode Definitions
+//
+#define ME_MODE_NORMAL        0x00
+#define ME_MODE_DEBUG         0x02
+#define ME_MODE_TEMP_DISABLED 0x03
+#define ME_MODE_SECOVER       0x04
+#define ME_MODE_FAILED        0x06
+
+//
+// Abstract ME Status definitions
+//
+#define ME_READY                    0x00
+#define ME_INITIALIZING             0x01
+#define ME_IN_RECOVERY_MODE         0x02
+#define ME_DISABLE_WAIT             0x06
+#define ME_TRANSITION               0x07
+#define ME_NOT_READY                0x0F
+#define ME_FW_INIT_COMPLETE         0x80
+#define ME_FW_BOOT_OPTIONS_PRESENT  0x100
+#define ME_FW_UPDATES_IN_PROGRESS   0x200
+
+#pragma pack()
+
+#endif // ME_STATE_H
diff --git a/ReferenceCode/ME/Library/MeKernel/include/MkhiMsgs.h b/ReferenceCode/ME/Library/MeKernel/include/MkhiMsgs.h
new file mode 100644
index 0000000..9005d62
--- /dev/null
+++ b/ReferenceCode/ME/Library/MeKernel/include/MkhiMsgs.h
@@ -0,0 +1,533 @@
+/** @file
+  MKHI Messages
+
+@copyright
+  Copyright (c) 2010 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _MKHI_MSGS_H
+#define _MKHI_MSGS_H
+
+#pragma pack(1)
+
+#define BIOS_FIXED_HOST_ADDR          0
+#define PREBOOT_FIXED_ME_ADDR         7
+#define BIOS_ASF_HOST_ADDR            1
+
+#define HECI_CORE_MESSAGE_ADDR        0x07
+#define HECI_ASF_MESSAGE_ADDR         0x02
+#define HECI_FSC_MESSAGE_ADDR         0x03
+#define HECI_POLICY_MANAGER_ADDR      0x05
+#define HECI_AT_MESSAGE_ADDR          0x05  ///< Added to support AT
+#define HECI_ME_PASSWORD_SERVICE_ADDR 0x06
+#define HECI_ICC_MESSAGE_ADDR         0x08
+#define HECI_TR_MESSAGE_ADDR          0x09
+#define HECI_SPI_MESSAGE_ADDR         0x0A
+
+#define NON_BLOCKING                  0
+#define BLOCKING                      1
+
+//
+// command handle by HCI
+//
+#define GEN_GET_MKHI_VERSION_CMD      0x01
+#define GEN_GET_MKHI_VERSION_CMD_ACK  0x81
+#define GEN_GET_FW_VERSION_CMD        0x02
+#define GEN_GET_FW_VERSION_CMD_ACK    0x82
+#define GEN_UNCFG_WO_PWD_CMD          0x0D
+#define GEN_UNCFG_WO_PWD_CMD_ACK      0x8D
+
+#define FWCAPS_GET_RULE_CMD           0x02
+#define FWCAPS_SET_RULE_CMD           0x03
+
+#define AT_ME_RULE_ID                 0xd0000
+
+//
+// Enums for Result field of MHKI Header
+//
+#define ME_SUCCESS                  0x00
+#define ME_ERROR_ALIAS_CHECK_FAILED 0x01
+#define ME_INVALID_MESSAGE          0x02
+#define ME_M1_DATA_OLDER_VER        0x03
+#define ME_M1_DATA_INVALID_VER      0x04
+#define ME_INVALID_M1_DATA          0x05
+
+//
+// MDES
+//
+#define MDES_ENABLE_MKHI_CMD      0x09
+#define MDES_ENABLE_MKHI_CMD_ACK  0x89
+
+///
+/// IFR Update
+///
+#define MEFWCAPS_ME_FWU_IFR_RULE  0x2E
+
+//
+// Manageability State Control
+//
+#define FIRMWARE_CAPABILITY_OVERRIDE_CMD      0x14
+#define FIRMWARE_CAPABILITY_OVERRIDE_CMD_ACK  0x94
+
+///
+/// Typedef for GroupID
+///
+typedef enum {
+  MKHI_CBM_GROUP_ID   = 0,
+  MKHI_PM_GROUP_ID,
+  MKHI_PWD_GROUP_ID,
+  MKHI_FWCAPS_GROUP_ID,
+  MKHI_APP_GROUP_ID,
+  MKHI_SPI_GROUP_ID,
+  MKHI_MDES_GROUP_ID  = 8,
+  MKHI_MAX_GROUP_ID,
+  MKHI_GEN_GROUP_ID   = 0xFF
+} MKHI_GROUP_ID;
+
+///
+/// Typedef for AT State
+///
+typedef enum _AT_STATE
+{
+  AT_STATE_INACTIVE  = 0,
+  AT_STATE_ACTIVE,
+  AT_STATE_STOLEN,
+  AT_STATE_SUSPEND,
+  AT_STATE_MAX
+} AT_STATE;
+
+///
+/// MKHI host message header. This header is part of HECI message sent from MEBx via
+/// Host Configuration Interface (HCI). ME Configuration Manager or Power Configuration
+/// Manager also include this header with appropriate fields set as part of the
+/// response message to the HCI.
+///
+typedef union _MKHI_MESSAGE_HEADER {
+  UINT32  Data;
+  struct {
+    UINT32  GroupId : 8;
+    UINT32  Command : 7;
+    UINT32  IsResponse : 1;
+    UINT32  Reserved : 8;
+    UINT32  Result : 8;
+  } Fields;
+} MKHI_MESSAGE_HEADER;
+
+///
+/// End of Post ACK message
+///
+typedef struct _CBM_EOP_ACK_DATA {
+  UINT32  RequestedActions;
+} CBM_EOP_ACK_DATA;
+
+typedef struct _GEN_END_OF_POST_ACK {
+  MKHI_MESSAGE_HEADER Header;
+  CBM_EOP_ACK_DATA    Data;
+} GEN_END_OF_POST_ACK;
+
+typedef union _MKHI_VERSION {
+  UINT32  Data;
+  struct {
+    UINT32  Minor : 16;
+    UINT32  Major : 16;
+  } Fields;
+} MKHI_VERSION;
+
+///
+/// MKHI version messages
+///
+typedef struct _GEN_GET_MKHI_VERSION {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+} GEN_GET_MKHI_VERSION;
+
+typedef struct _GET_MKHI_VERSION_ACK_DATA {
+  MKHI_VERSION  MKHIVersion;
+} GET_MKHI_VERSION_ACK_DATA;
+
+typedef struct _GEN_GET_MKHI_VERSION_ACK {
+  MKHI_MESSAGE_HEADER       MKHIHeader;
+  GET_MKHI_VERSION_ACK_DATA Data;
+} GEN_GET_MKHI_VERSION_ACK;
+
+///
+/// FW version messages
+///
+typedef struct _GEN_GET_FW_VER {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+} GEN_GET_FW_VER;
+
+typedef struct _GEN_GET_FW_VER_ACK_DATA {
+  UINT32  CodeMinor : 16;
+  UINT32  CodeMajor : 16;
+  UINT32  CodeBuildNo : 16;
+  UINT32  CodeHotFix : 16;
+  UINT32  RcvyMinor : 16;
+  UINT32  RcvyMajor : 16;
+  UINT32  RcvyBuildNo : 16;
+  UINT32  RcvyHotFix : 16;
+  UINT32  FitcMinor : 16;
+  UINT32  FitcMajor : 16;
+  UINT32  FitcBuildNo : 16;
+  UINT32  FitcHotFix : 16;
+} GEN_GET_FW_VER_ACK_DATA;
+
+typedef struct _GEN_GET_FW_VER_ACK {
+  MKHI_MESSAGE_HEADER     MKHIHeader;
+  GEN_GET_FW_VER_ACK_DATA Data;
+} GEN_GET_FW_VER_ACK;
+
+///
+/// Unconfig without password messages
+///
+typedef struct _GEN_UNCFG_WO_PWD {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+} GEN_UNCFG_WO_PWD;
+
+typedef struct _GEN_UNCFG_WO_PWD_ACK {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+} GEN_UNCFG_WO_PWD_ACK;
+
+///
+/// Get Firmware Capability MKHI
+///
+typedef struct _GET_RULE_DATA {
+  UINT32  RuleId;
+} GET_RULE_DATA;
+
+typedef struct _GEN_GET_FW_CAPSKU {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  GET_RULE_DATA       Data;
+} GEN_GET_FW_CAPSKU;
+
+typedef union _RULE_ID {
+  UINT32  Data;
+  struct {
+    UINT32  RuleTypeId : 16;
+    UINT32  FeatureId : 8;
+    UINT32  Reserved : 8;
+  } Fields;
+} RULE_ID;
+
+typedef struct _SET_RULE_DATA {
+  RULE_ID RuleId;
+  UINT8   RuleDataLen;
+  UINT8   RuleData;
+} SET_RULE_DATA;
+
+typedef struct _SET_RULE_ACK_DATA {
+  UINT32  RuleId;
+} SET_RULE_ACK_DATA;
+
+typedef struct _GEN_SET_FW_CAPSKU {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  SET_RULE_DATA       Data;
+} GEN_SET_FW_CAPSKU;
+
+typedef struct _GEN_SET_FW_CAPSKU_ACK {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  SET_RULE_ACK_DATA   Data;
+} GEN_SET_FW_CAPSKU_ACK;
+typedef union _MEFWCAPS_SKU {
+  UINT32  Data;
+  struct {
+    UINT32  FullNet : 1;              ///< [0] Full network manageability
+    UINT32  StdNet : 1;               ///< [1] Standard network manageability
+    UINT32  Manageability : 1;        ///< [2] Manageability
+    UINT32  SmallBusiness : 1;        ///< [3] Small business technology
+    UINT32  Reserved2 : 1;            ///< [4] Reserved
+    UINT32  IntelAT : 1;              ///< [5] IntelR Anti-Theft (AT)
+    UINT32  IntelCLS : 1;             ///< [6] IntelR Capability Licensing Service (CLS)
+    UINT32  Reserved : 3;             ///< [9:7] Reserved
+    UINT32  IntelMPC : 1;             ///< [10] IntelR Power Sharing Technology (MPC)
+    UINT32  IccOverClocking : 1;      ///< [11] ICC Over Clocking
+    UINT32  PAVP : 1;                 ///< [12] Protected Audio Video Path (PAVP)
+    UINT32  Reserved1 : 4;            ///< [16:13] Reserved
+    UINT32  IPV6 : 1;                 ///< [17] IPV6
+    UINT32  KVM : 1;                  ///< [18] KVM Remote Control (KVM)
+    UINT32  OCH : 1;                  ///< [19] Outbreak Containment Heuristic (OCH)
+    UINT32  VLAN : 1;                 ///< [20] Virtual LAN (VLAN)
+    UINT32  TLS : 1;                  ///< [21] TLS
+    UINT32  Reserved4 : 1;            ///< [22] Reserved
+    UINT32  WLAN : 1;                 ///< [23] Wireless LAN (WLAN)
+    UINT32  Reserved5 : 5;            ///< [28:24] Reserved
+    UINT32  PTT : 1;                  ///< [29] Platform Trust Technoogy (PTT)
+    UINT32  Reserved6 : 1;            ///< [30] Reserved
+    UINT32  NFC : 1;                  ///< [31] NFC
+  } Fields;
+} MEFWCAPS_SKU;
+
+typedef struct _AT_STATE_FLAG {
+  UINT16  LockState : 1;              ///< Indicate whether the platform is locked */
+  UINT16  AuthenticateModule : 1;     ///< Preferred Authentication Module */
+  UINT16  S3Authentication : 1;       ///< indicates whether S3 authentication  is enabled */
+  UINT16  FlashWearOut : 1;           ///< indicates whether the AT flash partition is currently in violation of flash wear out rules */
+  UINT16  FlashVariableSecurity : 1;  ///< indicates whether the AT flash variables have been tampered with */
+  UINT16  Reserved : 11;
+} AT_STATE_FLAG;
+
+typedef struct _AT_STATE_INFO {
+  UINT8          State;
+  UINT8          LastTheftTrigger;
+  AT_STATE_FLAG  flags;
+} AT_STATE_INFO;
+
+typedef struct {
+  UINT8         AtState;              ///< State of AT
+  UINT8         AtLastTheftTrigger;   ///< Reason for the last trigger
+  AT_STATE_FLAG AtStateFlags;         ///< State of AT Fw
+} AT_STATE_STRUCT;
+
+typedef struct _GEN_GET_FW_CAPS_SKU_ACK_DATA {
+  UINT32        RuleID;
+  UINT8         RuleDataLen;
+  MEFWCAPS_SKU  FWCapSku;
+} GEN_GET_FW_CAPS_SKU_ACK_DATA;
+
+typedef struct _GEN_GET_FW_CAPSKU_ACK {
+  MKHI_MESSAGE_HEADER           MKHIHeader;
+  GEN_GET_FW_CAPS_SKU_ACK_DATA  Data;
+} GEN_GET_FW_CAPS_SKU_ACK;
+
+typedef union _GEN_GET_FW_CAPS_SKU_BUFFER {
+  GEN_GET_FW_CAPSKU       Request;
+  GEN_GET_FW_CAPS_SKU_ACK Response;
+} GEN_GET_FW_CAPS_SKU_BUFFER;
+
+typedef enum {
+  UPDATE_DISABLED     = 0,
+  UPDATE_ENABLED
+} LOCAL_FW_UPDATE;
+
+typedef enum {
+  LOCAL_FW_ALWAYS     = 0,
+  LOCAL_FW_NEVER,
+  LOCAL_FW_RESTRICTED,
+} LOCAL_FW_QUALIFIER;
+
+typedef struct _GEN_LOCAL_FW_UPDATE_DATA {
+  UINT32  RuleId;
+  UINT8   RuleDataLen;
+  UINT8   RuleData;
+  UINT8   Reserved[30];
+} GEN_LOCAL_FW_UPDATE_DATA;
+
+typedef struct _GEN_GET_LOCAL_FW_UPDATE {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  GET_RULE_DATA       Data;
+} GEN_GET_LOCAL_FW_UPDATE;
+
+typedef struct _GEN_GET_LOCAL_FW_UPDATE_ACK {
+  MKHI_MESSAGE_HEADER       MKHIHeader;
+  GEN_LOCAL_FW_UPDATE_DATA  Data;
+} GEN_GET_LOCAL_FW_UPDATE_ACK;
+
+typedef struct _GEN_SET_LOCAL_FW_UPDATE {
+  MKHI_MESSAGE_HEADER       MKHIHeader;
+  GEN_LOCAL_FW_UPDATE_DATA  Data;
+} GEN_SET_LOCAL_FW_UPDATE;
+
+typedef struct _GEN_SET_LOCAL_FW_UPDATE_ACK {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  GET_RULE_DATA       Data;
+} GEN_SET_LOCAL_FW_UPDATE_ACK;
+
+typedef enum {
+  NO_BRAND                                    = 0,
+  INTEL_AMT_BRAND,
+  INTEL_STAND_MANAGEABILITY_BRAND,
+  INTEL_LEVEL_III_MANAGEABILITY_UPGRADE_BRAND,
+  INTEL_RESERVED_BRAND,
+  INTEL_SMALL_BUSINESS_TECHNOLOGY_BRAND,
+} PLATFORM_BRAND;
+
+typedef enum {
+  INTEL_ME_1_5MB_FW                           = 3,
+  INTEL_ME_5MB_FW,
+} ME_IMAGE_TYPE;
+
+#define REGULAR_SKU               0
+#define SUPER_SKU                 1
+
+#define PLATFORM_MARKET_CORPORATE 1
+#define PLATFORM_MARKET_CONSUMER  2
+
+#define PLATFORM_MOBILE           1
+#define PLATFORM_DESKTOP          2
+#define PLATFORM_SERVER           4
+#define PLATFORM_WORKSTATION      8
+
+typedef union _PLATFORM_TYPE_RULE_DATA {
+  UINT32  Data;
+  struct {
+    UINT32  PlatformTargetUsageType : 4;
+    UINT32  PlatformTargetMarketType : 2;
+    UINT32  SuperSku : 1;
+    UINT32  Reserved : 1;
+    UINT32  IntelMeFwImageType : 4;
+    UINT32  PlatformBrand : 4;
+    UINT32  Reserved1 : 16;
+  } Fields;
+} PLATFORM_TYPE_RULE_DATA;
+
+typedef struct _GEN_PLATFORM_TYPE_DATA {
+  UINT32                  RuleId;
+  UINT8                   RuleDataLen;
+  PLATFORM_TYPE_RULE_DATA RuleData;
+  UINT8                   Reserved[27];
+} GEN_PLATFORM_TYPE_DATA;
+
+typedef struct _GEN_GET_PLATFORM_TYPE {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  GET_RULE_DATA       Data;
+} GEN_GET_PLATFORM_TYPE;
+
+typedef struct _GEN_GET_PLATFORM_TYPE_ACK {
+  MKHI_MESSAGE_HEADER     MKHIHeader;
+  GEN_PLATFORM_TYPE_DATA  Data;
+} GEN_GET_PLATFORM_TYPE_ACK;
+
+typedef union _GEN_GET_PLATFORM_TYPE_BUFFER {
+  GEN_GET_PLATFORM_TYPE     Request;
+  GEN_GET_PLATFORM_TYPE_ACK Response;
+} GEN_GET_PLATFORM_TYPE_BUFFER;
+
+typedef struct _GET_AT_ME_RULE_CMD {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  UINT32              RuleId;
+
+} GET_AT_ME_RULE_CMD;
+
+typedef struct _GET_AT_ME_RULE_RSP {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  UINT32              RuleId;
+  UINT8               RuleDataLength;
+  AT_STATE_INFO       AtRuleData;
+
+} GET_AT_ME_RULE_RSP;
+
+typedef struct _GET_FW_FEATURE_STATUS {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  GET_RULE_DATA       Data;
+} GEN_GET_FW_FEATURE_STATUS;
+
+typedef struct _GET_FW_FEATURE_STATUS_ACK {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  UINT32              RuleId;
+  UINT8               RuleDataLength;
+  MEFWCAPS_SKU        RuleData;
+} GEN_GET_FW_FEATURE_STATUS_ACK;
+
+typedef struct _GEN_AMT_BIOS_SYNCH_INFO {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  GET_RULE_DATA       Data;
+} GEN_AMT_BIOS_SYNCH_INFO;
+
+typedef struct _GEN_AMT_BIOS_SYNCH_INFO_ACK {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  UINT32              RuleId;
+  UINT8               RuleDataLength;
+  UINT32              RuleData;
+} GEN_AMT_BIOS_SYNCH_INFO_ACK;
+
+typedef struct _GEN_GET_OEM_TAG_MSG {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  GET_RULE_DATA       Data;
+} GEN_GET_OEM_TAG_MSG;
+
+typedef struct _GEN_GET_OEM_TAG_MSG_ACK {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  UINT32              RuleId;
+  UINT8               RuleDataLength;
+  UINT32              RuleData;
+} GEN_GET_OEM_TAG_MSG_ACK;
+
+typedef union _PLATFORM_DEBUG_CAP {
+  UINT8   Data;
+  struct {
+    UINT8 Mdes : 1;
+    UINT8 SvtForPch : 1;
+    UINT8 Reserved : 6;
+  } Fields;
+} PLATFORM_DEBUG_CAP;
+
+typedef struct _GEN_PLATFORM_DEBUG_CAP_MKHI_CMD_MSG {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  PLATFORM_DEBUG_CAP  Capability;
+} GEN_PLATFORM_DEBUG_CAP_MKHI_CMD_MSG;
+
+///
+/// Manageability State Control MKHI definitions
+///
+typedef struct _FIRMWARE_CAPABILITY_OVERRIDE_DATA {
+  UINT32  EnableFeature;
+  UINT32  DisableFeature;
+} FIRMWARE_CAPABILITY_OVERRIDE_DATA;
+
+typedef struct _FIRMWARE_CAPABILITY_OVERRIDE {
+  MKHI_MESSAGE_HEADER               MKHIHeader;
+  FIRMWARE_CAPABILITY_OVERRIDE_DATA FeatureState;
+} FIRMWARE_CAPABILITY_OVERRIDE;
+
+typedef enum _FIRMWARE_CAPABILITY_RESPONSE
+{
+  SET_FEATURE_STATE_ACCEPTED                  = 0,
+  SET_FEATURE_STATE_REJECTED
+} FIRMWARE_CAPABILITY_RESPONSE;
+
+typedef struct _FIRMWARE_CAPABILITY_OVERRIDE_ACK_DATA {
+  FIRMWARE_CAPABILITY_RESPONSE  Response;
+} FIRMWARE_CAPABILITY_OVERRIDE_ACK_DATA;
+
+typedef struct _FIRMWARE_CAPABILITY_OVERRIDE_ACK {
+  MKHI_MESSAGE_HEADER                   Header;
+  FIRMWARE_CAPABILITY_OVERRIDE_ACK_DATA Data;
+} FIRMWARE_CAPABILITY_OVERRIDE_ACK;
+
+///
+/// Set ACM TPM Data MKHI
+///
+#define ACM_TPM_DATA_MKHI_DATA        0x00000303
+#define ACM_TPM_DATA_RULE_TYPE_ID     0x2F
+#define ACM_TPM_DATA_RULE_DATA_LENGTH 0x04
+
+typedef union _TPM_STATE {
+  UINT16 Data;
+  struct {
+    UINT16 Reserved_0: 8;
+    UINT16 TpmDeactivate: 1;
+    UINT16 Reserved_1: 7;
+  } Fields;
+} TPM_STATE;
+
+typedef struct _ACM_TPM_DATA {
+  RULE_ID   RuleId;
+  UINT8     RuleDataLen;
+  TPM_STATE TpmState;
+  UINT8     Reserved[2];  
+} ACM_TPM_DATA;
+
+typedef struct _BIOSNV_SET_ACM_TPM_DATA {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  ACM_TPM_DATA        AcmTpmData;
+} BIOSNV_SET_ACM_TPM;
+
+typedef struct _BIOSNV_SET_ACM_TPM_DATA_ACK {
+  MKHI_MESSAGE_HEADER MKHIHeader;
+  RULE_ID             RuleId;
+} BIOSNV_SET_ACM_TPM_ACK;
+
+#pragma pack()
+
+#endif // _MKHI_MSGS_H