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-rw-r--r--Board/IO/F81216/ACPI/Uart1.ASL10
-rw-r--r--Board/IO/F81216/ACPI/Uart2.ASL8
-rw-r--r--Board/IO/F81216/ACPI/Uart3.ASL8
-rw-r--r--Board/IO/F81216/ACPI/Uart4.ASL8
-rw-r--r--Board/IO/F81216/F81216.ASL8
-rw-r--r--Board/IO/F81216/F81216DXE.C70
-rw-r--r--Board/IO/F81216/F81216PEI.C2
-rw-r--r--Board/IO/F81866/F81866DXE.C78
-rw-r--r--Board/IO/F81866/F81866PEI.C2
-rw-r--r--Board/SB/SBSECInit.asm2
-rw-r--r--CRB/CSP.sdl86
-rw-r--r--actionitems.txt4
12 files changed, 186 insertions, 100 deletions
diff --git a/Board/IO/F81216/ACPI/Uart1.ASL b/Board/IO/F81216/ACPI/Uart1.ASL
index ce9eb04..9ceeb2c 100644
--- a/Board/IO/F81216/ACPI/Uart1.ASL
+++ b/Board/IO/F81216/ACPI/Uart1.ASL
@@ -47,12 +47,12 @@ Device(UR11) {
Name(_UID, 0x11) //Generic ID for COMC
Name(_DDN, "COM7")
- Method(_HID, 0) {Return(^^SIO2.UHID(0x11))} //PnP Device ID
- Method(_STA, 0) {Return(^^SIO2.DSTA(0x11))} //Get UART status
- Method(_DIS, 0) {^^SIO2.DCNT(0x11, 0)} //Disable UART
+ Method(_HID, 0) {Return(^^SIO2.UHID(0x08))} //PnP Device ID
+ Method(_STA, 0) {Return(^^SIO2.DSTA(0x08))} //Get UART status
+ Method(_DIS, 0) {^^SIO2.DCNT(0x08, 0)} //Disable UART
//Default is share mode
- Method(_CRS, 0) {Return(^^SIO2.DCR3(0x11, 0))} //Get UART current resources
- Method(_SRS, 1) {^^SIO2.DSR3(Arg0, 0x11)} //Set UART recources
+ Method(_CRS, 0) {Return(^^SIO2.DCR3(0x08, 0))} //Get UART current resources
+ Method(_SRS, 1) {^^SIO2.DSR3(Arg0, 0x08)} //Set UART recources
//-----------------------------------------------------------------------
// UART1 Possible Resources
//-----------------------------------------------------------------------
diff --git a/Board/IO/F81216/ACPI/Uart2.ASL b/Board/IO/F81216/ACPI/Uart2.ASL
index 5f861fb..b53f515 100644
--- a/Board/IO/F81216/ACPI/Uart2.ASL
+++ b/Board/IO/F81216/ACPI/Uart2.ASL
@@ -43,11 +43,11 @@ Device(UR12) {
Name(_DDN, "COM8")
//Generic ID for COMD
// Method(_HID, 0) {Return(^^SIO2.UHID(0x12))} //PnP Device ID
- Method(_STA, 0) {Return(^^SIO2.DSTA(0x12))} //Get UART status
- Method(_DIS, 0) {^^SIO2.DCNT(0x12, 0)} //Disable UART
+ Method(_STA, 0) {Return(^^SIO2.DSTA(0x09))} //Get UART status
+ Method(_DIS, 0) {^^SIO2.DCNT(0x09, 0)} //Disable UART
//Default is share mode
- Method(_CRS, 0) {Return(^^SIO2.DCR3(0x12, 0))} //Get UART current resources
- Method(_SRS, 1) {^^SIO2.DSR3(Arg0, 0x12)} //Set UART recources
+ Method(_CRS, 0) {Return(^^SIO2.DCR3(0x09, 0))} //Get UART current resources
+ Method(_SRS, 1) {^^SIO2.DSR3(Arg0, 0x09)} //Set UART recources
//-----------------------------------------------------------------------
// UART2 Possible Resources
diff --git a/Board/IO/F81216/ACPI/Uart3.ASL b/Board/IO/F81216/ACPI/Uart3.ASL
index f1ed8fe..ffbbb90 100644
--- a/Board/IO/F81216/ACPI/Uart3.ASL
+++ b/Board/IO/F81216/ACPI/Uart3.ASL
@@ -43,11 +43,11 @@ Device(UR13) {
Name(_DDN, "COM9")
// Method(_HID, 0) {Return(^^SIO2.UHID(0x13))} //PnP Device ID
- Method(_STA, 0) {Return(^^SIO2.DSTA(0x13))} //Get UART status
- Method(_DIS, 0) {^^SIO2.DCNT(0x13, 0)} //Disable UART
+ Method(_STA, 0) {Return(^^SIO2.DSTA(0x0C))} //Get UART status
+ Method(_DIS, 0) {^^SIO2.DCNT(0x0C, 0)} //Disable UART
//Default is share mode
- Method(_CRS, 0) {Return(^^SIO2.DCR3(0x13, 0))} //Get UART current resources
- Method(_SRS, 1) {^^SIO2.DSR3(Arg0, 0x13)} //Set UART recources
+ Method(_CRS, 0) {Return(^^SIO2.DCR3(0x0C, 0))} //Get UART current resources
+ Method(_SRS, 1) {^^SIO2.DSR3(Arg0, 0x0C)} //Set UART recources
//-----------------------------------------------------------------------
// UART3 Possible Resources
diff --git a/Board/IO/F81216/ACPI/Uart4.ASL b/Board/IO/F81216/ACPI/Uart4.ASL
index baa4e55..b96d81c 100644
--- a/Board/IO/F81216/ACPI/Uart4.ASL
+++ b/Board/IO/F81216/ACPI/Uart4.ASL
@@ -43,11 +43,11 @@ Device(UR14) {
Name(_DDN, "COM10")
// Method(_HID, 0) {Return(^^SIO2.UHID(0x14))} //PnP Device ID
- Method(_STA, 0) {Return(^^SIO2.DSTA(0x14))} //Get UART status
- Method(_DIS, 0) {^^SIO2.DCNT(0x14, 0)} //Disable UART
+ Method(_STA, 0) {Return(^^SIO2.DSTA(0x0D))} //Get UART status
+ Method(_DIS, 0) {^^SIO2.DCNT(0x0D, 0)} //Disable UART
//Default is share mode
- Method(_CRS, 0) {Return(^^SIO2.DCR3(0x14, 0))} //Get UART current resources
- Method(_SRS, 1) {^^SIO2.DSR3(Arg0, 0x14)} //Set UART recources
+ Method(_CRS, 0) {Return(^^SIO2.DCR3(0x0D, 0))} //Get UART current resources
+ Method(_SRS, 1) {^^SIO2.DSR3(Arg0, 0x0D)} //Set UART recources
//-----------------------------------------------------------------------
// UART4 Possible Resources
diff --git a/Board/IO/F81216/F81216.ASL b/Board/IO/F81216/F81216.ASL
index ebc950f..24e0493 100644
--- a/Board/IO/F81216/F81216.ASL
+++ b/Board/IO/F81216/F81216.ASL
@@ -136,12 +136,12 @@ Device(SIO2) {
0xFF, // 05 - MIDI
0xFF, // 06 - MSS Audio
0xFF, // 07 - AdLib sound (FM synth)
- 0xFF, // 08 - Game port #1
- 0xFF, // 09 - Game port #2
+ 0x00, // 08 - Game port #1
+ 0x01, // 09 - Game port #2
0xFF, // 0A - KBC 60 & 64
0xFF, // 0B - EC 62 & 66
- 0xFF, // 0C - Reserved
- 0xFF, // 0D - Reserved
+ 0x02, // 0C - Reserved
+ 0x03, // 0D - Reserved
0xFF, // 0E - PS/2 Mouse
0xFF, // 0F - Reserved
//----add your other device below,if no,please cut and modify Package number----------//
diff --git a/Board/IO/F81216/F81216DXE.C b/Board/IO/F81216/F81216DXE.C
index e68bb69..03160b4 100644
--- a/Board/IO/F81216/F81216DXE.C
+++ b/Board/IO/F81216/F81216DXE.C
@@ -420,11 +420,11 @@ static EFI_STATUS COM_Init(
switch (InitStep)
{
case isGetSetupData:
- // Disable IODecode?
- if((!dev->DeviceInfo->Implemented) || (!dev->NvData.DevEnable)) {
- LoopCspIoDecodeListInit(NULL,AmiSio);
- ClearDevResource(dev);
- }
+ // // Disable IODecode?
+ // if((!dev->DeviceInfo->Implemented) || (!dev->NvData.DevEnable)) {
+ // LoopCspIoDecodeListInit(NULL,AmiSio);
+ // ClearDevResource(dev);
+ // }
break;
case isPrsSelect:
@@ -434,36 +434,36 @@ static EFI_STATUS COM_Init(
//Programm Device Mode register here(if NEEDED)use AmiSioProtocol
//make serial port 0 as IR port funtion only
- if(dev->DeviceInfo->UID == 0x10)
- {
- //Programm Device Mode register here(if NEEDED)use AmiSioProtocol
- Status=AmiSio->Access(AmiSio,FALSE,FALSE,0xF1,&rv);
- ASSERT_EFI_ERROR(Status);
- if(EFI_ERROR(Status)) return Status;
-
- rv &= 0xE3;
-
- switch (dev->NvData.DevMode)
- {
- case 0: //Bit4 = 0, Serial Port Function Mode
- break;
- case 1:
- rv|=0x10; //Bit4 = 1 Bit3,Bit2 = 00 , IR Mode,Pusle 1.6us,Full Duplex
- break;
- case 2:
- rv|=0x14; //Bit4 = 1 Bit3,Bit2 = 01 , IR Mode,Pusle 1.6us,Half Duplex
- break;
- case 3:
- rv|=0x18; //Bit4 = 1 Bit3,Bit2 = 10 , IR Mode,Pusle 3/16 Bit Time,Full Duplex
- break;
- case 4:
- rv|=0x1C; //Bit4 = 1 Bit3,Bit2 = 11 , IR Mode,Pusle 3/16 Bit Time,Half Duplex
- break;
- default: return EFI_INVALID_PARAMETER;
- }
- Status=AmiSio->Access(AmiSio,TRUE,FALSE,0xF1,&rv);
- ASSERT_EFI_ERROR(Status);
- }
+// if(dev->DeviceInfo->UID == 0x10)
+// {
+// //Programm Device Mode register here(if NEEDED)use AmiSioProtocol
+// Status=AmiSio->Access(AmiSio,FALSE,FALSE,0xF1,&rv);
+// ASSERT_EFI_ERROR(Status);
+// if(EFI_ERROR(Status)) return Status;
+//
+// rv &= 0xE3;
+//
+// switch (dev->NvData.DevMode)
+// {
+// case 0: //Bit4 = 0, Serial Port Function Mode
+// break;
+// case 1:
+// rv|=0x10; //Bit4 = 1 Bit3,Bit2 = 00 , IR Mode,Pusle 1.6us,Full Duplex
+// break;
+// case 2:
+// rv|=0x14; //Bit4 = 1 Bit3,Bit2 = 01 , IR Mode,Pusle 1.6us,Half Duplex
+// break;
+// case 3:
+// rv|=0x18; //Bit4 = 1 Bit3,Bit2 = 10 , IR Mode,Pusle 3/16 Bit Time,Full Duplex
+// break;
+// case 4:
+// rv|=0x1C; //Bit4 = 1 Bit3,Bit2 = 11 , IR Mode,Pusle 3/16 Bit Time,Half Duplex
+// break;
+// default: return EFI_INVALID_PARAMETER;
+// }
+// Status=AmiSio->Access(AmiSio,TRUE,FALSE,0xF1,&rv);
+// ASSERT_EFI_ERROR(Status);
+// }
//Programm Serial_X IRQ Share register.
if((dev->DeviceInfo->Flags & SIO_SHR_IRQ1) && dev->ResOwner) {
//enter cfgmode
diff --git a/Board/IO/F81216/F81216PEI.C b/Board/IO/F81216/F81216PEI.C
index 8e0d564..a1737a1 100644
--- a/Board/IO/F81216/F81216PEI.C
+++ b/Board/IO/F81216/F81216PEI.C
@@ -139,7 +139,7 @@ VOID F81216SEC_INIT(VOID)
UINTN i;
// Decode neccessary IO resource in PEI phase
- PeiSetLpcDeviceDecoding();
+// PeiSetLpcDeviceDecoding();
// Step through table and initialize the Serial Port
for(i=0; i<(sizeof(F81216SEC_PEI_Init_Table))/(sizeof(SIO_DATA));i++) {
diff --git a/Board/IO/F81866/F81866DXE.C b/Board/IO/F81866/F81866DXE.C
index 269cbb1..28cdf35 100644
--- a/Board/IO/F81866/F81866DXE.C
+++ b/Board/IO/F81866/F81866DXE.C
@@ -627,10 +627,10 @@ static EFI_STATUS COM_Init(
switch (InitStep)
{
case isGetSetupData:
- if((!dev->DeviceInfo->Implemented) || (!dev->NvData.DevEnable)) {
- LoopCspIoDecodeListInit(NULL,AmiSio);
- ClearDevResource(dev);
- }
+// if((!dev->DeviceInfo->Implemented) || (!dev->NvData.DevEnable)) {
+// LoopCspIoDecodeListInit(NULL,AmiSio);
+// ClearDevResource(dev);
+// }
break;
case isPrsSelect:
@@ -638,45 +638,45 @@ static EFI_STATUS COM_Init(
case isBeforeActivate:
- //Only decode UART1/UART2. More others UART port is decode in PEI
- //Attention! Remove the more com ports to PEI decode.
- if(dev->DeviceInfo->UID <= 0x02)
- LoopCspIoDecodeListInit(PciIo,AmiSio);
+// //Only decode UART1/UART2. More others UART port is decode in PEI
+// //Attention! Remove the more com ports to PEI decode.
+// if(dev->DeviceInfo->UID <= 0x02)
+// LoopCspIoDecodeListInit(PciIo,AmiSio);
//Programm Device Mode register here(if NEEDED)use AmiSioProtocol
- if(DXE_COM_Mode_Init_Table[dev->DeviceInfo->UID].AndData8 == 0xFF) {
- rv=DXE_COM_Mode_Init_Table[dev->DeviceInfo->UID].OrData8;
- } else {
- Status=AmiSio->Access(AmiSio, FALSE, FALSE, 0xF0, &rv);
- ASSERT_EFI_ERROR(Status);
- rv &= DXE_COM_Mode_Init_Table[dev->DeviceInfo->UID].AndData8;
- rv |= DXE_COM_Mode_Init_Table[dev->DeviceInfo->UID].OrData8;
- }
- Status=AmiSio->Access(AmiSio,TRUE,FALSE,0xF0,&rv);
+// if(DXE_COM_Mode_Init_Table[dev->DeviceInfo->UID].AndData8 == 0xFF) {
+// rv=DXE_COM_Mode_Init_Table[dev->DeviceInfo->UID].OrData8;
+// } else {
+// Status=AmiSio->Access(AmiSio, FALSE, FALSE, 0xF0, &rv);
+// ASSERT_EFI_ERROR(Status);
+// rv &= DXE_COM_Mode_Init_Table[dev->DeviceInfo->UID].AndData8;
+// rv |= DXE_COM_Mode_Init_Table[dev->DeviceInfo->UID].OrData8;
+// }
+// Status=AmiSio->Access(AmiSio,TRUE,FALSE,0xF0,&rv);
//AMI_TODO: You can program device mode as follow:
- if(dev->DeviceInfo->UID == 0x05) {
- Status=AmiSio->Access(AmiSio,FALSE,FALSE,0xF1,&rv);
- ASSERT_EFI_ERROR(Status);
- if(EFI_ERROR(Status))return Status;
- //clear Bit4~3 where COM Port mode is:
- rv &= 0xE7;
- switch (dev->NvData.DevMode) {
- case 0:
- rv |= 0x00; //Bit4~3 = 000, Disable IR1 function
- break;
- case 1:
- rv |= 0x10; //Bit4~3 = 010, Enable IR1 function, active pulse is 1.6uS
- break;
- case 2:
- rv |= 0x18; //Bit4~3 = 011, Enable IR1 function, active pulse is 3/16 bit time
- break;
- default: return EFI_INVALID_PARAMETER;
- }
- Status=AmiSio->Access(AmiSio,TRUE,FALSE,0xF1,&rv);
- ASSERT_EFI_ERROR(Status);
- }
+// if(dev->DeviceInfo->UID == 0x05) {
+// Status=AmiSio->Access(AmiSio,FALSE,FALSE,0xF1,&rv);
+// ASSERT_EFI_ERROR(Status);
+// if(EFI_ERROR(Status))return Status;
+// //clear Bit4~3 where COM Port mode is:
+// rv &= 0xE7;
+// switch (dev->NvData.DevMode) {
+// case 0:
+// rv |= 0x00; //Bit4~3 = 000, Disable IR1 function
+// break;
+// case 1:
+// rv |= 0x10; //Bit4~3 = 010, Enable IR1 function, active pulse is 1.6uS
+// break;
+// case 2:
+// rv |= 0x18; //Bit4~3 = 011, Enable IR1 function, active pulse is 3/16 bit time
+// break;
+// default: return EFI_INVALID_PARAMETER;
+// }
+// Status=AmiSio->Access(AmiSio,TRUE,FALSE,0xF1,&rv);
+// ASSERT_EFI_ERROR(Status);
+// }
//Programm Serial_X IRQ Share register.
if((dev->DeviceInfo->Flags & SIO_SHR_IRQ1) && dev->ResOwner) {
@@ -878,7 +878,7 @@ static EFI_STATUS KBC_Init(
break;
case isBeforeActivate:
- LoopCspIoDecodeListInit(PciIo,AmiSio); // Enable IODecode
+// LoopCspIoDecodeListInit(PciIo,AmiSio); // Enable IODecode
break;
default: Status=EFI_INVALID_PARAMETER;
diff --git a/Board/IO/F81866/F81866PEI.C b/Board/IO/F81866/F81866PEI.C
index 844336a..91cf7a7 100644
--- a/Board/IO/F81866/F81866PEI.C
+++ b/Board/IO/F81866/F81866PEI.C
@@ -146,7 +146,7 @@ VOID F81866_INIT(VOID)
UINTN i;
// Decode neccessary IO resource in PEI phase
- PeiSetLpcDeviceDecoding();
+// PeiSetLpcDeviceDecoding();
// Step through table and initialize the Serial Port
for(i=0; i<(sizeof(F81866_PEI_Init_Table))/(sizeof(SIO_DATA));i++) {
diff --git a/Board/SB/SBSECInit.asm b/Board/SB/SBSECInit.asm
index a65a50e..2ab1c3c 100644
--- a/Board/SB/SBSECInit.asm
+++ b/Board/SB/SBSECInit.asm
@@ -247,7 +247,7 @@ IF MKF_SB_IO_DECODE_IN_SEC
mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 80h
out dx, eax
add dx, 04h
- mov eax, 370F0010h
+ mov eax, 34030070h
IFDEF MKF_EC_SUPPORT
or eax, (MKF_EC_SUPPORT shl 27t) ; Enable MC_LPC_EN
ENDIF
diff --git a/CRB/CSP.sdl b/CRB/CSP.sdl
index f07be0a..fac0d89 100644
--- a/CRB/CSP.sdl
+++ b/CRB/CSP.sdl
@@ -570,6 +570,16 @@ TOKEN
Help = "Main switch to enable Pfat support in Project, needs NvramSmiSupport Enabled"
Token = "NvramSmiSupport" "=" "1"
End
+TOKEN
+ Name = "NFC_SUPPORT_DXE_SUPPORT"
+ Value = "0"
+ Help = "Main switch to enable NfcSupportDxe support in DXE Phase"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+# Master = Yes
+End
## Override
## CRB\CSP.sdl
@@ -676,6 +686,54 @@ PCIDEVICE
End
## Board\SB\SB.sdl
+IRQLINK
+ Name = "LNKA"
+ Reg = 060h
+ IrqList = 3,4,5,6,7,10,11,12,14,15
+ InterruptType = LevelLow
+End
+IRQLINK
+ Name = "LNKB"
+ Reg = 061h
+ IrqList = 3,4,5,6,7,10,11,12,14,15
+ InterruptType = LevelLow
+End
+IRQLINK
+ Name = "LNKC"
+ Reg = 062h
+ IrqList = 3,4,5,6,7,10,11,12,14,15
+ InterruptType = LevelLow
+End
+IRQLINK
+ Name = "LNKD"
+ Reg = 063h
+ IrqList = 3,4,5,6,7,10,11,12,14,15
+ InterruptType = LevelLow
+End
+IRQLINK
+ Name = "LNKE"
+ Reg = 068h
+ IrqList = 3,4,5,6,7,10,11,12,14,15
+ InterruptType = LevelLow
+End
+IRQLINK
+ Name = "LNKF"
+ Reg = 069h
+ IrqList = 3,4,5,6,7,10,11,12,14,15
+ InterruptType = LevelLow
+End
+IRQLINK
+ Name = "LNKG"
+ Reg = 06ah
+ IrqList = 3,4,5,6,7,10,11,12,14,15
+ InterruptType = LevelLow
+End
+IRQLINK
+ Name = "LNKH"
+ Reg = 06bh
+ IrqList = 3,4,5,6,7,10,11,12,14,15
+ InterruptType = LevelLow
+End
PCIDEVICE
Title = "GbE Controller"
Bus = 00h
@@ -699,6 +757,34 @@ TOKEN
TokenType = Boolean
TargetH = Yes
End
+TOKEN
+ Name = "SB_IO_DECODE_IN_SEC"
+ Value = "1"
+ Help = "The value of SIO_PME_BASE_ADDRESS, '0' means no function."
+ TokenType = Boolean
+ TargetEQU = Yes
+End
+TOKEN
+ Name = "SB_GEN_DECODE_RANGE_1"
+ Value = "0x200"
+ Help = "The value of SIO_PME_BASE_ADDRESS, '0' means no function."
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetH = Yes
+ Range = "00 - 0FFFFh"
+ Token = "SB_IO_DECODE_IN_SEC" "=" "1"
+End
+TOKEN
+ Name = "SB_GEN_DECODE_RANGE_2"
+ Value = "0xA00"
+ Help = "The value of SIO_PME_BASE_ADDRESS, '0' means no function."
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetH = Yes
+ Range = "00 - 0FFFFh"
+ Token = "SB_IO_DECODE_IN_SEC" "=" "1"
+End
+
## Program PCH GPIO
TOKEN
Name = "PROGRAM_GPIO_TYPE"
diff --git a/actionitems.txt b/actionitems.txt
index d47dc2a..e109e76 100644
--- a/actionitems.txt
+++ b/actionitems.txt
@@ -1,14 +1,14 @@
2018/06/16
LAN EEPROM
2018/06/15
- Review decode algorithm
+// Review decode algorithm - 2018/06/16 done
// Clock Gen - 2018/06/15 no need
// GPIO Multifunction - 2018/06/15 done
// VBIOS - 2018/06/15 done
// Disable Gbe Controller - 2018/06/15 done
Discussion : LAN_DIS PULL H/L
Discussion : GPIO32 only GPIO mode
- Review tables in schematics
+// Review tables in schematics
SML1/2 CLK / DATA should not be connected to SIO
// SIO GPIO Porting - 2018/06/16 done
SIO Function Porting
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 22:44:39 +0000