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-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.c404
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.cif11
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.dxs68
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.mak107
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.sdl35
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNVdGPU.asl710
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGDmisc.asl241
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGPU.asl963
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvGPS.asl337
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvVentura.asl502
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.asl196
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.cif15
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.mak134
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.sdl47
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.c988
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.cif15
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.mak101
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.sdl110
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpitables.h254
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/ATdGPUPCH.asl179
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/ATiGDmiscPCH.asl277
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/ATiGPUPCH.asl1339
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/AtiSSDTPCH.asl145
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NVdGPUPCH.asl621
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NViGDmiscPCH.asl280
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NViGPUPCH.asl1078
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvGC6PCH.asl365
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvGPSPCH.asl331
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvSSDTPCH.asl365
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvVenturaPCH.asl521
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/OpSSDTPCH.asl292
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgTpvPCH.cif12
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgTpvPCH.mak132
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgTpvPCH.sdl53
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgUltAti.cif11
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgUltNvidia.cif15
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/ATdGPU.asl204
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/ATiGDmisc.asl302
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/ATiGPU.asl1359
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/AtiSSDT.asl143
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NVdGPU.asl806
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NViGDmisc.asl306
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NViGPU.asl1108
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvGC6.asl363
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvGPS.asl356
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvSSDT.asl391
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvVentura.asl546
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/OpSSDT.asl281
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgAti.cif11
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgNvidia.cif15
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgTpvPEG.cif12
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgTpvPEG.mak131
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgTpvPEG.sdl53
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/MXM30/MXM30.cif18
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/MXM30/MXM30.mak161
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/MXM30/MXM30.sdl135
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30Dxe.c377
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30Dxe.dxs105
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30Efi.c425
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30ElkCreek4.mxmbin0 -> 102 bytes
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30ElkCreekIII.mxmbin0 -> 85 bytes
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/MXM30/MxmInt15.asm553
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/MXM30/NBCIEfi.c367
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.asl79
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.c223
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.cif13
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.dxs65
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.mak109
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.sdl67
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.ssp59
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/SgTpv.cif20
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/SgTpv.mak266
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/SgTpv.sdl40
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/SgTpvDxe.c260
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/SgTpvDxe.dxs88
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/SgTpvPei.c266
-rw-r--r--Board/EM/SwitchableGraphics/SgTpv/SgTpvPei.dxs85
-rw-r--r--Board/EM/SwitchableGraphics/SwitchableGraphics.chmbin0 -> 131323 bytes
-rw-r--r--Board/EM/SwitchableGraphics/SwitchableGraphics.cif14
-rw-r--r--Board/EM/SwitchableGraphics/SwitchableGraphics.mak100
-rw-r--r--Board/EM/SwitchableGraphics/SwitchableGraphics.sd216
-rw-r--r--Board/EM/SwitchableGraphics/SwitchableGraphics.sdl155
-rw-r--r--Board/EM/SwitchableGraphics/SwitchableGraphics.unibin0 -> 7796 bytes
83 files changed, 21907 insertions, 0 deletions
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.c b/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.c
new file mode 100644
index 0000000..c179dbc
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.c
@@ -0,0 +1,404 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi S3 Save/SgTpvAcpiS3Save.c 6 7/16/13 5:04a Joshchou $
+//
+// $Revision: 6 $
+//
+// $Date: 7/16/13 5:04a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi S3 Save/SgTpvAcpiS3Save.c $
+//
+// 6 7/16/13 5:04a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Save the dGPU ssid to SANV for restore.
+//
+// 5 3/21/13 3:39a Joshchou
+//
+// 4 1/15/13 5:04a Joshchou
+// [TAG] EIP107237
+// [Category] New Feature
+// [Description] Support SG on ULT platform.
+//
+// 3 10/16/12 4:45a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Update for SA and ACPI RC 0.7.1
+// [Files] SgTpvAcpiS3Save.c
+//
+// 2 9/09/12 10:53p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] SgTpvAcpiS3Save.mak
+// SgTpvAcpiS3Save.c
+// SgTpvAcpiS3Save.dxs
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgTpvAcpiS3Save.cif
+// SgTpvAcpiS3Save.sdl
+// SgTpvAcpiS3Save.mak
+// SgTpvAcpiS3Save.c
+// SgTpvAcpiS3Save.dxs
+//
+//
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name: SgTpvAcpiS3Save.c
+//
+// Description: This file will save SG TPV related offset date for S3 resume restore.
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+#include <Token.h>
+#include <AmiCspLib.h>
+#include <AmiDxeLib.h>
+#include <Setup.h>
+#include <PCI.h>
+#include <SaGlobalNvsArea\SaGlobalNvsArea.h>
+#include "CpuRegs.h"
+//#include "CpuPlatformLib.h"
+
+#include "PchRegsPcie.h"
+
+//----------------------------------------------------------------------------
+// Constant, Macro and Type Definition(s)
+//----------------------------------------------------------------------------
+// Constant Definition(s)
+#define NVIDIA_VID 0x10DE
+#define NVOPT_SSID_OFFSET 0x40
+
+#define AMD_SVID_OFFSET 0x4C
+#define AMD_SDID_OFFSET 0x4E
+#define AMD_VID 0x1002
+
+// Function Prototype(s)
+VOID SgTpvAcpiS3Save (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+);
+
+//----------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//----------------------------------------------------------------------------
+// Variable Declaration(s)
+EFI_EVENT gEvent;
+SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL *SaGlobalNvsArea;
+
+// GUID Definition(s)
+EFI_GUID gEfiPciIoProtocolGuid = EFI_PCI_IO_PROTOCOL_GUID;
+EFI_GUID gSetupGuid = SETUP_GUID;
+EFI_GUID gSaGlobalNvsAreaProtocolGuid = SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL_GUID;
+EFI_GUID gEfiBootScriptSaveGuid = EFI_BOOT_SCRIPT_SAVE_GUID;
+
+CPU_FAMILY CpuFamilyId;
+
+
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: SgTpvAcpiS3Save_Init
+//
+// Description: This function is the entry point for this DXE. This function
+// will save SG TPV related offset date for S3 resume restore.
+//
+// Input: ImageHandle - Image handle
+// SystemTable - Pointer to the system table
+//
+// Output: Return Status based on errors that occurred while waiting for
+// time to expire.
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS
+SgTpvAcpiS3Save_Init (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN VariableSize = NULL;
+ SETUP_DATA *SetupData = NULL;
+
+
+
+ InitAmiLib(ImageHandle,SystemTable);
+
+ // Initialize Setup Data
+ Status = GetEfiVariable(
+ L"Setup",
+ &gSetupGuid,
+ NULL,
+ &VariableSize,
+ &SetupData
+ );
+
+
+ // If Select SG mode
+ if (SetupData->PrimaryDisplay == 4){
+
+ Status = CreateReadyToBootEvent( TPL_NOTIFY, SgTpvAcpiS3Save, \
+ NULL, &gEvent );
+
+ ASSERT_EFI_ERROR(Status);
+
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: SgTpvAcpiS3Save
+//
+// Description: This callback function is called when ReadyToBoot is
+// installed.
+//
+// Input: Event - Event of callback
+// Context - Context of callback.
+//
+// Output: EFI_SUCCESS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+VOID SgTpvAcpiS3Save (
+ IN EFI_EVENT Event,
+ IN VOID *Context )
+{
+
+ EFI_STATUS Status;
+ UINT16 VendorId;
+ UINT8 EndpointBus;
+ UINT16 Data16;
+ UINT32 Data32;
+ UINT16 Count;
+ UINTN Index;
+ UINTN VariableSize = NULL;
+ UINT32 RegEax, RegEbx, RegEcx, RegEdx;
+ SETUP_DATA *SetupData = NULL;
+ EFI_BOOT_SCRIPT_SAVE_PROTOCOL *BootScriptSave;
+ UINT8 RootPortDev;
+ UINT8 RootPortFun;
+
+
+ TRACE((-1, "==============SgTpvAcpiS3Save==========\n"));
+ // Initialize Setup Data
+ Status = GetEfiVariable(
+ L"Setup",
+ &gSetupGuid,
+ NULL,
+ &VariableSize,
+ &SetupData
+ );
+ if (EFI_ERROR (Status)) {
+ return ;
+ }
+ //
+ // Locate the SA Global NVS Protocol.
+ //
+ Status = pBS->LocateProtocol (
+ &gSaGlobalNvsAreaProtocolGuid,
+ NULL,
+ &SaGlobalNvsArea
+ );
+ if (EFI_ERROR (Status)) {
+ return ;
+ }
+
+ Status = pBS->LocateProtocol( \
+ &gEfiBootScriptSaveGuid, \
+ NULL, \
+ &BootScriptSave
+ );
+ if (EFI_ERROR (Status)) {
+ return ;
+ }
+
+ CPULib_CpuID(1, &RegEax, &RegEbx, &RegEcx, &RegEdx);
+ CpuFamilyId = (RegEax & CPUID_FULL_FAMILY_MODEL);
+
+ TRACE((-1, "CpuFamilyId = 0x%x\n",CpuFamilyId));
+ RootPortDev = 1;
+ RootPortFun = 0;
+
+ if (CpuFamilyId == EnumCpuHswUlt) {
+ /// For SwitchableGraphics support the dGPU is present on PCH RootPort
+ RootPortDev = PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS;
+ RootPortFun = SG_ULT_PORT_FUNC;
+ }
+
+ //EndpointBus = READ_PCI8 (0, 1, 0, PCI_SBUS);
+ EndpointBus = READ_PCI8 ( 0, RootPortDev, RootPortFun, PCI_SBUS);
+ //
+ // Endpoint Device Not found
+ //
+ if (EndpointBus == 0xFF) {
+ return ;
+ }
+
+ VendorId = READ_PCI16 (EndpointBus, 0, 0, PCI_VID);
+ //
+ // if Device Not found or Devide is not AMD and Nvidia VGA device
+ //
+ if (VendorId == 0xFFFF || ((VendorId != NVIDIA_VID) && (VendorId != AMD_VID))) {
+ return ;
+ }
+
+
+ //
+ // Store the Root port Bus assignemnt for S3 resume path
+ //
+
+ Data32 = READ_PCI32 (0, RootPortDev, RootPortFun, PCI_PBUS);
+ BOOT_SCRIPT_S3_MEM_WRITE_MACRO (
+ BootScriptSave,
+ EfiBootScriptWidthUint32,
+ NB_PCIE_CFG_ADDRESS(0, RootPortDev, RootPortFun, PCI_PBUS),
+ 1,
+ &Data32
+ );
+
+ Data16 = READ_PCI16 (0, RootPortDev, RootPortFun, PCI_BAR3);
+ BOOT_SCRIPT_S3_MEM_WRITE_MACRO (
+ BootScriptSave,
+ EfiBootScriptWidthUint16,
+ NB_PCIE_CFG_ADDRESS(0, RootPortDev, RootPortFun, PCI_BAR3),
+ 1,
+ &Data16
+ );
+
+ //
+ // Store the Generic PCI config space of dGPU for S3 resume path
+ //
+
+ for (Count = 4; Count < 0x40; Count+=4) {
+ Data32 = READ_PCI32 (EndpointBus, 0, 0, Count);
+ BOOT_SCRIPT_S3_MEM_WRITE_MACRO (
+ BootScriptSave,
+ EfiBootScriptWidthUint32,
+ NB_PCIE_CFG_ADDRESS(EndpointBus, 0, 0, Count),
+ 1,
+ &Data32
+ );
+ }
+
+ switch(VendorId){
+ case NVIDIA_VID:
+ //
+ // if PEG is NVIDIA and supports Muxless mode
+ //
+ if (SetupData->SgMuxMode == 2){
+
+
+ //
+ // Set a unique SSID on the Nv Optimus Graphics
+ //
+ Data32 = READ_PCI32 (0, 2, 0, PCI_SVID);
+ WRITE_PCI32 (EndpointBus, 0, 0, NVOPT_SSID_OFFSET, Data32);
+
+ SaGlobalNvsArea->Area->DgpuSsid = READ_PCI32 (EndpointBus, 0, 0, NVOPT_SSID_OFFSET); // DEBUG
+ TRACE((-1, "DgpuSsid in SgTpvAcpiS3Save =0x%X\n", SaGlobalNvsArea->Area->DgpuSsid));
+
+ BOOT_SCRIPT_S3_MEM_WRITE_MACRO (
+ BootScriptSave,
+ EfiBootScriptWidthUint32,
+ NB_PCIE_CFG_ADDRESS(EndpointBus, 0, 0, NVOPT_SSID_OFFSET),
+ 1,
+ &Data32
+ );
+
+ //
+ // Disable Peg Endpoint Function 1 (HDMI Support)
+ //
+ Data16 = READ_PCI16(EndpointBus, 0, 0, PCI_CMD);
+ Data16 = (Data16 & (!(BIT0+BIT1+BIT2)));
+ Data16 = (Data16 | (BIT1+BIT2));
+ WRITE_PCI16 (EndpointBus, 0, 0, PCI_CMD, Data16);
+
+ Data32 = READ_PCI32 (EndpointBus, 0, 0, PCI_BAR0); // Resd Bar 0 MMIO address
+ Data32 += 0x88488;
+ Index = (UINT32)Data32;
+ *(UINT32*)(Data32) &= ~BIT25; // Clear Bit 25
+ // Keep HDA enabled on cold boots. Optimus Gfx driver shall disable it if not needed
+ // or read from CMOS...
+ Data32 = ((SaGlobalNvsArea->Area->SgFeatureList & 0x2) << 24); // dGPUAudioCodec bit2
+ BOOT_SCRIPT_S3_MEM_WRITE_MACRO (
+ BootScriptSave,
+ EfiBootScriptWidthUint32,
+ (UINTN)(Index),
+ 1,
+ &Data32
+ );
+
+ }
+ break;
+ case AMD_VID:
+ //
+ // if PEG is AMD
+ //
+ //
+ // Set a unique SSID on the AMD MXM
+ //
+ Data32 = READ_PCI32 (0, 2, 0, PCI_SVID);
+ WRITE_PCI32 (EndpointBus, 0, 0, AMD_SVID_OFFSET, Data32);
+
+ SaGlobalNvsArea->Area->DgpuSsid = READ_PCI32 (EndpointBus, 0, 0, AMD_SVID_OFFSET); // DEBUG
+ TRACE((-1, "DgpuSsid in SgTpvAcpiS3Save =0x%X\n", SaGlobalNvsArea->Area->DgpuSsid));
+
+ BOOT_SCRIPT_S3_MEM_WRITE_MACRO (
+ BootScriptSave,
+ EfiBootScriptWidthUint32,
+ NB_PCIE_CFG_ADDRESS(EndpointBus, 0, 0, AMD_SVID_OFFSET),
+ 1,
+ &Data32
+ );
+
+ break;
+ default:
+ //
+ // either means the Device ID is not on the list of devices we know - we return from this function
+ break;
+ //
+ }
+
+ pBS->CloseEvent(Event);
+}
+
+
+
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012 American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.cif b/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.cif
new file mode 100644
index 0000000..a606e64
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.cif
@@ -0,0 +1,11 @@
+<component>
+ name = "Sg Acpi S3 Save"
+ category = ModulePart
+ LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\AcpiS3Save"
+ RefName = "SgTpvAcpiS3Save"
+[files]
+"SgTpvAcpiS3Save.sdl"
+"SgTpvAcpiS3Save.mak"
+"SgTpvAcpiS3Save.c"
+"SgTpvAcpiS3Save.dxs"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.dxs b/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.dxs
new file mode 100644
index 0000000..97e1840
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.dxs
@@ -0,0 +1,68 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi S3 Save/SgTpvAcpiS3Save.dxs 2 9/09/12 10:53p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 10:53p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi S3 Save/SgTpvAcpiS3Save.dxs $
+//
+// 2 9/09/12 10:53p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] SgTpvAcpiS3Save.mak
+// SgTpvAcpiS3Save.c
+// SgTpvAcpiS3Save.dxs
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgTpvAcpiS3Save.cif
+// SgTpvAcpiS3Save.sdl
+// SgTpvAcpiS3Save.mak
+// SgTpvAcpiS3Save.c
+// SgTpvAcpiS3Save.dxs
+//
+//
+//
+//**********************************************************************
+#include <Protocol\GlobalNvsArea\GlobalNvsArea.h>
+#include <protocol\AcpiSupport.h>
+
+DEPENDENCY_START
+ EFI_ACPI_SUPPORT_GUID AND
+ EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID
+DEPENDENCY_END
+
+
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//**************************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.mak b/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.mak
new file mode 100644
index 0000000..db66ed0
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.mak
@@ -0,0 +1,107 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi S3 Save/SgTpvAcpiS3Save.mak 4 1/15/13 5:06a Joshchou $
+#
+# $Revision: 4 $
+#
+# $Date: 1/15/13 5:06a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi S3 Save/SgTpvAcpiS3Save.mak $
+#
+# 4 1/15/13 5:06a Joshchou
+# [TAG] EIP107237
+# [Category] New Feature
+# [Description] Support SG function onULT platform.
+#
+# 3 10/16/12 4:46a Joshchou
+# [TAG] None
+# [Category] New Feature
+# [Description] Update for SA and ACPI RC 0.7.1
+# [Files] SgTpvAcpiS3Save.mak
+#
+# 2 9/09/12 10:53p Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Tpv module support for sharkbay.
+# [Files] SgTpvAcpiS3Save.mak
+# SgTpvAcpiS3Save.c
+# SgTpvAcpiS3Save.dxs
+#
+# 1 6/27/11 5:27a Alanlin
+# [TAG] EIP61848
+# [Category] New Feature
+# [Description] Initial check-in.Integrated SwitchableGraphics Intel
+# Reference code 0.6.0
+# [Files] SgTpvAcpiS3Save.cif
+# SgTpvAcpiS3Save.sdl
+# SgTpvAcpiS3Save.mak
+# SgTpvAcpiS3Save.c
+# SgTpvAcpiS3Save.dxs
+#
+#
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name: SgTpvAcpiS3Save.mak
+#
+# Description: Make file to build SG TPV ACPI components
+#
+#
+#<AMI_FHDR_END>
+#*************************************************************************
+SgTpv : SgTpvAcpiS3Save
+
+SgTpvAcpiS3Save: $(BUILD_DIR)\SgTpvAcpiS3Save.mak SgTpvAcpiS3SaveBin
+
+#---------------------------------------------------------------------------
+# Generic SgTpvAcpiTables dependencies
+#---------------------------------------------------------------------------
+$(BUILD_DIR)\SgTpvAcpiS3Save.mak : $(SGTPV_ACPIS3_DIR)\SgTpvAcpiS3Save.cif $(BUILD_RULES)
+ $(CIF2MAK) $(SGTPV_ACPIS3_DIR)\SgTpvAcpiS3Save.cif $(CIF2MAK_DEFAULTS)
+
+
+#---------------------------------------------------------------------------
+# Create SgTpvAcpiS3Save DXE Component
+#---------------------------------------------------------------------------
+
+SgTpvAcpiS3SaveBin : $(AMIDXELIB) $(AMICSPLib) $(INTEL_SA_PROTOCOL_LIB) $(CpuPlatformLib_LIB) $(PchPlatformSmmLib_LIB)
+ $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+ /f $(BUILD_DIR)\SgTpvAcpiS3Save.mak all\
+ GUID=C18B8105-AB89-44de-8D37-50B31FAE5D1E\
+ "MY_INCLUDES= $(ACPI_PLATFORM_INCLUDES) $(PLATFORM_INFO_INCLUDES) $(PROJECT_CPU_INCLUDES) /I $(INTEL_SA_PROTOCOL_LIB_DIR)"\
+ ENTRY_POINT=SgTpvAcpiS3Save_Init\
+ OBJECTS="$(SgTpvAcpiS3Save_OBJECTS)" \
+ TYPE=BS_DRIVER \
+ DEPEX1=$(SGTPV_ACPIS3_DIR)\SgTpvAcpiS3Save.dxs\
+ DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+ COMPRESS=1
+
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.sdl b/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.sdl
new file mode 100644
index 0000000..e7f6e7e
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiS3Save/SgTpvAcpiS3Save.sdl
@@ -0,0 +1,35 @@
+TOKEN
+ Name = "SgTpvAcpiS3Save_SUPPORT"
+ Value = "1"
+ Help = "Main switch to enable SgAcpiS3Save support in Project"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ Master = Yes
+End
+
+PATH
+ Name = "SGTPV_ACPIS3_DIR"
+ Help = "Path to SG AcpiS3Save folder"
+End
+
+MODULE
+ File = "SgTpvAcpiS3Save.mak"
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\SGTPVAcpiS3Save.ffs"
+ Parent = "FV_MAIN"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "SgTpvAcpiS3Save_OBJECTS"
+ InvokeOrder = ReplaceParent
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\$(SGTPV_ACPIS3_DIR)\SgTpvAcpiS3Save.obj"
+ Parent = "SgTpvAcpiS3Save_OBJECTS"
+ InvokeOrder = AfterParent
+End
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNVdGPU.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNVdGPU.asl
new file mode 100644
index 0000000..b8f2b90
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNVdGPU.asl
@@ -0,0 +1,710 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNVdGPU.asl 2 9/09/12 11:01p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:01p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNVdGPU.asl $
+//
+// 2 9/09/12 11:01p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] OEMSSDT.mak
+// OEMSSDT.asl
+// OEMNVdGPU.asl
+// OEMNViGPU.asl
+// OEMNViGDmisc.asl
+// OEMNvVentura.asl
+// OEMNvGPS.asl
+// OEMSSDT.cif
+//
+// 3 12/26/11 5:00a Alanlin
+// 1.Change OperationRegion of BPCI access type from "AnyAcc" to
+// "DWordAcc" for nVidia VGA.
+//
+//
+// 1 12/12/11 9:10p Alanlin
+//
+//
+//**********************************************************************
+// PEG Endpoint PCIe Base Address.
+External(EBAS)
+External(NVHA)
+
+#ifdef OPTIMUS_DSM_GUID
+Scope(PCI_SCOPE){
+
+ Name(OTM, "OTMACPI 2010-Mar-09 12:08:26") // OTMACPIP build time stamp.
+} // end of Scope
+#endif
+
+Scope(DGPU_SCOPE)
+{
+
+//<AMI_SHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: NVHM
+//
+// Description: Nvidia NVHG (dGPU) OperationRegion
+// OpRegion address (NVHA)is defined in IDG Nvs OpRegion
+//
+//-------------------------------------------------------------------------
+//<AMI_SHDR_END>
+ OperationRegion(NVHM,SystemMemory, NVHA, 0x20400)
+ Field(NVHM, DWordAcc, NoLock, Preserve)
+ {
+ // OpRegion Header
+
+ NVSG, 0x80, // (000h) Signature-"NVSG".
+ NVSZ, 0x20, // (010h) OpRegion Size in KB.
+ NVVR, 0x20, // (014h) OpRegion Version.
+
+ // NVHG data
+
+ NVHO, 0x20, // (018h)NVHM opregion address
+ RVBS, 0x20, // (01Ch)NVIDIA VBIOS image size
+ // (020h)for _ROM
+ RBF1, 0x80000, // 0x10000 bytes in bits
+ RBF2, 0x80000, // 0x10000 bytes in bits
+ MXML, 0x20, // Mxm3 buffer length
+#if MXM30_SUPPORT
+ MXM3, MXM_ROM_MAX_SIZE_bits // MXM 3.0 Data buffer
+#else
+ MXM3, 0x640 // MXM 3.0 Data buffer
+#endif
+
+ }
+
+ Name(OPCE, 2) // Optimus Power-Control ENABLE
+ // 2: The platform should not power down the GPU subsystem
+ // in the _PS3 method (Default)
+ // 3: The platform should power down the GPU subsystem
+ // at the end of the _PS3 ACPI method
+
+ Name(DGPS, Zero)// Power State. dummy control field. Can be a GPIO in EC or PCH
+
+#ifdef OPTIMUS_DSM_GUID
+
+//If dGPU power control is available....
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _PSC
+//
+// Description: Curent dGPU power state, 0-D0, 3-D3, etc.
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Name(_PSC, Zero)
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _PS0
+//
+// Description: dGPU power ON control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(_PS0, 0, NotSerialized)
+ {
+ P8DB(0xB0, OPCE, 2000)
+ Store(Zero, _PSC)
+ If(LNotEqual(DGPS, Zero))
+ {
+ _ON() // with Optimus w/a
+ Store(Zero, DGPS)
+ }
+ }
+
+ Method(_PS1, 0x0, NotSerialized)
+ {
+ Store(One, _PSC)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _PS3
+//
+// Description: dGPU power OFF control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(_PS3, 0, NotSerialized)
+ {
+ P8DB(0xB3, OPCE, 2000)
+ If(LEqual(OPCE, 0x3))
+ {
+ If(LEqual(DGPS, Zero))
+ {
+ _OFF() // w Optimus w/a
+ Store(One, DGPS)
+ }
+ Store(0x2, OPCE) // Reset NV GPU power down flag
+ }
+ Store(0x3, _PSC)
+ }
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _STA
+//
+// Description: dGPU power status.
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_STA,0x0)
+ {
+ Return(0x0F) // Always return DGPU is powered-ON
+ }
+
+#endif // OPTIMUS_DSM_GUID
+
+#if HYBRID_DSM_GUID || MXM_DSM_GUID
+// NON-OPTIMUS mode - MUXed
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _IRC
+//
+// Description: In-rush current
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+// Name(_IRC, 0)
+ Method(_IRC,0,Serialized)
+ {
+ Return(0x00)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _ON
+//
+// Description: dGPU power ON control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_ON,0,Serialized)
+ {
+ SGON() // OEM Mxm Power On
+
+ //Ask OS to do a PnP rescan
+ Notify(PEG_SCOPE,0)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _OFF
+//
+// Description: dGPU power OFF control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_OFF,0,Serialized)
+ {
+ SGOF() // OEM Mxm Power On
+
+ //Ask OS to do a PnP rescan
+ Notify(PEG_SCOPE,0)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _STA
+//
+// Description: Returns curent dGPU power/presence state
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_STA,0,Serialized)
+ {
+ Return(SGST()) // OEM Mxm Power status
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: MXMX
+//
+// Description: Display DDC Mux Control
+//
+// Input:
+// Arg0: Get/Set DDC/Aux Mux State
+// 0- Acquire DDC/Aux Mux on this GPU
+// 1- Release Mux from this GPU
+// 2- Get Mux state
+//
+// Output:
+// 0, Not Acquired.
+// if Arg0 = 0 or 1, Non-Zero return indicates success acquiring MUX
+// (and MUX has switched to this output)
+// if Arg0 = 2, Non-Zero return indicates MUX is currently set to this output
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (MXMX, 1, Serialized)
+ {
+ P8DB(0x99, Arg0, 2000)
+
+ If (LEqual (Arg0, 0))
+ {
+
+ //Acquire DDC/AUX mux
+ // No mutex implemented. No need to acquire mutex.
+ // Set mux to dGPU
+// SGPO(DSEL, 1)// dGPU_SELECT#
+ SGPO(ESEL, 1)// use EDID_SELECT# as Mutex flag
+ Return(1)
+ }
+
+ If (LEqual (Arg0, 1))
+ {
+
+ //Release DDC/AUX mux
+ // No mutex implemented. No need to release mutex.
+ // 2-way mux. Hence no need to do anything
+ Return(0x1)
+
+ }
+
+ If (LEqual (Arg0, 2))
+ {
+
+ //Get ddc/aux mux status for dGPU
+ Return(SGPI(ESEL))
+ }
+
+ Return(0x0) // mutex not acquired
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: MXDS
+//
+// Description: Display output MUX control
+//
+// Input:
+// Arg0:
+// 0 - Get Mux state
+// 1 - Set Display to active on this GPU
+// 2 - Set Backlight control to active on this GPU
+// 3 - Set Display & Backlight to active on this GPU
+//
+// Output:
+// If Arg0 = 0, Error = Display is not MUXed
+// Else return value of the state of the MUX
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(MXDS, 1, Serialized)
+ {
+ P8DB(0x9A, Arg0, 2000)
+
+ If(LEqual (Arg0, 0))
+ {
+ //Get display mux status for dGPU
+ return(SGPI(DSEL))
+ } else
+// If(LOr(LEqual (Arg0, 1), LEqual (Arg0, 2)))
+ {
+ //Set display mux to dgpu
+ SGPO(DSEL, 1) // dGPU_SELECT
+ SGPO(PSEL, 1) // dGPU_PWM_SELECT
+ }
+
+ Return (0)
+ }
+#endif // MXM && HYBRID
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _ROM
+//
+// Description: Video ROM data buffer
+//
+// Input:
+// Arg0: Integer Offset of the graphics device ROM data
+// Arg1: Integer Size of the buffer to fill in (up to 4K)
+//
+// Output:
+// Buffer Buffer of requested video ROM bytes
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_ROM,2)
+ {
+
+ Store (Arg0, Local0)
+ Store (Arg1, Local1)
+
+ P8DB(0x44, Local1, 100)
+// CreateWordField (RBF1, 2, RVBS) // Vbios image size
+// ShiftLeft(And(RVBS,0xff), 9, RVBS) // size in Bytes (* 512)
+
+ If (LGreater (Local1, 0x1000))
+ {
+ Store (0x1000, Local1)
+ }
+ If (LGreater (Local0, 0x20000))
+ {
+ Return(Buffer(Local1){0})
+ }
+// If (LGreater (Local0, RVBS))
+// {
+// Return(Buffer(Local1){0})
+// }
+//// If (LGreater (Add (Local0, Local1), RVBS))
+//// {
+//// Store (0x00, Local0)
+//// }
+
+ Multiply (Local1, 0x08, Local3)
+ Name (ROM1, Buffer (0x10000) {0})
+ Name (ROM2, Buffer (Local1) {0})
+
+ If(LLess(Local0,0x10000))
+ {
+ Store (RBF1, ROM1)
+ }
+ Else
+ {
+ Subtract(Local0,0x10000,Local0)
+ Store (RBF2, ROM1)
+ }
+
+ Multiply (Local0, 0x08, Local2)
+ CreateField (ROM1, Local2, Local3, TMPB)
+ Store (TMPB, ROM2)
+ Return (ROM2)
+ }
+
+//
+// Check for Nvidia _DSM UUIDs
+//
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HDSM
+//
+// Description: Device Specific Methods for Hybrid dGPU (may be invoked from iGD as well)
+// Implements Mxm and SG specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// nVidia
+// MXM dGPU GUID :9D95A0A0-0060-4D48-B34D-7E5FEA129FD4
+//
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(HDSM, 4, SERIALIZED)
+ {
+
+#ifdef MXM_DSM_GUID
+
+ If(LEqual(Arg0, ToUUID("4004A400-917D-4cf2-B89C-79B62FD55665")))
+ {
+
+ P8DB(0xEE, Arg2, 1000)
+
+ Switch(ToInteger(Arg2))
+ {
+ //
+ // Function 0: MXM_FUNC_MXSS
+ //
+ case (0)
+ {
+ //Sub-Functions 0,16,24 are supported
+ Return(ToBuffer(0x01010001))
+ }
+
+ //
+ // Function 24: MXM_FUNC_MXMI
+ //
+ case (24)
+ {
+ Return(ToBuffer(0x300)) // MXM 1.101 defines revision as 0x300
+ // Return(ToBuffer(0x30)) // MXM 1.101 defines revision as 0x300
+ }
+
+ //
+ // Function 16: MXM_FUNC_MXMS
+ //
+ case (16)
+ {
+ If(LEqual (Arg1, 0x300)) // MXM 1.101 defines revision as 0x300
+ {
+#if MXM30_SUPPORT
+ // calculate true length of MXM block
+ CreateWordField(MXM3, 6, MXLN)
+ Add(MXLN, 8, Local0) // Add length of MXM header
+ CreateField(MXM3, 0, Local0, MXM)
+ Return(ToBuffer(MXM))
+#else
+ // ElkCreek 4 Mxm data structure
+ Name(MXM3, Buffer()
+ {
+ 0x4d, 0x58, 0x4d, 0x5f, 0x03, 0x00, 0x5d, 0x00,
+ 0x30, 0x11, 0xb8, 0xff, 0xf9, 0x3e, 0x00, 0x00,
+ 0x00, 0x00, 0x0a, 0xf0, 0xf9, 0x3e, 0x00, 0x00,
+ 0x60, 0xe9, 0xd0, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x60, 0x6a, 0xda, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x20, 0x2b, 0xe2, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x60, 0x6c, 0xea, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x20, 0x6a, 0xda, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x20, 0x6c, 0xea, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x01, 0x90, 0x01, 0x00, 0x03, 0x00, 0x90, 0x01,
+ 0x13, 0x00, 0x90, 0x01, 0xe5, 0x0d, 0x01, 0x01,
+ 0x01, 0x00, 0x00, 0x00, 0xe5, 0x0d, 0x01, 0x03,
+ 0x00, 0x90, 0xd8, 0x09, 0x11, 0x0a
+ })
+ Return(MXM3)
+#endif
+ }
+ }
+ } // switch
+ Return(0x80000002) //MXM_ERROR_UNSUPPORTED - FunctionCode or SubfunctionCode not supported
+ } // "4004A400-917D-4cf2-B89C-79B62FD55665"
+
+#endif // MXM_DSM_GUID
+
+ Return (0x80000001) //MXM_ERROR_UNSPECIFIED
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _DSM Device Specific Method for dGPU device
+//
+// Description: Implement Mxm and SG specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// MXM dGPU GUID :9D95A0A0-0060-4D48-B34D-7E5FEA129FD4
+// NBCI GUID :D4A50B75-65C7-46F7-BfB7-41514CEA0244
+// Ventura GUID :95DB88FD-940A-4253-A446-70CE0504AEDF
+// Optimus DSM_GUID :A486D8F8-0BDA-471B-A72B-6042A6B5BEE0
+//
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_DSM,4,SERIALIZED)
+ {
+ CreateByteField (Arg0, 3, GUID)
+ P8DB(0xDD, GUID, 1000)
+ //
+ // Check for Nvidia _DSM UUIDs
+ //
+ // common _DSM for dGPU and iGPU: NBCI, SG DSM, Ventura
+ return(IGPU_SCOPE.HDSM(Arg0, Arg1, Arg2, Arg3))
+ }
+
+
+#ifdef OPTIMUS_DSM_GUID
+///////////////////////////////////////////////////////////////////
+// Nvidia Optimus driver w/a. Save PCI context of PEG Video card
+///////////////////////////////////////////////////////////////////
+// PEG Endpoint PCIe Base Address.
+ OperationRegion (BPCI, SystemMemory, EBAS, 0x1000)
+ Field (BPCI, DWordAcc, NoLock, Preserve)
+ {
+// VGAR, 2048,
+ Offset(0x04),
+ //PCIC, 16,
+ PCIC, 32,
+
+ Offset(0x10),
+ GMM1, 32,
+
+ Offset(0x14),
+ GMM2, 32,
+
+ //Offset(0x18),
+ //GMB1, 32,
+
+ Offset(0x1C),
+ GMM3, 32,
+
+ Offset(0x24),
+ GIO1, 32,
+
+ Offset(0x3C),
+ //GIRQ, 8,
+ GIRQ, 32,
+
+ Offset(0x40),
+ SID, 32,
+
+// Offset(0x88),
+// , 5,
+// RETR, 1,
+
+ //Offset(0x114),
+ //VC0R, 32,
+ Offset(0x488),
+ , 25,
+ NHDM, 1 // HDA Enable bit.
+ }
+
+// Create the dGPU PCI Configuration data buffer for dGPU save/restore resources
+ Name(BUFF, Buffer(32){}) // Create dGPU PCI Configuration data buffer as BUFF
+ CreateDWordField(BUFF, 0x00, BUF1) //
+ CreateDWordField(BUFF, 0x01, BUF2) //
+ CreateDWordField(BUFF, 0x02, BUF3) //
+ CreateDWordField(BUFF, 0x03, BUF4) //
+ CreateDWordField(BUFF, 0x04, BUF5) //
+ CreateDWordField(BUFF, 0x05, BUF6) //
+ CreateDWordField(BUFF, 0x06, BUF7) //
+ CreateDWordField(BUFF, 0x07, BUF8) //
+
+// TEST !!! TEST !!! TEST !!!!
+// NvOptimus should not be be using _ON and _OFF methods for power cycling
+// Used here for testing with Intel ElkCreek Mxm interposer
+//
+ Name(CTXT, Zero)// Save Context flag
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _ON
+//
+// Description: Optimus w/a for before dGPU _ON
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(_ON, 0, Serialized)
+ {
+ P8DB(0x01, 0x11, 2000)
+
+ // OEM Mxm Power status
+ SGON()
+
+// Nvidia Optimus driver w/a. Restore saved PCI context of PEG Video card
+// Store(BUF8,VC0R)
+
+ Store(BUF1,PCIC)
+ Store(BUF2,GMM1)
+ Store(BUF3,GMM2)
+ Store(BUF4,GMM3)
+ Store(BUF5,GIO1)
+ Store(BUF6,GIRQ)
+ Store(BUF7,SID)
+
+// Store(1, RETR) // retrain PCI-E bus
+//+<
+// doesn't look like we need delay here...
+// Sleep(0x64)
+
+ Store(SWSMI_NVOEM_CMOS_R, SSMP) // Read CMOS:AudioCodec flag to AcpiNvs:SGFL
+// Clear HDA enable bit if flag not set
+ if(LEqual(And(SGFL, 2), 0))
+ {
+ Store(0, NHDM)
+ }
+
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _OFF
+//
+// Description: Optimus w/a before dGPU _OFF
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(_OFF, 0, Serialized)
+ {
+
+ P8DB(0x0F, 0xFF, 2000)
+
+// store PCI context only once
+ If(LEqual(CTXT, Zero))
+ {
+// Nvidia Optimus driver w/a. Save PCI context of PEG Video card
+// Store(VGAR, VGAB)
+//+>save dGPU resources
+ Store(PCIC,BUF1)
+ Store(GMM1,BUF2)
+ Store(GMM2,BUF3)
+ Store(GMM3,BUF4)
+ Store(GIO1,BUF5)
+ Store(GIRQ,BUF6)
+ Store(SID,BUF7)
+// Store(VC0R,BUF8)
+//+<
+ Store(1, CTXT)
+ }
+ SGOF()
+
+ }
+#endif
+} // end Scope(DGPU_SCOPE)
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGDmisc.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGDmisc.asl
new file mode 100644
index 0000000..6e3ee2e
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGDmisc.asl
@@ -0,0 +1,241 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNViGDmisc.asl 2 9/09/12 11:01p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:01p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNViGDmisc.asl $
+//
+// 2 9/09/12 11:01p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] OEMSSDT.mak
+// OEMSSDT.asl
+// OEMNVdGPU.asl
+// OEMNViGPU.asl
+// OEMNViGDmisc.asl
+// OEMNvVentura.asl
+// OEMNvGPS.asl
+// OEMSSDT.cif
+//
+// 1 12/12/11 9:10p Alanlin
+//
+//
+//
+//**********************************************************************
+
+External(DSEN)
+External(IGPU_SCOPE.CDCK)
+External(DGPU_SCOPE.DD02)
+External(IGPU_SCOPE.IDAB, MethodObj)
+
+//Do not remove this function.
+Method(IDAB, 0, Serialized)
+{
+ If (CondRefOf(IGPU_SCOPE.IDAB))
+ {
+ IGPU_SCOPE.IDAB()
+ }
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HGAS
+//
+// Description: HG Adaptor select, notify
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HGAS) //HG Adaptor select
+{
+ //Stateless button/Hotkey supporting 3 states - Power Saver, Adaptive and Perf
+
+ Increment(IGPU_SCOPE.GPSS)
+ Mod(IGPU_SCOPE.GPSS, 3, IGPU_SCOPE.GPSS)
+
+ Store(1,IGPU_SCOPE.GPPO)
+ Store(1,IGPU_SCOPE.SGNC) //indicate 'policy select' change
+
+ Notify(IGPU_SCOPE, 0xD0)
+ Notify(PCI_SCOPE.WMI1, 0xD0) // Mirror Notify on WMI1
+
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HBRT
+//
+// Description: Send backlight notifications to the DGPU LFP device
+// This is required for Win7 and is backward compatible with Vista
+//
+// Input: Arg0 - 4 - Brightnes Down, 3- Up
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HBRT, 1 , Serialized)
+{
+ Store(Arg0,IGPU_SCOPE.DACE)
+
+ If(And(4,DSEN)) //Note: DSEN variable is expected to be set by IGD miniport only.
+ {
+ If(LEqual(Arg0,4))
+ {
+ Notify(DGPU_SCOPE.DD02,0x87) //Note: DD02 is hardcoded as the LFP device in intelgfx.asl
+ }
+ If(LEqual(Arg0,3))
+ {
+ Notify(DGPU_SCOPE.DD02,0x86)
+ }
+ }
+
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HPFS
+//
+// Description: Panel Fitting Hot Key
+//
+// Input: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HPFS, 0, Serialized) //Panel Fitting Hot Key
+{
+ //
+ // HG Handling of Panel Fitting Switch
+ //
+
+ Store(5,IGPU_SCOPE.DACE) // Indicate display scaling hot key event
+ Store(2,IGPU_SCOPE.SGNC) // Indicate platpolicy change
+
+ //
+ // Expansion Mode toggling
+ //
+ Increment(IGPU_SCOPE.GPSP)
+ Mod(IGPU_SCOPE.GPSP, 4 , IGPU_SCOPE.GPSP)
+
+ Notify(IGPU_SCOPE,0xDC)
+
+}
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HNOT
+//
+// Description: Notification handler for Switchable graphics. Called from GNOT()
+//
+// Input: Arg0 = Current event type:
+// 1 = display switch
+// 2 = lid
+// 3 = dock (!!!!!Acpi ref code, Method(GDCK)sends 4 for Dock notifications )
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method (HNOT, 1, Serialized)
+{
+ Switch(ToInteger(Arg0))
+ {
+ case(1) //Display Switch event
+ {
+ Store(3,IGPU_SCOPE.SGNC) // indicate 'Displaystatus' change
+ Store(1,IGPU_SCOPE.DACE)
+ Notify(IGPU_SCOPE, 0x80)
+ Notify(PCI_SCOPE.WMI1, 0x80) // Mirror Notify on WMI1
+ }
+
+ case (2) //Lid switch event
+ {
+ //Note: NV clarified that only LDES needs to be set
+ Store(1,IGPU_SCOPE.LDES)
+ Notify(IGPU_SCOPE, 0xDB)
+ Notify(PCI_SCOPE.WMI1, 0xDB) // Mirror Notify on WMI1
+ }
+// case (3) //Dock event
+ case (4) //Dock event (!!!Acpi ref code, Method(GDCK)sends 4 for Dock notifications)
+ {
+ Store(IGPU_SCOPE.CDCK, IGPU_SCOPE.DKST) // Store the current dock state
+ Notify(IGPU_SCOPE, 0x81)
+ Notify(PCI_SCOPE.WMI1, 0x81) // Mirror Notify on WMI1
+ }
+
+ Default
+ {
+ Notify(IGPU_SCOPE,0x80)
+ }
+
+ }
+
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: CHPS
+//
+// Description: Shows current Hybrid Policy status on Port80 header
+// Adaptive -> 1, Save power -> 2 and High performance -> 3
+//
+// Input: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(CHPS)
+{
+ P8DB(0xEC, Add(IGPU_SCOPE.GPSS, 1), 2000)
+}
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HDOS
+//
+// Description: Check if the _DOS flag was set during the hot key handling
+//
+// Input: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HDOS, 0, Serialized)
+{
+ If(LEqual(IGPU_SCOPE.DOSF,1))
+ {
+ Store(1,IGPU_SCOPE.SGNC) // indicate 'policy select' change
+ Notify(IGPU_SCOPE,0xD0)
+ Notify(PCI_SCOPE.WMI1, 0xD0) // Mirror Notify on WMI1
+ Store(0, IGPU_SCOPE.DOSF) // Clear the DOSF
+ }
+}
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGPU.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGPU.asl
new file mode 100644
index 0000000..ae569d1
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGPU.asl
@@ -0,0 +1,963 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNViGPU.asl 2 9/09/12 11:01p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:01p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNViGPU.asl $
+//
+// 2 9/09/12 11:01p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] OEMSSDT.mak
+// OEMSSDT.asl
+// OEMNVdGPU.asl
+// OEMNViGPU.asl
+// OEMNViGDmisc.asl
+// OEMNvVentura.asl
+// OEMNvGPS.asl
+// OEMSSDT.cif
+//
+// 1 12/12/11 9:10p Alanlin
+//
+//
+//**********************************************************************
+External(NVGA)
+
+External(NXD1)
+External(NXD2)
+External(NXD3)
+External(NXD4)
+External(NXD5)
+External(NXD6)
+External(NXD7)
+External(NXD8)
+External(DID1)
+External(DID2)
+External(DID3)
+External(DID4)
+External(DID5)
+External(DID6)
+External(DID7)
+External(DID8)
+
+Scope (IGPU_SCOPE)
+{
+
+ Method(_INI,0)
+ {
+ //DIDx values have been changed in MxmAcpiTables.c
+ //Port - D to be used for eDP only and not as DFP. Hence generating a new toggle list
+ Store(DID1, Index(TLPK,0)) // CRT
+ Store(DID2, Index(TLPK,2)) // LFP
+ Store(DID3, Index(TLPK,4)) // DP_B
+ Store(DID4, Index(TLPK,6)) // HDMI_B
+ Store(DID5, Index(TLPK,8)) // HDMI_C
+ Store(DID6, Index(TLPK,10)) // DP_D
+ Store(DID7, Index(TLPK,12)) // HDMI_D
+ Store(DID2, Index(TLPK,14)) // LFP+CRT
+ Store(DID1, Index(TLPK,15))
+ Store(DID2, Index(TLPK,17)) // LFP+DP_B
+ Store(DID3, Index(TLPK,18))
+ Store(DID2, Index(TLPK,20)) // LFP+HDMI_B
+ Store(DID4, Index(TLPK,21))
+ Store(DID2, Index(TLPK,23)) // LFP+HDMI_C
+ Store(DID5, Index(TLPK,24))
+ Store(DID2, Index(TLPK,26)) // LFP+DP_D
+ Store(DID6, Index(TLPK,27))
+ Store(DID2, Index(TLPK,29)) // LFP+HDMI_D
+ Store(DID7, Index(TLPK,30))
+ }
+
+//
+// MXMX method is dupplicated under GFX0 scope in INTELGFX.ASL
+// need to replace it with method in this file.
+//
+#ifndef OPTIMUS_DSM_GUID
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: MXMX
+//
+// Description: Display DDC Mux Control
+//
+// Input:
+// Arg0: Get/Set DDC/Aux Mux State
+// 0- Acquire DDC/Aux Mux on this GPU
+// 1- Release Mux from this GPU
+// 2- Get Mux state
+//
+// Output:
+// 0, Not Acquired.
+// if Arg0 = 0 or 1, Non-Zero return indicates success acquiring MUX
+// (and MUX has switched to this output)
+// if Arg0 = 2, Non-Zero return indicates MUX is currently set to this output
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (MXMX, 1, Serialized)
+ {
+ P8DB(0x77, Arg0, 2000)
+
+ If (LEqual (Arg0, 0))
+ {
+ //Acquire DDC/AUX mux
+ // No mutex implemented. No need to acquire mutex.
+ // Set mux to iGPU
+ DGPU_SCOPE.SGPO(DSEL, 0)
+ DGPU_SCOPE.SGPO(ESEL, 0) // use edid_select# as mutex flag
+
+ Return(0x1)
+ }
+
+ If (LEqual (Arg0, 1))
+ {
+ //Release DDC/AUX mux
+ // No mutex implemented. No need to release mutex.
+ // 2-way mux. Hence no need to do anything
+ Return(0x1)
+ }
+
+ If (LEqual (Arg0, 2))
+ {
+
+ //Get ddc/aux mux status for iGPU
+ Return(LNot(DGPU_SCOPE.SGPI(ESEL)))
+ }
+
+ Return(0x0) // mutex not acquired
+ }
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: MXDS
+//
+// Description: Display output MUX control
+//
+// Input:
+// Arg0:
+// 0 - Get Mux state
+// 1 - Set Display to active on this GPU
+// 2 - Set Backlight control to active on this GPU
+// 3 - Set Display & Backlight to active on this GPU
+//
+// Output:
+// If Arg0 = 0, Error = Display is not MUXed
+// Else return value of the state of the MUX
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(MXDS, 1, Serialized)
+ {
+ P8DB(0x7A, Arg0, 2000)
+
+ If(LEqual (Arg0, 0))
+ {
+ //Get display mux status for iGPU
+ return(LNot(DGPU_SCOPE.SGPI(DSEL)))
+ } else
+// If(LOr(LEqual (Arg0, 1), LEqual (Arg0, 2)))
+ {
+ //Set display mux to igpu
+ DGPU_SCOPE.SGPO(DSEL, 0)
+ DGPU_SCOPE.SGPO(PSEL, 0)
+ }
+
+ Return (0)
+ }
+
+#endif // OPTIMUS_DSM_GUID
+
+//<AMI_SHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: NVIG
+//
+// Description: Nvidia NVIG (iGPU) OperationRegion
+//
+//-------------------------------------------------------------------------
+//<AMI_SHDR_END>
+ OperationRegion(NVIG,SystemMemory,NVGA,0x400)
+ Field(NVIG, DWordAcc, NoLock, Preserve)
+ {
+ // OpRegion Header
+
+ NISG, 0x80, // (000h) Signature-"NVSG-IGD-DSM-VAR".
+ NISZ, 0x20, // (010h) OpRegion Size in KB.
+ NIVR, 0x20, // (014h) OpRegion Version.
+
+ // OpRegion Data
+ GPSS, 0x20, // Policy Selection Switch Status (Policy selection)
+ GACD, 0x10, // Active Displays
+ GATD, 0x10, // Attached Displays
+ LDES, 0x08, // Lid Event State
+ DKST, 0x08, // Dock State
+ DACE, 0x08, // Display ACPI event
+ DHPE, 0x08, // Display Hot-Plug Event
+ DHPS, 0x08, // Display Hot-Plug Status
+ SGNC, 0x08, // Notify Code (Cause of Notify(..,0xD0))
+ GPPO, 0x08, // Policy Override (Temporary ASL variables)
+ USPM, 0x08, // Update Scaling Preference Mask (Temporary ASL variable)
+ GPSP, 0x08, // Panel Scaling Preference
+ TLSN, 0x08, // Toggle List Sequence Number
+ DOSF, 0x08, // Flag for _DOS
+ ELCL, 0x10, // Endpoint Link Contol Register Value
+ }
+
+ // Toggle List Package
+ Name(TLPK,Package()
+ {
+ //fix this toggle list. DIDx values have been changed in MxmAcpiTables.c
+ 0xFFFFFFFF, 0x2C, // CRT
+ 0xFFFFFFFF, 0x2C, // LFP
+ 0xFFFFFFFF, 0x2C, // DP_B
+ 0xFFFFFFFF, 0x2C, // HDMI_B
+ 0xFFFFFFFF, 0x2C, // HDMI_C
+ 0xFFFFFFFF, 0x2C, // DP_D
+ 0xFFFFFFFF, 0x2C, // HDMI_D
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+CRT
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+DP_B
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+HDMI_B
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+HDMI_C
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+DP_D
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+HDMI_D
+
+ })
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: INDL
+//
+// Description: Initialize Global Next active device list.
+//
+// Input: None
+//
+// Output: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(INDL, 0, Serialized)
+ {
+ Store(0, NXD1)
+ Store(0, NXD2)
+ Store(0, NXD3)
+ Store(0, NXD4)
+ Store(0, NXD5)
+ Store(0, NXD6)
+ Store(0, NXD7)
+ Store(0, NXD8)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: SND1
+//
+// Description: Set Next active device for a single device
+//
+// Input:
+// Arg0 : Device ID of the device that's to be set as next active device.
+//
+// Output: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(SND1, 1, Serialized)
+ {
+ If(LEqual(Arg0, DID1))
+ {
+ Store(1, NXD1)
+ }
+ If(LEqual(Arg0, DID2))
+ {
+ Store(1, NXD2)
+ }
+ If(LEqual(Arg0, DID3))
+ {
+ Store(1, NXD3)
+ }
+ If(LEqual(Arg0, DID4))
+ {
+ Store(1, NXD4)
+ }
+ If(LEqual(Arg0, DID5))
+ {
+ Store(1, NXD5)
+ }
+ If(LEqual(Arg0, DID6))
+ {
+ Store(1, NXD6)
+ }
+ If(LEqual(Arg0, DID7))
+ {
+ Store(1, NXD7)
+ }
+ If(LEqual(Arg0, DID8))
+ {
+ Store(1, NXD8)
+ }
+
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: SNXD
+//
+// Description: Set Next active device
+//
+// Input:
+// Arg0 TLSN
+//
+// Output: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(SNXD, 1, Serialized)
+ {
+ INDL()
+
+ //
+ // Locate the toggle table entry corresponding to TLSN value
+ // Toggle list entries are separated by 0x2C.
+ //
+
+ Store(1, Local0) // Local0 to track entries. Point to the first entry (TLSN starts from 1)
+ Store(0, Local1) // Local1 to track elements inside the TLPK package (ACPI IDs and '0x2C')
+
+ while(LLess(Local0, Arg0)) // TLSN start from 1!!
+ {
+ if(LEqual(DeRefOf(Index(TLPK,Local1)), 0x2C))
+ {
+ Increment(Local0)
+ }
+ Increment(Local1)
+
+ }
+
+ SND1(DeRefOf(Index(TLPK, Local1))) // 1 st ACPI ID in the entry corresponding to TLSN
+ Increment(Local1)
+ if(LNotEqual(DeRefOf(Index(TLPK,Local1)), 0x2C)) // Check for separator
+ {
+ SND1(DeRefOf(Index(TLPK, Local1))) // 2 nd ACPI ID in the entry corresponding to TLSN
+ }
+
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: CTOI
+//
+// Description: Convert _DOD indices-> MDTL index
+//
+// Input:
+// Arg 0 is the currently active display list
+//
+// Output: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(CTOI,1, Serialized)
+ {
+ Switch(ToInteger(Arg0)) //Arg 0 is the currently active display list
+ {
+ //_DOD indices-> MDTL index
+ case(0x1) {Return(1)} //CRT
+ case(0x2) {Return(2)} //LFP
+ case(0x4) {Return(3)} //DP_B
+ case(0x8) {Return(4)} //HDMI_B
+ case(0x10) {Return(5)} //HDMI_C
+ case(0x20) {Return(6)} //DP_D
+ case(0x40) {Return(7)} //HDMI_D
+ case(0x3) {Return(8)} //LFP+CRT
+ case(0x6) {Return(9)} //LFP+DP_B
+ case(0xA) {Return(10)} //LFP+HDMI_B
+ case(0x12) {Return(11)} //LFP+HDMI_C
+ case(0x22) {Return(12)} //LFP+DP_D
+ case(0x42) {Return(13)} //LFP+HDMI_D
+ Default {Return(1)}
+ }
+ }
+
+// Check for Nvidia _DSM UUIDs
+//
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HDSM
+//
+// Description: Device Specific Methods for Hybrid GPU (may be invoked from dGP and iGD)
+// Implements Mxm and SG specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// nVidia
+// SG dGPU GUID :9D95A0A0-0060-4D48-B34D-7E5FEA129FD4
+// NBCI GUID :D4A50B75-65C7-46F7-BfB7-41514CEA0244
+// Ventura GUID :95DB88FD-940A-4253-A446-70CE0504AEDF
+// Optimus DSM_GUID :A486D8F8-0BDA-471B-A72B-6042A6B5BEE0
+//
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(HDSM, 4, SERIALIZED)
+ {
+
+#if NV_VENTURA_SUPPORT == 1
+ //SPB_DSM_GUID {95DB88FD-940A-4253-A446-70CE0504AEDF}
+//x if(CMPB(Arg0, Buffer(){0xFD,0x88,0xDB,0x95,0x0A,0x94,0x53,0x42,0xA4,0x46,0x70,0xCE,0x05,0x04,0xAE,0xDF}))
+ If(LEqual(Arg0, ToUUID("95DB88FD-940A-4253-A446-70CE0504AEDF")))
+ {
+ return ( DGPU_SCOPE.SPB(Arg0, Arg1, Arg2, Arg3))
+ }
+#endif
+
+#if NV_GPS_SUPPORT == 1
+ //SPB_DSM_GUID {A3132D01-8CDA-49BA-A52E-BC9D46DF6B81}
+//x if(CMPB(Arg0, Buffer(){0x01, 0x2D, 0x13, 0xA3, 0xDA, 0x8C, 0xBA, 0x49,0xA5, 0x2E, 0xBC, 0x9D, 0x46, 0xDF, 0x6B, 0x81}))
+ If(LEqual(Arg0, ToUUID("A3132D01-8CDA-49BA-A52E-BC9D46DF6B81")))
+ {
+ return ( DGPU_SCOPE.GPS(Arg0, Arg1, Arg2, Arg3))
+ }
+#endif
+
+#if HYBRID_DSM_GUID || NBCI_DSM_GUID || OPTIMUS_DSM_GUID
+
+ Name(SGCI, 0) // SG Common Interface
+ Name(NBCI, 0) // Notebok Common Interface
+ Name(OPCI, 0) // Optimus Common Interface
+ Name(BUFF, 0) // Buff Parameter
+
+// Hybrid Graphics Methods supported only if MUXed mode is selected
+#ifdef HYBRID_DSM_GUID
+ If(LEqual(Arg0, ToUUID("9D95A0A0-0060-4D48-B34D-7E5FEA129FD4")))
+ {
+ Store(1, SGCI)
+ }
+#endif
+// NBCI Methods can be querried in botd MUXed and MUXless modes
+#ifdef NBCI_DSM_GUID
+ if(LEqual(Arg0, ToUUID("D4A50B75-65C7-46F7-BfB7-41514CEA0244")))
+ {
+ Store(1, NBCI)
+ }
+#endif
+// Optimus Methods can be querried in botd MUXed and MUXless modes
+#ifdef OPTIMUS_DSM_GUID
+ If(LEqual(Arg0, ToUUID("A486D8F8-0BDA-471B-A72B-6042A6B5BEE0")))
+ {
+ Store(1, OPCI)
+ }
+#endif
+
+ If(LOr(OPCI, LOr( SGCI, NBCI)) )
+ {
+
+ P8DB(0xEE, Arg2, 1000)
+
+ if(OPCI) {
+ if(LNotEqual(Arg1, 0x100)) {
+ Return(0x80000002)
+ }
+ }
+ else { // NBCI & SGCI
+ If(LNotEqual(Arg1,0x0102))
+ {
+ Return(0x80000002)
+ }
+ }
+ //
+ // Function 0: NVSG_FUNC_SUPPORT - Return Supported Functions
+ //
+ // Returns:
+ // SGCI: Functions 0-6,18 are supported
+ // NBCI: Functions 0,4-6,18 are supported
+ // OPCI: Functions 0,5,6,12,13,16,17,26,27
+ //
+ If(LEqual(Arg2,0))
+ {
+ if(SGCI){
+ Return(Buffer(){0x7F, 0x00, 0x04, 0x00})
+ } else {
+ if(NBCI){
+ Return(Buffer(){0x73, 0x00, 0x04, 0x00})
+ }
+ else {
+ if(OPCI){
+ //Sub-Functions 0,16,17,26 are supported
+ // Return(ToBuffer(0x04030001))
+ //Sub-Functions 0,5, 6, 12, 13, 16, 17, 26,27 are supported
+ // Return(ToBuffer(0x0c031861))
+ Return(Buffer(){0x61, 0x18, 0x03, 0x0C})
+ //Sub-Functions 0,16 26,27 are supported
+// Return(ToBuffer(0x0c010001))
+
+ }
+ }
+ }
+ }
+
+ //
+ // Function 1: NVSG_FUNC_CAP
+ //
+ // Returns the capabilities of the Switchable Graphics
+ // implementation on the platform
+ //
+ If(LEqual(Arg2,1))
+ {
+ Name (TEMP, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TEMP,0,STS0)
+ if(SGCI){
+ // Return status (bit0-1 Hybrid enabled) and indicate Hybrid power On/Off
+
+ // 0 HG Enable Status = 1
+ // 1 GPU Output MUX Capabilities= 1
+ // 2 GPU Policy Selector Capabilities = 1
+ // 3-4 GPU Control Status = 3
+ // 5 GPU Reset Control = 1
+ // 6 MUX'ed Hot-Plug Capabilities = 0
+ // 7 MUX'ed DDC/AUX Capabilities = 1
+ // 8-10 Notify Codes
+ // 0= Not a Notify(0xD0)
+ // 1= POLICYSELECT change
+ // 2= PLATPOLICY change
+ // 3= DISPLAYSTATUS change
+ // 11-12 EC Notify code
+ // 14-15 Eject Capabilities = 0
+ // 16 Mux'd backlight cap = 0
+ // 17-23 Hybrid EC version = 0
+ // 24-26 HG capability = 3 (Power saver & Boost performance)
+ // 27-28 HG switch = 1 (hot-key or stateless button)
+ // 29 Fasl LCD swithing = 0
+ // 31 = 0
+
+ // Switchable caps
+ Or(STS0,0x0B0000BF,STS0)
+
+ // Switchable Notify Code (Cause of Notify(..,0xD0))
+ Or(STS0,ShiftLeft(SGNC,8,SGNC),STS0)
+ } else {
+ // NBCI
+ // 0..3 Reserved=00
+ // 4 Aux Power States
+ // 6:5 LID State Event
+ // 0= Use the event List to determine support
+ // 1= Force use of Generic Hot-Plug Notify(0x81)
+ // 2= Force use of Specific Lid Event, e.g. Notify (0xDB)
+ // 3= Reserved for future use
+ // 7:8 LID State Enumeration
+ // 0= Use _DCS under _LCD device(default)
+ // 1= Provides status DISPLAYSTATUS Bit[4], for single pannel systems only(recommended)
+ // 2,3= Reserved
+ // 9 Dock State Enumerartion
+ // 0= Doesn't have a Dock(or _DCS under device reflects attachments-via-dock (default)
+ // 1= Provides dock status info via DISPLAYSTATUS Bit[5] (recommended)
+ // 10:30 Reserved
+ // 31 = 0
+
+ // use all defaults for now
+ Or(STS0,0x00000,STS0)
+ }
+ return(TEMP)
+ }
+
+ //
+ // Function 2: NVSG_FUNC_SELECTOR
+ //
+ // Returns device preference between iGPU and dGPU
+ //
+ If(LEqual(Arg2,2))
+ {
+ Name (TMP1, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TMP1,0,STS1)
+
+ //Ignore bits[6:5] since we are not supporting Switchable enable/disable policy selection
+ //Only Switchable policy selection is supported via CAS+F6 hotkey
+
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(DerefOf(Index(Arg3,0)), Local0)
+ ToInteger(Arg3, Local0)
+ And(Local0, 0x1F, Local0)
+
+ If(And(Local0,0x10)) //If Switchable policy update bit is set
+ {
+ And(Local0,0xF,Local0)
+ Store(Local0,GPSS)
+ Notify(IGPU_SCOPE,0xD9) //Broadcast "policy completed" notification
+ Notify(PCI_SCOPE.WMI1, 0xD9) // Mirror Notify on WMI1
+
+ }
+ Else
+ {
+ And(Local0,0xF,Local0)
+ If(LEqual(GPPO,1))
+ {
+ // Retrieve the setting from NVS
+ Store(GPSS,Local0)
+ Or(Local0,0x10,Local0)
+ Store(0,GPPO)
+ }
+ }
+
+ Or(STS1,Local0,STS1)
+
+ Return(TMP1)
+ }
+
+ //
+ // Function 3: NVSG_FUNC_POWERCONTROL
+ //
+ // Allows control of dGPU power methods from the iGPU
+ //
+ If(LEqual(Arg2,3))
+ {
+ Name (TMP2, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TMP2,0,STS2)
+
+ // GPU Power Control
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(DerefOf(Index(Arg3,0)), Local0)
+ ToInteger(Arg3, Local0)
+ And(Local0, 0x3, Local0)
+
+ If(LEqual(Local0,0))
+ {
+ DGPU_SCOPE.SGST()
+ }
+
+ If(LEqual(Local0,1))
+ {
+ DGPU_SCOPE.SGON()
+ }
+
+ If(LEqual(Local0,2))
+ {
+ DGPU_SCOPE.SGOF()
+ }
+
+ //dGPU_PWROK is not working. Using dGPU_PWR_EN# instead as w/a
+ //Or(STS2,DGPU_SCOPE.MPOK,STS2)
+ If(LEqual(DGPU_SCOPE.SGST(), 0xF))
+ {
+ Or(STS2,0x1,STS2)
+ }
+ //else do nothing since STS2 is already 0
+ Return(TMP2)
+ }
+
+ //
+ // Function 4: NVSG_FUNC_PLATPOLICY
+ //
+ // Sets or Returns the current System Policy settings
+ //
+ If(LEqual(Arg2,4))
+ {
+
+// common for SGCI and NBCI
+ Name (TMP3, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TMP3,0,STS3)
+
+ // Panel Scaling Preference
+
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(DerefOf(Index(Arg3,0)), Local0)
+ ToInteger(Arg3, Local0)
+ Store(Local0, Local1)
+ ShiftRight(Local0, 16, Local0)
+ And(Local0, 0x1, USPM)
+
+ ShiftRight(Local1, 13, Local1)
+ And(Local1, 0x3, Local1)
+
+
+ If(LNotEqual(Local1,GPSP))
+ {
+ If(LEqual(USPM,1))
+ {
+ Store(Local1,GPSP)
+ }
+ Else
+ {
+ // Retrieve the setting from NVS
+ Store(GPSP,Local1)
+ Or(STS3,0x8000,STS3) // Set Panel Scaling override
+ }
+ }
+ Or(STS3,ShiftLeft(Local1,13),STS3)
+
+
+ Return(TMP3)
+ }
+
+ //
+ // Function 5: NVSG_FUNC_DISPLAYSTATUS
+ //
+ // Sets or Returns the current display detection,
+ // hot-key toggle sequence
+ //
+ If(LEqual(Arg2,5))
+ {
+// common for SGCI and NBCI
+ Name (TMP4, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TMP4,0,STS4)
+
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(Derefof(Index(Arg3,0)), Local0) //Store input field in local0
+ ToInteger(Arg3, Local0)
+
+ // Next Combination Sequence
+
+ If(And(Local0,0x80000000)) //If Bit31 is set
+ {
+ Store(And(ShiftRight(Local0,25),0x1F),TLSN)
+
+ If(And(Local0,0x40000000)) //If Bit30 is set
+ {
+ Store(1,DOSF)
+ }
+ }
+
+ // Display Mask for Attached and Active Displays
+
+ If(And(Local0,0x01000000)) //If Bit24 is set
+ {
+ Store(And(ShiftRight(Local0,12),0xFFF),GACD)
+ Store(And(Local0,0xFFF),GATD)
+
+ //Get current toggle list index based on currently active display list
+ Store(CTOI(GACD),TLSN)
+ Increment(TLSN)
+
+ If(LGreater(TLSN, 13)) //For Huron River ,13 is the number of entries in the toggle list
+ {
+ Store(1, TLSN)
+ }
+
+ SNXD(TLSN) //This is optional for NV SG
+ }
+
+ // Display Hot-Plug Event/Status
+ Or(STS4,ShiftLeft(DHPE,21),STS4)
+ Or(STS4,ShiftLeft(DHPS,20),STS4)
+
+ // Toggle Sequence number
+ Or(STS4,ShiftLeft(TLSN,8),STS4)
+
+ // Dock State
+ Or(STS4,ShiftLeft(DKST,5),STS4)
+
+ // Lid Event State
+ Or(STS4,ShiftLeft(LDES,4),STS4)
+
+ // Display ACPI Event(SGCI only)
+ Or(STS4,DACE,STS4)
+
+ Store(0,LDES)
+ Store(0,DHPS)
+ Store(0,DHPE)
+ Store(0,DACE)
+
+ Return(TMP4)
+ }
+
+ //
+ // Function 6: NVSG_FUNC_MDTL - Returns Hot-Key display switch toggle sequence
+ //
+ // Returns:
+ // Returns Hot-Key display switch toggle sequence
+ //
+ If(LEqual(Arg2,6))
+ {
+// common for SGCI and NBCI
+ Return(TLPK)
+ }
+ //
+ // Function 16:
+ //
+ If(LEqual(Arg2,16))
+ {
+ CreateWordField(Arg3, 2, USRG) // Object type signature passed in by driver.
+ Name(OPVK, Buffer()
+ {
+ // Key below is for Emerald Lake Fab2 platform
+ // Customer need to ask NVIDIA PM to get the key
+ // Customer need to put the key in between labels "// key start -" and
+ // "// key end -". Please consult NVIDIA PM if any issues
+ //148597456985Genuine NVIDIA Certified Optimus Ready Motherboard for 736019_MIRc
+ // Key start -
+ 0xE4,0x42,0x5F,0x14,0x36,0x26,0x16,0x37,0x4B,0x56,0xE6,0x00,0x00,0x00,0x01,0x00,
+ 0x31,0x34,0x38,0x35,0x39,0x37,0x34,0x35,0x36,0x39,0x38,0x35,0x47,0x65,0x6E,0x75,
+ 0x69,0x6E,0x65,0x20,0x4E,0x56,0x49,0x44,0x49,0x41,0x20,0x43,0x65,0x72,0x74,0x69,
+ 0x66,0x69,0x65,0x64,0x20,0x4F,0x70,0x74,0x69,0x6D,0x75,0x73,0x20,0x52,0x65,0x61,
+ 0x64,0x79,0x20,0x4D,0x6F,0x74,0x68,0x65,0x72,0x62,0x6F,0x61,0x72,0x64,0x20,0x66,
+ 0x6F,0x72,0x20,0x37,0x33,0x36,0x30,0x31,0x39,0x5F,0x4D,0x49,0x52,0x63,0x20,0x20,
+ 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x2D,0x20,0x3C,0x34,0x27,0x21,0x58,0x29,
+ 0x57,0x27,0x58,0x20,0x27,0x25,0x59,0x5D,0x31,0x29,0x3A,0x2A,0x26,0x39,0x59,0x43,
+ 0x56,0x3B,0x58,0x56,0x58,0x3D,0x59,0x4E,0x3B,0x3A,0x35,0x44,0x25,0x42,0x5A,0x48,
+ 0x55,0x3A,0x58,0x4C,0x25,0x48,0x54,0x21,0x35,0x4B,0x4D,0x37,0x2C,0x3C,0x20,0x2D,
+ 0x20,0x43,0x6F,0x70,0x79,0x72,0x69,0x67,0x68,0x74,0x20,0x32,0x30,0x31,0x30,0x20,
+ 0x4E,0x56,0x49,0x44,0x49,0x41,0x20,0x43,0x6F,0x72,0x70,0x6F,0x72,0x61,0x74,0x69,
+ 0x6F,0x6E,0x20,0x41,0x6C,0x6C,0x20,0x52,0x69,0x67,0x68,0x74,0x73,0x20,0x52,0x65,
+ 0x73,0x65,0x72,0x76,0x65,0x64,0x2D,0x31,0x34,0x38,0x35,0x39,0x37,0x34,0x35,0x36,
+ 0x39,0x38,0x35,0x28,0x52,0x29,
+ //Copyright 2010 NVIDIA Corporation All Rights Reserved-148597456985(R)
+ // Key end -
+ })
+ If(LEqual(USRG, 0x564B)) { // 'VK' for Optimus Validation Key Object.
+ Return(OPVK)
+ }
+ Return(Zero)
+ }
+ //
+ // Function 17 NVOP_FUNC_GETALLOBJECTS
+ //
+ If(LEqual(Arg2,17))
+
+ {
+ Return(Zero)
+ }
+ //
+ // Function 18: NVSG_FUNC_GETEVENTLIST
+ //
+ // Returns:
+ // Returns list of notifiers and their meanings
+ //
+ If(LEqual(Arg2,18))
+ {
+// common for SGCI and NBCI
+ return(Package(){
+ 0xD0, ToUUID("921A2F40-0DC4-402d-AC18-B48444EF9ED2"), // Policy request
+ 0xD9, ToUUID("C12AD361-9FA9-4C74-901F-95CB0945CF3E"), // Policy set
+ 0xDB, ToUUID("42848006-8886-490E-8C72-2BDCA93A8A09"), // Display scaling
+
+ 0xEF, ToUUID("B3E485D2-3CC1-4B54-8F31-77BA2FDC9EBE"), // Policy change
+ 0xF0, ToUUID("360d6fb6-1d4e-4fa6-b848-1be33dd8ec7b"), // Display status
+
+ // unfinished list of events. we do not need this Func18 unless event notifiers differ from standard ones defined in BWG.
+ })
+ }
+ //
+ // Function 26: NVOP_FUNC_OPTIMUSCAPS
+ //
+ If(LEqual(Arg2,26))
+ {
+ // On Input
+ //Bit25-24 Power Control Enable
+ // 2-Platform should not power down GPU in the _PS3 method(default)
+ // 3-Platform should power down GPU in the _PS3 method(default)
+ // Bit0 No flag upd present in this call (SBIOS returns curent status)
+ //
+ CreateField(Arg3,24,2,OMPR)
+ CreateField(Arg3,0,1,FLCH)
+ If(ToInteger(FLCH))
+ {
+ Store(OMPR, DGPU_SCOPE.OPCE) // Optimus Power Control Enable - From DD
+ }
+ // On return
+ // Bit 24:26 Capabilities
+ // 0: No special platf cap
+ // 1: Platform has dynamic GPU power control
+ // Bit6 GPU Display Hot Plug NEW Optimus BWG v02
+ // Bit4:3 Current GPU Control status
+ // 0: GPU is powered off
+ // 1: GPU is powered on and enabled
+ // 2: reserved
+ // 3: GPU Power has stabilized
+ // Bit0
+ // 0:Optimus Disabled
+ // 1:Optimus Enabled
+ Store(Buffer(4) {0, 0, 0, 0}, Local0)
+ CreateField(Local0,0,1,OPEN)
+ CreateField(Local0,3,2,CGCS)
+ CreateField(Local0,6,1,SHPC)
+ CreateField(Local0,24,3,DGPC) // DGPC - Default: No Dynamic GPU Power Control
+ CreateField(Local0,27,2,HDAC) // HDAC - HD Audio Codec Cap
+
+ Store(One, OPEN) // Optimus Enabled
+
+ Store(One, SHPC) // GPU Display Hotplug Supported
+ Store(0x2, HDAC) // HDA BIOS control Supported
+
+ Store(One, DGPC) // Dynamic GPU Power Control Available
+ If(LNotEqual(DGPU_SCOPE.SGST(), 0))
+ {
+ Store(0x3, CGCS) // Current GPU Control status
+ }
+ Return(Local0)
+
+ }//case (26)
+ //
+ // Function 27: NVOP_FUNC_OPTIMUSFLAGS
+ //
+ If(LEqual(Arg2,27))
+ {
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(Derefof(Index(Arg3,0)), Local0) //Store input field in local0
+ ToInteger(Arg3, Local0)
+// Store(Arg3, Local0)
+// CreateField(Local0,0,1,OPFL)
+// CreateField(Local0,1,1,OPVL)
+ If(And(Local0,0x00000002))
+ {
+ Store(Zero, BUFF)
+ If(And(Local0,0x00000001))
+ {
+ Store(One, BUFF)
+ }
+ }
+ And(SGFL, Not(0x2), SGFL)
+ Or(SGFL, ShiftLeft(BUFF,1), SGFL)
+ Store(SWSMI_NVOEM_CMOS_W, SSMP) // Set Audio Codec flag to CMOS
+ Return(Local0)
+ }
+ // FunctionCode or SubFunctionCode not supported
+ Return(0x80000002) // OTHER ARGUMENTS NOT SUPPORTED
+ }
+#endif // common scope for Hybrid/Nbci/Optimus
+
+ // Check for common with dGPU _DSM UUIDs
+// return (DGPU_SCOPE.HDSM(Arg0, Arg1, Arg2, Arg3))
+ Return (0x80000001)
+ }
+} // end PCI0.GFX0 scope
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvGPS.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvGPS.asl
new file mode 100644
index 0000000..216f78d
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvGPS.asl
@@ -0,0 +1,337 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNvGPS.asl 2 9/09/12 11:01p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:01p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNvGPS.asl $
+//
+// 2 9/09/12 11:01p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] OEMSSDT.mak
+// OEMSSDT.asl
+// OEMNVdGPU.asl
+// OEMNViGPU.asl
+// OEMNViGDmisc.asl
+// OEMNvVentura.asl
+// OEMNvGPS.asl
+// OEMSSDT.cif
+//
+// 1 12/12/11 9:10p Alanlin
+//
+//
+//
+//**********************************************************************
+External(\_PR.CPU0._PSS, BuffObj)
+
+External(\_PR.CPU0._PPC, IntObj)
+External(\_PR.CPU1._PPC, IntObj)
+External(\_PR.CPU2._PPC, IntObj)
+External(\_PR.CPU3._PPC, IntObj)
+External(\_PR.CPU4._PPC, IntObj)
+External(\_PR.CPU5._PPC, IntObj)
+External(\_PR.CPU6._PPC, IntObj)
+External(\_PR.CPU7._PPC, IntObj)
+External(\_SB.PCI0.LPCB.H_EC.GTVR) // CPU GT VR (IMVP) Temperature
+External(\_PR.CPU0._TSS, MethodObj)
+External(\_PR.CPU0._PTC, MethodObj)
+
+#define GPS_REVISION_ID 0x00000100 // Revision number
+#define GPS_ERROR_SUCCESS 0x00000000 // Generic Success
+#define GPS_ERROR_UNSPECIFIED 0x00000001 // Generic unspecified error code
+#define GPS_ERROR_UNSUPPORTED 0x00000002 // Sub-Function not supported
+
+#define GPS_FUNC_SUPPORT 0x00000000 // Bit list of supported functions
+#define GPS_FUNC_GETCALLBACKS 0x00000013 // Get system requested callback
+#define GPS_FUNC_PSHARESTATUS 0x00000020 // Get system requested Power Steering Setting
+#define GPS_FUNC_GETPSS 0x00000021 // Get _PSS object
+#define GPS_FUNC_SETPPC 0x00000022 // Set _PCC object
+#define GPS_FUNC_GETPPC 0x00000023 // Get _PCC object
+#define GPS_FUNC_PSHAREPARAMS 0x0000002A // Get sensor information and capabilities
+
+Scope(PCI_SCOPE){
+
+ Name(GPS, "GPSACPI 2012-Aug-12 14:56:05") // MCPACPIP build time stamp.
+
+} // end of Scope
+
+Scope (DGPU_SCOPE)
+{
+
+Name(PSAP, Zero)
+ Name(ECBF, Buffer(20) {})
+ CreateDWordField(ECBF, 0, EDS1)
+ CreateDWordField(ECBF, 4, EDS2)
+ CreateDWordField(ECBF, 8, EDS3)
+ CreateDWordField(ECBF, 12, EDS4)
+ CreateDWordField(ECBF, 16, EPDT)
+
+ Name(GPSP, Buffer(36) {})
+ CreateDWordField(GPSP, 0, RETN)
+ CreateDWordField(GPSP, 4, VRV1)
+ CreateDWordField(GPSP, 8, TGPU)
+ CreateDWordField(GPSP, 12, PDTS)
+ CreateDWordField(GPSP, 16, SFAN)
+ CreateDWordField(GPSP, 20, SKNT)
+ CreateDWordField(GPSP, 24, CPUE)
+ CreateDWordField(GPSP, 28, TMP1)
+ CreateDWordField(GPSP, 32, TMP2)
+
+Name(NLIM, 0) //set one flag for GPS_EVENT_STATUS_CHANGE 1: will update parameter: 0 just call function 0x1c _PCONTROL
+
+ Name(PSCP, 0) // P-State capacity, mainly for s/w debugging
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: GPS
+//
+// Description: Called from _DSM -Device Specific Method for dGPU device.
+// Implement Ventura specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// Ventura DSM_GUID A3132D01-8CDA-49BA-A52E-BC9D46DF6B81
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (GPS, 4, NotSerialized)
+ {
+
+ Store("------- GPS DSM --------", Debug)
+ // Only Interface Revision 0x0100 is supported
+ If (LNotEqual(Arg1, 0x100))
+ {
+ Return(0x80000002)
+ }
+
+ P8DB(0xDD, Arg2, 1000)
+ // (Arg2) Sub-Function
+ Switch (ToInteger(Arg2))
+ {
+
+ case (GPS_FUNC_SUPPORT)
+ {
+
+ Name(FMSK, Buffer(0x8)
+ {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ })
+ Store(Buffer(0x8)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }, Local0)
+ Divide(GPS_FUNC_SUPPORT, 0x8, Local2, Local1)
+ // Local1 is Quotient, Local2 is Remainder
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_GETCALLBACKS, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_PSHARESTATUS, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_GETPSS, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_SETPPC, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_GETPPC, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_PSHAREPARAMS, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+
+ // mask out specific functions
+ Store( SizeOf(Local0), Local1)
+ While( LNotEqual(Local1, 0) ) {
+ Decrement(Local1)
+ Store( DeRefOf(Index(FMSK, Local1)), Local2)
+ And( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1) )
+ }
+
+ Return(Local0)
+ }
+ //
+ // Function 19: GPS_FUNC_GETCALLBACKS,
+ //
+ case(GPS_FUNC_GETCALLBACKS)
+ {
+ Store("GPS fun 19", Debug)
+ return(arg3)
+ }
+ //
+ // Function 32: GPS_FUNC_PSHARESTATUS,
+ //
+ case(GPS_FUNC_PSHARESTATUS)
+ {
+ Store("GPS fun 20", Debug)
+
+ Name(RET1, Zero)
+ CreateBitField(Arg3,24,NRIT) //new request new IGP turbo state(bit 24 is valid)
+ CreateBitField(Arg3,25,NRIS) //request new IGP turbo state
+ if (NRIS){
+ if(NRIT){
+ Or(RET1, 0x01000000, RET1)
+ }else
+ {
+ //help disable IGP turbo boost
+ And(RET1, 0xFeFFFFFF, RET1)
+ }
+ }
+ Or(RET1, 0x40000000, RET1) // if this machine support GPS
+
+ if(NLIM){
+ Or(RET1, 0x00000001, RET1) // if NLIM falg is set, set bit0 =1
+ }
+
+ Return(RET1)
+ }
+ //
+ // Function 33: GPS_FUNC_GETPSS, Get CPU _PSS structure
+ //
+ case(GPS_FUNC_GETPSS)
+ {
+ Return(\_PR.CPU0._PSS)
+ }
+ //
+ // Function 34: GPS_FUNC_SETPPC, Set current CPU _PPC limit
+ //
+ case(GPS_FUNC_SETPPC)
+ {
+ CreateBYTEField(Arg3, 0, PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU0, 0x80)
+ store(PCAP, PSAP)
+ Return(PCAP)
+ }
+ //
+ // Function 35: GPS_FUNC_GETPPC, Get current CPU _PPC limit
+ //
+ case(GPS_FUNC_GETPPC)
+ {
+ Return(PSAP)
+ }
+
+ case(0x25)
+ {
+ Store("GPS fun 25", Debug)
+ return(\_PR_.CPU0._TSS)
+ }
+ case(0x26)
+ {
+ Store("GPS fun 26", Debug)
+ CreateDWordField(Arg3, Zero, TCAP)
+ Store(TCAP, \_PR_.CPU0._PTC)
+ Notify(\_PR_.CPU0, 0x80)
+ return(TCAP) }
+ //
+ // Function 42: GPS_FUNC_PSHAREPARAMS, Get Power Steering platform parameters
+ //
+ case(GPS_FUNC_PSHAREPARAMS)
+ {
+ Store("GPS fun 2a", Debug)
+
+ CreateBYTEField(Arg3,0,PSH0)
+ CreateBYTEField(Arg3,1,PSH1)
+ CreateBitField(Arg3,8,GPUT)
+ CreateBitField(Arg3,9,CPUT)
+ CreateBitField(Arg3,10,FANS)
+ CreateBitField(Arg3,11,SKIN)
+ CreateBitField(Arg3,12,ENGR)
+ CreateBitField(Arg3,13,SEN1)
+ CreateBitField(Arg3,14,SEN2)
+
+ switch (PSH0){
+ case(0){
+ if(CPUT){
+ store(0x00000200, RETN)
+ Or(RETN, PSH0, RETN)
+ // Please return CPU or EC tempture to PDTS
+ store(\_SB.PCI0.LPCB.H_EC.GTVR,PDTS)
+ }
+ return(GPSP)
+ } //case(0)
+
+ case(1){
+ store(0x00000200, RETN)
+ Or(RETN, PSH0, RETN)
+ store(1000,PDTS)
+ return(GPSP)
+ } //case(1)
+
+ case(2){
+ Or(RETN, PSH0, RETN)
+ store(0x00000000, VRV1)
+ store(0x00000000, TGPU)
+ store(0x00000000, PDTS)
+ store(0x00000000, SFAN)
+ store(0x00000000, CPUE)
+ store(0x00000000, SKNT)
+ store(0x00000000, TMP1)
+ store(0x00000000, TMP2)
+ return(GPSP)
+ } //case(2)
+ } // PSH0 of switch
+
+ }
+ } // end of switch
+
+ Return(0x80000002)
+ } // end GPS
+
+
+} // end DGPU_SCOPE scope
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvVentura.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvVentura.asl
new file mode 100644
index 0000000..2de6a1c
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvVentura.asl
@@ -0,0 +1,502 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNvVentura.asl 2 9/09/12 11:01p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:01p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNvVentura.asl $
+//
+// 2 9/09/12 11:01p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] OEMSSDT.mak
+// OEMSSDT.asl
+// OEMNVdGPU.asl
+// OEMNViGPU.asl
+// OEMNViGDmisc.asl
+// OEMNvVentura.asl
+// OEMNvGPS.asl
+// OEMSSDT.cif
+//
+// 1 12/12/11 9:10p Alanlin
+//
+//
+//**********************************************************************
+// (Ventura+)>
+EXTERNAL(\_PR.CPU0, DeviceObj)
+EXTERNAL(\_PR.CPU1, DeviceObj)
+EXTERNAL(\_PR.CPU2, DeviceObj)
+EXTERNAL(\_PR.CPU3, DeviceObj)
+//> Andy+ for ClarksField -- 8 processors
+EXTERNAL(\_PR.CPU4, DeviceObj)
+EXTERNAL(\_PR.CPU5, DeviceObj)
+EXTERNAL(\_PR.CPU6, DeviceObj)
+EXTERNAL(\_PR.CPU7, DeviceObj)
+//<
+External(\_PR.CPU0._PSS, BuffObj)
+External(\_PR.CPU0._TSS, BuffObj)
+
+External(\_PR.CPU0._PPC, IntObj)
+External(\_PR.CPU1._PPC, IntObj)
+External(\_PR.CPU2._PPC, IntObj)
+External(\_PR.CPU3._PPC, IntObj)
+//> Andy+ for ClarksField -- 8 processors
+External(\_PR.CPU4._PPC, IntObj)
+External(\_PR.CPU5._PPC, IntObj)
+External(\_PR.CPU6._PPC, IntObj)
+External(\_PR.CPU7._PPC, IntObj)
+//<
+External(\_PR.CPU0._TPC, IntObj)
+External(\_PR.CPU1._TPC, IntObj)
+External(\_PR.CPU2._TPC, IntObj)
+External(\_PR.CPU3._TPC, IntObj)
+//> Andy+ for ClarksField -- 8 processors
+External(\_PR.CPU4._TPC, IntObj)
+External(\_PR.CPU5._TPC, IntObj)
+External(\_PR.CPU6._TPC, IntObj)
+External(\_PR.CPU7._TPC, IntObj)
+//<
+Scope(PCI_SCOPE){
+
+ Name(VEN, "VENACPI 2009-Nov-23 14:56:05") // MCPACPIP build time stamp.
+
+} // end of Scope
+
+Scope (DGPU_SCOPE)
+{
+ // value used to notify iGPU
+
+ Name(VSTS, 1) // Ventura Status
+ Name(THBG, 50000) // Thermal Budget
+ Name(PSCP, 0) // P-State capacity, mainly for s/w debugging
+ Name(TBUD, 0x88B8) // Thermal Budget
+// Name(PBCM, 0)
+
+ // Called by EC to notify thermal budget/status change
+ // Arg0 is one of SPB_EC_ values
+ // Arg1 is an object reference
+ Method (THCH, 2, NotSerialized)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ case ( 0x03)
+ {
+ // VSTS needs to be updated before notification
+ Store(DeRefOf(Arg1), VSTS)
+ Notify(DGPU_SCOPE, 0xC0)
+ }
+ case ( 0x01)
+ {
+ // THBG needs to be updated before notification
+ Store(DeRefOf(Arg1), THBG)
+ Notify(DGPU_SCOPE, 0xC1)
+ }
+ }
+ }
+
+ // Wrapper to call Method(SPB)
+ Method (SPB2, 2, NotSerialized)
+ {
+ Store( Buffer() {0x00, 0x00, 0x00, 0x00}, Local0 )
+ CreateDwordField(Local0, 0, LLLL)
+ Store( Arg1, LLLL )
+ Return( SPB(0x00, 0x101, Arg0, Local0) )
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: SPB
+//
+// Description: Called from _DSM -Device Specific Method for dGPU device.
+// Implement Ventura specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// Ventura DSM_GUID 95DB88FD-940A-4253-A446-70CE0504AEDF
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (SPB, 4, NotSerialized)
+ {
+
+ Store("------- SPB DSM --------", Debug)
+ // Only Interface Revision 0x0101 is supported
+ If (LNotEqual(Arg1, 0x101))
+ {
+ Return(0x80000002)
+ }
+
+ // (Arg2) Sub-Function
+ Switch (ToInteger(Arg2))
+ {
+ case (0x00)
+ {
+ Name(FMSK, Buffer(0x8)
+ {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ })
+ Store(Buffer(0x8)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }, Local0)
+ Divide(Zero, 0x8, Local2, Local1)
+ // Local1 is Quotient, Local2 is Remainder
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x20, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x21, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x22, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x23, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x24, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x2A, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ // mask out specific functions
+ Store( SizeOf(Local0), Local1)
+ While( LNotEqual(Local1, 0) ) {
+ Decrement(Local1)
+ Store( DeRefOf(Index(FMSK, Local1)), Local2)
+ And( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1) )
+ }
+
+ Return(Local0)
+ }
+
+ // Unit is mWAT
+ case(0x20)
+ {
+ Store(TBUD, Local1)
+ //failsafe to clear ventura status bit
+ And(Local1, 0xFFFFF, Local1)
+ // Just return SPB status for now (bit[0]=1 SPB enabled)
+// If(CondRefOf(PBCM,Local0)){ // Make sure this object is present.
+// If(PBCM){
+// // Software/EC have another chance to disable ventura through VSTS
+// If(LNotEqual(VSTS, 0)) {
+// Or( Local1, 0x40000000, Local1 )
+// }
+// }
+// }
+ Return(Local1)
+ }
+
+ case(0x21)
+ {
+ Return(\_PR.CPU0._PSS)
+ }
+
+ case(0x22)
+ {
+ CreateByteField(Arg3, 0, PCAP)
+
+ Store(PCAP, PSCP)
+ // \_PR.CPU0._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU0, 0x80)
+
+ If(CondRefOf(\_PR.CPU1._PPC, Local0)) {
+ // \_PR.CPU1._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU1, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU2._PPC, Local0)) {
+ // \_PR.CPU2._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU2, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU3._PPC, Local0)) {
+ // \_PR.CPU3._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU3, 0x80)
+ }
+
+//> Andy+ for ClarksField -- 8 processors
+ If(CondRefOf(\_PR.CPU4._PPC, Local0)) {
+ // \_PR.CPU4._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU4, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU5._PPC, Local0)) {
+ // \_PR.CPU5._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU5, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU6._PPC, Local0)) {
+ // \_PR.CPU6._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU6, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU7._PPC, Local0)) {
+ // \_PR.CPU7._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU7, 0x80)
+ }
+//<
+
+ Return(PCAP)
+ }
+
+ case( 0x23)
+ {
+ Return(PSCP)
+ }
+
+ case(0x24)
+ {
+ CreateField(Arg3, 0, 20, THBG)
+ CreateField(Arg3, 30, 1, DDVE)
+ }
+ case(0x2a)
+ {
+ Return(SSNR(Arg3))
+ }
+ } // end of switch
+
+ Return(0x80000002)
+ } // end SPB
+
+ // Ventura Sensor parameters header structure
+ Name(SBHS, Buffer(0x8) {})
+ CreateDWordField(SBHS, 0, VERV)
+ CreateDWordField(SBHS, 4, NUMS)
+
+ // Ventura CPU Sensor structure
+ Name(SSCP, Buffer(44) {})
+ CreateDWordField(SSCP, 4, CSNT)
+ CreateDWordField(SSCP, 8, CPTI)
+ CreateDWordField(SSCP, 12, CICA)
+ CreateDWordField(SSCP, 16, CIRC)
+ CreateDWordField(SSCP, 20, CICV)
+ CreateDWordField(SSCP, 24, CIRA)
+ CreateDWordField(SSCP, 28, CIAV)
+ CreateDWordField(SSCP, 32, CIEP)
+ CreateDWordField(SSCP, 36, CPPF)
+ CreateDWordField(SSCP, 40, CSNR)
+
+ // Ventura GPU Sensor structure
+ Name(SSGP, Buffer(44) {})
+ CreateDWordField(SSGP, 4, GSNT)
+ CreateDWordField(SSGP, 8, GPTI)
+ CreateDWordField(SSGP, 12, GICA)
+ CreateDWordField(SSGP, 16, GIRC)
+ CreateDWordField(SSGP, 20, GICV)
+ CreateDWordField(SSGP, 24, GIRA)
+ CreateDWordField(SSGP, 28, GIAV)
+ CreateDWordField(SSGP, 32, GIEP)
+ CreateDWordField(SSGP, 36, GPPF)
+ CreateDWordField(SSGP, 40, GSNR)
+
+ // Ventura CPU Parameters Structure
+ Name(SCPP, Buffer(72) {})
+ CreateDWordField(SCPP, 0, VRV1)
+ CreateDWordField(SCPP, 4, VCAP)
+ CreateDWordField(SCPP, 8, VCCP)
+ CreateDWordField(SCPP, 12, VCDP)
+ CreateDWordField(SCPP, 16, VCEP)
+ CreateDWordField(SCPP, 20, VCGP)
+ CreateDWordField(SCPP, 24, VCHP)
+ CreateDWordField(SCPP, 28, VCXP)
+ CreateDWordField(SCPP, 32, VCYP)
+ CreateDWordField(SCPP, 36, VCZP)
+ CreateDWordField(SCPP, 40, VCKP)
+ CreateDWordField(SCPP, 44, VCMP)
+ CreateDWordField(SCPP, 48, VCNP)
+ CreateDWordField(SCPP, 52, VCAL)
+ CreateDWordField(SCPP, 56, VCBE)
+ CreateDWordField(SCPP, 60, VCGA)
+ CreateDWordField(SCPP, 64, VCPP)
+ CreateDWordField(SCPP, 68, VCDE)
+
+// Ventura GPU Parameters Structure
+ Name(SGPP, Buffer(40) {})
+ CreateDWordField(SGPP, 0, VRV2)
+ CreateDWordField(SGPP, 4, VGWP)
+ CreateDWordField(SGPP, 8, VGPP)
+ CreateDWordField(SGPP, 12, VGQP)
+ CreateDWordField(SGPP, 16, VGRP)
+ CreateDWordField(SGPP, 20, VGAP)
+ CreateDWordField(SGPP, 24, VGBP)
+ CreateDWordField(SGPP, 28, VGCP)
+ CreateDWordField(SGPP, 32, VGDP)
+ CreateDWordField(SGPP, 36, VGDE)
+
+ Method(SSNR, 1)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ case (0x00)
+ {
+ // Populate Header Structure
+ Store(0x00010000, VERV)
+ Store(0x02, NUMS)
+ Return(SBHS)
+ }
+ case (0x01)
+ {
+ Store(0x00010000, VRV1)
+ Store(0x3E8, VCAP) //VEN_CPU_PARAM_A_CK 0x3E8
+ Store(0x2EE, VCCP) //VEN_CPU_PARAM_C_CK 0x2EE
+ Store(0x2EE, VCDP) //VEN_CPU_PARAM_D_CK 0x2EE
+ Store(0x2EE, VCEP) //VEN_CPU_PARAM_E_CK 0x2EE
+ Store(0x79e, VCGP) //VEN_CPU_PARAM_G_CK 0x79e
+ Store(0x2bc, VCHP) //VEN_CPU_PARAM_H_CK 0x2bc
+ Store(0x258, VCXP) //VEN_CPU_PARAM_X_CK 0x258
+ Store(0x0fa, VCYP) //VEN_CPU_PARAM_Y_CK 0x0fa
+ Store(0x1f4, VCZP) //VEN_CPU_PARAM_Z_CK 0x1f4
+ Store(0x000, VCKP) //VEN_CPU_PARAM_K_CK 0x000
+ Store(0x000, VCMP) //VEN_CPU_PARAM_M_CK 0x000
+ Store(0x000, VCNP) //VEN_CPU_PARAM_N_CK 0x000
+ Store(0x000, VCPP) //VEN_CPU_PARAM_P_CK 0x000
+ Store(0x421, VCAL) //VEN_CPU_PARAM_AL_CK 0x421
+ Store(0x708, VCBE) //VEN_CPU_PARAM_BE_CK 0x708
+ Store(0x016, VCGA) //VEN_CPU_PARAM_GA_CK 0x016
+ Store(0x001, VCDE) //VEN_CPU_PARAM_DEL_CK 0x001
+/* Clarksfield 8 CPU
+ Store(0x3E8, VCAP)
+ Store(0x258, VCCP)
+ Store(0x258, VCDP)
+ Store(0x258, VCEP)
+ Store(0x2CF, VCGP)
+ Store(0x311, VCHP)
+ Store(0x136, VCXP)
+ Store(0x118, VCYP)
+ Store(0x19A, VCZP)
+ Store(0x001, VCKP)
+ Store(0x001, VCMP)
+ Store(0x001, VCNP)
+ Store(0x000, VCPP)
+ Store(0x36B, VCAL)
+ Store(0x13C, VCBE)
+ Store(0x019, VCGA)
+ Store(0x001, VCDE)
+end Clarksfield 8CPUs*/
+
+ Return(SCPP)
+ }
+ case (0x02)
+ {
+ Store(0x00010000, VRV2)
+ Store(0x3E8, VGWP)
+ Store(0x2EE, VGPP)
+ Store(0x2EE, VGQP)
+ Store(0x2EE, VGRP)
+ Store(0x001, VGAP)
+ Store(0x1F4, VGBP)
+ Store(0x000, VGCP)
+ Store(0x000, VGDP)
+ Store(0x001, VGDE)
+/* Clarksfield 8 CPU
+ Store(0x3E8, VGBP)
+ Store(0x001, VGCP)
+ Store(0x001, VGDP)
+ Store(0x000, VGDE)
+end Clarksfield 8CPUs*/
+ Return(SGPP)
+ }
+ case (0x03)
+ {
+ // The below sensor parameter values for GPU and CPU
+ // are board specific. To support for ventura, fill
+ // the SSCP and SSGP structures
+
+ // Populate CPU Sensor values
+ Store(0x0, Index(SSCP, 0)) // Indicate CPU sensor
+ Store(0x00, CSNT)
+ Store(0x01, CPTI)
+ Store(0x84, CICA) // 0x80
+ Store(0x00, CIRC)
+ Store(0x27FF, CICV)
+ Store(0x05, CIRA)
+ Store(0xA000, CIAV)
+ Store(0x03, CIEP)
+ Store(0x0F, CPPF)
+ Store(0x04, CSNR)
+
+ // Populate GPU Sensor values
+ Store(0x1, Index(SSGP, 0)) // Indicate GPU sensor
+ Store(0x00, GSNT)
+ Store(0x01, GPTI)
+ Store(0x8C, GICA) // 0x8A
+ Store(0x00, GIRC)
+ Store(0x27FF, GICV)
+ Store(0x05, GIRA)
+ Store(0xA000, GIAV)
+ Store(0x03, GIEP)
+ Store(0x0F, GPPF)
+ Store(0x04, GSNR)
+
+ Return(Concatenate(SSCP, SSGP))
+ }
+
+ } //switch end
+
+ Return(0x80000002)
+ }
+} // end DGPU_SCOPE scope
+
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.asl
new file mode 100644
index 0000000..f086336
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.asl
@@ -0,0 +1,196 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMSSDT.asl 2 9/09/12 11:01p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:01p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMSSDT.asl $
+//
+// 2 9/09/12 11:01p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] OEMSSDT.mak
+// OEMSSDT.asl
+// OEMNVdGPU.asl
+// OEMNViGPU.asl
+// OEMNViGDmisc.asl
+// OEMNvVentura.asl
+// OEMNvGPS.asl
+// OEMSSDT.cif
+//
+// 2 12/22/11 6:38a Alanlin
+// Declared "defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)"
+//
+// 1 12/12/11 9:10p Alanlin
+//
+//
+//**********************************************************************
+
+DefinitionBlock (
+ "OEMACPI.aml",
+ "SSDT",
+ 1,
+ "OEMRef",
+ "OEMTabl",
+ 0x1000
+ ) {
+
+#define OPTIMUS_DSM_GUID 1
+//#define NBCI_DSM_GUID 1
+
+External(P8XH, MethodObj)
+#if defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)
+#define P8DB(arg0, arg1, arg2) P8XH (0, arg1) P8XH (1, arg0) sleep(arg2)
+#else
+#define P8DB(arg0, arg1, arg2)
+#endif
+
+
+External(PCI_SCOPE, DeviceObj)
+External(PEG_SCOPE, DeviceObj)
+External(DGPU_SCOPE, DeviceObj)
+External(IGPU_SCOPE, DeviceObj)
+External(DGPU_SCOPE._ADR, DeviceObj)
+External(IGPU_SCOPE._DSM, MethodObj)
+External(DGPU_SCOPE.SGST, MethodObj)
+External(DGPU_SCOPE.SGON, MethodObj)
+External(DGPU_SCOPE.SGOF, MethodObj)
+External(DGPU_SCOPE.SGPI, MethodObj)
+External(DGPU_SCOPE.SGPO, MethodObj)
+External(\DSEL)
+External(\ESEL)
+External(\SSEL)
+External(\PSEL)
+External(\HLRS)
+External(\PWEN)
+External(\PWOK)
+External(\SGMD)
+External(\SGFL)
+External(\SSMP)
+
+#include <OEMNVdGPU.ASL> // Include DGPU device namespace
+#include <OEMNViGPU.ASL> // Include NVHG DSM calls
+//#include <NViGDmisc.ASL> // Include misc event callback methods
+#include <OEMNvGPS.ASL> // Include GPS support
+
+
+Scope(PEG_SCOPE)
+{
+ Method(_STA,0,Serialized)
+ {
+ Return(0x000F)
+ }
+}
+
+ Scope(PCI_SCOPE)
+ {
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: WMI1
+//
+// Description: WMI MXM Mapper. ASL Device is used to acccess Nv Optimus native method via WMI API
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Device(WMI1) // placed within PCI Bus scope parallel to iGPU
+ {
+ Name(_HID, "PNP0C14")
+ Name(_UID, "OPT1")
+
+ Name(_WDG, Buffer()
+ {
+ // Methods GUID {F6CB5C3C-9CAE-4ebd-B577-931EA32A2CC0}
+ 0x3C, 0x5C, 0xCB, 0xF6, 0xAE, 0x9C, 0xbd, 0x4e, 0xB5, 0x77, 0x93, 0x1E,
+ 0xA3, 0x2A, 0x2C, 0xC0,
+ 0x4D, 0x58, // Object ID "MX" = method "WMMX"
+ 1, // Instance Count
+ 0x02, // Flags (WMIACPI_REGFLAG_METHOD)
+ }) // End of _WDG
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: WMMX
+//
+// Description: WMI Method execution tunnel. MXM Native methods are called via WMMX index.
+//
+// Input:
+// Arg1: Integer GPU index. 0x10-iGPU, 0x100+PCIe Bus number for the GPU
+//
+// Output:
+// Buffer specific to the funcion being called
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(WMMX, 3)
+ {
+
+ //Arg1 = 0x10 indicates iGPU, 0x100+PCIe Bus number for the GPU
+ //
+ CreateDwordField(Arg2, 0, FUNC) // Get the function name
+
+ If (LEqual(FUNC, 0x534F525F)) // "_ROM"
+ {
+ If (LGreaterEqual(SizeOf(Arg2), 8))
+ {
+ CreateDwordField(Arg2, 4, ARGS)
+ CreateDwordField(Arg2, 8, XARG)
+ Return(DGPU_SCOPE._ROM(ARGS, XARG))
+ }
+ }
+
+ If (LEqual(FUNC, 0x4D53445F)) // "_DSM"
+ {
+ If (LGreaterEqual(SizeOf(Arg2), 28))
+ {
+ CreateField(Arg2, 0, 128, MUID)
+ CreateDwordField(Arg2, 16, REVI)
+ CreateDwordField(Arg2, 20, SFNC)
+ CreateField(Arg2, 0xe0, 0x20, XRG0)
+
+// If(LNotEqual(Arg1,0x10))
+// {
+ If (CondRefOf(IGPU_SCOPE._DSM)) // common with dGPU DSM functions
+ {
+ Return(IGPU_SCOPE._DSM(MUID, REVI, SFNC, XRG0))
+ }
+// }
+ }
+ }
+ Return(0)
+ } // End of WMMX
+ } // End of WMI1 Device
+ } // end scope PCI0
+} // end SSDT
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.cif b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.cif
new file mode 100644
index 0000000..764d465
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.cif
@@ -0,0 +1,15 @@
+<component>
+ name = "OEMSSDT"
+ category = ModulePart
+ LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\AcpiTables\OEMSSDT"
+ RefName = "OEMSSDT"
+[files]
+"OEMSSDT.sdl"
+"OEMSSDT.mak"
+"OEMSSDT.asl"
+"OEMNVdGPU.asl"
+"OEMNViGPU.asl"
+"OEMNViGDmisc.asl"
+"OEMNvVentura.asl"
+"OEMNvGPS.asl"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.mak b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.mak
new file mode 100644
index 0000000..3546d35
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.mak
@@ -0,0 +1,134 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMSSDT.mak 4 6/02/13 8:15a Joshchou $
+#
+# $Revision: 4 $
+#
+# $Date: 6/02/13 8:15a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMSSDT.mak $
+#
+# 4 6/02/13 8:15a Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Change IASL compiler path to
+# $(ACPIPLATFORM_ASL_COMPILER) in SharkBay project.
+#
+# 3 11/20/12 3:48a Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Create Token for OEM clone
+#
+# 2 9/09/12 11:01p Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Tpv module support for sharkbay.
+# [Files] OEMSSDT.mak
+# OEMSSDT.asl
+# OEMNVdGPU.asl
+# OEMNViGPU.asl
+# OEMNViGDmisc.asl
+# OEMNvVentura.asl
+# OEMNvGPS.asl
+# OEMSSDT.cif
+#
+# 1 12/12/11 9:10p Alanlin
+#
+#
+#
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name: OEMSSDT.mak
+#
+# Description: MAke file to build Aptio ACPI ASL components
+#
+#
+#<AMI_FHDR_END>
+#*************************************************************************
+all : BuildOEMSSDT
+
+BuildOEMSSDT : $(BUILD_DIR)\OEMSSDT.ffs
+
+#---------------------------------------------------------------------------
+# Generic AcpiPlatform dependencies
+#---------------------------------------------------------------------------
+$(BUILD_DIR)\OEMSSDT.mak : $(SG_OEMSSDT_DIR)\OEMSSDT.cif $(BUILD_RULES)
+ $(CIF2MAK) $(SG_OEMSSDT_DIR)\OEMSSDT.cif $(CIF2MAK_DEFAULTS)
+
+
+#-----------------------------------------------------------------------
+# ASL compiler definition
+#-----------------------------------------------------------------------
+!IF "$(ACPIPLATFORM_ASL_COMPILER)"==""
+!ERROR It is an invalid path, please check your ASL compiler path.
+!ENDIF
+
+IASL = $(ACPIPLATFORM_ASL_COMPILER)
+#-----------------------------------------------------------------------
+$(BUILD_DIR)\OEMSSDT.aml : $(BUILD_DIR)\OEMSSDT.asl
+# @cl /C /EP $(AOACACPI_ASL_FILE) > $(BUILD_DIR)\AoacAcpi.asl
+# $(IASL) -p $(BUILD_DIR)\OEMSSDT.aml $(SGOEMSSDT_ASL_FILE)
+ $(IASL) -p $@ $*.asl
+
+$(BUILD_DIR)\OEMSSDT.sec: $(BUILD_DIR)\OEMSSDT.aml
+ $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW
+
+#Note. Expand the package with OEMSSDT tables.
+# DXE phase will load the tables
+# and update Aml contents if provided in SgTpvAcpiTables.c
+
+$(BUILD_DIR)\OEMSSDT.ffs: $(BUILD_DIR)\OEMSSDT.sec
+ $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\OEMSSDT.pkg
+
+PACKAGE.INF
+[.]
+BASE_NAME = OEMSSDT
+FFS_FILEGUID = 5B232086-350A-42c7-A70E-3497B5765D85
+FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM
+FFS_ATTRIB_CHECKSUM = TRUE
+
+IMAGE_SCRIPT =
+{
+ Compress (dummy) {
+ $(PROJECT_DIR)\$(BUILD_DIR)\OEMSSDT.sec
+ }
+}
+<<KEEP
+
+#-----------------------------------------------------------------------#
+# Process SG asl files
+#-----------------------------------------------------------------------#
+$(BUILD_DIR)\OEMSSDT.asl : $(SGOEMSSDT_ASL_FILE)
+ $(CP) /I$(SG_OEMSSDT_DIR) /FItoken.h /C $(SG_OEMSSDT_DIR)\$(@F) > $@
+# include the token.h if needed to check for SDL flags
+# /FItoken.h
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.sdl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.sdl
new file mode 100644
index 0000000..9d79dd6
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.sdl
@@ -0,0 +1,47 @@
+TOKEN
+ Name = "SGOEMSSDT_SUPPORT"
+ Value = "0"
+ Help = "Add an OEM SSDT for discrete VGA card. When Primarydisplay = Auto or PEG, the system can report OEM SSDT talbes for AMD or nVidia dGPU VGA card."
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+ Master = Yes
+End
+
+TOKEN
+ Name = "SGOEM_ACPI_SSDT_TABLE"
+ Value = "EFI_SIGNATURE_64 ('O', 'E', 'M', 'T', 'a', 'b', 'l', 0)"
+ Help = "SGOEM Acpi table name"
+ TokenType = Expression
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "SGOEM_ACPI_SSDT_GUID"
+ Value = "{0x5B232086, 0x350A, 0x42c7, 0xA7, 0x0E, 0x34, 0x97, 0xB5, 0x76, 0x5D, 0x85}"
+ Help = "SGTpv Acpi Package"
+ TokenType = Expression
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "SGOEMSSDT_ASL_FILE"
+ Value = "$(SG_OEMSSDT_DIR)\*.asl"
+ TokenType = Expression
+ TargetMAK = Yes
+End
+
+PATH
+ Name = "SG_OEMSSDT_DIR"
+End
+
+MODULE
+ Help = "Includes OEMSSDT.mak to Project"
+ File = "OEMSSDT.mak"
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\OEMSSDT.ffs"
+ Parent = "FV_MAIN"
+ InvokeOrder = AfterParent
+End
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.c b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.c
new file mode 100644
index 0000000..8359da3
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.c
@@ -0,0 +1,988 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvAcpiTables.c 7 3/21/13 3:48a Joshchou $
+//
+// $Revision: 7 $
+//
+// $Date: 3/21/13 3:48a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvAcpiTables.c $
+//
+// 7 3/21/13 3:48a Joshchou
+// [TAG] EIPEIP116106
+// [Category] Bug Fix
+// [Severity] Minor
+// [Symptom] ACPI error in Win8 event viewer on ULT platform
+// [RootCause] We use the PCI_config to save/restore registers,and the
+// value of EBAS is wrong.
+// [Solution] Save the correct value of EBAS in "SgTpvAcpiTables.c"
+// Use the MMIO to save/restore registers
+//
+// 6 1/15/13 6:06a Joshchou
+// [TAG] EIP107237
+// [Category] Improvement
+// [Description] Modify for support SG on ULT platform.
+//
+// 5 12/22/12 2:38a Joshchou
+// [TAG] None
+// [Category] Bug Fix
+// [Severity] Normal
+// [Symptom] Did not get the correct Endpoint Link Contol Register Value
+// [RootCause] Give the wrong address.
+// [Solution] Fix the address.
+//
+// 4 12/18/12 6:21a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Update for SA RC 081
+//
+// 3 10/16/12 4:41a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Update for SA and ACPI RC 0.7.1
+// [Files] SgTpvAcpiTables.c
+//
+// 2 9/09/12 10:57p Joshchou
+//
+// 3 12/12/11 9:17p Alanlin
+// [TAG] EIP74169
+// [Category] Improvement
+// [Description] Add OEMSSDT module part. Token "SGOEMSSDT_SUPPORT" to
+// create OEM SSDT
+// for discrete VGA card.When Primarydisplay = Auto or PEG, it can report
+// OEM SSDT
+// talbes for AMD or nVidia dGPU VGA card.
+// [Files] SgTpvAcpiTables.c
+// SgTpvAcpiTables.cif
+//
+// 2 12/02/11 5:38a Alanlin
+// [TAG] EIP75211
+// [Category] Improvement
+// [Description] Changeing VBIOS size to 128k for _ROM method for nVidia
+// chip.
+//
+// 1 6/27/11 5:26a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgTpvAcpiTables.cif
+// SgTpvAcpiTables.sdl
+// SgTpvAcpiTables.mak
+// SgTpvAcpiTables.c
+//
+//
+// 10 3/17/11 6:15p Alexp
+// Optimus:Add code to preserve HD AudioCodec enable flag in CMOS
+//
+// 9 1/03/11 12:35p Alexp
+// [TAG] EIP50104
+// [Category] Bug Fix
+// [Severity] Normal
+// [Symptom] Nvidia GPU device disappears after S3 resume
+// [RootCause] PEG bridge controller was not restoring secondary and
+// subiordinate bus numbers on S3 resume
+// [Solution] add code to save/restore PCI context using S3_resume
+// Scripts
+// [Files] SgTpvAcpiTables.c
+//
+// 8 11/12/10 1:19p Alexp
+// rearrange the code for Amd and Nvidia tables.
+// Add WiDi DID number if WiDi support is selected in GlobalAcpiNvs flags
+//
+// 7 11/11/10 3:09p Alexp
+// Add debug messages
+//
+// 6 10/06/10 4:17p Alexp
+// comments chnage for NvidiaOpRegion header
+//
+// 5 10/05/10 7:08p Alexp
+// added new field in NVH OpRegion to pass MXM3 data block.
+//
+// 4 9/29/10 1:23p Alexp
+// [TAG] EIP43103 --->change code to update dGPU SVID registers
+//
+// 3 9/23/10 1:12p Alexp
+// BUG fix in disable logic for Func1 on PEG endpoint (HDA) for Optimus
+//
+// 2 9/21/10 5:09p Alexp
+// [TAG] EIP43103 --->fix debug messages
+//
+// 1 9/17/10 1:18p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgTpvAcpiTables.cif;*.sdl;*.mak;*.c
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name: SgTpvAcpiTables.c
+//
+// Description: This file contains the routine LoadTpvAcpiTables which installs
+// Acpi Tables for Tpv's Switchable Graphics.
+// File is linked with Intel's SwitchableGraphicsDxe module
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+
+#include "SgTpvAcpitables.h"
+//<AMI_THDR_START>
+//----------------------------------------------------------------------------
+// Procedure: NvidiaOpRegion & AmdOpRegion
+//
+// Description: Gfx Vendor specific OperationRegion data structures.
+// Must match ones defined in Asl code
+//
+//----------------------------------------------------------------------------
+//<AMI_THDR_END>
+NVIDIA_OPREGION NvidiaOpRegion;
+AMD_OPREGION AmdOpRegion;
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: LoadTpvAcpiTables
+//
+// Description: Load Third part graphics vendor support SSDT Tables
+//
+// Input: VOID
+//
+// Output:
+// EFI_SUCCESS - SSDT Table load successful.
+// EFI_UNSUPPORTED - Supported SSDT not found.
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS
+LoadTpvAcpiTables (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ BOOLEAN LoadTable;
+ INTN Instance;
+ UINTN NumberOfHandles;
+ UINTN Index;
+ UINTN Size;
+ UINTN TableHandle;
+//UINT16 Data16;
+//UINT32 Data32;
+ UINT32 FvStatus;
+#if (PI_SPECIFICATION_VERSION < 0x00010000)
+ EFI_FIRMWARE_VOLUME_PROTOCOL *FwVol;
+#else
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+#endif
+ EFI_FV_FILETYPE FileType;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
+ EFI_ACPI_TABLE_VERSION Version;
+// EFI_GUID SGTPV_AcpiTableGuid= SGTPV_ACPI_SSDT_GUID;
+ EFI_GUID SGTPV_AcpiTableGuid;
+ EFI_GUID gSgtpvAcpiSsdtGuid= SGTPV_ACPI_SSDT_GUID;
+ EFI_GUID gSgtpvAcpiPchSsdtGuid= SGTPV_ACPIPCH_SSDT_GUID;
+
+#if SGOEMSSDT_SUPPORT
+ EFI_GUID SGOEM_AcpiTableGuid = SGOEM_ACPI_SSDT_GUID;
+#endif
+ EFI_ACPI_SUPPORT_PROTOCOL *AcpiSupport;
+ EFI_ACPI_COMMON_HEADER *Table;
+
+ UINT16 VendorId;
+
+
+ FwVol = NULL;
+ Table = NULL;
+
+ DEBUG ((EFI_D_ERROR, "CpuFamilyId ==0x%X\n", CpuFamilyId));
+ SGTPV_AcpiTableGuid = gSgtpvAcpiSsdtGuid;
+ if (CpuFamilyId == EnumCpuHswUlt) {
+ SGTPV_AcpiTableGuid = gSgtpvAcpiPchSsdtGuid;
+ }
+
+
+
+ VendorId = McDevFunPciCfg16 (EndpointBus, 0, 0, PCI_VID); // DEBUG
+ DEBUG ((EFI_D_ERROR, "SG TPV Vendor ID %X\n", VendorId));
+
+ switch(VendorId){
+ case NVIDIA_VID:
+ //
+ // Set VendorId if PEG is NVIDIA and supports HG
+ //
+ VendorId = NVIDIA_VID;
+ break;
+ case AMD_VID:
+ //
+ // Set VendorId if PEG is AMD and supports HG
+ //
+ VendorId = AMD_VID;
+ break;
+ default:
+ //
+ // either means the Device ID is not on the list of devices we know - we return from this function
+ //
+ DEBUG ((EFI_D_ERROR, "SG TPV Unsupported Vendor ID\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+
+ ///
+ /// Locate the SA Global NVS Protocol.
+ ///
+ Status = gBS->LocateProtocol (
+ &gSaGlobalNvsAreaProtocolGuid,
+ NULL,
+ (VOID **) &SaGlobalNvsArea
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ SaGlobalNvsArea->Area->EndpointBaseAddress = (UINT32) (MmPciAddress (0, EndpointBus, 0, 0, 0x0));
+
+ //
+ // Locate FV protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ #if (PI_SPECIFICATION_VERSION < 0x00010000)
+ &gEfiFirmwareVolumeProtocolGuid,
+ #else
+ &gEfiFirmwareVolume2ProtocolGuid,
+ #endif
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Look for FV with ACPI storage file
+ //
+ for (Index = 0; Index < NumberOfHandles; Index++) {
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ #if (PI_SPECIFICATION_VERSION < 0x00010000)
+ &gEfiFirmwareVolumeProtocolGuid,
+ #else
+ &gEfiFirmwareVolume2ProtocolGuid,
+ #endif
+ &FwVol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // See if it has the ACPI storage file
+ //
+ Size = 0;
+ FvStatus = 0;
+ Status = FwVol->ReadFile (
+ FwVol,
+ &SGTPV_AcpiTableGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ //
+ // If we found it, then we are done
+ //
+ if (!EFI_ERROR (Status)) {
+ break;
+ }
+ }
+
+ //
+ // Our exit status is determined by the success of the previous operations
+ // If the protocol was found, Instance already points to it.
+ //
+ //
+ // Free any allocated buffers
+ //
+ (gBS->FreePool) (HandleBuffer);
+
+ //
+ // Sanity check that we found our data file
+ //
+ ASSERT (FwVol);
+
+ //
+ // By default, a table belongs in all ACPI table versions published.
+ //
+ Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
+
+ //
+ // Locate ACPI tables
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiSupportGuid,
+ NULL,
+ &AcpiSupport
+ );
+
+
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Read tables from the storage file.
+ //
+ Instance = 0;
+
+ while (Status == EFI_SUCCESS) {
+ //
+ // Read the ACPI tables
+ //
+ Status = FwVol->ReadSection (
+ FwVol,
+ &SGTPV_AcpiTableGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ &Table,
+ &Size,
+ &FvStatus
+ );
+ if (!EFI_ERROR (Status)) {
+ //
+ // check for SwitchableGraphics tables and decide which SSDT should be loaded
+ //
+ LoadTable = FALSE;
+ TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
+
+ DEBUG ((EFI_D_ERROR, "SG TPV SSDT TblID %X\n", TableHeader->OemTableId));
+
+ switch (((EFI_ACPI_DESCRIPTION_HEADER *) TableHeader)->OemTableId) {
+
+ case EFI_SIGNATURE_64 ('N', 'v', 'd', 'T', 'a', 'b', 'l', 0):
+ if(VendorId != NVIDIA_VID ||
+ SaGlobalNvsArea->Area->SgMode != SgModeMuxed)
+ break;
+
+ DEBUG ((EFI_D_ERROR, "SG TPV Nvidia SG Table\n"));
+ //
+ // This is Nvidia SSDT
+ //
+ LoadTable = TRUE;
+ Status = InstallNvidiaOpRegion ();
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ break;
+
+ case EFI_SIGNATURE_64 ('O', 'p', 't', 'T', 'a', 'b', 'l', 0):
+ if(VendorId != NVIDIA_VID ||
+ SaGlobalNvsArea->Area->SgMode != SgModeMuxless)
+ break;
+
+ DEBUG ((EFI_D_ERROR, "SG TPV Nvidia Optimus Table\n"));
+ //
+ // This is nVidia Optimus SSDT
+ //
+ LoadTable = TRUE;
+ Status = InstallNvidiaOpRegion();
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ break;
+
+ case EFI_SIGNATURE_64 ('A', 'm', 'd', 'T', 'a', 'b', 'l', 0):
+ if(VendorId != AMD_VID)
+ break;
+ //
+ // This is Amd SSDT
+ //
+ LoadTable = TRUE;
+ Status = InstallAmdOpRegion ();
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ break;
+
+ default:
+ DEBUG ((EFI_D_ERROR, "WARNING: SG TPV Unsupported SSDT Signature...\n"));
+ break;
+ }
+
+ //
+ // Add the table
+ //
+ if (LoadTable) {
+ TableHandle = 0;
+ Status = AcpiSupport->SetAcpiTable (
+ AcpiSupport,
+ TableHeader,
+ TRUE,
+ Version,
+ &TableHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+ Status = AcpiSupport->PublishTables (
+ AcpiSupport,
+ Version
+ );
+ ASSERT_EFI_ERROR (Status);
+// if (EFI_ERROR(Status)) break;
+ break; // only one ACPI SG/Optimus table should be loaded
+ }
+ //
+ // Increment the instance
+ //
+ Instance++;
+ Table = NULL;
+ }
+ }
+
+#if SGOEMSSDT_SUPPORT
+ //
+ // Locate ACPI tables
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiSupportGuid,
+ NULL,
+ &AcpiSupport
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Read tables from the storage file.
+ //
+ Instance = 0;
+
+ while (Status == EFI_SUCCESS) {
+ //
+ // Read the ACPI tables
+ //
+ Status = FwVol->ReadSection (
+ FwVol,
+ &SGOEM_AcpiTableGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ &Table,
+ &Size,
+ &FvStatus
+ );
+ if (!EFI_ERROR (Status)) {
+ //
+ // check for SwitchableGraphics tables and decide which SSDT should be loaded
+ //
+ LoadTable = FALSE;
+ TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
+
+ DEBUG ((EFI_D_ERROR, "SG TPV SSDT TblID %X\n", TableHeader->OemTableId));
+
+ switch (((EFI_ACPI_DESCRIPTION_HEADER *) TableHeader)->OemTableId) {
+
+ //
+ // Set OEM SSDT
+ //
+
+ case SGOEM_ACPI_SSDT_TABLE:
+ if(SaGlobalNvsArea->Area->SgMode != SgModeDgpu)
+ break;
+
+ DEBUG ((EFI_D_ERROR, "OEM SSDT Table\n"));
+ //
+ // This is OEM SSDT
+ //
+ LoadTable = TRUE;
+ if(VendorId == NVIDIA_VID)
+ Status = InstallNvidiaOpRegion ();
+ else
+ Status = InstallAmdOpRegion();
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ break;
+
+ default:
+ DEBUG ((EFI_D_ERROR, "WARNING: SG OEM Unsupported SSDT Signature...\n"));
+ break;
+ }
+
+ //
+ // Add the table
+ //
+ if (LoadTable) {
+ TableHandle = 0;
+ Status = AcpiSupport->SetAcpiTable (
+ AcpiSupport,
+ TableHeader,
+ TRUE,
+ Version,
+ &TableHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+ Status = AcpiSupport->PublishTables (
+ AcpiSupport,
+ Version
+ );
+ ASSERT_EFI_ERROR (Status);
+// if (EFI_ERROR(Status)) break;
+ break; // only one ACPI SG/Optimus table should be loaded
+ }
+ //
+ // Increment the instance
+ //
+ Instance++;
+ Table = NULL;
+ }
+ }
+#endif
+
+ DEBUG ((EFI_D_ERROR, "SGtpv:: NDID:0x%x\n", SaGlobalNvsArea->Area->NumberOfValidDeviceId));
+ DEBUG ((EFI_D_ERROR, "SGtpv:: DID1:0x%x\n", SaGlobalNvsArea->Area->DeviceId1));
+ DEBUG ((EFI_D_ERROR, "SGtpv:: DID2:0x%x\n", SaGlobalNvsArea->Area->DeviceId2));
+ DEBUG ((EFI_D_ERROR, "SGtpv:: DID3:0x%x\n", SaGlobalNvsArea->Area->DeviceId3));
+ DEBUG ((EFI_D_ERROR, "SGtpv:: DID4:0x%x\n", SaGlobalNvsArea->Area->DeviceId4));
+ DEBUG ((EFI_D_ERROR, "SGtpv:: DID5:0x%x\n", SaGlobalNvsArea->Area->DeviceId5));
+ DEBUG ((EFI_D_ERROR, "SGtpv:: DID6:0x%x\n", SaGlobalNvsArea->Area->DeviceId6));
+ DEBUG ((EFI_D_ERROR, "SGtpv:: DID7:0x%x\n", SaGlobalNvsArea->Area->DeviceId7));
+ DEBUG ((EFI_D_ERROR, "SGtpv:: DID8:0x%x\n", SaGlobalNvsArea->Area->DeviceId8));
+
+ DEBUG ((EFI_D_ERROR, "SG TPV Gfx acpi UPDATE - COMPLETED\n"));
+ return EFI_SUCCESS;
+}
+
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+//Procedure: InstallNvidiaOpRegion
+//
+//Description: Nvidia SG specific Asl OpRegion installation function.
+//
+//Input:
+//
+// ImageHandle Handle for this drivers loaded image protocol.
+// SystemTable EFI system table.
+//
+//Output:
+//
+// EFI_SUCCESS The driver installed without error.
+// EFI_ABORTED The driver encountered an error and could not complete
+// installation of the ACPI tables.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS
+InstallNvidiaOpRegion (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN Size;
+// Locate MXM3 protocol and get Mxm data pointer from function->MxmReturnStructure
+ EFI_GUID EfiMxm3ProtocolGuid = MXM3_EFI_GUID;
+#if MXM30_SUPPORT == 1
+ MXM3_EFI_PROTOCOL *Mxm30Protocol;
+ VOID *MxmLegMemAddr = NULL;
+ UINT32 MxmLegMemSize = 0;
+#endif
+ //
+ // Allocate an ACPI NVS memory buffer as the Nvidia NVIG OpRegion, zero initialize
+ // the entire 1K, and set the Nvidia NVIG OpRegion pointer in the Global NVS
+ // area structure.
+ //
+ Size = sizeof (NVIG_OPREGION);
+ Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, Size, &NvidiaOpRegion.NvIgOpRegion);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ (gBS->SetMem) (NvidiaOpRegion.NvIgOpRegion, Size, 0);
+
+ //
+ // Set up DeviceID values for _DOD.
+ // Note that Display Subtype bits[15-12] and Port index bits[7:4] are set as per NV Switchable 3.0 spec.
+ // Not used by Intel driver.
+ //
+ //
+ // Display Type - CRT
+ //
+ SaGlobalNvsArea->Area->DeviceId1 = 0x80010100;
+
+ if (SaGlobalNvsArea->Area->ActiveLFP == 3) {
+ //
+ // If Active LFP = EDP_A
+ //
+ // Display type - LFP Device Sub Type - eDP
+ //
+ SaGlobalNvsArea->Area->DeviceId2 = 0x8001A420;
+ } else {
+ //
+ // Display Type - LFP Device Sub Type - LVDS
+ //
+ SaGlobalNvsArea->Area->DeviceId2 = 0x80010410;
+ }
+ //
+ // Display type - EFP Device Sub type - DisplayPort 1.1
+ //
+ SaGlobalNvsArea->Area->DeviceId3 = 0x80016330 | ((SaGlobalNvsArea->Area->SgMuxDid3 & 0xFF00) << 10);
+
+ //
+ // Display type - EFP Device Sub type - HDMI 1.2 or 1.3a
+ //
+ SaGlobalNvsArea->Area->DeviceId4 = 0x80017331 | ((SaGlobalNvsArea->Area->SgMuxDid4 & 0xFF00) << 10);
+
+ //
+ // Display type - EFP Device Sub type - HDMI 1.2 or 1.3a
+ //
+ SaGlobalNvsArea->Area->DeviceId5 = 0x80017342 | ((SaGlobalNvsArea->Area->SgMuxDid5 & 0xFF00) << 10);
+
+ //
+ // Display type - EFP Device Sub type - DisplayPort 1.1
+ //
+ SaGlobalNvsArea->Area->DeviceId6 = 0x80016353 | ((SaGlobalNvsArea->Area->SgMuxDid6 & 0xFF00) << 10);
+
+ //
+ // Display type - EFP Device Sub type - HDMI 1.2 or 1.3a
+ //
+ SaGlobalNvsArea->Area->DeviceId7 = 0x80017354 | ((SaGlobalNvsArea->Area->SgMuxDid7 & 0xFF00) << 10);
+
+ //
+ // DeviceId8 is not being used on HuronRiver SG
+ //
+ SaGlobalNvsArea->Area->DeviceId8 = 0x0;
+
+ //
+ // NDID
+ //
+ SaGlobalNvsArea->Area->NumberOfValidDeviceId = VALIDDIDS;//0x7;
+
+ //
+ // NVIG
+ //
+ SaGlobalNvsArea->Area->NvIgOpRegionAddress = (UINT32)(UINTN)(NvidiaOpRegion.NvIgOpRegion);
+
+ //
+ // NVIG Header
+ //
+ (gBS->CopyMem) (NvidiaOpRegion.NvIgOpRegion->NISG, NVIG_HEADER_SIGNATURE, sizeof (NVIG_HEADER_SIGNATURE));
+ NvidiaOpRegion.NvIgOpRegion->NISZ = NVIG_OPREGION_SIZE;
+ NvidiaOpRegion.NvIgOpRegion->NIVR = NVIG_OPREGION_VER;
+
+ //
+ // Panel Scaling Preference
+ //
+ NvidiaOpRegion.NvIgOpRegion->GPSP = SaGlobalNvsArea->Area->IgdPanelScaling;
+
+
+ // Save Link Control register
+ NvidiaOpRegion.NvIgOpRegion->ELCL= MemoryRead16((UINTN)SaGlobalNvsArea->Area->EndpointPcieCapOffset + 0x10);
+
+
+ //
+ // Allocate an ACPI NVS memory buffer as the Nvidia NVHM OpRegion, zero initialize
+ // the entire 62K, and set the Nvidia NVHM OpRegion pointer in the Global NVS
+ // area structure.
+ //
+ Size = sizeof (NVHM_OPREGION);
+ Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, Size, &NvidiaOpRegion.NvHmOpRegion);
+
+ if (EFI_ERROR (Status)) {
+ (gBS->FreePool) (NvidiaOpRegion.NvIgOpRegion);
+ return Status;
+ }
+
+ (gBS->SetMem) (NvidiaOpRegion.NvHmOpRegion, Size, 0);
+
+ //
+ // NVHM
+ //
+ SaGlobalNvsArea->Area->NvHmOpRegionAddress = (UINT32) (UINTN) (NvidiaOpRegion.NvHmOpRegion);
+
+ //
+ // NVHM Header Signature, Size, Version
+ //
+ (gBS->CopyMem) (NvidiaOpRegion.NvHmOpRegion->NVSG, NVHM_HEADER_SIGNATURE, sizeof (NVHM_HEADER_SIGNATURE));
+ NvidiaOpRegion.NvHmOpRegion->NVSZ = NVHM_OPREGION_SIZE;
+ NvidiaOpRegion.NvHmOpRegion->NVVR = NVHM_OPREGION_VER;
+
+ //
+ // NVHM opregion address
+ //
+ NvidiaOpRegion.NvHmOpRegion->NVHO = (UINT32) (UINTN) (NvidiaOpRegion.NvHmOpRegion);
+
+ //
+ // Copy Oprom to allocated space in NV Opregion
+ //
+ NvidiaOpRegion.NvHmOpRegion->RVBS = VbiosSize;
+ (gBS->CopyMem) ((VOID *) (UINTN) NvidiaOpRegion.NvHmOpRegion->RBUF, VbiosAddress, NvidiaOpRegion.NvHmOpRegion->RVBS);
+
+ //
+ // Locate the MXM3 Protocol and update Mxm struct pointers
+ //
+#if MXM30_SUPPORT == 1
+ Status = gBS->LocateProtocol (
+ &EfiMxm3ProtocolGuid,
+ NULL,
+ &Mxm30Protocol
+ );
+ if (!EFI_ERROR(Status))
+ {
+ Status = Mxm30Protocol->MxmReturnStructure(
+ Mxm30Protocol,
+ NULL,
+ (CHAR16*)&MxmLegMemSize,
+ (CHAR16)EFI30_DataBlockID,
+ (CHAR8**)&MxmLegMemAddr
+ );
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Copy MXM3 data structure to allocated space in NV Opregion
+ //
+ NvidiaOpRegion.NvHmOpRegion->MXML = MxmLegMemSize;
+ (gBS->CopyMem) ((VOID *) (UINTN) NvidiaOpRegion.NvHmOpRegion->MXM3, MxmLegMemAddr, MxmLegMemSize);
+ }
+#endif
+ if (Status != EFI_SUCCESS) {
+ (gBS->FreePool) (NvidiaOpRegion.NvIgOpRegion);
+ (gBS->FreePool) (NvidiaOpRegion.NvHmOpRegion);
+ }
+
+ return Status;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+//Procedure: InstallAmdOpRegion
+//
+//Description: Amd(ATI) SG specific Asl Graphics OpRegion installation function.
+//
+//Input:
+//
+// ImageHandle Handle for this drivers loaded image protocol.
+// SystemTable EFI system table.
+//
+//Output:
+//
+// EFI_SUCCESS The driver installed without error.
+// EFI_ABORTED The driver encountered an error and could not complete
+// installation of the ACPI tables.
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS
+InstallAmdOpRegion (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN Size;
+
+ //
+ // Allocate an ACPI NVS memory buffer as the Amd APXM OpRegion, zero initialize
+ // the entire 1K, and set the Amd APXM OpRegion pointer in the Global NVS
+ // area structure.
+ //
+ Size = sizeof (APXM_OPREGION);
+ Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, Size, &AmdOpRegion.ApXmOpRegion);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ (gBS->SetMem) (AmdOpRegion.ApXmOpRegion, Size, 0);
+
+ //
+ // APXM address
+ //
+ SaGlobalNvsArea->Area->ApXmOpRegionAddress = (UINT32) (UINTN) (AmdOpRegion.ApXmOpRegion);
+ AmdOpRegion.ApXmOpRegion->APXA = (UINT32) (UINTN) (AmdOpRegion.ApXmOpRegion);
+
+ //
+ // Note. All fields in Amd OpRegion will be initialized with Zeroes.
+ // Only update those that differ from 0.
+
+ // Set up DIDx values for _DOD
+ //
+ // Device ID - CRT on IGPU
+ //
+ SaGlobalNvsArea->Area->DeviceId1 = 0x80010100;
+
+ //
+ // Device ID - LFP (LVDS or eDP)
+ //
+ SaGlobalNvsArea->Area->DeviceId2 = 0x80010400;
+
+ //
+ // Display type - EFP Device Sub type - DisplayPort 1.1
+ //
+ SaGlobalNvsArea->Area->DeviceId3 = 0x80010300;
+
+ //
+ // Display type - EFP Device Sub type - HDMI 1.2 or 1.3a
+ //
+ SaGlobalNvsArea->Area->DeviceId4 = 0x80010301;
+
+ //
+ // Display type - EFP Device Sub type - HDMI 1.2 or 1.3a
+ //
+ SaGlobalNvsArea->Area->DeviceId5 = 0x80010302;
+
+ //
+ // Display type - EFP Device Sub type - DisplayPort 1.1
+ //
+ SaGlobalNvsArea->Area->DeviceId6 = 0x80010303;
+
+ //
+ // Display type - EFP Device Sub type - HDMI 1.2 or 1.3a
+ //
+
+ //
+ // SG Feature List for ASL usage
+ //
+ if(SaGlobalNvsArea->Area->SgFeatureList & 1) // WIRELESSDISPLAY
+ SaGlobalNvsArea->Area->DeviceId7 = 0x80010306;
+ else
+ SaGlobalNvsArea->Area->DeviceId7 = 0x80010304;
+ //
+ // DeviceId8 is not being used on HuronRiver SG
+ //
+ SaGlobalNvsArea->Area->DeviceId8 = 0x0;
+
+ //
+ // NDID
+ //
+ SaGlobalNvsArea->Area->NumberOfValidDeviceId = VALIDDIDS;//0x7;
+
+ //
+ // APXM Header
+ //
+ (gBS->CopyMem) (AmdOpRegion.ApXmOpRegion->APSG, APXM_HEADER_SIGNATURE, sizeof (APXM_HEADER_SIGNATURE));
+ AmdOpRegion.ApXmOpRegion->APSZ = APXM_OPREGION_SIZE;
+ AmdOpRegion.ApXmOpRegion->APVR = APXM_OPREGION_VER;
+
+ //
+ // Total number of toggle list entries
+ //
+ AmdOpRegion.ApXmOpRegion->NTLE = 15;
+
+ //
+ // The display combinations in the list...
+ //
+ //
+ // CRT
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[0] = 0x0002;
+ //
+ // LFP
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[1] = 0x0001;
+ //
+ // DP_B
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[2] = 0x0008;
+ //
+ // HDMI_B
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[3] = 0x0080;
+ //
+ // HDMI_C
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[4] = 0x0200;
+ //
+ // DP_D
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[5] = 0x0400;
+ //
+ // HDMI_D
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[6] = 0x0800;
+ //
+ // LFP+CRT
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[7] = 0x0003;
+ //
+ // LFP+DP_B
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[8] = 0x0009;
+ //
+ // LFP+HDMI_B
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[9] = 0x0081;
+ //
+ // LFP+HDMI_C
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[10] = 0x0201;
+ //
+ // LFP+DP_D
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[11] = 0x0401;
+ //
+ // LFP+HDMI_D
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[12] = 0x0801;
+ //
+ // Dummy 1
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[13] = 0x0;
+ //
+ // Dummy 2
+ //
+ AmdOpRegion.ApXmOpRegion->TLEX[14] = 0x0;
+
+ //
+ // Panel Scaling Preference
+ //
+ AmdOpRegion.ApXmOpRegion->EXPM = SaGlobalNvsArea->Area->IgdPanelScaling;
+
+
+ // Save Link Control register
+ AmdOpRegion.ApXmOpRegion->ELCL= MemoryRead16((UINTN)SaGlobalNvsArea->Area->EndpointPcieCapOffset + 0x10);
+
+
+ //
+ // Copy Oprom to allocated space in ATI Opregion
+ //
+ AmdOpRegion.ApXmOpRegion->RVBS = VbiosSize;
+ (gBS->CopyMem) ((VOID *) (UINTN) AmdOpRegion.ApXmOpRegion->RBUF, VbiosAddress, AmdOpRegion.ApXmOpRegion->RVBS);
+
+ if (Status != EFI_SUCCESS) {
+ (gBS->FreePool) (AmdOpRegion.ApXmOpRegion);
+ }
+
+ return Status;
+}
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.cif b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.cif
new file mode 100644
index 0000000..cf21dc9
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.cif
@@ -0,0 +1,15 @@
+<component>
+ name = "Sg Acpi Tables"
+ category = ModulePart
+ LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\AcpiTables"
+ RefName = "SgTpvAcpiTables"
+[files]
+"SgTpvAcpiTables.sdl"
+"SgTpvAcpiTables.mak"
+"SgTpvAcpiTables.c"
+"SgTpvAcpitables.h"
+[parts]
+"SgTpvPEG"
+"SgTpvPCH"
+"OEMSSDT"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.mak b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.mak
new file mode 100644
index 0000000..23f5961
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.mak
@@ -0,0 +1,101 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvAcpiTables.mak 5 1/15/13 6:07a Joshchou $
+#
+# $Revision: 5 $
+#
+# $Date: 1/15/13 6:07a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvAcpiTables.mak $
+#
+# 5 1/15/13 6:07a Joshchou
+# [TAG] EIP107237
+# [Category] New Feature
+# [Description] Modify for support SG on ULT platform.
+#
+# 4 12/22/12 2:39a Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Update for SA RC 081,rename the name for corrcet make.
+#
+# 3 11/20/12 3:46a Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Create Token for OEM clone
+#
+# 2 9/09/12 10:57p Joshchou
+#
+# 1 6/27/11 5:26a Alanlin
+# [TAG] EIP61848
+# [Category] New Feature
+# [Description] Initial check-in.Integrated SwitchableGraphics Intel
+# Reference code 0.6.0
+# [Files] SgTpvAcpiTables.cif
+# SgTpvAcpiTables.sdl
+# SgTpvAcpiTables.mak
+# SgTpvAcpiTables.c
+#
+#
+# 3 11/12/10 1:17p Alexp
+# include the token.h in command line to CL preprocessor
+#
+# 2 10/05/10 7:07p Alexp
+# change the default build target
+#
+# 1 9/17/10 1:18p Alexp
+# [TAG] EIP43103
+# [Category] Function Request
+# [Severity] Normal
+# [Symptom] Initial check-in of SgTPV module
+# [RootCause] Request to implement SG reference code .
+# [Solution] Initial check-in.
+# [Files]
+# SgTpvAcpiTables.cif;*.sdl;*.mak;*.c
+#
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name: SgTpvAcpiTables.mak
+#
+# Description: Make file to build SG TPV ACPI components
+#
+#
+#<AMI_FHDR_END>
+#*************************************************************************
+BUILD_SGTPV_DIR = $(BUILD_DIR)\$(SGTPV_DIR)
+
+SaInitDxeBin: $(BUILD_SGTPV_DIR)\SgTpvAcpiTables.obj
+
+
+
+$(BUILD_SGTPV_DIR)\SgTpvAcpiTables.obj: $(SGTPV_ACPI_DIR)\SgTpvAcpiTables.c
+ $(CC) $(CFLAGS) /I$(INCLUDE_DIR)/ /DTIANO_RELEASE_VERSION=$(TIANO_RELEASE_VERSION) $(SgTpvDxe_INCLUDES) /Fo$@ $**
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.sdl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.sdl
new file mode 100644
index 0000000..5e121c8
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpiTables.sdl
@@ -0,0 +1,110 @@
+TOKEN
+ Name = "SgTpvAcpiTables_SUPPORT"
+ Value = "1"
+ Help = "Main switch to enable SgAcpiTables support in Project"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ Master = Yes
+End
+
+TOKEN
+ Name = "SGTPV_ACPI_SSDT_GUID"
+ Value = "{0x6A061113, 0xFE54, 0x4A07, 0xA2, 0x8E, 0x0A, 0x69, 0x35, 0x9E, 0xB0, 0x69}"
+ Help = "SGTpv Acpi Package"
+ TokenType = Expression
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "SGTPV_ACPIPCH_SSDT_GUID"
+ Value = "{0x9b65fe7c, 0x855e, 0x43cc, 0xa1, 0x70, 0xa2, 0xa6, 0x85, 0xf3, 0x65, 0x5f}"
+ Help = "SGTpv Acpi Package"
+ TokenType = Expression
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "SGTPV_ASL_DEBUG"
+ Value = "1"
+ Help = "Turns on debug check points in ASL code"
+ TokenType = Boolean
+ TargetH = Yes
+ Token = "DEBUG_MODE" "=" "1"
+End
+
+TOKEN
+ Name = "NV_VENTURA_SUPPORT"
+ Value = "0"
+ Help = "Switch to enable Nvidia Ventura support with SG and Optimus.\Controls inclusion of different ASL reference code"
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "NV_GPS_SUPPORT"
+ Value = "0"
+ Help = "Switch to enable Nvidia GPS support with SG and Optimus.\Controls inclusion of different ASL reference code"
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "NV_GC6_SUPPORT"
+ Value = "0"
+ Help = "Switch to enable Nvidia GC6 support Optimus.Notice:It is sample code for reference,should be modified it by different board design"
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "NV_OPTIMUS_DISPLAYLESS"
+ Value = "0"
+ Help = "Follow nVidia's suggetion, Optimus displayless platform has no used for other sub-functions.just support sub-functions NVOP_FUNC_SUPPORT, NVOP_FUNC_GETOBJBYTYPE, NVOP_FUNC_GETALLONJS, NVOP_FUNC_OPTIMUSCAPS) in _DSM NVOP_FUNC_SUPPORT (0x00000000) function"
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "PCI_SCOPE"
+ Value = "\_SB.PCI0"
+ TokenType = Expression
+ TargetH = Yes
+ Lock = Yes
+End
+
+TOKEN
+ Name = "PEG_SCOPE"
+ Value = "\_SB.PCI0.PEG0"
+ Help = "PLATFORM PORTING!!! Update iGPU and dGPU device names as defined in SB/NB.SDL"
+ TokenType = Expression
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "IGPU_SCOPE"
+ Value = "\_SB.PCI0.GFX0"
+ Help = "PLATFORM PORTING!!! Update iGPU and dGPU device names as defined in SB/NB.SDL"
+ TokenType = Expression
+ TargetH = Yes
+End
+
+PATH
+ Name = "SGTPV_ACPI_DIR"
+ Help = "Path to SG AcpiTable folder"
+End
+
+MODULE
+ File = "SgTpvAcpiTables.mak"
+End
+
+ELINK
+ Name = "/I$(SGTPV_ACPI_DIR)"
+ Parent = "SwitchableGraphics_INCLUDES"
+ InvokeOrder = AfterParent
+End
+
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpitables.h b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpitables.h
new file mode 100644
index 0000000..5ee40e5
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvAcpitables.h
@@ -0,0 +1,254 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvAcpitables.h 6 6/05/13 5:08a Joshchou $
+//
+// $Revision: 6 $
+//
+// $Date: 6/05/13 5:08a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvAcpitables.h $
+//
+// 6 6/05/13 5:08a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Increase the size of RBUF to support hybrid Vbios.
+//
+// 5 1/15/13 6:07a Joshchou
+// [TAG] EIP107237
+// [Category] Improvement
+// [Description] Modify for support SG on ULT plaform
+//
+// 4 12/18/12 6:22a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Update for SA RC 081
+//
+// 3 10/16/12 4:41a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Update for SA and ACPI RC 0.7.1
+// [Files] SgTpvAcpitables.h
+//
+// 2 9/09/12 10:57p Joshchou
+//
+//**********************************************************************
+
+#ifndef _SG_TPV_ACPITABLES_H_
+#define _SG_TPV_ACPITABLES_H_
+
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+#include "EfiScriptLib.h"
+#endif
+
+#include "Acpi3_0.h"
+#include <Token.h>
+#include <Protocol\Mxm30.h>
+
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+
+//#include EFI_PROTOCOL_DEPENDENCY (PciIo)
+#include EFI_PROTOCOL_DEPENDENCY (AcpiSupport)
+#include EFI_PROTOCOL_DEPENDENCY (FirmwareVolume)
+#include EFI_PROTOCOL_DEPENDENCY (SaGlobalNvsArea)
+#include EFI_GUID_DEFINITION (SaDataHob)
+#include EFI_PROTOCOL_DEFINITION (SaPlatformPolicy)
+
+#define MemoryRead16(Address) * (UINT16 *) (Address)
+#define MemoryRead8(Address) * (UINT8 *) (Address)
+
+extern EFI_BOOT_SERVICES *gBS;
+extern EFI_GUID gSaGlobalNvsAreaProtocolGuid;
+extern VOID *VbiosAddress;
+extern UINT32 VbiosSize;
+extern UINT8 EndpointBus;
+extern UINT16 GpioBaseAddress;
+
+extern CPU_FAMILY CpuFamilyId;
+
+SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL *SaGlobalNvsArea;
+
+// Function Prototype declaration
+EFI_STATUS LoadTpvAcpiTables();
+EFI_STATUS InstallNvidiaOpRegion (VOID);
+EFI_STATUS InstallAmdOpRegion (VOID);
+
+//----------------------------------------------------------------------------
+//
+// Switchable Graphics defines.
+//
+//----------------------------------------------------------------------------
+
+//
+// SSDT Guid file
+//
+#define NVIDIA_VID 0x10DE
+#define NVOPT_SSID_OFFSET 0x40
+
+#define AMD_SVID_OFFSET 0x4C
+#define AMD_SDID_OFFSET 0x4E
+#define AMD_VID 0x1002
+
+//
+// OpRegion Header #defines.
+//
+#define NVIG_HEADER_SIGNATURE "NVSG-IGD-DSM-VAR"
+#define NVIG_OPREGION_SIZE 1
+#define NVIG_OPREGION_VER 0x00000201
+#define NVHM_HEADER_SIGNATURE "NvSwitchable_Gfx"
+#define NVHM_OPREGION_SIZE 129
+#define NVHM_OPREGION_VER 0x00000201
+#define APXM_HEADER_SIGNATURE "AMD--PowerXpress"
+#define APXM_OPREGION_SIZE 129
+#define APXM_OPREGION_VER 0x00000201
+
+//
+// OpRegion structures:
+//
+// Note: These structures are packed to 1 byte offsets because the exact
+// data location is requred by the supporting design specification due to
+// the fact that the data is used by ASL and Graphics driver code compiled
+// separatly.
+//
+
+//
+// NVIG OpRegion
+//
+#pragma pack (1)
+typedef struct {
+ // OpRegion Header // Byte offset(decimal)
+
+ CHAR8 NISG[0x10]; // 0 NVIG OpRegion Signature
+ UINT32 NISZ; // 16 NVIG OpRegion Size in KB
+ UINT32 NIVR; // 20 NVIG OpRegion Version
+
+ // OpRegion Data
+ UINT32 GPSS; // 24 Policy Selection Switch Status (Current GPU)
+ UINT16 GACD; // 32 Active Displays
+ UINT16 GATD; // 34 Attached Displays
+ CHAR8 LDES; // 36 Lid Event State
+ CHAR8 DKST; // 37 Dock State
+ CHAR8 DACE; // 38 Display ACPI Event
+ CHAR8 DHPE; // 39 Display Hot-Plug Event
+ CHAR8 DHPS; // 40 Display Hot-Plug Status
+ CHAR8 SGNC; // 41 Notify Code (Cause of Notify(..,0xD0))
+ CHAR8 GPPO; // 42 Policy Override
+ CHAR8 USPM; // 43 Update Scaling Preference Mask
+ CHAR8 GPSP; // 44 Panel Scaling Preference
+ CHAR8 TLSN; // 45 Toggle List Sequence Number
+ CHAR8 DOSF; // 46 Flag for _DOS
+ UINT16 ELCL; // 47 Endpoint Link Contol Register Value
+
+} NVIG_OPREGION; // Total 49 Bytes
+#pragma pack ()
+
+//
+// NVHM OpRegion
+//
+#pragma pack (1)
+typedef struct {
+ // OpRegion Header // Byte offset(decimal)
+
+ CHAR8 NVSG[0x10]; // 0 NVHM OpRegion Signature
+ UINT32 NVSZ; // 16 NVHM OpRegion Size in KB
+ UINT32 NVVR; // 20 NVHM OpRegion Version
+
+ // OpRegion Data
+ UINT32 NVHO; // 24 NVHM Opregion Address
+ UINT32 RVBS; // 28 Nvidia VBIOS Image Size
+ CHAR8 RBUF[0x20000]; // 32 64KB VBIOS
+ UINT32 MXML; // 64k+32 Nvidia Mxm3 Buffer length
+#if MXM30_SUPPORT == 1
+ CHAR8 MXM3[MXM_ROM_MAX_SIZE];// 64k+36 Nvidia Mxm3 Buffer
+#else
+ CHAR8 MXM3[200];
+#endif
+} NVHM_OPREGION; // Total 65568 Bytes
+#pragma pack ()
+
+//
+// Entire Nvidia OpRegion
+//
+#pragma pack(1)
+typedef struct {
+ NVIG_OPREGION *NvIgOpRegion; // 47 Bytes
+ NVHM_OPREGION *NvHmOpRegion; // 65568 Bytes
+} NVIDIA_OPREGION; // Total 65615 Bytes
+#pragma pack()
+
+//
+// APXM OpRegion
+//
+#pragma pack (1)
+typedef struct {
+ // OpRegion Header // Byte offset(decimal)
+
+ CHAR8 APSG[0x10]; // 0 APXM OpRegion Signature
+ UINT32 APSZ; // 16 APXM OpRegion Size in KB
+ UINT32 APVR; // 20 APXM OpRegion Version
+
+ // OpRegion Data
+ UINT32 APXA; // 24 PX OpRegion Address
+ UINT32 RVBS; // 28 PX Runtime VBIOS Image Size
+ UINT16 NTLE; // 32 Total number of toggle list entries
+ UINT16 TLEX[15]; // 34 The display combinations in the list...
+ UINT16 TGXA; // 64 Target GFX adapter as notified by ATPX function 5
+ UINT16 AGXA; // 66 Active GFX adapter as notified by ATPX function 6
+ CHAR8 GSTP; // 68 GPU switch transition in progress
+ CHAR8 DSWR; // 69 Display Switch Request
+ CHAR8 SPSR; // 70 System power source change request
+ CHAR8 DCFR; // 71 Display configuration change request
+ CHAR8 EMDR; // 72 Expansion Mode Change Request
+ CHAR8 PXGS; // 73 PowerXpress graphics switch toggle request
+ UINT16 CACD; // 74 Currently Active Displays
+ UINT16 CCND; // 76 Currently Connected Displays
+ UINT16 NACD; // 78 Next Active Index
+ CHAR8 EXPM; // 80 Expansion Mode
+ UINT16 TLSN; // 81 Toggle list sequence index
+ UINT16 ELCL; // 83 Endpoint Link Contol Register Value
+
+ CHAR8 RBUF[0x20000]; // 83 VBIOS 128KB
+} APXM_OPREGION; // Total 65626 Bytes
+#pragma pack ()
+
+//
+// Entire AMD OpRegion
+//
+#pragma pack (1)
+typedef struct {
+ APXM_OPREGION *ApXmOpRegion; // Total 65617 Bytes
+} AMD_OPREGION;
+#pragma pack ()
+
+#endif
+
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/ATdGPUPCH.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/ATdGPUPCH.asl
new file mode 100644
index 0000000..2467fdc
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/ATdGPUPCH.asl
@@ -0,0 +1,179 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/ATdGPUPCH.asl 1 1/15/13 6:02a Joshchou $
+//
+// $Revision: 1 $
+//
+// $Date: 1/15/13 6:02a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/ATdGPUPCH.asl $
+//
+// 1 1/15/13 6:02a Joshchou
+// [TAG] EIP107237
+// [Category] Improvement
+// [Description] Create componet for SG support on PCH
+// [Files] SgUltAti.cif
+// AtiSSDTPCH.asl
+// ATdGPUPCH.asl
+// ATiGPUPCH.asl
+// ATiGDmiscPCH.asl
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgAti.cif
+// AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+//
+//
+// 2 10/05/10 7:09p Alexp
+// Added debug macro to be able to insert include check points in target
+// ASL code
+//
+// 1 9/17/10 1:20p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgAti.cif;
+// AtiSSDT.asl; ATdGPU.asl;ATiGPU.asl;ATiGDmisc
+//
+// 1 6/08/10 3:45p Alexp
+//
+// 1 6/03/10 2:54p Alexp
+//
+// 10 4/29/10 11:42a Alexp
+// updated ASL names for Mxm power control and switching from GPIO to
+// functional names. E.g. old- PO16 to new-MRST etc.
+//
+// 9 4/02/10 5:06p Alexp
+// Change per Calpella SG BIOS spec 1.03:
+// - add link control register
+// - add WiDi display
+//
+// 8 1/11/10 4:03p Alexp
+// Added Nvidia Optimus Gfx support
+//
+// 7 12/08/09 10:20a Alexp
+// Per BWG 1.2 Added code to save/restore Endpoint Link Contol Register
+// during power cycle of DGPU
+//
+// 6 10/06/09 1:27p Alexp
+// replaced Alias definitions with actual device name scopes for PEG
+// display devices
+//
+// 5 10/05/09 5:35p Alexp
+// updated asl code for Ati and Nvidia according to Calpella SG BWG 1.1
+//
+// 4 8/21/09 4:45p Alexp
+// Updated Nvidia and ATI SG code to match latest Intel Calpella Acpi
+// reference code from Intel code drop v#68 and Ati SG BWG
+// SG Asl code. Made PEG PCIe MMIO base address dependent on
+// PCIE_BASE_ADDRESS SDL token. Before it was hardwired in ASL code which
+// caused SG logic to fail in Mxm & SG Label 005
+//
+// 3 8/20/09 7:08p Alexp
+// upgraded Ati and Nvidia SSDT Asl files to match latest Acpi code drop
+// #68
+//
+// 1 7/16/09 11:17a Alexp
+// Added SG support for AMD ATI Gfx adaptors
+//**********************************************************************
+Scope(DGPUPCH_SCOPE)
+{
+// OperationRegion (PEGR, PCI_Config, 0, 0x100)
+// Field(PEGR, DWordAcc, Lock, Preserve)
+// {
+// Offset(0x4C),
+// SSID, 32,
+// }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _ON
+//
+// Description: dGPU power ON control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_ON,0,Serialized)
+ {
+ SGON() // OEM Mxm Power On
+
+ //Set the SSID for the ATI MXM
+// Store(MXM_SSVID_DID, SSID)
+
+ //Ask OS to do a PnP rescan
+ Notify(SG_ULT_RP_NUM,0)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _OFF
+//
+// Description: dGPU power OFF control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_OFF,0,Serialized)
+ {
+ SGOF() // OEM Mxm Power On
+
+ //Ask OS to do a PnP rescan
+ Notify(SG_ULT_RP_NUM,0)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _STA
+//
+// Description: Returns curent dGPU power/presence state
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_STA,0,Serialized)
+ {
+ Return(SGST()) // OEM Mxm Power status
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _INI
+//
+// Description: dGPU Init control method. Used to force dGPU _ADR to return proper PCI address
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+// Method (_INI)
+// {
+// should already be set by now...
+//// Store(MXM_SSVID_DID, SSID) //Set the SSID for the ATI MXM
+// Store(0x0, DGPUPCH_SCOPE._ADR) //make sure PEGP address returns 0x00000000
+// }
+
+} // end Scope(DGPUPCH_SCOPE)
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/ATiGDmiscPCH.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/ATiGDmiscPCH.asl
new file mode 100644
index 0000000..6c12f59
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/ATiGDmiscPCH.asl
@@ -0,0 +1,277 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/ATiGDmiscPCH.asl 1 1/15/13 6:02a Joshchou $
+//
+// $Revision: 1 $
+//
+// $Date: 1/15/13 6:02a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/ATiGDmiscPCH.asl $
+//
+// 1 1/15/13 6:02a Joshchou
+// [TAG] EIP107237
+// [Category] Improvement
+// [Description] Create componet for SG support on PCH
+// [Files] SgUltAti.cif
+// AtiSSDTPCH.asl
+// ATdGPUPCH.asl
+// ATiGPUPCH.asl
+// ATiGDmiscPCH.asl
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgAti.cif
+// AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+//
+//
+// 4 3/17/11 6:18p Alexp
+// cleaned up the code.
+//
+// 3 11/12/10 1:25p Alexp
+// Change IDAB method: invoke IGD_SCOPE.IDAB is defined there
+//
+// 2 10/05/10 7:09p Alexp
+// Added debug macro to be able to insert include check points in target
+// ASL code
+//
+// 1 9/17/10 1:20p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgAti.cif;
+// AtiSSDT.asl; ATdGPU.asl;ATiGPU.asl;ATiGDmisc
+//
+// 1 6/08/10 3:45p Alexp
+//
+// 1 6/03/10 2:54p Alexp
+//
+// 4 10/05/09 5:35p Alexp
+// updated asl code for Ati and Nvidia according to Calpella SG BWG 1.1
+//
+// 3 8/20/09 7:08p Alexp
+// upgraded Ati and Nvidia SSDT Asl files to match latest Acpi code drop
+// #68
+//
+// 1 7/16/09 11:17a Alexp
+// Added SG support for AMD ATI Gfx adaptors
+//**********************************************************************
+
+External(DSEN)
+External(IGPU_SCOPE.AINT, MethodObj)
+External(DGPUPCH_SCOPE.DD02)
+External(IGPU_SCOPE.IDAB, MethodObj)
+
+//Do not remove this function.
+Method(IDAB, 0, Serialized)
+{
+ If (CondRefOf(IGPU_SCOPE.IDAB))
+ {
+ IGPU_SCOPE.IDAB()
+ }
+}
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HGAS
+//
+// Description: HG Adaptor select, notify
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HGAS) // HG Adaptor Select
+{
+ // Toggle GFX Adapter.
+ Store(1,IGPU_SCOPE.PXGS)
+ Notify(IGPU_SCOPE,0x81)
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HBRT
+//
+// Description: Send backlight notifications to the DGPU LFP device
+// This is required for Win7 and is backward compatible with Vista
+//
+// Input: Arg0 - 4 - Brightnes Down, 3- Up
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HBRT, 1 , Serialized)
+{
+
+ If(And(4,DSEN)) //Note: DSEN variable is expected to be set by IGD miniport only.
+ {
+ If(LEqual(Arg0,4))
+ {
+ Notify(DGPUPCH_SCOPE.DD02,0x87) //Note: DD02 is hardcoded as the LFP device in intelgfx.asl
+ }
+ If(LEqual(Arg0,3))
+ {
+ Notify(DGPUPCH_SCOPE.DD02,0x86)
+ }
+ }
+
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HPFS
+//
+// Description: Panel Fitting Hot Key
+//
+// Input: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HPFS, 0, Serialized) //Panel Fitting Hot Key
+{
+ If(LNotEqual(IGPU_SCOPE.GSTP,1))
+ {
+
+ //
+ // HG Handling of Panel Fitting Switch
+ //
+ If(LEqual(IGPU_SCOPE.AGXA,0))
+ {
+ IGPU_SCOPE.AINT(2, 0)
+ }
+ Else
+ {
+ Store(1,IGPU_SCOPE.EMDR)
+
+ //
+ // Expansion Mode toggling
+ //
+ If(LEqual(IGPU_SCOPE.EXPM,2))
+ {
+ Store(0,IGPU_SCOPE.EXPM)
+ }
+ Else
+ {
+ Increment(IGPU_SCOPE.EXPM)
+ }
+ Notify(IGPU_SCOPE,0x81)
+ }
+ }
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HNOT
+//
+// Description: Notification handler for Switchable graphics. Called from GNOT()
+//
+// Input: Arg0 = Current event type:
+// 1 = display switch
+// 2 = lid
+// 3 = dock (!!!!!Calpella ref code, Method(GDCK)sends 4 for Dock notifications )
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method (HNOT, 1, Serialized)
+{
+
+ Switch(ToInteger(Arg0))
+ {
+ case(1) //Display Switch event
+ {
+ If(LNotEqual(IGPU_SCOPE.GSTP,1))
+ {
+ //
+ // HG Handling of Display Switch Event
+ //
+ // Muxless?
+ If(LEqual(SGMD,0x2))
+ {
+ If(LEqual(IGPU_SCOPE.AGXA,0))
+ {
+ Notify(IGPU_SCOPE,0x80)
+ }
+
+ If(LEqual(IGPU_SCOPE.AGXA,1))
+ {
+ Notify(DGPUPCH_SCOPE,0x80)
+ }
+ }
+ Else
+ {
+ Store(1,IGPU_SCOPE.DSWR)
+ Notify(IGPU_SCOPE,0x81)
+ }
+ }
+ }
+ case (2) //Lid switch event
+ {
+ // Muxless?
+ If(LEqual(SGMD,0x2))
+ {
+ If(LEqual(IGPU_SCOPE.AGXA,0))
+ {
+ Notify(IGPU_SCOPE,0x80)
+ }
+
+ If(LEqual(IGPU_SCOPE.AGXA,1))
+ {
+ Notify(DGPUPCH_SCOPE,0x80)
+ }
+ }
+ Else
+ {
+ Notify(IGPU_SCOPE,0x80) //Placeholder for LID event
+ }
+ }
+// case (3) //Dock event
+ case (4) //Dock event
+ {
+ // Muxless?
+ If(LEqual(SGMD,0x2))
+ {
+ If(LEqual(IGPU_SCOPE.AGXA,0))
+ {
+ Notify(IGPU_SCOPE,0x80)
+ }
+
+ If(LEqual(IGPU_SCOPE.AGXA,1))
+ {
+ Notify(DGPUPCH_SCOPE,0x80)
+ }
+ }
+ Else
+ {
+ Notify(IGPU_SCOPE,0x80) //Placeholder for handling dock event
+ }
+ }
+ Default
+ {
+ Notify(IGPU_SCOPE,0x80)
+ }
+
+ }
+
+} \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/ATiGPUPCH.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/ATiGPUPCH.asl
new file mode 100644
index 0000000..7f653da
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/ATiGPUPCH.asl
@@ -0,0 +1,1339 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/ATiGPUPCH.asl 5 7/16/13 5:18a Joshchou $
+//
+// $Revision: 5 $
+//
+// $Date: 7/16/13 5:18a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/ATiGPUPCH.asl $
+//
+// 5 7/16/13 5:18a Joshchou
+// [TAG] None
+// [Category] New Feature
+// [Description] Enable falg bit14 of ATPX Function 1 to support
+// MSHybrid.
+//
+// 4 6/05/13 5:13a Joshchou
+//
+// 3 3/21/13 4:42a Joshchou
+// [TAG] EIP105607
+// [Category] Spec Update
+// [Severity] Minor
+// [Description] Update for support PX5.6
+//
+// 2 2/21/13 5:46a Joshchou
+// [TAG] EIP107720
+// [Category] Spec Update
+// [Severity] Minor
+// [Description] Add ATIF function 15 sample code for reference.
+//
+// 1 1/15/13 6:02a Joshchou
+// [TAG] EIP107237
+// [Category] Improvement
+// [Description] Create componet for SG support on PCH
+// [Files] SgUltAti.cif
+// AtiSSDTPCH.asl
+// ATdGPUPCH.asl
+// ATiGPUPCH.asl
+// ATiGDmiscPCH.asl
+//
+// 3 12/06/11 2:14a Alanlin
+// [TAG] EIP76148
+// [Category] New Feature
+// [Description] PX 5.0 feature updated
+//
+// 2 7/14/11 5:39a Alanlin
+// [TAG] EIP64370
+// [Category] Bug Fix
+// [Severity] Important
+// [Symptom] Screen can't be displayed after install ATI SG driver
+// [RootCause] ASL method return value is incorrect.
+// [Solution] Return correct value to driver.
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgAti.cif
+// AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+//
+//
+// 5 3/17/11 6:18p Alexp
+// cleaned up the code.
+//
+// 4 1/03/11 12:26p Alexp
+// [TAG] EIP47451
+// [Category] Improvement
+// [Description] fixed checkpoint display in ATRM method
+// [Files] atidgpu.asl
+//
+// 3 11/12/10 1:23p Alexp
+// rename ELCT to ELCL in order to avoid name conflict with Intel's ref
+// code in SgDGPU.asl
+//
+// 2 10/05/10 7:09p Alexp
+// Added debug macro to be able to insert include check points in target
+// ASL code
+//
+// 1 9/17/10 1:20p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgAti.cif;
+// AtiSSDT.asl; ATdGPU.asl;ATiGPU.asl;ATiGDmisc
+//
+// 2 6/08/10 4:21p Alexp
+//
+// 1 6/08/10 3:46p Alexp
+//
+// 1 6/08/10 3:45p Alexp
+//
+// 1 6/03/10 2:56p Alexp
+//
+// 8 4/29/10 11:42a Alexp
+// updated ASL names for Mxm power control and switching from GPIO to
+// functional names. E.g. old- PO16 to new-MRST etc.
+//
+// 7 4/02/10 5:06p Alexp
+// Change per Calpella SG BIOS spec 1.03:
+// - add link control register
+// - add WiDi display
+//
+// 6 12/08/09 10:20a Alexp
+// Per BWG 1.2 Added code to save/restore Endpoint Link Contol Register
+// during power cycle of DGPU
+//
+// 5 10/05/09 5:35p Alexp
+// updated asl code for Ati and Nvidia according to Calpella SG BWG 1.1
+//
+// 4 8/21/09 4:45p Alexp
+// Updated Nvidia and ATI SG code to match latest Intel Calpella Acpi
+// reference code from Intel code drop v#68 and Ati SG BWG
+// SG Asl code. Made PEG PCIe MMIO base address dependent on
+// PCIE_BASE_ADDRESS SDL token. Before it was hardwired in ASL code which
+// caused SG logic to fail in Mxm & SG Label 005
+//
+// 1 7/16/09 11:17a Alexp
+// Added SG support for AMD ATI Gfx adaptors
+//
+//
+//**********************************************************************
+External(\ECON, IntObj) // Embedded Controller Availability Flag.
+External(PCI_SCOPE.LPCB.H_EC.LSTE)
+External(MXD1)
+External(MXD2)
+External(MXD3)
+External(MXD4)
+External(MXD5)
+External(MXD6)
+External(MXD7)
+External(MXD8)
+
+External(NXD1)
+External(NXD2)
+External(NXD3)
+External(NXD4)
+External(NXD5)
+External(NXD6)
+External(NXD7)
+External(NXD8)
+
+External(AMDA)
+External(SGMD)
+External(SGFL)
+External(PXFX)
+External(PXDY)
+External(PXFD)
+
+Scope (IGPU_SCOPE)
+{
+/*
+ Method(_INI,0)
+ {
+// Init all scratch pad fields if not already done so in OpRegion Init
+ }
+*/
+
+//<AMI_SHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: APXM
+//
+// Description: AMD PowerExpress OperationRegion.
+// OpRegion address (AMDA)is defined in IDG Nvs OpRegion
+//
+//-------------------------------------------------------------------------
+//<AMI_SHDR_END>
+ OperationRegion(APXM,SystemMemory,AMDA,0x20400)
+ Field(APXM, AnyAcc, NoLock, Preserve)
+ {
+ // OpRegion Header
+
+ APSG, 0x80, // (000h) Signature-"AMD--PowerXpress".
+ APSZ, 0x20, // (010h) OpRegion Size.
+ APVR, 0x20, // (014h) OpRegion Version.
+
+ // OpRegion Data
+ APXA, 0x20, // PX opregion address
+ RVBS, 0x20, // PX Runtime VBIOS image size
+ NTLE, 0x10, // Total number of toggle list entries
+ TLE1, 0x10, // The display combinations in the list...
+ TLE2, 0x10,
+ TLE3, 0x10,
+ TLE4, 0x10,
+ TLE5, 0x10,
+ TLE6, 0x10,
+ TLE7, 0x10,
+ TLE8, 0x10,
+ TLE9, 0x10,
+ TL10, 0x10,
+ TL11, 0x10,
+ TL12, 0x10,
+ TL13, 0x10,
+ TL14, 0x10,
+ TL15, 0x10,
+ TGXA, 0x10, // Target GFX adapter as notified by ATPX function 5
+ AGXA, 0x10, // Active GFX adapter as notified by ATPX function 6
+ GSTP, 0x08, // GPU switch transition in progress
+ DSWR, 0x08, // Display switch request
+ SPSR, 0x08, // System power source change request
+ DCFR, 0x08, // Display configuration change request
+ EMDR, 0x08, // Expansion mode change request
+ PXGS, 0x08, // PowerXpress graphics switch toggle request
+ CACD, 0x10, // Currently active displays
+ CCND, 0x10, // Currently connected displays
+ NACD, 0x10, // Next active displays
+ EXPM, 0x08, // Expansion Mode
+ TLSN, 0x10, // Toggle list sequence index
+ ELCL, 0x10, // Endpoint Link Contol Register Value
+ // for ATRM (_ROM equivalent) data
+ RBF1, 0x40000, // 0x8000 bytes in bits
+ RBF2, 0x40000, // 0x8000 bytes in bits
+ RBF3, 0x40000, // 0x8000 bytes in bits
+ RBF4, 0x40000 // 0x8000 bytes in bits
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: ADPM
+//
+// Description: ADPM -> ATPX Fn 8 Digital port mux mode
+//
+// Input:
+// Arg0 : Integer User selected option (via., setup 0 -> Shared, 1 -> iGPU Only, 2 -> dGPU Only)
+// Arg1 : 1 -> iGPU connector record, 2->dgpu connector record
+//
+// Output:
+// Flag value for ATPX Fn 8.
+// Bit0-> display can be driven by the GPU
+// Bit1-> HPD can be detected by the GPU
+// Bit2-> AUX/DDC can be driven by the GPU
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(ADPM, 2, Serialized)
+ {
+ Store(0, Local1)
+
+ // AUX/DDC Mux settings
+ ShiftRight(Arg0, 16, Local0)
+
+ if(LEqual(Arg1, 1)) // If iGPU connector record
+ {
+ Or (And(Local0, 0x1), Local1, Local1)
+ }
+ else // If dGPU connector record
+ {
+ Or (ShiftRight(And(Local0, 0x2),1), Local1, Local1)
+ }
+ ShiftLeft(Local1, 1, Local1)
+
+
+ // HPD Mux settings
+ ShiftRight(Arg0, 24, Local0)
+
+ if(LEqual(Arg1, 1)) // If iGPU connector record
+ {
+ Or (And(Local0, 0x1), Local1, Local1)
+ }
+ else // If dGPU connector record
+ {
+ Or (ShiftRight(And(Local0, 0x2),1), Local1, Local1)
+ }
+ ShiftLeft(Local1, 1, Local1)
+
+
+ // Display Mux settings
+ ShiftRight(Arg0, 8, Local0)
+
+ if(LEqual(Arg1, 1)) // If iGPU connector record
+ {
+ Or (And(Local0, 0x1), Local1, Local1)
+ }
+ else // If dGPU connector record
+ {
+ Or (ShiftRight(And(Local0, 0x2),1), Local1, Local1)
+ }
+
+ Return (Local1)
+
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: ATPX
+//
+// Description: ATI PowerXpress (PX) Contrl Method: Revision 0.19
+// PX specific Control Method used by integrated graphics
+// or discrete graphics driver on PX enabled platforms.
+//
+// Input:
+// Arg0: Integer Function code.
+// Arg1: Buffer Parameter buffer, 256 bytes
+//
+// Output:
+// Returns Buffer 256 bytes
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(ATPX,2,Serialized)
+ {
+ P8DB(0xA1, Arg0, 2000)
+ //
+ // Function 0: Verify PowerXpress Interface
+ //
+ // Returns the PX interface version and
+ // functions supported by PX System BIOS
+ //
+ If(LEqual(Arg0,0))
+ {
+ Name(TMP1,Buffer(256) {0x00})
+ CreateWordField ( TMP1, 0, F0SS)
+ CreateWordField ( TMP1, 2, F0IV)
+ CreateDwordField( TMP1, 4, F0SF)
+
+ Store(0x0008,F0SS)
+ Store(0x0001,F0IV)
+ Store(0x000000BF,F0SF)
+
+ // For Muxless: Support only Fun1, Fun2, Fun5 and Fun6
+ If(LEqual(SGMD,0x2))
+ {
+
+ Store(0x00000033,F0SF)
+/*
+ If (LEqual(PXDY, 0x01)) { // PX Dynamic Mode Switch Enabled
+ And(F0SF, 0xFFFFFFFD, F0SF) // Don't support PX02
+ }
+ If (LAnd(LEqual(PXDY, 0x01), // Support both Dynamic and Fixed PX switch
+ LEqual(PXFX, 0x01))) {
+ Or(F0SF, 0x2, F0SF) // Support PX02
+ }
+*/
+ }
+
+ Return(TMP1)
+ }
+
+ //
+ // Function 1: Get PowerXpress Parameters
+ //
+ // Returns various PX related platform parameters
+ //
+ If(LEqual(Arg0,1))
+ {
+ Name(TMP2,Buffer(256) {0x00})
+ CreateWordField ( TMP2, 0, F1SS)
+ CreateDwordField ( TMP2, 2, F1VM)
+ CreateDwordField( TMP2, 6, F1FG)
+ Store(0x000A,F1SS) //Structure size of return package
+ Store(0x00007FFF,F1VM) // Bit[14:0]Mask used for valid bit fields
+
+ // Bit0: LVDS I2C is accessible to both graphics controllers.
+ // Bit1: CRT1 I2C is accessible to both graphics controllers.
+ // Bit2: DVI1 I2C is accessible to both graphics controllers.
+ // Bit3: CRT1 RGB signals are multiplexed.
+ // Bit4: TV1 signals are multiplexed.
+ // Bit5: DFP1 signals are multiplexed.
+ // Bit6: Indicates that a separate multiplexer control for I2C/Aux/HPD exists.
+ // Bit7: Indicates that a "dynamic" PX scheme is supported.
+ // Bit8: Reserved.
+ // Bit9: Indicates that "fixed" scheme is not supported, if set to one.
+ // Bit10: Indicates that full dGPU power off in gdynamich scheme is supported, if set to one.
+ // Bit11: Indicates that discrete graphics must be powerd on while a monitor is connected to discrete graphics connector,if set to one
+ // Bit12: Indicates that discrete graphics can drive display outpurs(local dGPU displays are supported),if set to one
+ // Bit13: Indicates that long idle detection is disabled ,if set to one
+ // Bit14: Indicates that Windows Blue "Hybrid Graphics" is required(supported),if set to one
+ // Bits[31:15]: Reserved (must be zero).
+
+ // For Muxless: Set BIT7 for dynamic" PX scheme is supported
+ If(LEqual(SGMD,0x2))
+ {
+ Store(0x00000280,F1FG) // BACO Mode under the Dynamic Scheme
+
+ If(LEqual(PXFD,0x1))
+ {
+ Store(0x00005E80,F1FG) // dGPU Power off under the Dynamic Scheme
+ }
+ }
+ Else
+ {
+ // For Muxed: Set BIT6 to Indicates that a separate multiplexer control for I2C/Aux/HPD exists
+ // and is controlled by function 4 (Monitor I2C Control).
+ Store(0x00000040,F1FG) // Actual PX parameters field
+ }
+
+ Return(TMP2)
+ }
+
+ //
+ // Function 2: Power Control
+ //
+ // Powers on/off the discrete graphics
+ //
+ If(LEqual(Arg0,2))
+ {
+ CreateWordField(Arg1,0,FN2S)
+ CreateByteField(Arg1,2,DGPR)
+
+ If(LEqual(DGPR,0)) // Powers off discrete graphics
+ {
+ DGPUPCH_SCOPE._OFF()
+ }
+ If(LEqual(DGPR,1)) // Powers on discrete graphics
+ {
+ DGPUPCH_SCOPE._ON()
+ }
+ Return(0)
+ }
+
+ //
+ // Function 3: Display Multiplexer Control
+ //
+ // Controls display multiplexers
+ //
+ If(LEqual(Arg0,3))
+ {
+ CreateWordField(Arg1,0,FN3S)
+ CreateWordField(Arg1,2,SDMG)
+
+ // Display Multiplexer Control
+ If(LEqual(SDMG,0)) // Switch Display Muxes to iGFX
+ {
+ DGPUPCH_SCOPE.SGPO(DSEL, 0)
+ }
+ If(LEqual(SDMG,1)) // Switch Display Muxes to dGFX
+ {
+ DGPUPCH_SCOPE.SGPO(SSEL, 1)
+ }
+
+ Return(0)
+ }
+
+ //
+ // Function 4: Monitor I2C Control
+ //
+ // Controls monitor I2C lines
+ //
+ If(LEqual(Arg0,4))
+ {
+ CreateWordField(Arg1,0,FN4S)
+ CreateWordField(Arg1,2,SIMG)
+
+ // I2C Multiplexer Control
+ If(LEqual(SIMG,0)) // Switch I2C Muxes to iGFX
+ {
+ DGPUPCH_SCOPE.SGPO(ESEL, 0)
+ }
+ If(LEqual(SIMG,1)) // Switch I2C Muxes to dGFX
+ {
+ DGPUPCH_SCOPE.SGPO(ESEL, 1)
+ }
+
+ Return(0)
+ }
+
+ //
+ // Function 5: Graphics Device Switch Start Notification
+ //
+ // Notifies SBIOS that GFX device switch process has been started
+ //
+ If(LEqual(Arg0,5))
+ {
+ CreateWordField(Arg1,0,FN5S)
+ CreateWordField(Arg1,2,TGFX)
+ Store(TGFX,TGXA)
+ Store(1,GSTP)
+
+ Return(0)
+ }
+
+ //
+ // Function 6: Graphics Device Switch End Notification
+ //
+ // Notifies SBIOS that GFX device switch process has been completed
+ //
+ If(LEqual(Arg0,6))
+ {
+ CreateWordField(Arg1,0,FN6S)
+ CreateWordField(Arg1,2,AGFX)
+ Store(AGFX,AGXA)
+ Store(0,GSTP)
+
+ Return(0)
+ }
+
+ //
+ // Function 8: Get Display Connectors mapping
+ //
+ If(LEqual(Arg0,8))
+ {
+ Name(TMP3,Buffer(256) {
+ 0x0e,0x00, //Number of reported display connectors
+ 0x46,0x00, //Total Connector structure size in bytes (num of structures * structure size)
+ 0x07,0x01,0x00,0x00,0x01, //Connector structure 1 - CRT on iGPU
+ 0x07,0x01,0x01,0x00,0x01, //Connector structure 2 - CRT on dGPU
+ 0x05,0x00,0x00,0x00,0x04, //Connector structure 3 - LFP on iGPU
+ 0x05,0x00,0x01,0x10,0x01, //Connector structure 4 - LFP on dGPU
+
+ // Digital port mapping on EC4
+ //
+ // Intel ATI EC4 output
+ // Port B -> Port B DP
+ // Port C -> Port C HDMI
+ // Port D -> Port D DP
+ //
+
+ 0x07,0x03,0x00,0x00,0x03, //Connector structure 5 - DisplayPort_B on iGPU
+ 0x07,0x03,0x01,0x10,0x02, //Connector structure 6 - DP on dGPU (MXM port B on EC4)
+ 0x07,0x07,0x00,0x01,0x03, //Connector structure 7 - HDMI/DVI dongle on port B
+ 0x07,0x07,0x01,0x10,0x02, //Connector structure 8 - HDMI/DVI dongle on dGPU (MXM port B on EC4)
+ 0x07,0x09,0x00,0x02,0x03, //Connector structure 9 - HDMI_C on iGPU
+ 0x07,0x09,0x01,0x20,0x02, //Connector structure 10 - HDMI on dGPU (MXM port C on EC4)
+ 0x07,0x0a,0x00,0x03,0x03, //Connector structure 11 - DisplayPort_D on iGPU
+ 0x07,0x0a,0x01,0x30,0x02, //Connector structure 12 - DP on dGPU (MXM port B. Not routed to EC4)
+ 0x07,0x0b,0x00,0x04,0x03, //Connector structure 13 - HDMI/DVI dongle on port D
+ 0x07,0x0b,0x01,0x30,0x02, //Connector structure 14 - HDMI/DVI dongle on dGPU (MXM port B. Not routed to EC4)
+ 0x07,0x0C,0x00,0x06,0x03, //Connector structure 15 - Place holder for Intel Wireless Display
+ })
+
+ CreateWordField (TMP3, 0, ATNO)
+ CreateWordField (TMP3, 2, ATSZ)
+
+ //Modify the display, HPD and Aux/DDC flag in the connector structure based on iGPU Digital port setup option
+
+ //Connector structure 3 - LFP on iGPU
+ Store(ADPM(MXD2, 1), Index(TMP3, 14))
+
+ //Connector structure 4 - LFP on dGPU
+ Store(ADPM(MXD2, 1), Index(TMP3, 19))
+
+ //Connector structure 5 - DisplayPort_B on iGPU
+ Store(ADPM(MXD3, 1), Index(TMP3, 24))
+
+ //Connector structure 6 - DP on dGPU
+ Store(ADPM(MXD3, 2), Index(TMP3, 29))
+
+ //Connector structure 7 - HDMI/DVI dongle on port B
+ Store(ADPM(MXD4, 1), Index(TMP3, 34))
+
+ //Connector structure 8 - HDMI/DVI dongle on dGPU
+ Store(ADPM(MXD4, 2), Index(TMP3, 39))
+
+ //Connector structure 9 - HDMI_C on iGPU
+ Store(ADPM(MXD5, 1), Index(TMP3, 44))
+
+ //Connector structure 10 - HDMI on dGPU
+ Store(ADPM(MXD5, 2), Index(TMP3, 49))
+
+ //Connector structure 11 - DisplayPort_D on iGPU
+ Store(ADPM(MXD6, 1), Index(TMP3, 54))
+
+ //Connector structure 12 - DP on dGPU
+ Store(ADPM(MXD6, 2), Index(TMP3, 59))
+
+ //Connector structure 13 - HDMI/DVI dongle on port D
+ Store(ADPM(MXD7, 1), Index(TMP3, 64))
+
+ //Connector structure 14 - HDMI/DVI dongle on dGPU
+ Store(ADPM(MXD7, 2), Index(TMP3, 69))
+
+ If(And(SGFL, 0x01))
+ {
+ Store(Add(ATNO, 0x1), ATNO)
+ Store(Add(ATSZ, 0x5), ATSZ)
+ }
+
+ Return(TMP3)
+ }
+
+ Return(0) //End of ATPX
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: ATRM
+//
+// Description: ATI PowerXpress (PX) get ROM Method: Revision 0.19
+// PX specific Control Method used by discrete graphics driver
+// on PX enabled platforms to get a runtime modified copy of
+// the discrete graphics device ROM data (Video BIOS).
+//
+// Input:
+// Arg0: Integer Offset of the graphics device ROM data
+// Arg1: Integer Size of the buffer to fill in (up to 4K)
+//
+// Output:
+// Buffer Buffer of requested video ROM bytes
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(ATRM,2,Serialized)
+ {
+ Store(Arg0,Local0)
+ Store(Arg1,Local1)
+
+ P8DB(0x44, ShiftRight(Local0, 8), 1000)
+
+ If(LGreater(Local1,0x1000))
+ {
+ Store(0x1000,Local1)
+ }
+ If(LGreater(Local0,0x10000))
+ {
+ Return(Buffer(Local1){0})
+ }
+ If(LGreater(Local0,RVBS))
+ {
+ Return(Buffer(Local1){0})
+ }
+// If (LGreater (Add (Local0, Local1), RVBS))
+// {
+// Store (0x00, Local0)
+// }
+
+ Multiply(Local1,0x08,Local3)
+ Name(ROM1,Buffer(0x8000){0})
+ Name(ROM2,Buffer(Local1){0})
+
+ If(LLess(Local0, 0x8000)){
+ Store(RBF1, ROM1)
+ }
+ ElseIf(LLess(Local0, 0x10000)){
+ Subtract(Local0,0x8000,Local0)
+ Store(RBF2, ROM1)
+ }
+ ElseIf(LLess(Local0, 0x18000)){
+ Subtract(Local0,0x10000,Local0)
+ Store(RBF3, ROM1)
+ }
+ ElseIf(LLess(Local0, 0x20000)){
+ Subtract(Local0,0x18000,Local0)
+ Store(RBF4, ROM1)
+ }
+ Multiply(Local0,0x08,Local2)
+ CreateField(ROM1,Local2,Local3,TMPB)
+ Store(TMPB,ROM2)
+ Return(ROM2)
+
+ }
+ //
+ // INDL : Initialize Global Next active device list.
+ //
+ // Argments : None.
+ //
+ // returns : None.
+ //
+ Method(INDL, 0, Serialized)
+ {
+ Store(0, NXD1)
+ Store(0, NXD2)
+ Store(0, NXD3)
+ Store(0, NXD4)
+ Store(0, NXD5)
+ Store(0, NXD6)
+ Store(0, NXD7)
+ Store(0, NXD8)
+ }
+ //
+ // SNXD -> Set Next active device.
+ //
+ // Arg0 : Display vector of devices that will be activated
+ //
+ // Returns : None.
+ //
+ Method(SNXD, 1, Serialized)
+ {
+ INDL()
+
+ Store(Arg0, Local0)
+ If(And(Local0, ShiftLeft(1, 1))) // 1-> BIT1 CRT1
+ {
+ Store(1, NXD1) // NXD1 -> CRT
+ }
+ If(And(Local0, ShiftLeft(1, 0))) // 0 -> BIT2 LCD1
+ {
+ Store(1, NXD2) // NXD2 -> LCD
+ }
+ If(And(Local0, ShiftLeft(1, 3))) // 3 -> BIT3 DFP1 (DP_B)
+ {
+ Store(1, NXD3) // NXD3 -> Display port B
+ }
+ If(And(Local0, ShiftLeft(1, 7))) // 7 -> BIT7 DFP2 (HDMI_B)
+ {
+ Store(1, NXD4) // NXD4 -> HDMI B
+ }
+ If(And(Local0, ShiftLeft(1, 9))) // 9 -> BIT9 DFP3 (HDMI_C)
+ {
+ Store(1, NXD5) // NXD5 -> HDMI C
+ }
+ If(And(Local0, ShiftLeft(1, 10))) // 10 -> BIT10 DFP4 (DP_D)
+ {
+ Store(1, NXD6) // NXD6 -> Display port D
+ }
+ If(And(Local0, ShiftLeft(1, 11))) // 11 -> BIT11 DFP5 (HDMI_D)
+ {
+ Store(1, NXD7) // NXD7 -> HDMI D
+ }
+
+ //NXD8 is not used since there are only 7 entries in _DOD
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: ATIF
+//
+// Description: ATI GFX Interface.Provides ATI specific GFX functionality on mobile platforms.
+//
+// Input:
+// Arg0: Integer Function code.
+// Arg1: Package Parameter buffer, 256 bytes
+//
+//
+// Output:
+// Returns Buffer, 256 bytes
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(ATIF,2,Serialized)
+ {
+ P8DB(0xAF, Arg0, 2000)
+
+ //
+ // Function 0: Verify Interface
+ //
+ // Returns the interface version and
+ // functions/notifications supported by System BIOS
+ //
+ If(LEqual(Arg0,0))
+ {
+ Name(TMP0,Buffer(256) {0x00})
+ CreateWordField (TMP0, 0, F0SS)
+ CreateWordField (TMP0, 2, F0IV)
+ CreateDwordField (TMP0, 4, F0SN)
+ CreateDwordField (TMP0, 8, F0SF)
+
+ // Size of return structure=12
+ Store(0x000C,F0SS)
+
+ // Interface version
+ Store(0x0001,F0IV)
+
+ // Supported Notifications Mask
+ Store(0x00000041,F0SN) // Display switch request and PowerXpress graphics switch toggle request supported
+// Store(0x00000001,F0SN) //<Overriding as per edited ATIF spec 0.22- only display switch request supported>>
+
+ //Supported Functions Bit Vector
+ Store(0x00000007,F0SF)
+
+ /*
+ // For Muxless: No ATIF Fn supported
+ If(LEqual(SGMD,0x2))
+ {
+ Store(0x00000000,F0SN)
+ Store(0x00000000,F0SF)
+ }
+ */
+ Return(TMP0)
+ }
+
+ //
+ // Function 1: Get System Parameters
+ //
+ // Returns various system parameters
+ //
+ If(LEqual(Arg0,1))
+ {
+ Name(TMP1,Buffer(256) {0x0})
+ CreateWordField (TMP1, 0, F1SS)
+ CreateDwordField (TMP1, 2, F1VF)
+ CreateDwordField (TMP1, 6, F1FG)
+
+ // Size of return structure=10
+ Store(0x000A, F1SS)
+
+ // Valid Fields Mask
+ Store(0x00000003,F1VF)
+
+ // Flags
+ Store(0x00000001,F1FG) // Notify (VGA, 0x81) is used as a general purpose notification
+ Return(TMP1)
+ }
+
+ //
+ // Function 2: Get System BIOS Requests
+ //
+ // Reports pending system BIOS requests
+ //
+ // Invoked whenever driver receives Notify(VGA,0x81) and
+ // the Notify is designated as a general purpose notification
+ // in the function "Get System Parameters"
+ //
+ If(LEqual(Arg0,2))
+ {
+ CreateBitField(PSBR, 0, PDSW) // Display switch request
+ CreateBitField(PSBR, 1, PEXM) // Expansion mode request
+ CreateBitField(PSBR, 2, PTHR) // Thermal state change request
+ CreateBitField(PSBR, 3, PFPS) // Forced power state change request
+ CreateBitField(PSBR, 4, PSPS) // System power state change request
+ CreateBitField(PSBR, 5, PDCC) // Display configuration change request
+ CreateBitField(PSBR, 6, PXPS) // PowerXpress? graphics controller switch request
+ CreateBitField(PSBR, 7, PBRT) // Panel brightness change request //[ODM_Change]2012/08/20 AMD GOP brightness2 WHQL fail.
+ CreateBitField(PSBR, 8, DCSC) // Panel brightness change request //[ODM_Change]2012/08/20 AMD GOP brightness2 WHQL fail.
+
+ CreateWordField(ATIB, 0, SSZE) // Structure size = 12
+ CreateDWordField(ATIB, 2, PSBI) // Pending System BIOS Requests
+ CreateByteField(ATIB, 6, EXPM) // Expansion Mode
+ CreateByteField(ATIB, 7, THRM) // Thermal State: Target Gfx controller
+ CreateByteField(ATIB, 8, THID) // Thermal State: State Id
+ CreateByteField(ATIB, 9, FPWR) // Forced Power State: Target Gfx controller
+ CreateByteField(ATIB, 10, FPID) // Forced Power State: State Id
+ CreateByteField(ATIB, 11, SPWR) // System Power Source
+ CreateByteField (ATIB, 12, BRTL) // Brightness Level //[ODM_Change]2012/08/20 AMD GOP brightness2 WHQL fail.
+
+ Store(13,SSZE)
+ Store(PSBR,PSBI)
+
+ IF(PDSW) {
+ Store(0,PDSW)
+ }
+
+ IF(PEXM) {
+ Store(0,EXPM)
+ Store(0,PEXM)
+ }
+
+ IF(PTHR) {
+ Store(0, THRM)
+ Store(0, THID)
+ Store(0, PTHR)
+ }
+
+ IF(PFPS) {
+ Store(0, PFPS)
+ }
+
+ IF(PSPS) {
+ Store(0, PSPS)
+ }
+
+ IF(PXPS) {
+ Store(0, PXPS)
+ }
+
+ IF(PBRT) {
+ Store(0, PBRT)
+ }
+
+ IF(DCSC) {
+ Store(0, DCSC )
+ }
+
+ Return(ATIB)
+ }
+
+ //
+ // Function 3: Select Active Displays
+ //
+ // Returns displays to be selected in reposnse to
+ // a display switch request notification
+ //
+ If(LEqual(Arg0,3))
+ {
+ Name(TMP3,Buffer(256) {0x0})
+ CreateWordField (TMP3, 0, F3SS)
+ CreateWordField (TMP3, 2, F3SD)
+ CreateWordField(Arg1,0,AI3S)
+ CreateWordField(Arg1,2,SLDS)
+ CreateWordField(Arg1,4,CODS)
+ Store(SLDS,CACD)
+ Store(CODS,CCND)
+
+ If (\ECON)
+ {
+ If(LEqual(PCI_SCOPE.LPCB.H_EC.LSTE,1))
+ {
+ Or(CCND,0x0001,CCND) // ATI does not send LFP as connected when not LFP is not active. This is as per design
+ }
+ }
+
+ // Size of return structure=4
+ Store(0x0004,F3SS)
+
+ // Next Displays to be Selected
+ // Populate next displays based on Currently Connected and Active displays and the Toggle List Index
+ // CCND, CACD, TLSN,
+ Store(CTOI(CACD),TLSN) // Get current toggle index based on currently Active display vector
+ Store(CACD, Local1) // Initialize Local1 to a safe value
+ Store(NTLE, Local0) // Total number of toggle list entries
+ While(Local0)
+ {
+ Store(NATL(TLSN),Local1) // Get the next combination from toggle list into Local1
+
+ If(LNotEqual(Local1, 0)) //If next toggle list entry is not empty, then
+ {
+ If(LEqual(And(Local1,CCND),Local1)) // If entries in the next combination are actually connected..
+ {
+ Store(1,Local0) // Exit since we got the next active list
+ }
+ }
+ Decrement(Local0) // Decrement toggle list sequence counter
+
+ Increment(TLSN) // Increment toggle list number to point to next active list
+ If(LGreater(TLSN, NTLE)) // If sequence index currently points to last entry....
+ {
+ Store(1,TLSN) // Roll-up to the start of the toggle list
+ }
+ }
+ SNXD(Local1) // Set the selected displays as the next active for _DGS
+ Store(Local1,NACD) // The next active toggle list - put it on Opregion
+ Store(NACD,F3SD) // Store it in the return buffer
+ Return(TMP3)
+ }
+
+//<Overriding as per edited ATIF spec 0.22- only Functions 0,1,2,3 supported>
+// //
+// // Function 5: Get TV Standard from CMOS
+// //
+// // Retrieves current TV standard
+// //
+// If(LEqual(Arg0,5))
+// {
+// Name(TMP5,Buffer(256) {0x0})
+// CreateWordField (TMP5, 0, F5SS)
+//
+// // Size of return structure
+// Store(0x0004,F5SS)
+//
+// // TV Standard Encoding Format
+// Store(0x00,Index(TMP5,2))
+//
+// // TV Standard
+// Store(TVSD,Index(TMP5,3))
+//
+// Return(TMP5)
+//
+// }
+ //
+// //
+// // Function 6: Set TV Standard in CMOS
+// //
+// // Records current TV standard in CMOS
+// //
+// If(LEqual(Arg0,6))
+// {
+// Name(TMP6,Buffer(256) {0x0})
+//
+// CreateWordField(Arg1,0,AI6S)
+// CreateByteField(Arg1,2,TSEF)
+// CreateByteField(Arg1,3,TVST)
+//
+// // Records current TV standard in CMOS
+// Store(TVST,TVSD)
+//
+// Return(TMP6)
+//
+// }
+//
+// //
+// // Function 7: Get Panel Expansion Mode from CMOS
+// //
+// // Retrieves built-in panel expansion mode
+// //
+// If(LEqual(Arg0,7))
+// {
+// Name(TMP7,Buffer(256) {0x0})
+// CreateWordField (TMP7, 0 , F7SS)
+//
+// // Size of return structure
+// Store(0x0003,F7SS)
+ //
+// // Expansion Mode
+// Store(EXPM,Index(TMP7,2))
+ //
+// Return(TMP7)
+ //
+// }
+ //
+// //
+// // Function 8: Set Panel Expansion Mode in CMOS
+// //
+// // Records built-in panel expansion mode in CMOS
+// //
+// If(LEqual(Arg0,8))
+// {
+// Name(TMP8,Buffer(256) {0x0})
+ //
+// CreateWordField(Arg1,0,AI8S)
+// CreateByteField(Arg1,2,EMCM)
+ //
+// // Record Expansion Mode in CMOS
+// Store(EMCM,EXPM)
+ //
+// Return(TMP8)
+// }
+ //
+// //
+// // Function 9: Get Selected Displays from CMOS
+// //
+// // Retrieves Selected Displays
+// //
+// If(LEqual(Arg0,9))
+// {
+// Name(TMP9,Buffer(256) {0x0})
+// CreateWordField (TMP5, 0, F9SS)
+// CreateWordField (TMP5, 2, F9SD)
+// CreateWordField (TMP5, 4, F9DV)
+ //
+// // Size of return structure
+// Store(0x0006,F9SS)
+ //
+// // Supported Displays Mask
+// Store(BSPD,F9SD)
+ //
+// // Selected Displays Vector
+// Store(And(BPSD,3),F9DV) // Only LFP, CRT supported by IGD in PX
+ //
+// Return(TMP9)
+// }
+ //
+// //
+// // Function 10: Set Selected Displays in CMOS
+// //
+// // Records Selected Displays in CMOS
+// //
+// If(LEqual(Arg0,0xA))
+// {
+// Name(TMPA,Buffer(256) {0x0})
+ //
+// CreateWordField(Arg1,0,AIAS)
+// CreateWordField(Arg1,2,SDCM)
+ //
+// // Records Selected Displays in CMOS
+// Store(And(SDCM,3),BPSD) // Only LFP, CRT supported by IGD in PX
+ //
+// Return(TMPA)
+// }
+ //
+// //
+// // Function 12: Thermal Change Notification
+// //
+// // GPU temperature threshold related function
+// //
+// If(LEqual(Arg0,0xC))
+// {
+// Name(TMPC,Package() {0xFFFF,0xFFFFFFFF,0xFF,0xFF,0xFF,0xFF})
+//
+// // Size of return structure
+// Store(0x000A,Index(TMPC,0))
+//
+// // Flags
+////<TO DO>check Store(0x00000003,Index(TMPC,1))
+//
+// // High Temperature Threshold
+////<TO DO>check Store(0x00,Index(TMPC,2))
+//
+// // Low Temperature Threshold
+////<TO DO>check Store(0x00,Index(TMPC,3))
+//
+// // Thermal State At High Temperature Threshold
+////<TO DO>check Store(0x00,Index(TMPC,4))
+//
+// // Thermal State At Low Temperature Threshold
+////<TO DO>check Store(0x00,Index(TMPC,5))
+//
+// Return(TMPC)
+// }
+ //
+// //
+// // Function 13: Temperature Change Notification
+// //
+// // GPU temperature threshold related function
+// //
+// If(LEqual(Arg0,0xD))
+// {
+// Name(TMPD,Package() {0xFFFF,0xFFFFFFFF,0xFF,0xFF,0xFF,0xFF})
+// CreateWordField(Arg1,0,AIDS)
+// CreateWordField(Arg1,2,TGCI)
+// CreateByteField(Arg1,4,CGPT)
+ //
+// Return(TMPD)
+// }
+ //
+ // Function 15: Get Graphics Device Types
+ //
+ // This function reports all graphics devices and XGP ports supported by a given platform
+ //
+ If(LEqual(Arg0,0xF))
+ {
+ Name(TMPF,Buffer(256) {0x0})
+ CreateWordField (TMPF, 0, FFND)
+ CreateWordField (TMPF, 2, FFDS)
+ CreateDwordField (TMPF, 4, FFFG)
+ CreateWordField (TMPF, 8, FFBS)
+ CreateWordField (TMPF, 10, FFDV)
+
+
+
+ Return(TMPF)
+ }
+
+
+
+ Return (0)
+ }
+ Name(ATIB, Buffer(0x100){})
+ Name(PSBR, Buffer(0x4){0x00}) // Pending System BIOS Requests. (these get cleared only when function 2 is called)
+ Name(SSPS, 0x00) // Save System Power Source
+ Method(AFN0, 0, Serialized)
+ {
+ CreateBitField(PSBR, 0, PDSW) // Display switch request
+ Store(One, PDSW) // Set the request to pending state
+ Notify(IGPU_SCOPE, 0x81) // Inform the display driver
+ }
+
+
+ Method(AFN4, 1, Serialized) // Arg0: System Power Source
+ {
+ Store(Arg0, Local0)
+ Store(SSPS, Local1)
+ Store(Local0, SSPS)
+ If(LEqual(Local0, Local1))
+ {
+ } Else
+ {
+ CreateBitField(PSBR,0x04,PSPS)
+ Store(One, PSPS)
+ Notify(IGPU_SCOPE, 0x81)
+ }
+ }
+
+ Method(AFN5, 0, Serialized)
+ {
+ CreateBitField(PSBR,0x05,PDCC)
+ Store(One, PDCC)
+ Notify(IGPU_SCOPE, 0x81)
+ }
+
+ Method(AFN6, 0, Serialized)
+ {
+ CreateBitField(PSBR, 6, PXPS) // PowerXpress graphics switch toggle request
+ Store(One, PXPS) // Set the request to pending state
+ Notify(IGPU_SCOPE, 0x81) // Inform the display driver
+ }
+
+ Method(AFN7, 1, Serialized) // Arg0: Panel Brightness: Backlight Level
+ {
+ CreateBitField(PSBR, 7, PBRT) // Brightness level change request
+ Store(One, PBRT) // Pending brightness level request
+
+ CreateByteField(ATIB, 12, BRTL) // Brightness Level
+ Store(Arg0, BRTL) // Brightness level
+ Notify(IGPU_SCOPE, 0x81)
+ }
+
+ Method(AFN8, 0, Serialized)
+ {
+ CreateBitField(PSBR, 8, DCSC) // Discrete GPU display connect state change request
+ Store(One, DCSC) // Pending brightness level request
+ Notify(IGPU_SCOPE, 0x81)
+ }
+
+ Method(CTOI,1)
+ {
+ If(LNotEqual(NTLE, Zero))
+ {
+ If(LEqual(TLE1, Arg0))
+ {
+ Return(1)
+ }
+ If(LEqual(TLE2, Arg0))
+ {
+ Return(2)
+ }
+ If(LEqual(TLE3, Arg0))
+ {
+ Return(3)
+ }
+ If(LEqual(TLE4, Arg0))
+ {
+ Return(4)
+ }
+ If(LEqual(TLE5, Arg0))
+ {
+ Return(5)
+ }
+ If(LEqual(TLE6, Arg0))
+ {
+ Return(6)
+ }
+ If(LEqual(TLE7, Arg0))
+ {
+ Return(7)
+ }
+ If(LEqual(TLE8, Arg0))
+ {
+ Return(8)
+ }
+ If(LEqual(TLE9, Arg0))
+ {
+ Return(9)
+ }
+ If(LEqual(TL10, Arg0))
+ {
+ Return(10)
+ }
+ If(LEqual(TL11, Arg0))
+ {
+ Return(11)
+ }
+ If(LEqual(TL12, Arg0))
+ {
+ Return(12)
+ }
+ If(LEqual(TL13, Arg0))
+ {
+ Return(13)
+ }
+ If(LEqual(TL14, Arg0))
+ {
+ Return(14)
+ }
+ If(LEqual(TL15, Arg0))
+ {
+ Return(15)
+ }
+ }
+ Return(1) //If no match, then set TLSN to 1
+ }
+
+ Method(NATL,1)
+ {
+ If(LNotEqual(NTLE, Zero))
+ {
+ If(LEqual(Arg0,1))
+ {
+ Return(TLE2)
+ }
+ If(LEqual(Arg0,2))
+ {
+ Return(TLE3)
+ }
+ If(LEqual(Arg0,3))
+ {
+ Return(TLE4)
+ }
+ If(LEqual(Arg0,4))
+ {
+ Return(TLE5)
+ }
+ If(LEqual(Arg0,5))
+ {
+ Return(TLE6)
+ }
+ If(LEqual(Arg0,6))
+ {
+ Return(TLE7)
+ }
+ If(LEqual(Arg0,7))
+ {
+ Return(TLE8)
+ }
+ If(LEqual(Arg0,8))
+ {
+ Return(TLE9)
+ }
+ If(LEqual(Arg0,9))
+ {
+ Return(TL10)
+ }
+ If(LEqual(Arg0,10))
+ {
+ Return(TL11)
+ }
+ If(LEqual(Arg0,11))
+ {
+ Return(TL12)
+ }
+ If(LEqual(Arg0,12))
+ {
+ Return(TL13)
+ }
+ If(LEqual(Arg0,13))
+ {
+ Return(TL14)
+ }
+ If(LEqual(Arg0,14))
+ {
+ Return(TL15)
+ }
+ If(LEqual(Arg0,15))
+ {
+ Return(TLE1)
+ }
+ }
+ Return(0)
+ }
+} // end PCI0.GFX0 scope
+
+
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/AtiSSDTPCH.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/AtiSSDTPCH.asl
new file mode 100644
index 0000000..5a2939c
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/AtiSSDTPCH.asl
@@ -0,0 +1,145 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/AtiSSDTPCH.asl 2 7/16/13 5:15a Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 7/16/13 5:15a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/AtiSSDTPCH.asl $
+//
+// 2 7/16/13 5:15a Joshchou
+// [TAG] None
+// [Category] New Feature
+// [Description] Add _DSW method to support MSHybrid.
+//
+// 1 1/15/13 6:02a Joshchou
+// [TAG] EIP107237
+// [Category] Improvement
+// [Description] Create componet for SG support on PCH
+// [Files] SgUltAti.cif
+// AtiSSDTPCH.asl
+// ATdGPUPCH.asl
+// ATiGPUPCH.asl
+// ATiGDmiscPCH.asl
+//
+// 2 12/22/11 6:36a Alanlin
+// Declared "defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)"
+//
+// 1 6/27/11 5:26a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgAti.cif
+// AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+//
+//
+// 3 11/12/10 1:22p Alexp
+// include "token.h" inside the command line to CL preprocessor in
+// SgAcpiTable.mak
+//
+// 2 10/05/10 7:09p Alexp
+// Added debug macro to be able to insert include check points in target
+// ASL code
+//
+// 1 9/17/10 1:20p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgAti.cif;
+// AtiSSDT.asl; ATdGPU.asl;ATiGPU.asl;ATiGDmisc
+//
+// 1 6/08/10 3:45p Alexp
+//
+// 1 6/03/10 2:56p Alexp
+//
+// 1 7/16/09 11:17a Alexp
+// Added SG support for AMD ATI Gfx adaptors
+//
+//
+//**********************************************************************
+
+DefinitionBlock (
+ "Amd.aml",
+ "SSDT",
+ 1,
+ "AmdRef",
+ "AmdTabl",
+ 0x1000
+ ){
+
+External(P8XH, MethodObj)
+#if defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)
+#define P8DB(arg0, arg1, arg2) P8XH (0, arg1) P8XH (1, arg0) sleep(arg2)
+#else
+#define P8DB(arg0, arg1, arg2)
+#endif
+
+External(PCI_SCOPE, DeviceObj)
+External(SG_ULT_RP_NUM, DeviceObj)
+External(DGPUPCH_SCOPE, DeviceObj)
+External(IGPU_SCOPE, DeviceObj)
+External(DGPUPCH_SCOPE._ADR, DeviceObj)
+External(DGPUPCH_SCOPE.SGST, MethodObj)
+External(DGPUPCH_SCOPE.SGON, MethodObj)
+External(DGPUPCH_SCOPE.SGOF, MethodObj)
+External(DGPUPCH_SCOPE.SGPI, MethodObj)
+External(DGPUPCH_SCOPE.SGPO, MethodObj)
+External(\DSEL)
+External(\ESEL)
+External(\SSEL)
+External(\PSEL)
+External(\HLRS)
+External(\PWEN)
+
+
+#include <ATdGPUPCH.ASL> // Include dGPU device namespace
+#include <ATiGPUPCH.ASL> // Include IGD _DSM and AMD ATIF/ATPM/ATRM methods
+#include <ATiGDmiscPCH.ASL> // Include misc event callback methods
+
+Scope(SG_ULT_RP_NUM)
+{
+ Method(_DSW, 3, NotSerialized)
+ {
+ If(Arg1)
+ {
+ Store("RP05 -_DSW call ", Debug)
+ }
+ Else
+ {
+ If(LAnd(Arg0, Arg2))
+ {
+ Store("RP05 -_DSW call-1 ", Debug)
+ }
+ Else
+ {
+ Store("RP05 -_DSW call-2 ", Debug)
+ }
+ }
+ }
+}
+
+} // end SSDT
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NVdGPUPCH.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NVdGPUPCH.asl
new file mode 100644
index 0000000..74a28b4
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NVdGPUPCH.asl
@@ -0,0 +1,621 @@
+//Endpoint PCIe Base Address.
+External(EBAS)
+External(NVHA)
+
+#ifdef OPTIMUS_DSM_GUID
+Scope(PCI_SCOPE){
+
+ Name(OTM, "OTMACPI 2010-Mar-09 12:08:26") // OTMACPIP build time stamp.
+} // end of Scope
+#endif
+
+Scope(DGPUPCH_SCOPE)
+{
+
+//<AMI_SHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: PCI2
+//
+// Description: For save/store PCIE NV PCI register from 0 to 256 byte by Dword access while do _ON & OFF
+//
+//-------------------------------------------------------------------------
+//<AMI_SHDR_END>
+ OperationRegion (PCI2, SystemMemory, EBAS, 0x500)
+ Field(PCI2, DWordAcc, Lock, Preserve)
+ {
+ Offset(0x4),
+ CMDR, 8,
+ VGAR, 2000,
+ Offset(0x48B),
+ , 1,
+ NHDA, 1,
+ }
+ Name(VGAB, Buffer(0xFA)
+ {
+ 0x00
+ })
+ Name(GPRF, Zero)
+
+//<AMI_SHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: NVHM
+//
+// Description: Nvidia NVHG (dGPU) OperationRegion
+// OpRegion address (NVHA)is defined in IDG Nvs OpRegion
+//
+//-------------------------------------------------------------------------
+//<AMI_SHDR_END>
+ OperationRegion(NVHM,SystemMemory, NVHA, 0x20400)
+ Field(NVHM, DWordAcc, NoLock, Preserve)
+ {
+ // OpRegion Header
+
+ NVSG, 0x80, // (000h) Signature-"NVSG".
+ NVSZ, 0x20, // (010h) OpRegion Size in KB.
+ NVVR, 0x20, // (014h) OpRegion Version.
+
+ // NVHG data
+
+ NVHO, 0x20, // (018h)NVHM opregion address
+ RVBS, 0x20, // (01Ch)NVIDIA VBIOS image size
+ // (020h)for _ROM
+ RBF1, 0x40000, // 0x8000 bytes in bits
+ RBF2, 0x40000, // 0x8000 bytes in bits
+ RBF3, 0x40000, // 0x8000 bytes in bits
+ RBF4, 0x40000, // 0x8000 bytes in bits
+ MXML, 0x20, // Mxm3 buffer length
+#if MXM30_SUPPORT
+ MXM3, MXM_ROM_MAX_SIZE_bits // MXM 3.0 Data buffer
+#else
+ MXM3, 0x640 // MXM 3.0 Data buffer
+#endif
+
+ }
+
+ Name(OPCE, 2) // Optimus Power-Control ENABLE
+ // 2: The platform should not power down the GPU subsystem
+ // in the _PS3 method (Default)
+ // 3: The platform should power down the GPU subsystem
+ // at the end of the _PS3 ACPI method
+
+ Name(DGPS, Zero)// Power State. dummy control field. Can be a GPIO in EC or PCH
+
+#ifdef OPTIMUS_DSM_GUID
+
+//If dGPU power control is available....
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _PSC
+//
+// Description: Curent dGPU power state, 0-D0, 3-D3, etc.
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Name(_PSC, Zero)
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _PS0
+//
+// Description: dGPU power ON control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(_PS0, 0, NotSerialized)
+ {
+ P8DB(0xB0, OPCE, 2000)
+ Store(Zero, _PSC)
+ If(LNotEqual(DGPS, Zero))
+ {
+ _ON() // with Optimus w/a
+ Store(Zero, DGPS)
+ }
+ Store(0x0,NHDA) //NV HDMI audio did not need enable
+ }
+
+ Method(_PS1, 0x0, NotSerialized)
+ {
+ Store(One, _PSC)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _PS3
+//
+// Description: dGPU power OFF control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(_PS3, 0, NotSerialized)
+ {
+ P8DB(0xB3, OPCE, 2000)
+ If(LEqual(OPCE, 0x3))
+ {
+ If(LEqual(DGPS, Zero))
+ {
+ _OFF() // w Optimus w/a
+ Store(One, DGPS)
+ }
+ Store(0x2, OPCE) // Reset NV GPU power down flag
+ }
+ Store(0x3, _PSC)
+ }
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _STA
+//
+// Description: dGPU power status.
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_STA,0x0)
+ {
+ Return(0x0F) // Always return DGPU is powered-ON
+ }
+
+#endif // OPTIMUS_DSM_GUID
+
+#if HYBRID_DSM_GUID || MXM_DSM_GUID
+// NON-OPTIMUS mode - MUXed
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _IRC
+//
+// Description: In-rush current
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+// Name(_IRC, 0)
+ Method(_IRC,0,Serialized)
+ {
+ Return(0x00)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _ON
+//
+// Description: dGPU power ON control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_ON,0,Serialized)
+ {
+ SGON() // OEM Mxm Power On
+ //Ask OS to do a PnP rescan
+ Notify(SG_ULT_RP_NUM,0)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _OFF
+//
+// Description: dGPU power OFF control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_OFF,0,Serialized)
+ {
+ SGOF() // OEM Mxm Power On
+
+ //Ask OS to do a PnP rescan
+ Notify(SG_ULT_RP_NUM,0)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _STA
+//
+// Description: Returns curent dGPU power/presence state
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_STA,0,Serialized)
+ {
+ Return(SGST()) // OEM Mxm Power status
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: MXMX
+//
+// Description: Display DDC Mux Control
+//
+// Input:
+// Arg0: Get/Set DDC/Aux Mux State
+// 0- Acquire DDC/Aux Mux on this GPU
+// 1- Release Mux from this GPU
+// 2- Get Mux state
+//
+// Output:
+// 0, Not Acquired.
+// if Arg0 = 0 or 1, Non-Zero return indicates success acquiring MUX
+// (and MUX has switched to this output)
+// if Arg0 = 2, Non-Zero return indicates MUX is currently set to this output
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (MXMX, 1, Serialized)
+ {
+ P8DB(0x99, Arg0, 2000)
+
+ If (LEqual (Arg0, 0))
+ {
+
+ //Acquire DDC/AUX mux
+ // No mutex implemented. No need to acquire mutex.
+ // Set mux to dGPU
+// SGPO(DSEL, 1)// dGPU_SELECT#
+ SGPO(ESEL, 1)// use EDID_SELECT# as Mutex flag
+ Return(1)
+ }
+
+ If (LEqual (Arg0, 1))
+ {
+
+ //Release DDC/AUX mux
+ // No mutex implemented. No need to release mutex.
+ // 2-way mux. Hence no need to do anything
+ Return(0x1)
+
+ }
+
+ If (LEqual (Arg0, 2))
+ {
+
+ //Get ddc/aux mux status for dGPU
+ Return(SGPI(ESEL))
+ }
+
+ Return(0x0) // mutex not acquired
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: MXDS
+//
+// Description: Display output MUX control
+//
+// Input:
+// Arg0:
+// 0 - Get Mux state
+// 1 - Set Display to active on this GPU
+// 2 - Set Backlight control to active on this GPU
+// 3 - Set Display & Backlight to active on this GPU
+//
+// Output:
+// If Arg0 = 0, Error = Display is not MUXed
+// Else return value of the state of the MUX
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(MXDS, 1, Serialized)
+ {
+ P8DB(0x9A, Arg0, 2000)
+
+ If(LEqual (Arg0, 0))
+ {
+ //Get display mux status for dGPU
+ return(SGPI(DSEL))
+ } else
+// If(LOr(LEqual (Arg0, 1), LEqual (Arg0, 2)))
+ {
+ //Set display mux to dgpu
+ SGPO(DSEL, 1) // dGPU_SELECT
+ SGPO(PSEL, 1) // dGPU_PWM_SELECT
+ }
+
+ Return (0)
+ }
+#endif // MXM && HYBRID
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _ROM
+//
+// Description: Video ROM data buffer
+//
+// Input:
+// Arg0: Integer Offset of the graphics device ROM data
+// Arg1: Integer Size of the buffer to fill in (up to 4K)
+//
+// Output:
+// Buffer Buffer of requested video ROM bytes
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_ROM,2)
+ {
+
+ Store (Arg0, Local0)
+ Store (Arg1, Local1)
+
+ P8DB(0x44, Local1, 100)
+
+
+ If (LGreater (Local1, 0x1000))
+ {
+ Store (0x1000, Local1)
+ }
+ If (LGreater (Local0, 0x20000))
+ {
+ Return(Buffer(Local1){0})
+ }
+
+
+ Multiply (Local1, 0x08, Local3)
+ Name (ROM1, Buffer (0x8000) {0})
+ Name (ROM2, Buffer (Local1) {0})
+
+ If(LLess(Local0, 0x8000)){
+ Store(RBF1, ROM1)
+ }
+ ElseIf(LLess(Local0, 0x10000)){
+ Subtract(Local0,0x8000,Local0)
+ Store(RBF2, ROM1)
+ }
+ ElseIf(LLess(Local0, 0x18000)){
+ Subtract(Local0,0x10000,Local0)
+ Store(RBF3, ROM1)
+ }
+ ElseIf(LLess(Local0, 0x20000)){
+ Subtract(Local0,0x18000,Local0)
+ Store(RBF4, ROM1)
+ }
+
+ Multiply (Local0, 0x08, Local2)
+ CreateField (ROM1, Local2, Local3, TMPB)
+ Store (TMPB, ROM2)
+ Return (ROM2)
+ }
+
+//
+// Check for Nvidia _DSM UUIDs
+//
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HDSM
+//
+// Description: Device Specific Methods for Hybrid dGPU (may be invoked from iGD as well)
+// Implements Mxm and SG specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// nVidia
+// MXM dGPU GUID :9D95A0A0-0060-4D48-B34D-7E5FEA129FD4
+//
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(HDSM, 4, SERIALIZED)
+ {
+
+#ifdef MXM_DSM_GUID
+
+ If(LEqual(Arg0, ToUUID("4004A400-917D-4cf2-B89C-79B62FD55665")))
+ {
+
+ P8DB(0xEE, Arg2, 1000)
+
+ Switch(ToInteger(Arg2))
+ {
+ //
+ // Function 0: MXM_FUNC_MXSS
+ //
+ case (0)
+ {
+ //Sub-Functions 0,16,24 are supported
+ Return(ToBuffer(0x01010001))
+ }
+
+ //
+ // Function 24: MXM_FUNC_MXMI
+ //
+ case (24)
+ {
+ Return(ToBuffer(0x300)) // MXM 1.101 defines revision as 0x300
+ // Return(ToBuffer(0x30)) // MXM 1.101 defines revision as 0x300
+ }
+
+ //
+ // Function 16: MXM_FUNC_MXMS
+ //
+ case (16)
+ {
+ If(LEqual (Arg1, 0x300)) // MXM 1.101 defines revision as 0x300
+ {
+#if MXM30_SUPPORT
+ // calculate true length of MXM block
+ CreateWordField(MXM3, 6, MXLN)
+ Add(MXLN, 8, Local0) // Add length of MXM header
+ CreateField(MXM3, 0, Local0, MXM)
+ Return(ToBuffer(MXM))
+#else
+ // ElkCreek 4 Mxm data structure
+ Name(MXM3, Buffer()
+ {
+ 0x4d, 0x58, 0x4d, 0x5f, 0x03, 0x00, 0x5d, 0x00,
+ 0x30, 0x11, 0xb8, 0xff, 0xf9, 0x3e, 0x00, 0x00,
+ 0x00, 0x00, 0x0a, 0xf0, 0xf9, 0x3e, 0x00, 0x00,
+ 0x60, 0xe9, 0xd0, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x60, 0x6a, 0xda, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x20, 0x2b, 0xe2, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x60, 0x6c, 0xea, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x20, 0x6a, 0xda, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x20, 0x6c, 0xea, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x01, 0x90, 0x01, 0x00, 0x03, 0x00, 0x90, 0x01,
+ 0x13, 0x00, 0x90, 0x01, 0xe5, 0x0d, 0x01, 0x01,
+ 0x01, 0x00, 0x00, 0x00, 0xe5, 0x0d, 0x01, 0x03,
+ 0x00, 0x90, 0xd8, 0x09, 0x11, 0x0a
+ })
+ Return(MXM3)
+#endif
+ }
+ }
+ } // switch
+ Return(0x80000002) //MXM_ERROR_UNSUPPORTED - FunctionCode or SubfunctionCode not supported
+ } // "4004A400-917D-4cf2-B89C-79B62FD55665"
+
+#endif // MXM_DSM_GUID
+
+ Return (0x80000001) //MXM_ERROR_UNSPECIFIED
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _DSM Device Specific Method for dGPU device
+//
+// Description: Implement Mxm and SG specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// MXM dGPU GUID :9D95A0A0-0060-4D48-B34D-7E5FEA129FD4
+// NBCI GUID :D4A50B75-65C7-46F7-BfB7-41514CEA0244
+// Ventura GUID :95DB88FD-940A-4253-A446-70CE0504AEDF
+// Optimus DSM_GUID :A486D8F8-0BDA-471B-A72B-6042A6B5BEE0
+//
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_DSM,4,SERIALIZED)
+ {
+ CreateByteField (Arg0, 3, GUID)
+ P8DB(0xDD, GUID, 1000)
+ //
+ // Check for Nvidia _DSM UUIDs
+ //
+ // common _DSM for dGPU and iGPU: NBCI, SG DSM, Ventura
+ return(IGPU_SCOPE.HDSM(Arg0, Arg1, Arg2, Arg3))
+ }
+
+
+#ifdef OPTIMUS_DSM_GUID
+
+
+// TEST !!! TEST !!! TEST !!!!
+// NvOptimus should not be be using _ON and _OFF methods for power cycling
+// Used here for testing with Intel ElkCreek Mxm interposer
+//
+ Name(CTXT, Zero)// Save Context flag
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _ON
+//
+// Description: Optimus w/a for before dGPU _ON
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(_ON, 0, Serialized)
+ {
+ P8DB(0x01, 0x11, 2000)
+
+ // OEM Mxm Power status
+ SGON()
+
+// Nvidia Optimus driver w/a. Restore saved PCI context of PEG Video card
+// Skip restore resource if GPRF = 1
+ If(LNotEqual(GPRF, One))
+ {
+ Store(CMDR,local0)
+ Store(Zero, CMDR)
+ Store(VGAB, VGAR)
+ Store(0x06, CMDR)
+ Store(0x0,NHDA) //NV HDMI audio did not need enable
+ Store(local0,CMDR)
+ }
+
+// Store(1, RETR) // retrain PCI-E bus
+//+<
+// doesn't look like we need delay here...
+// Sleep(0x64)
+
+ Store(SWSMI_NVOEM_CMOS_R, SSMP) // Read CMOS:AudioCodec flag to AcpiNvs:SGFL
+// Clear HDA enable bit if flag not set
+/* if(LEqual(And(SGFL, 2), 0))
+ {
+ Store(0, NHDM)
+ }
+*/
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _OFF
+//
+// Description: Optimus w/a before dGPU _OFF
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(_OFF, 0, Serialized)
+ {
+
+ P8DB(0x0F, 0xFF, 2000)
+
+// store PCI context only once
+ If(LEqual(CTXT, Zero))
+ {
+// Nvidia Optimus driver w/a. Save PCI context of PEG Video card
+ //+ for GC6 , need to de-assert EC FB_CLAMP
+
+ //-
+ // Skip restore resource if GPRF = 1
+ If(LNotEqual(GPRF, One))
+ {
+ Store(VGAR, VGAB)
+
+ }
+//+<
+ Store(1, CTXT)
+ }
+ SGOF()
+
+ }
+#endif
+} // end Scope(DGPUPCH_SCOPE)
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NViGDmiscPCH.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NViGDmiscPCH.asl
new file mode 100644
index 0000000..b642537
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NViGDmiscPCH.asl
@@ -0,0 +1,280 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/NViGDmiscPCH.asl 1 1/15/13 6:03a Joshchou $
+//
+// $Revision: 1 $
+//
+// $Date: 1/15/13 6:03a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/NViGDmiscPCH.asl $
+//
+// 1 1/15/13 6:03a Joshchou
+// [TAG] EIP107237
+// [Category] Improvement
+// [Description] Create componet for SG support on PCH
+// [Files] SgUltNvidia.cif
+// NVdGPUPCH.asl
+// NViGPUPCH.asl
+// NViGDmiscPCH.asl
+// OpSSDTPCH.asl
+// NvVenturaPCH.asl
+// NvGPSPCH.asl
+// NvSSDTPCH.asl
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+//
+//
+// 4 11/12/10 1:27p Alexp
+// Change IDAB method: invoke IGD_SCOPE.IDAB is it's defined
+//
+// 3 10/08/10 12:04p Alexp
+// code clean up: removed unused externs
+//
+// 2 10/05/10 7:14p Alexp
+// 1. Added debug macro to be able to insert check points in target ASL
+// code
+// 2. Reuse NVdGPU.asl file to build OpSSDT for Optimus and NvSSDT for
+// MUXed SG targets.
+// NvOptimus.asl no longer required
+//
+// 1 9/17/10 1:21p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgNvidia.cif;
+// NvSSDT.asl; NVdGPU.asl;NViGPU.asl;NViGDmisc
+// OpSSDT.asl;NvOptimus.asl;NvVenture.asl
+//
+// 1 6/08/10 3:45p Alexp
+//
+// 1 6/03/10 2:54p Alexp
+//
+// 6 10/05/09 5:35p Alexp
+// updated asl code for Ati and Nvidia according to Calpella SG BWG 1.1
+//
+// 5 8/20/09 7:08p Alexp
+// upgraded Ati and Nvidia SSDT Asl files to match latest Acpi code drop
+// #68
+//
+// 4 8/10/09 4:21p Alexp
+// changed with latest reference code from Intel MPG. not yet tested
+//
+// 3 7/16/09 11:17a Alexp
+// Added SG support for AMD ATI Gfx adaptors
+//
+//
+//**********************************************************************
+
+External(DSEN)
+External(IGPU_SCOPE.CDCK)
+External(DGPUPCH_SCOPE.DD02)
+External(IGPU_SCOPE.IDAB, MethodObj)
+
+//Do not remove this function.
+Method(IDAB, 0, Serialized)
+{
+ If (CondRefOf(IGPU_SCOPE.IDAB))
+ {
+ IGPU_SCOPE.IDAB()
+ }
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HGAS
+//
+// Description: HG Adaptor select, notify
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HGAS) //HG Adaptor select
+{
+ //Stateless button/Hotkey supporting 3 states - Power Saver, Adaptive and Perf
+
+ Increment(IGPU_SCOPE.GPSS)
+ Mod(IGPU_SCOPE.GPSS, 3, IGPU_SCOPE.GPSS)
+
+ Store(1,IGPU_SCOPE.GPPO)
+ Store(1,IGPU_SCOPE.SGNC) //indicate 'policy select' change
+
+ Notify(IGPU_SCOPE, 0xD0)
+ Notify(PCI_SCOPE.WMI1, 0xD0) // Mirror Notify on WMI1
+
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HBRT
+//
+// Description: Send backlight notifications to the DGPU LFP device
+// This is required for Win7 and is backward compatible with Vista
+//
+// Input: Arg0 - 4 - Brightnes Down, 3- Up
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HBRT, 1 , Serialized)
+{
+ Store(Arg0,IGPU_SCOPE.DACE)
+
+ If(And(4,DSEN)) //Note: DSEN variable is expected to be set by IGD miniport only.
+ {
+ If(LEqual(Arg0,4))
+ {
+ Notify(DGPUPCH_SCOPE.DD02,0x87) //Note: DD02 is hardcoded as the LFP device in intelgfx.asl
+ }
+ If(LEqual(Arg0,3))
+ {
+ Notify(DGPUPCH_SCOPE.DD02,0x86)
+ }
+ }
+
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HPFS
+//
+// Description: Panel Fitting Hot Key
+//
+// Input: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HPFS, 0, Serialized) //Panel Fitting Hot Key
+{
+ //
+ // HG Handling of Panel Fitting Switch
+ //
+
+ Store(5,IGPU_SCOPE.DACE) // Indicate display scaling hot key event
+ Store(2,IGPU_SCOPE.SGNC) // Indicate platpolicy change
+
+ //
+ // Expansion Mode toggling
+ //
+ Increment(IGPU_SCOPE.GPSP)
+ Mod(IGPU_SCOPE.GPSP, 4 , IGPU_SCOPE.GPSP)
+
+ Notify(IGPU_SCOPE,0xDC)
+
+}
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HNOT
+//
+// Description: Notification handler for Switchable graphics. Called from GNOT()
+//
+// Input: Arg0 = Current event type:
+// 1 = display switch
+// 2 = lid
+// 3 = dock (!!!!!Acpi ref code, Method(GDCK)sends 4 for Dock notifications )
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method (HNOT, 1, Serialized)
+{
+ Switch(ToInteger(Arg0))
+ {
+ case(1) //Display Switch event
+ {
+ Store(3,IGPU_SCOPE.SGNC) // indicate 'Displaystatus' change
+ Store(1,IGPU_SCOPE.DACE)
+ Notify(IGPU_SCOPE, 0x80)
+ Notify(PCI_SCOPE.WMI1, 0x80) // Mirror Notify on WMI1
+ }
+
+ case (2) //Lid switch event
+ {
+ //Note: NV clarified that only LDES needs to be set
+ Store(1,IGPU_SCOPE.LDES)
+ Notify(IGPU_SCOPE, 0xDB)
+ Notify(PCI_SCOPE.WMI1, 0xDB) // Mirror Notify on WMI1
+ }
+// case (3) //Dock event
+ case (4) //Dock event (!!!Acpi ref code, Method(GDCK)sends 4 for Dock notifications)
+ {
+ Store(IGPU_SCOPE.CDCK, IGPU_SCOPE.DKST) // Store the current dock state
+ Notify(IGPU_SCOPE, 0x81)
+ Notify(PCI_SCOPE.WMI1, 0x81) // Mirror Notify on WMI1
+ }
+
+ Default
+ {
+ Notify(IGPU_SCOPE,0x80)
+ }
+
+ }
+
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: CHPS
+//
+// Description: Shows current Hybrid Policy status on Port80 header
+// Adaptive -> 1, Save power -> 2 and High performance -> 3
+//
+// Input: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(CHPS)
+{
+ P8DB(0xEC, Add(IGPU_SCOPE.GPSS, 1), 2000)
+}
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HDOS
+//
+// Description: Check if the _DOS flag was set during the hot key handling
+//
+// Input: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HDOS, 0, Serialized)
+{
+ If(LEqual(IGPU_SCOPE.DOSF,1))
+ {
+ Store(1,IGPU_SCOPE.SGNC) // indicate 'policy select' change
+ Notify(IGPU_SCOPE,0xD0)
+ Notify(PCI_SCOPE.WMI1, 0xD0) // Mirror Notify on WMI1
+ Store(0, IGPU_SCOPE.DOSF) // Clear the DOSF
+ }
+}
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NViGPUPCH.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NViGPUPCH.asl
new file mode 100644
index 0000000..cdb7061
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NViGPUPCH.asl
@@ -0,0 +1,1078 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/NViGPUPCH.asl 2 2/21/13 5:41a Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 2/21/13 5:41a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/NViGPUPCH.asl $
+//
+// 2 2/21/13 5:41a Joshchou
+// [TAG] EIP106524
+// [Category] New Feature
+// [Description] Support GC6 function for Optimus
+//
+// 1 1/15/13 6:03a Joshchou
+// [TAG] EIP107237
+// [Category] Improvement
+// [Description] Create componet for SG support on PCH
+// [Files] SgUltNvidia.cif
+// NVdGPUPCH.asl
+// NViGPUPCH.asl
+// NViGDmiscPCH.asl
+// OpSSDTPCH.asl
+// NvVenturaPCH.asl
+// NvGPSPCH.asl
+// NvSSDTPCH.asl
+//
+// 6 4/11/12 3:54a Alanlin
+// [TAG] EIP82808
+// [Category] Improvement
+// [Description] nVidia GPS function improvement.
+// [Files] Board\EM\SgTpv\AcpiTables\SgTpvAcpiTables.sdl
+// Board\EM\SgTpv\AcpiTables\NvGPS.asl
+// Board\EM\SgTpv\AcpiTables\NViGPU.asl
+//
+// 5 12/02/11 5:37a Alanlin
+// [TAG] EIP75211
+// [Category] Improvement
+// [Description] Following nVidia's suggestion to change OperationRegion
+// access type from "AnyAcc" to "DWordAcc" for nVidia new chip.
+//
+// 4 12/02/11 1:00a Alanlin
+// [TAG] EIP75359
+// [Category] Improvement
+// [Description] 1.Fixed \_SB_.PCI0.GFX0.HDSM method can't be
+// unassembled if use windebug utility to check it.
+// 2.Fixed _DSM sub function 0x1B will report "Unexpected argument type"
+// message if use windebug utility to check it.
+//
+// 2 10/14/11 2:59a Alanlin
+// [TAG] EIP64451
+// [Category] New Feature
+// [Description] Optimus GPS feature update
+// [Files] NvSSDT.asl
+// NViGPU.asl
+// OpSSDT.asl
+// NvGPS.asl
+// SgNvidia.cif
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+//
+//
+// 7 3/17/11 6:17p Alexp
+// Optimus:Add code to preserve HD AudioCodec enable flag in CMOS
+//
+// 6 11/12/10 1:28p Alexp
+// bring back the field ELCL to hold the Link Control register value. Not
+// used as it's overriden in SG Reference Code in SgDGPU.asl
+//
+// 5 11/11/10 3:15p Alexp
+// Optimization: bring Optimus _DSM functions from NvdGPU.asl
+//
+// 4 10/08/10 1:50p Alexp
+// re-arrange debug messages
+//
+// 3 10/06/10 3:34p Alexp
+// Include defines for different Nvidia GUID functions. Helps to control
+// inclusion of peices of ASL depending on type of desired SG mode
+//
+// 2 10/05/10 7:14p Alexp
+// 1. Added debug macro to be able to insert check points in target ASL
+// code
+// 2. Reuse NVdGPU.asl file to build OpSSDT for Optimus and NvSSDT for
+// MUXed SG targets.
+// NvOptimus.asl no longer required
+//
+// 1 9/17/10 1:21p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgNvidia.cif;
+// NvSSDT.asl; NVdGPU.asl;NViGPU.asl;NViGDmisc
+// OpSSDT.asl;NvOptimus.asl;NvVenture.asl
+//
+//**********************************************************************
+External(NVGA)
+
+External(NXD1)
+External(NXD2)
+External(NXD3)
+External(NXD4)
+External(NXD5)
+External(NXD6)
+External(NXD7)
+External(NXD8)
+External(DID1)
+External(DID2)
+External(DID3)
+External(DID4)
+External(DID5)
+External(DID6)
+External(DID7)
+External(DID8)
+
+Scope (IGPU_SCOPE)
+{
+
+ Method(_INI,0)
+ {
+ //DIDx values have been changed in MxmAcpiTables.c
+ //Port - D to be used for eDP only and not as DFP. Hence generating a new toggle list
+ Store(DID1, Index(TLPK,0)) // CRT
+ Store(DID2, Index(TLPK,2)) // LFP
+ Store(DID3, Index(TLPK,4)) // DP_B
+ Store(DID4, Index(TLPK,6)) // HDMI_B
+ Store(DID5, Index(TLPK,8)) // HDMI_C
+ Store(DID6, Index(TLPK,10)) // DP_D
+ Store(DID7, Index(TLPK,12)) // HDMI_D
+ Store(DID2, Index(TLPK,14)) // LFP+CRT
+ Store(DID1, Index(TLPK,15))
+ Store(DID2, Index(TLPK,17)) // LFP+DP_B
+ Store(DID3, Index(TLPK,18))
+ Store(DID2, Index(TLPK,20)) // LFP+HDMI_B
+ Store(DID4, Index(TLPK,21))
+ Store(DID2, Index(TLPK,23)) // LFP+HDMI_C
+ Store(DID5, Index(TLPK,24))
+ Store(DID2, Index(TLPK,26)) // LFP+DP_D
+ Store(DID6, Index(TLPK,27))
+ Store(DID2, Index(TLPK,29)) // LFP+HDMI_D
+ Store(DID7, Index(TLPK,30))
+ }
+
+//
+// MXMX method is dupplicated under GFX0 scope in INTELGFX.ASL
+// need to replace it with method in this file.
+//
+#ifndef OPTIMUS_DSM_GUID
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: MXMX
+//
+// Description: Display DDC Mux Control
+//
+// Input:
+// Arg0: Get/Set DDC/Aux Mux State
+// 0- Acquire DDC/Aux Mux on this GPU
+// 1- Release Mux from this GPU
+// 2- Get Mux state
+//
+// Output:
+// 0, Not Acquired.
+// if Arg0 = 0 or 1, Non-Zero return indicates success acquiring MUX
+// (and MUX has switched to this output)
+// if Arg0 = 2, Non-Zero return indicates MUX is currently set to this output
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (MXMX, 1, Serialized)
+ {
+ P8DB(0x77, Arg0, 2000)
+
+ If (LEqual (Arg0, 0))
+ {
+ //Acquire DDC/AUX mux
+ // No mutex implemented. No need to acquire mutex.
+ // Set mux to iGPU
+ DGPUPCH_SCOPE.SGPO(DSEL, 0)
+ DGPUPCH_SCOPE.SGPO(ESEL, 0) // use edid_select# as mutex flag
+
+ Return(0x1)
+ }
+
+ If (LEqual (Arg0, 1))
+ {
+ //Release DDC/AUX mux
+ // No mutex implemented. No need to release mutex.
+ // 2-way mux. Hence no need to do anything
+ Return(0x1)
+ }
+
+ If (LEqual (Arg0, 2))
+ {
+
+ //Get ddc/aux mux status for iGPU
+ Return(LNot(DGPUPCH_SCOPE.SGPI(ESEL)))
+ }
+
+ Return(0x0) // mutex not acquired
+ }
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: MXDS
+//
+// Description: Display output MUX control
+//
+// Input:
+// Arg0:
+// 0 - Get Mux state
+// 1 - Set Display to active on this GPU
+// 2 - Set Backlight control to active on this GPU
+// 3 - Set Display & Backlight to active on this GPU
+//
+// Output:
+// If Arg0 = 0, Error = Display is not MUXed
+// Else return value of the state of the MUX
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(MXDS, 1, Serialized)
+ {
+ P8DB(0x7A, Arg0, 2000)
+
+ If(LEqual (Arg0, 0))
+ {
+ //Get display mux status for iGPU
+ return(LNot(DGPUPCH_SCOPE.SGPI(DSEL)))
+ } else
+// If(LOr(LEqual (Arg0, 1), LEqual (Arg0, 2)))
+ {
+ //Set display mux to igpu
+ DGPUPCH_SCOPE.SGPO(DSEL, 0)
+ DGPUPCH_SCOPE.SGPO(PSEL, 0)
+ }
+
+ Return (0)
+ }
+
+#endif // OPTIMUS_DSM_GUID
+
+//<AMI_SHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: NVIG
+//
+// Description: Nvidia NVIG (iGPU) OperationRegion
+//
+//-------------------------------------------------------------------------
+//<AMI_SHDR_END>
+ OperationRegion(NVIG,SystemMemory,NVGA,0x45)
+ Field(NVIG, DWordAcc, NoLock, Preserve)
+ {
+ // OpRegion Header
+
+ NISG, 0x80, // (000h) Signature-"NVSG-IGD-DSM-VAR".
+ NISZ, 0x20, // (010h) OpRegion Size in KB.
+ NIVR, 0x20, // (014h) OpRegion Version.
+
+ // OpRegion Data
+ GPSS, 0x20, // Policy Selection Switch Status (Policy selection)
+ GACD, 0x10, // Active Displays
+ GATD, 0x10, // Attached Displays
+ LDES, 0x08, // Lid Event State
+ DKST, 0x08, // Dock State
+ DACE, 0x08, // Display ACPI event
+ DHPE, 0x08, // Display Hot-Plug Event
+ DHPS, 0x08, // Display Hot-Plug Status
+ SGNC, 0x08, // Notify Code (Cause of Notify(..,0xD0))
+ GPPO, 0x08, // Policy Override (Temporary ASL variables)
+ USPM, 0x08, // Update Scaling Preference Mask (Temporary ASL variable)
+ GPSP, 0x08, // Panel Scaling Preference
+ TLSN, 0x08, // Toggle List Sequence Number
+ DOSF, 0x08, // Flag for _DOS
+ ELCL, 0x10, // Endpoint Link Contol Register Value
+ }
+
+ // Toggle List Package
+ Name(TLPK,Package()
+ {
+ //fix this toggle list. DIDx values have been changed in MxmAcpiTables.c
+ 0xFFFFFFFF, 0x2C, // CRT
+ 0xFFFFFFFF, 0x2C, // LFP
+ 0xFFFFFFFF, 0x2C, // DP_B
+ 0xFFFFFFFF, 0x2C, // HDMI_B
+ 0xFFFFFFFF, 0x2C, // HDMI_C
+ 0xFFFFFFFF, 0x2C, // DP_D
+ 0xFFFFFFFF, 0x2C, // HDMI_D
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+CRT
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+DP_B
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+HDMI_B
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+HDMI_C
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+DP_D
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+HDMI_D
+
+ })
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: INDL
+//
+// Description: Initialize Global Next active device list.
+//
+// Input: None
+//
+// Output: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(INDL, 0, Serialized)
+ {
+ Store(0, NXD1)
+ Store(0, NXD2)
+ Store(0, NXD3)
+ Store(0, NXD4)
+ Store(0, NXD5)
+ Store(0, NXD6)
+ Store(0, NXD7)
+ Store(0, NXD8)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: SND1
+//
+// Description: Set Next active device for a single device
+//
+// Input:
+// Arg0 : Device ID of the device that's to be set as next active device.
+//
+// Output: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(SND1, 1, Serialized)
+ {
+ If(LEqual(Arg0, DID1))
+ {
+ Store(1, NXD1)
+ }
+ If(LEqual(Arg0, DID2))
+ {
+ Store(1, NXD2)
+ }
+ If(LEqual(Arg0, DID3))
+ {
+ Store(1, NXD3)
+ }
+ If(LEqual(Arg0, DID4))
+ {
+ Store(1, NXD4)
+ }
+ If(LEqual(Arg0, DID5))
+ {
+ Store(1, NXD5)
+ }
+ If(LEqual(Arg0, DID6))
+ {
+ Store(1, NXD6)
+ }
+ If(LEqual(Arg0, DID7))
+ {
+ Store(1, NXD7)
+ }
+ If(LEqual(Arg0, DID8))
+ {
+ Store(1, NXD8)
+ }
+
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: SNXD
+//
+// Description: Set Next active device
+//
+// Input:
+// Arg0 TLSN
+//
+// Output: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(SNXD, 1, Serialized)
+ {
+ INDL()
+
+ //
+ // Locate the toggle table entry corresponding to TLSN value
+ // Toggle list entries are separated by 0x2C.
+ //
+
+ Store(1, Local0) // Local0 to track entries. Point to the first entry (TLSN starts from 1)
+ Store(0, Local1) // Local1 to track elements inside the TLPK package (ACPI IDs and '0x2C')
+
+ while(LLess(Local0, Arg0)) // TLSN start from 1!!
+ {
+ if(LEqual(DeRefOf(Index(TLPK,Local1)), 0x2C))
+ {
+ Increment(Local0)
+ }
+ Increment(Local1)
+
+ }
+
+ SND1(DeRefOf(Index(TLPK, Local1))) // 1 st ACPI ID in the entry corresponding to TLSN
+ Increment(Local1)
+ if(LNotEqual(DeRefOf(Index(TLPK,Local1)), 0x2C)) // Check for separator
+ {
+ SND1(DeRefOf(Index(TLPK, Local1))) // 2 nd ACPI ID in the entry corresponding to TLSN
+ }
+
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: CTOI
+//
+// Description: Convert _DOD indices-> MDTL index
+//
+// Input:
+// Arg 0 is the currently active display list
+//
+// Output: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(CTOI,1, Serialized)
+ {
+ Switch(ToInteger(Arg0)) //Arg 0 is the currently active display list
+ {
+ //_DOD indices-> MDTL index
+ case(0x1) {Return(1)} //CRT
+ case(0x2) {Return(2)} //LFP
+ case(0x4) {Return(3)} //DP_B
+ case(0x8) {Return(4)} //HDMI_B
+ case(0x10) {Return(5)} //HDMI_C
+ case(0x20) {Return(6)} //DP_D
+ case(0x40) {Return(7)} //HDMI_D
+ case(0x3) {Return(8)} //LFP+CRT
+ case(0x6) {Return(9)} //LFP+DP_B
+ case(0xA) {Return(10)} //LFP+HDMI_B
+ case(0x12) {Return(11)} //LFP+HDMI_C
+ case(0x22) {Return(12)} //LFP+DP_D
+ case(0x42) {Return(13)} //LFP+HDMI_D
+ Default {Return(1)}
+ }
+ }
+
+// Check for Nvidia _DSM UUIDs
+//
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HDSM
+//
+// Description: Device Specific Methods for Hybrid GPU (may be invoked from dGP and iGD)
+// Implements Mxm and SG specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// nVidia
+// SG dGPU GUID :9D95A0A0-0060-4D48-B34D-7E5FEA129FD4
+// NBCI GUID :D4A50B75-65C7-46F7-BfB7-41514CEA0244
+// Ventura GUID :95DB88FD-940A-4253-A446-70CE0504AEDF
+// Optimus DSM_GUID :A486D8F8-0BDA-471B-A72B-6042A6B5BEE0
+//
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(HDSM, 4, SERIALIZED)
+ {
+
+#if NV_VENTURA_SUPPORT == 1
+ //SPB_DSM_GUID {95DB88FD-940A-4253-A446-70CE0504AEDF}
+//x if(CMPB(Arg0, Buffer(){0xFD,0x88,0xDB,0x95,0x0A,0x94,0x53,0x42,0xA4,0x46,0x70,0xCE,0x05,0x04,0xAE,0xDF}))
+ If(LEqual(Arg0, ToUUID("95DB88FD-940A-4253-A446-70CE0504AEDF")))
+ {
+ return ( DGPUPCH_SCOPE.SPB(Arg0, Arg1, Arg2, Arg3))
+ }
+#endif
+
+#if NV_GPS_SUPPORT == 1
+ //SPB_DSM_GUID {A3132D01-8CDA-49BA-A52E-BC9D46DF6B81}
+//x if(CMPB(Arg0, Buffer(){0x01, 0x2D, 0x13, 0xA3, 0xDA, 0x8C, 0xBA, 0x49,0xA5, 0x2E, 0xBC, 0x9D, 0x46, 0xDF, 0x6B, 0x81}))
+ If(LEqual(Arg0, ToUUID("A3132D01-8CDA-49BA-A52E-BC9D46DF6B81")))
+ {
+ return ( DGPUPCH_SCOPE.GPS(Arg0, Arg1, Arg2, Arg3))
+ }
+#endif
+
+#if NV_GC6_SUPPORT == 1
+ If(LEqual(Arg0, ToUUID("CBECA351-067B-4924-9CBD-B46B00B86F34")))
+ {
+ return ( DGPUPCH_SCOPE.NGC6(Arg0, Arg1, Arg2, Arg3))
+ }
+#endif
+
+#if HYBRID_DSM_GUID || NBCI_DSM_GUID || OPTIMUS_DSM_GUID
+
+ Name(SGCI, 0) // SG Common Interface
+ Name(NBCI, 0) // Notebok Common Interface
+ Name(OPCI, 0) // Optimus Common Interface
+ Name(BUFF, 0) // Buff Parameter
+
+// Hybrid Graphics Methods supported only if MUXed mode is selected
+#ifdef HYBRID_DSM_GUID
+ If(LEqual(Arg0, ToUUID("9D95A0A0-0060-4D48-B34D-7E5FEA129FD4")))
+ {
+ Store(1, SGCI)
+ }
+#endif
+// NBCI Methods can be querried in botd MUXed and MUXless modes
+#ifdef NBCI_DSM_GUID
+ if(LEqual(Arg0, ToUUID("D4A50B75-65C7-46F7-BfB7-41514CEA0244")))
+ {
+ Store(1, NBCI)
+ }
+#endif
+// Optimus Methods can be querried in botd MUXed and MUXless modes
+#ifdef OPTIMUS_DSM_GUID
+ If(LEqual(Arg0, ToUUID("A486D8F8-0BDA-471B-A72B-6042A6B5BEE0")))
+ {
+ Store(1, OPCI)
+ }
+#endif
+
+ If(LOr(OPCI, LOr( SGCI, NBCI)) )
+ {
+
+ P8DB(0xEE, Arg2, 1000)
+
+ if(OPCI) {
+ if(LNotEqual(Arg1, 0x100)) {
+ Return(0x80000002)
+ }
+ }
+ else { // NBCI & SGCI
+ If(LNotEqual(Arg1,0x0102))
+ {
+ Return(0x80000002)
+ }
+ }
+ //
+ // Function 0: NVSG_FUNC_SUPPORT - Return Supported Functions
+ //
+ // Returns:
+ // SGCI: Functions 0-6,18 are supported
+ // NBCI: Functions 0,4-6,18 are supported
+ // OPCI: Functions 0,5,6,12,13,16,17,26,27
+ //
+ If(LEqual(Arg2,0))
+ {
+ if(SGCI){
+ Return(Buffer(){0x7F, 0x00, 0x04, 0x00})
+ } else {
+ if(NBCI){
+ Return(Buffer(){0x73, 0x00, 0x04, 0x00})
+ }
+ else {
+ if(OPCI){
+ //Sub-Functions 0,16,17,26 are supported
+ // Return(ToBuffer(0x04030001))
+ //Sub-Functions 0,5, 6, 12, 13, 16, 17, 26,27 are supported
+ // Return(ToBuffer(0x0c031861))
+ // Follow nVidia's suggetion, Optimus displayless platform has no used for other sub-functions.
+ #if NV_OPTIMUS_DISPLAYLESS == 1
+ Return(Buffer(){0x01, 0x00, 0x03, 0x04})
+ #else
+ Return(Buffer(){0x61, 0x18, 0x03, 0x0C})
+ #endif
+ //Sub-Functions 0,16 26,27 are supported
+// Return(ToBuffer(0x0c010001))
+
+ }
+ }
+ }
+ }
+
+ //
+ // Function 1: NVSG_FUNC_CAP
+ //
+ // Returns the capabilities of the Switchable Graphics
+ // implementation on the platform
+ //
+ If(LEqual(Arg2,1))
+ {
+ Name (TEMP, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TEMP,0,STS0)
+ if(SGCI){
+ // Return status (bit0-1 Hybrid enabled) and indicate Hybrid power On/Off
+
+ // 0 HG Enable Status = 1
+ // 1 GPU Output MUX Capabilities= 1
+ // 2 GPU Policy Selector Capabilities = 1
+ // 3-4 GPU Control Status = 3
+ // 5 GPU Reset Control = 1
+ // 6 MUX'ed Hot-Plug Capabilities = 0
+ // 7 MUX'ed DDC/AUX Capabilities = 1
+ // 8-10 Notify Codes
+ // 0= Not a Notify(0xD0)
+ // 1= POLICYSELECT change
+ // 2= PLATPOLICY change
+ // 3= DISPLAYSTATUS change
+ // 11-12 EC Notify code
+ // 14-15 Eject Capabilities = 0
+ // 16 Mux'd backlight cap = 0
+ // 17-23 Hybrid EC version = 0
+ // 24-26 HG capability = 3 (Power saver & Boost performance)
+ // 27-28 HG switch = 1 (hot-key or stateless button)
+ // 29 Fasl LCD swithing = 0
+ // 31 = 0
+
+ // Switchable caps
+ Or(STS0,0x0B0000BF,STS0)
+
+ // Switchable Notify Code (Cause of Notify(..,0xD0))
+ Or(STS0,ShiftLeft(SGNC,8,SGNC),STS0)
+ } else {
+ // NBCI
+ // 0..3 Reserved=00
+ // 4 Aux Power States
+ // 6:5 LID State Event
+ // 0= Use the event List to determine support
+ // 1= Force use of Generic Hot-Plug Notify(0x81)
+ // 2= Force use of Specific Lid Event, e.g. Notify (0xDB)
+ // 3= Reserved for future use
+ // 7:8 LID State Enumeration
+ // 0= Use _DCS under _LCD device(default)
+ // 1= Provides status DISPLAYSTATUS Bit[4], for single pannel systems only(recommended)
+ // 2,3= Reserved
+ // 9 Dock State Enumerartion
+ // 0= Doesn't have a Dock(or _DCS under device reflects attachments-via-dock (default)
+ // 1= Provides dock status info via DISPLAYSTATUS Bit[5] (recommended)
+ // 10:30 Reserved
+ // 31 = 0
+
+ // use all defaults for now
+ Or(STS0,0x00000,STS0)
+ }
+ return(TEMP)
+ }
+
+ //
+ // Function 2: NVSG_FUNC_SELECTOR
+ //
+ // Returns device preference between iGPU and dGPU
+ //
+ If(LEqual(Arg2,2))
+ {
+ Name (TMP1, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TMP1,0,STS1)
+
+ //Ignore bits[6:5] since we are not supporting Switchable enable/disable policy selection
+ //Only Switchable policy selection is supported via CAS+F6 hotkey
+
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(DerefOf(Index(Arg3,0)), Local0)
+ ToInteger(Arg3, Local0)
+ And(Local0, 0x1F, Local0)
+
+ If(And(Local0,0x10)) //If Switchable policy update bit is set
+ {
+ And(Local0,0xF,Local0)
+ Store(Local0,GPSS)
+ Notify(IGPU_SCOPE,0xD9) //Broadcast "policy completed" notification
+ Notify(PCI_SCOPE.WMI1, 0xD9) // Mirror Notify on WMI1
+
+ }
+ Else
+ {
+ And(Local0,0xF,Local0)
+ If(LEqual(GPPO,1))
+ {
+ // Retrieve the setting from NVS
+ Store(GPSS,Local0)
+ Or(Local0,0x10,Local0)
+ Store(0,GPPO)
+ }
+ }
+
+ Or(STS1,Local0,STS1)
+
+ Return(TMP1)
+ }
+
+ //
+ // Function 3: NVSG_FUNC_POWERCONTROL
+ //
+ // Allows control of dGPU power methods from the iGPU
+ //
+ If(LEqual(Arg2,3))
+ {
+ Name (TMP2, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TMP2,0,STS2)
+
+ // GPU Power Control
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(DerefOf(Index(Arg3,0)), Local0)
+ ToInteger(Arg3, Local0)
+ And(Local0, 0x3, Local0)
+
+ If(LEqual(Local0,0))
+ {
+ DGPUPCH_SCOPE.SGST()
+ }
+
+ If(LEqual(Local0,1))
+ {
+ DGPUPCH_SCOPE.SGON()
+ }
+
+ If(LEqual(Local0,2))
+ {
+ DGPUPCH_SCOPE.SGOF()
+ }
+
+ //dGPU_PWROK is not working. Using dGPU_PWR_EN# instead as w/a
+ //Or(STS2,DGPUPCH_SCOPE.MPOK,STS2)
+ If(LEqual(DGPUPCH_SCOPE.SGST(), 0xF))
+ {
+ Or(STS2,0x1,STS2)
+ }
+ //else do nothing since STS2 is already 0
+ Return(TMP2)
+ }
+
+ //
+ // Function 4: NVSG_FUNC_PLATPOLICY
+ //
+ // Sets or Returns the current System Policy settings
+ //
+ If(LEqual(Arg2,4))
+ {
+
+// common for SGCI and NBCI
+ Name (TMP3, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TMP3,0,STS3)
+
+ // Panel Scaling Preference
+
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(DerefOf(Index(Arg3,0)), Local0)
+ ToInteger(Arg3, Local0)
+ Store(Local0, Local1)
+ ShiftRight(Local0, 16, Local0)
+ And(Local0, 0x1, USPM)
+
+ ShiftRight(Local1, 13, Local1)
+ And(Local1, 0x3, Local1)
+
+
+ If(LNotEqual(Local1,GPSP))
+ {
+ If(LEqual(USPM,1))
+ {
+ Store(Local1,GPSP)
+ }
+ Else
+ {
+ // Retrieve the setting from NVS
+ Store(GPSP,Local1)
+ Or(STS3,0x8000,STS3) // Set Panel Scaling override
+ }
+ }
+ Or(STS3,ShiftLeft(Local1,13),STS3)
+
+
+ Return(TMP3)
+ }
+
+ //
+ // Function 5: NVSG_FUNC_DISPLAYSTATUS
+ //
+ // Sets or Returns the current display detection,
+ // hot-key toggle sequence
+ //
+ If(LEqual(Arg2,5))
+ {
+// common for SGCI and NBCI
+ Name (TMP4, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TMP4,0,STS4)
+
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(Derefof(Index(Arg3,0)), Local0) //Store input field in local0
+ ToInteger(Arg3, Local0)
+
+ // Next Combination Sequence
+
+ If(And(Local0,0x80000000)) //If Bit31 is set
+ {
+ Store(And(ShiftRight(Local0,25),0x1F),TLSN)
+
+ If(And(Local0,0x40000000)) //If Bit30 is set
+ {
+ Store(1,DOSF)
+ }
+ }
+
+ // Display Mask for Attached and Active Displays
+
+ If(And(Local0,0x01000000)) //If Bit24 is set
+ {
+ Store(And(ShiftRight(Local0,12),0xFFF),GACD)
+ Store(And(Local0,0xFFF),GATD)
+
+ //Get current toggle list index based on currently active display list
+ Store(CTOI(GACD),TLSN)
+ Increment(TLSN)
+
+ If(LGreater(TLSN, 13)) //For Huron River ,13 is the number of entries in the toggle list
+ {
+ Store(1, TLSN)
+ }
+
+ SNXD(TLSN) //This is optional for NV SG
+ }
+
+ // Display Hot-Plug Event/Status
+ Or(STS4,ShiftLeft(DHPE,21),STS4)
+ Or(STS4,ShiftLeft(DHPS,20),STS4)
+
+ // Toggle Sequence number
+ Or(STS4,ShiftLeft(TLSN,8),STS4)
+
+ // Dock State
+ Or(STS4,ShiftLeft(DKST,5),STS4)
+
+ // Lid Event State
+ Or(STS4,ShiftLeft(LDES,4),STS4)
+
+ // Display ACPI Event(SGCI only)
+ Or(STS4,DACE,STS4)
+
+ Store(0,LDES)
+ Store(0,DHPS)
+ Store(0,DHPE)
+ Store(0,DACE)
+
+ Return(TMP4)
+ }
+
+ //
+ // Function 6: NVSG_FUNC_MDTL - Returns Hot-Key display switch toggle sequence
+ //
+ // Returns:
+ // Returns Hot-Key display switch toggle sequence
+ //
+ If(LEqual(Arg2,6))
+ {
+// common for SGCI and NBCI
+ Return(TLPK)
+ }
+ //
+ // Function 16:
+ //
+ If(LEqual(Arg2,16))
+ {
+ CreateWordField(Arg3, 2, USRG) // Object type signature passed in by driver.
+ Name(OPVK, Buffer()
+ {
+ // Key below is for Emerald Lake Fab2 platform
+ // Customer need to ask NVIDIA PM to get the key
+ // Customer need to put the key in between labels "// key start -" and
+ // "// key end -". Please consult NVIDIA PM if any issues
+ //148597456985Genuine NVIDIA Certified Optimus Ready Motherboard for 736019_MIRc
+ // Key start -
+ 0xE4,0x42,0x5F,0x14,0x36,0x26,0x16,0x37,0x4B,0x56,0xE6,0x00,0x00,0x00,0x01,0x00,
+ 0x31,0x34,0x38,0x35,0x39,0x37,0x34,0x35,0x36,0x39,0x38,0x35,0x47,0x65,0x6E,0x75,
+ 0x69,0x6E,0x65,0x20,0x4E,0x56,0x49,0x44,0x49,0x41,0x20,0x43,0x65,0x72,0x74,0x69,
+ 0x66,0x69,0x65,0x64,0x20,0x4F,0x70,0x74,0x69,0x6D,0x75,0x73,0x20,0x52,0x65,0x61,
+ 0x64,0x79,0x20,0x4D,0x6F,0x74,0x68,0x65,0x72,0x62,0x6F,0x61,0x72,0x64,0x20,0x66,
+ 0x6F,0x72,0x20,0x37,0x33,0x36,0x30,0x31,0x39,0x5F,0x4D,0x49,0x52,0x63,0x20,0x20,
+ 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x2D,0x20,0x3C,0x34,0x27,0x21,0x58,0x29,
+ 0x57,0x27,0x58,0x20,0x27,0x25,0x59,0x5D,0x31,0x29,0x3A,0x2A,0x26,0x39,0x59,0x43,
+ 0x56,0x3B,0x58,0x56,0x58,0x3D,0x59,0x4E,0x3B,0x3A,0x35,0x44,0x25,0x42,0x5A,0x48,
+ 0x55,0x3A,0x58,0x4C,0x25,0x48,0x54,0x21,0x35,0x4B,0x4D,0x37,0x2C,0x3C,0x20,0x2D,
+ 0x20,0x43,0x6F,0x70,0x79,0x72,0x69,0x67,0x68,0x74,0x20,0x32,0x30,0x31,0x30,0x20,
+ 0x4E,0x56,0x49,0x44,0x49,0x41,0x20,0x43,0x6F,0x72,0x70,0x6F,0x72,0x61,0x74,0x69,
+ 0x6F,0x6E,0x20,0x41,0x6C,0x6C,0x20,0x52,0x69,0x67,0x68,0x74,0x73,0x20,0x52,0x65,
+ 0x73,0x65,0x72,0x76,0x65,0x64,0x2D,0x31,0x34,0x38,0x35,0x39,0x37,0x34,0x35,0x36,
+ 0x39,0x38,0x35,0x28,0x52,0x29,
+ //Copyright 2010 NVIDIA Corporation All Rights Reserved-148597456985(R)
+ // Key end -
+ })
+ If(LEqual(USRG, 0x564B)) { // 'VK' for Optimus Validation Key Object.
+ Return(OPVK)
+ }
+ Return(Zero)
+ }
+ //
+ // Function 17 NVOP_FUNC_GETALLOBJECTS
+ //
+ If(LEqual(Arg2,17))
+
+ {
+ Return(Zero)
+ }
+ //
+ // Function 18: NVSG_FUNC_GETEVENTLIST
+ //
+ // Returns:
+ // Returns list of notifiers and their meanings
+ //
+ If(LEqual(Arg2,18))
+ {
+// common for SGCI and NBCI
+ return(Package(){
+ 0xD0, ToUUID("921A2F40-0DC4-402d-AC18-B48444EF9ED2"), // Policy request
+ 0xD9, ToUUID("C12AD361-9FA9-4C74-901F-95CB0945CF3E"), // Policy set
+ 0xDB, ToUUID("42848006-8886-490E-8C72-2BDCA93A8A09"), // Display scaling
+
+ 0xEF, ToUUID("B3E485D2-3CC1-4B54-8F31-77BA2FDC9EBE"), // Policy change
+ 0xF0, ToUUID("360d6fb6-1d4e-4fa6-b848-1be33dd8ec7b"), // Display status
+
+ // unfinished list of events. we do not need this Func18 unless event notifiers differ from standard ones defined in BWG.
+ })
+ }
+ //
+ // Function 26: NVOP_FUNC_OPTIMUSCAPS
+ //
+ If(LEqual(Arg2,26))
+ {
+ // On Input
+ //Bit25-24 Power Control Enable
+ // 2-Platform should not power down GPU in the _PS3 method(default)
+ // 3-Platform should power down GPU in the _PS3 method(default)
+ // Bit0 No flag upd present in this call (SBIOS returns curent status)
+ //
+ CreateField(Arg3,24,2,OMPR)
+ CreateField(Arg3,0,1,FLCH)
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET 1:1
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET_SBIOS 0x00000000
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET_DRIVER 0x00000001
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN 2:2
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN_FALSE 0x00000000
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN_TRUE 0x00000001
+ CreateField(Arg3,One,One,DVSR)
+ CreateField(Arg3,0x02,One,DVSC)
+ If(ToInteger(FLCH))
+ {
+ Store(OMPR, DGPUPCH_SCOPE.OPCE) // Optimus Power Control Enable - From DD
+ }
+ // On return
+ // Bit 24:26 Capabilities
+ // 0: No special platf cap
+ // 1: Platform has dynamic GPU power control
+ // Bit6 GPU Display Hot Plug NEW Optimus BWG v02
+ // Bit4:3 Current GPU Control status
+ // 0: GPU is powered off
+ // 1: GPU is powered on and enabled
+ // 2: reserved
+ // 3: GPU Power has stabilized
+ // Bit0
+ // 0:Optimus Disabled
+ // 1:Optimus Enabled
+ Store(Buffer(4) {0, 0, 0, 0}, Local0)
+ CreateField(Local0,0,1,OPEN)
+ CreateField(Local0,3,2,CGCS)
+ CreateField(Local0,6,1,SHPC)
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL 8:8
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL_SBIOS 0x00000000
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL_DRIVER 0x00000001
+ CreateField(Local0,0x08,One,SNSR)
+ CreateField(Local0,24,3,DGPC) // DGPC - Default: No Dynamic GPU Power Control
+ CreateField(Local0,27,2,HDAC) // HDAC - HD Audio Codec Cap
+
+ Store(One, OPEN) // Optimus Enabled
+
+ Store(One, SHPC) // GPU Display Hotplug Supported
+ Store(0x2, HDAC) // HDA BIOS control Supported
+
+ Store(One, DGPC) // Dynamic GPU Power Control Available
+ //if (NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN is set)
+ //{
+ // GPRF = NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET
+ //}
+ //NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL = GPRF
+ If(ToInteger(DVSC))
+ {
+ If(ToInteger(DVSR))
+ {
+ Store(One, DGPUPCH_SCOPE.GPRF)
+ }
+ Else
+ {
+ Store(Zero, DGPUPCH_SCOPE.GPRF)
+ }
+ }
+ Store(DGPUPCH_SCOPE.GPRF, SNSR)
+
+
+
+ If(LNotEqual(DGPUPCH_SCOPE.SGST(), 0))
+ {
+ Store(0x3, CGCS) // Current GPU Control status
+ }
+ Return(Local0)
+
+ }//case (26)
+ //
+ // Function 27: NVOP_FUNC_OPTIMUSFLAGS
+ //
+ If(LEqual(Arg2,27))
+ {
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(Derefof(Index(Arg3,0)), Local0) //Store input field in local0
+ ToInteger(Arg3, Local0)
+// Store(Arg3, Local0)
+// CreateField(Local0,0,1,OPFL)
+// CreateField(Local0,1,1,OPVL)
+ If(And(Local0,0x00000002))
+ {
+ Store(Zero, BUFF)
+ If(And(Local0,0x00000001))
+ {
+ Store(One, BUFF)
+ }
+ }
+ And(SGFL, Not(0x2), SGFL)
+ Or(SGFL, ShiftLeft(BUFF,1), SGFL)
+ Store(SWSMI_NVOEM_CMOS_W, SSMP) // Set Audio Codec flag to CMOS
+ Return(Local0)
+ }
+ // FunctionCode or SubFunctionCode not supported
+ Return(0x80000002) // OTHER ARGUMENTS NOT SUPPORTED
+ }
+#endif // common scope for Hybrid/Nbci/Optimus
+
+ // Check for common with dGPU _DSM UUIDs
+// return (DGPUPCH_SCOPE.HDSM(Arg0, Arg1, Arg2, Arg3))
+ Return (0x80000001)
+ }
+} // end PCI0.GFX0 scope
+
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvGC6PCH.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvGC6PCH.asl
new file mode 100644
index 0000000..01d467b
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvGC6PCH.asl
@@ -0,0 +1,365 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2013, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/NvGC6PCH.asl 1 2/21/13 5:39a Joshchou $Revision:
+//
+// $Date: 2/21/13 5:39a $Log:
+//
+//
+//
+//**********************************************************************
+External(\_SB.PCI0.LPCB.H_EC, DeviceObj)
+
+External(SG_ULT_RP_NUM.LNKD)
+External(SG_ULT_RP_NUM.LNKS)
+External(DGPUPCH_SCOPE.TGPC, MethodObj)
+
+#define JT_REVISION_ID 0x00000103 // Revision number
+#define JT_FUNC_SUPPORT 0x00000000 // Function is supported?
+#define JT_FUNC_CAPS 0x00000001 // Capabilities
+#define JT_FUNC_POWERCONTROL 0x00000003 // dGPU Power Control
+#define JT_FUNC_PLATPOLICY 0x00000004 // Platform Policy
+#define JT_FUNC_DISPLAYSTATUS 0x00000005 // Query the Display Hot-Key
+#define JT_FUNC_MDTK 0x00000006 // Display Hot-Key Toggle List
+
+
+//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+//!!!!!!!Note:This Asl Code is sample code for reference,should be modified it by different board design!!!!!!!!!!
+//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+
+Scope(\_SB.PCI0.LPCB.H_EC)
+{
+ // Nvidia recommneded to use EC IO for SBIOS to communicate GC6 entry/exit to EC,
+ // Use EC RAM is polling mechanism and might cause the longer delay time for GC6 T1/T2 timing.
+ // Here we just use EC RAM for example, pleae use EC IO access for production solution.
+ OperationRegion(ECF3,EmbeddedControl,0,0xFF)
+ Field(ECF3, ByteAcc, Lock, Preserve)
+ {
+ Offset(0xF0), // assume GC6 control flags located at offset 0xE0
+ EC6I, 1, // EC flag to prepare GC6 entry
+ EC6O, 1, // EC flag to prepare GC6 exit
+ FBST, 1, // the state of FB_CLAMP
+ }
+ Mutex(GC6M, 0)
+ Method(ECNV, 1, NotSerialized)
+ {
+ Acquire(GC6M, 0xFFFF)
+ If(LEqual(Arg0, Zero))
+ {
+ Store(One, EC6I)
+ }
+ If(LEqual(Arg0, One))
+ {
+ Store(One, EC6O)
+ }
+ Release(GC6M)
+ }
+
+ Method(_Q60, 0, NotSerialized) // for GC6 entry Q-event
+ {
+ Store("------- GC6I-SCI _Q event --------", Debug)
+ CreateField(DGPUPCH_SCOPE.TGPC,0x0A,0x2,PRGE) // PRGE : PCIe Root Power GC6 Enter Sequence
+ If(LEqual(ToInteger(PRGE), 0x0)) // DAGC : Link Disable after GC6 Entry complete & before GPU Power Down
+ {
+ Store(One, SG_ULT_RP_NUM.LNKD) // PCIE link disabling.
+ }
+
+ DGPUPCH_SCOPE.SGPO(HLRS, 0) // dGPU RST# to low
+ DGPUPCH_SCOPE.SGPO(PWEN, 0) // dGPU PWN Enable to low
+
+ If(LEqual(ToInteger(PRGE), 0x2)) // DAGP : Link Disable after GC6 Entry & GPU Power down is complete
+ {
+ Store(One, SG_ULT_RP_NUM.LNKD) // PCIE link disabling.
+ }
+ }
+ Method(_Q61, 0, NotSerialized) // for GC6 exit Q-event
+ {
+ Store("------- GC6O-SCI _Q event --------",Debug)
+ }
+}
+
+Scope (DGPUPCH_SCOPE)
+{
+ Name(TGPC, Buffer(0x04)
+ {
+ 0x00
+ }
+ )
+
+ Method(GC6I, 0, Serialized)
+ {
+ Store("<<< GC6I >>>", Debug)
+ CreateField(TGPC,0x06,0x2,ECOC) // NOC: Notify on complete: Reserve
+ CreateField(TGPC,0x0A,0x2,PRGE) // PRGE : PCIe Root Power GC6 Enter Sequence
+ If(Lor(LEqual(ToInteger(PRGE), 0x3), LEqual(ToInteger(PRGE), 0x1))) // DBGS : Link Disable before GC6 Entry starts (E0)
+ {
+ Store(One, SG_ULT_RP_NUM.LNKD) // PCIE link disabling.
+ }
+ \_SB.PCI0.LPCB.H_EC.ECNV (0) // notify EC to prepare GC6 entry.
+ }
+
+ Method(GC6O, 0, Serialized)
+ {
+ Store("<<< GC6O >>>", Debug)
+ CreateField(TGPC,0x06,0x2,ECOC) // NOC: Notify on complete: Reserve
+ CreateField(TGPC,0x08,0x2,PRGX) // PRGX : PCIe Root Power GC6 Exit Sequence
+ If(LEqual(ToInteger(PRGX), Zero)) // EBPG : Link Enable before GPU Power-On & GC6 Exit begins (X0)
+ {
+ Store(Zero, SG_ULT_RP_NUM.LNKD) // PCIE link enabling
+ }
+ DGPUPCH_SCOPE.SGPO(HLRS, 0) // dGPU RST# is low
+ DGPUPCH_SCOPE.SGPO(PWEN, 1) // dGPU PWR Enable is high
+ //+ Todo - need to addd more delay to make sure all power rail is ready and stable
+ // if you have PWR_OK to check, please check PWR_OK instead of delay here
+ //....................
+ //-
+ // GC6 T5 1.5ms
+ Store(Zero, Local0) // Delay by Stall(0x32) *30 times.= 1.5ms , you can add more if you don't think 1.5ms is good enough
+ While(LLess(Local0, 0x1E))
+ {
+ Add(Local0, One, Local0)
+ Stall(0x32)
+ }
+ DGPUPCH_SCOPE.SGPO(HLRS, 1) // dGPU RST# is high
+ If(LEqual(ToInteger(PRGX), 0x3)) // EAPG : Link Enable after GPU Power-On Reset, but before GC6 Exit begins
+ {
+ Store(Zero, SG_ULT_RP_NUM.LNKD) // PCIE link enabling
+ }
+
+ // Haswell UTL has no LNKS register, please remove it from Haswell platform
+ While(LLess(SG_ULT_RP_NUM.LNKS, 0x07))
+ {
+ Sleep(One)
+ }
+ \_SB.PCI0.LPCB.H_EC.ECNV (1) // notify EC to prepare GC6 exit.
+ }
+
+ Method(GETS, 0, Serialized)
+ {
+ If(LEqual(DGPUPCH_SCOPE.SGPI(PWEN), One)) // dGPU PWR Enable is high
+ {
+ Store("<<< GETS() return 0x1 >>>", Debug)
+ Return(One)// GC6 - dGPU on
+ }
+ Else
+ {
+ If(LEqual(\_SB.PCI0.LPCB.H_EC.FBST, One)) // FB_CLAMP asserted.
+ {
+ Store("<<< GETS() return 0x3 >>>", Debug)
+ Return(0x03)// GC6 - dGPU off, FB On, w/ FB_CLAMP asserted
+ }
+ Else
+ {
+ Store("<<< GETS() return 0x2 >>>", Debug)
+ Return(0x02)// GC6 - dGPU & FB Powered off
+ }
+ }
+ }
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: NGC6
+//
+// Description: Called from _DSM -Device Specific Method for dGPU device.
+// Implement Ventura specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// Ventura DSM_GUID CBECA351-067B4924-9CBDB46B00B86F34
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (NGC6, 4, NotSerialized)
+ {
+
+ Store("------- GC6 DSM --------", Debug)
+ // Only Interface Revision 0x0100 is supported
+ If (LLess(Arg1, 0x100))
+ {
+ Return(0x80000001)
+ }
+
+ // (Arg2) Sub-Function
+ Switch (ToInteger(Arg2))
+ {
+ //
+ // Function 0:
+ //
+ case (JT_FUNC_SUPPORT)
+ {
+ Return(Buffer(0x04)
+ {
+ 0x1B, 0x00, 0x00, 0x00
+ })
+ }
+ //
+ // Function 1:
+ //
+ case (JT_FUNC_CAPS)
+ {
+
+ Name(JTB1, Buffer(0x4)
+ {
+ 0x00
+ })
+ CreateField(JTB1,Zero,One,JTEN)
+ CreateField(JTB1,One,0x02,SREN)
+ CreateField(JTB1,0x03,0x03,PLPR)
+ CreateField(JTB1,0x06,0x02,FBPR)
+ CreateField(JTB1,0x08,0x02,GUPR)
+ CreateField(JTB1,0x0A,One,GC6R)
+ CreateField(JTB1,0x0B,One,PTRH)
+ CreateField(JTB1,0x14,0x0C,JTRV)
+ Store(One, JTEN) // JT enable
+ Store(One, GC6R) // GC6 integrated ROM
+ Store(One, PTRH) // No SMI Handler
+ Store(One, SREN) // Disable NVSR
+ Store(JT_REVISION_ID, JTRV) // JT rev
+
+ Return(JTB1)
+ }
+ //
+ // Function 2:
+ //
+ case(0x00000002)
+ {
+ Store("GPS fun 19", Debug)
+ return(arg3)
+ }
+ //
+ // Function 3:
+ //
+ case(0x00000003)
+ {
+ CreateField(Arg3,Zero,0x03,GUPC)
+ CreateField(Arg3,0x04,One,PLPC)
+ Name(JTB3, Buffer(0x04)
+ {
+ 0x00
+ })
+ CreateField(JTB3,Zero,0x03,GUPS)
+ CreateField(JTB3,0x03,One,GPGS) // dGPU Power status
+ CreateField(JTB3,0x07,One,PLST)
+ If(LEqual(ToInteger(GUPC), One)) // EGNS
+ {
+ Store(Arg3,TGPC) // Store GC6 control input for GC6I GC6O
+ GC6I()
+ Store(One, PLST)
+ }
+ Else
+ {
+ If(LEqual(ToInteger(GUPC), 0x02)) // EGIS
+ {
+ Store(Arg3,TGPC) // Store GC6 control input for GC6I GC6O
+ GC6I()
+ If(LEqual(ToInteger(PLPC), Zero))
+ {
+ Store(Zero, PLST)
+ }
+ }
+ Else
+ {
+ If(LEqual(ToInteger(GUPC), 0x03)) // XGXS
+ {
+ Store(Arg3,TGPC) // Store GC6 control input for GC6I GC6O
+ GC6O()
+ If(LNotEqual(ToInteger(PLPC), Zero))
+ {
+ Store(Zero, PLST)
+ }
+ }
+ Else
+ {
+ If(LEqual(ToInteger(GUPC), 0x04)) // XGIS
+ {
+ Store(Arg3,TGPC) // Store GC6 control input for GC6I GC6O
+ GC6O()
+ If(LNotEqual(ToInteger(PLPC), Zero))
+ {
+ Store(Zero, PLST)
+ }
+ }
+ Else
+ {
+ If(LEqual(ToInteger(GUPC), Zero))
+ {
+ Store(GETS(), GUPS)
+ If(LEqual(ToInteger(GUPS), 0x01))
+ {
+ Store(One, GPGS) // dGPU power status is Power OK
+ }
+ Else
+ {
+ Store(Zero, GPGS) // dGPU power status is Power off
+ }
+ }
+ Else
+ {
+ If(LEqual(ToInteger(GUPC), 0x6)) // XLCM
+ {
+ //+ De-assert FB_CLAMP
+
+ //-
+ }
+ }
+ }
+ }
+ }
+ }
+ Return(JTB3)
+ }
+ //
+ // Function 4:
+ //
+ case(JT_FUNC_PLATPOLICY)
+ {
+ Return(0x80000002)
+ }
+
+ } // end of switch
+
+ Return(0x80000002)
+ } // end NGC6
+
+
+} // end DGPUPCH_SCOPE scope
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2013, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvGPSPCH.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvGPSPCH.asl
new file mode 100644
index 0000000..fc6fd14
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvGPSPCH.asl
@@ -0,0 +1,331 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/NvGPSPCH.asl 1 1/15/13 6:03a Joshchou $
+//
+// $Revision: 1 $
+//
+// $Date: 1/15/13 6:03a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/NvGPSPCH.asl $
+//
+// 1 1/15/13 6:03a Joshchou
+// [TAG] EIP107237
+// [Category] Improvement
+// [Description] Create componet for SG support on PCH
+// [Files] SgUltNvidia.cif
+// NVdGPUPCH.asl
+// NViGPUPCH.asl
+// NViGDmiscPCH.asl
+// OpSSDTPCH.asl
+// NvVenturaPCH.asl
+// NvGPSPCH.asl
+// NvSSDTPCH.asl
+//
+// 2 4/11/12 3:52a Alanlin
+// [TAG] EIP82808
+// [Category] Improvement
+// [Description] nVidia GPS function improvement.
+// [Files] Board\EM\SgTpv\AcpiTables\SgTpvAcpiTables.sdl
+// Board\EM\SgTpv\AcpiTables\NvGPS.asl
+// Board\EM\SgTpv\AcpiTables\NViGPU.asl
+//
+// 1 10/14/11 2:56a Alanlin
+//
+//
+//**********************************************************************
+External(\_PR.CPU0._PSS, BuffObj)
+
+External(\_PR.CPU0._PPC, IntObj)
+External(\_PR.CPU1._PPC, IntObj)
+External(\_PR.CPU2._PPC, IntObj)
+External(\_PR.CPU3._PPC, IntObj)
+External(\_PR.CPU4._PPC, IntObj)
+External(\_PR.CPU5._PPC, IntObj)
+External(\_PR.CPU6._PPC, IntObj)
+External(\_PR.CPU7._PPC, IntObj)
+External(\_SB.PCI0.LPCB.H_EC.GTVR) // CPU GT VR (IMVP) Temperature
+External(\_PR.CPU0._TSS, MethodObj)
+External(\_PR.CPU0._PTC, MethodObj)
+
+#define GPS_REVISION_ID 0x00000100 // Revision number
+#define GPS_ERROR_SUCCESS 0x00000000 // Generic Success
+#define GPS_ERROR_UNSPECIFIED 0x00000001 // Generic unspecified error code
+#define GPS_ERROR_UNSUPPORTED 0x00000002 // Sub-Function not supported
+
+#define GPS_FUNC_SUPPORT 0x00000000 // Bit list of supported functions
+#define GPS_FUNC_GETCALLBACKS 0x00000013 // Get system requested callback
+#define GPS_FUNC_PSHARESTATUS 0x00000020 // Get system requested Power Steering Setting
+#define GPS_FUNC_GETPSS 0x00000021 // Get _PSS object
+#define GPS_FUNC_SETPPC 0x00000022 // Set _PCC object
+#define GPS_FUNC_GETPPC 0x00000023 // Get _PCC object
+#define GPS_FUNC_PSHAREPARAMS 0x0000002A // Get sensor information and capabilities
+
+Scope(PCI_SCOPE){
+
+ Name(GPS, "GPSACPI 2012-Aug-12 14:56:05") // MCPACPIP build time stamp.
+
+} // end of Scope
+
+Scope (DGPUPCH_SCOPE)
+{
+
+Name(PSAP, Zero)
+ Name(ECBF, Buffer(20) {})
+ CreateDWordField(ECBF, 0, EDS1)
+ CreateDWordField(ECBF, 4, EDS2)
+ CreateDWordField(ECBF, 8, EDS3)
+ CreateDWordField(ECBF, 12, EDS4)
+ CreateDWordField(ECBF, 16, EPDT)
+
+ Name(GPSP, Buffer(36) {})
+ CreateDWordField(GPSP, 0, RETN)
+ CreateDWordField(GPSP, 4, VRV1)
+ CreateDWordField(GPSP, 8, TGPU)
+ CreateDWordField(GPSP, 12, PDTS)
+ CreateDWordField(GPSP, 16, SFAN)
+ CreateDWordField(GPSP, 20, SKNT)
+ CreateDWordField(GPSP, 24, CPUE)
+ CreateDWordField(GPSP, 28, TMP1)
+ CreateDWordField(GPSP, 32, TMP2)
+
+Name(NLIM, 0) //set one flag for GPS_EVENT_STATUS_CHANGE 1: will update parameter: 0 just call function 0x1c _PCONTROL
+
+ Name(PSCP, 0) // P-State capacity, mainly for s/w debugging
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: GPS
+//
+// Description: Called from _DSM -Device Specific Method for dGPU device.
+// Implement Ventura specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// Ventura DSM_GUID A3132D01-8CDA-49BA-A52E-BC9D46DF6B81
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (GPS, 4, NotSerialized)
+ {
+
+ Store("------- GPS DSM --------", Debug)
+ // Only Interface Revision 0x0100 is supported
+ If (LNotEqual(Arg1, 0x100))
+ {
+ Return(0x80000002)
+ }
+
+ P8DB(0xDD, Arg2, 1000)
+ // (Arg2) Sub-Function
+ Switch (ToInteger(Arg2))
+ {
+
+ case (GPS_FUNC_SUPPORT)
+ {
+
+ Name(FMSK, Buffer(0x8)
+ {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ })
+ Store(Buffer(0x8)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }, Local0)
+ Divide(GPS_FUNC_SUPPORT, 0x8, Local2, Local1)
+ // Local1 is Quotient, Local2 is Remainder
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_GETCALLBACKS, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_PSHARESTATUS, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_GETPSS, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_SETPPC, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_GETPPC, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_PSHAREPARAMS, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+
+ // mask out specific functions
+ Store( SizeOf(Local0), Local1)
+ While( LNotEqual(Local1, 0) ) {
+ Decrement(Local1)
+ Store( DeRefOf(Index(FMSK, Local1)), Local2)
+ And( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1) )
+ }
+
+ Return(Local0)
+ }
+ //
+ // Function 19: GPS_FUNC_GETCALLBACKS,
+ //
+ case(GPS_FUNC_GETCALLBACKS)
+ {
+ Store("GPS fun 19", Debug)
+ return(arg3)
+ }
+ //
+ // Function 32: GPS_FUNC_PSHARESTATUS,
+ //
+ case(GPS_FUNC_PSHARESTATUS)
+ {
+ Store("GPS fun 20", Debug)
+
+ Name(RET1, Zero)
+ CreateBitField(Arg3,24,NRIT) //new request new IGP turbo state(bit 24 is valid)
+ CreateBitField(Arg3,25,NRIS) //request new IGP turbo state
+ if (NRIS){
+ if(NRIT){
+ Or(RET1, 0x01000000, RET1)
+ }else
+ {
+ //help disable IGP turbo boost
+ And(RET1, 0xFeFFFFFF, RET1)
+ }
+ }
+ Or(RET1, 0x40000000, RET1) // if this machine support GPS
+
+ if(NLIM){
+ Or(RET1, 0x00000001, RET1) // if NLIM falg is set, set bit0 =1
+ }
+
+ Return(RET1)
+ }
+ //
+ // Function 33: GPS_FUNC_GETPSS, Get CPU _PSS structure
+ //
+ case(GPS_FUNC_GETPSS)
+ {
+ Return(\_PR.CPU0._PSS)
+ }
+ //
+ // Function 34: GPS_FUNC_SETPPC, Set current CPU _PPC limit
+ //
+ case(GPS_FUNC_SETPPC)
+ {
+ CreateBYTEField(Arg3, 0, PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU0, 0x80)
+ store(PCAP, PSAP)
+ Return(PCAP)
+ }
+ //
+ // Function 35: GPS_FUNC_GETPPC, Get current CPU _PPC limit
+ //
+ case(GPS_FUNC_GETPPC)
+ {
+ Return(PSAP)
+ }
+
+ case(0x25)
+ {
+ Store("GPS fun 25", Debug)
+ return(\_PR_.CPU0._TSS)
+ }
+ case(0x26)
+ {
+ Store("GPS fun 26", Debug)
+ CreateDWordField(Arg3, Zero, TCAP)
+ Store(TCAP, \_PR_.CPU0._PTC)
+ Notify(\_PR_.CPU0, 0x80)
+ return(TCAP) }
+ //
+ // Function 42: GPS_FUNC_PSHAREPARAMS, Get Power Steering platform parameters
+ //
+ case(GPS_FUNC_PSHAREPARAMS)
+ {
+ Store("GPS fun 2a", Debug)
+
+ CreateBYTEField(Arg3,0,PSH0)
+ CreateBYTEField(Arg3,1,PSH1)
+ CreateBitField(Arg3,8,GPUT)
+ CreateBitField(Arg3,9,CPUT)
+ CreateBitField(Arg3,10,FANS)
+ CreateBitField(Arg3,11,SKIN)
+ CreateBitField(Arg3,12,ENGR)
+ CreateBitField(Arg3,13,SEN1)
+ CreateBitField(Arg3,14,SEN2)
+
+ switch (PSH0){
+ case(0){
+ if(CPUT){
+ store(0x00000200, RETN)
+ Or(RETN, PSH0, RETN)
+ // Please return CPU or EC tempture to PDTS
+ store(\_SB.PCI0.LPCB.H_EC.GTVR,PDTS)
+ }
+ return(GPSP)
+ } //case(0)
+
+ case(1){
+ store(0x00000300, RETN) //need to return CPU and GPU status bits for Querytype1
+ Or(RETN, PSH0, RETN)
+ store(1000,PDTS)
+ return(GPSP)
+ } //case(1)
+
+ case(2){
+ store(0x0102, RETN) //RETN[0:3] need to be the same as input argument, bit8 is GPU temp status bit
+ store(0x00000000, VRV1)
+ store(0x00000000, TGPU)
+ store(0x00000000, PDTS)
+ store(0x00000000, SFAN)
+ store(0x00000000, CPUE)
+ store(0x00000000, SKNT)
+ store(0x00000000, TMP1)
+ store(0x00000000, TMP2)
+ return(GPSP)
+ } //case(2)
+ } // PSH0 of switch
+
+ }
+ } // end of switch
+
+ Return(0x80000002)
+ } // end GPS
+
+
+} // end DGPUPCH_SCOPE scope
+
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvSSDTPCH.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvSSDTPCH.asl
new file mode 100644
index 0000000..a4d8fc3
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvSSDTPCH.asl
@@ -0,0 +1,365 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/NvSSDTPCH.asl 2 2/21/13 5:42a Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 2/21/13 5:42a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/NvSSDTPCH.asl $
+//
+// 2 2/21/13 5:42a Joshchou
+// [TAG] EIP106524
+// [Category] New Feature
+// [Description] Support GC6 function for Optimus
+//
+// 1 1/15/13 6:03a Joshchou
+// [TAG] EIP107237
+// [Category] Improvement
+// [Description] Create componet for SG support on PCH
+// [Files] SgUltNvidia.cif
+// NVdGPUPCH.asl
+// NViGPUPCH.asl
+// NViGDmiscPCH.asl
+// OpSSDTPCH.asl
+// NvVenturaPCH.asl
+// NvGPSPCH.asl
+// NvSSDTPCH.asl
+//
+// 5 12/22/11 6:31a Alanlin
+// Declared "defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)"
+//
+//
+// 3 12/02/11 12:38a Alanlin
+// [TAG] EIP75359
+// [Category] Improvement
+// [Description] Report _STA asl method to PCIe root port for nVidia
+// GPU.
+//
+// 2 10/14/11 2:59a Alanlin
+// [TAG] EIP64451
+// [Category] New Feature
+// [Description] Optimus GPS feature update
+// [Files] NvSSDT.asl
+// NViGPU.asl
+// OpSSDT.asl
+// NvGPS.asl
+// SgNvidia.cif
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+//
+//
+// 5 3/17/11 6:17p Alexp
+// Optimus:Add code to preserve HD AudioCodec enable flag in CMOS
+//
+// 4 11/12/10 1:25p Alexp
+// rename ELCT to ELCL in order to avoid name conflict with Intel's ref
+// code in SgDGPU.asl
+//
+// 3 10/06/10 3:34p Alexp
+// Include defines for different Nvidia GUID functions. Helps to control
+// inclusion of peices of ASL depending on type of desired SG mode
+//
+// 2 10/05/10 7:14p Alexp
+// 1. Added debug macro to be able to insert check points in target ASL
+// code
+// 2. Reuse NVdGPU.asl file to build OpSSDT for Optimus and NvSSDT for
+// MUXed SG targets.
+// NvOptimus.asl no longer required
+//
+// 1 9/17/10 1:21p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgNvidia.cif;
+// NvSSDT.asl; NVdGPU.asl;NViGPU.asl;NViGDmisc
+// OpSSDT.asl;NvOptimus.asl;NvVenture.asl
+//
+//
+//**********************************************************************
+
+DefinitionBlock (
+ "Nvidia.aml",
+ "SSDT",
+ 1,
+ "NvdRef",
+ "NvdTabl",
+ 0x1000
+ ) {
+
+#define HYBRID_DSM_GUID 1
+#define MXM_DSM_GUID 1
+//#define NBCI_DSM_GUID 1
+
+External(P8XH, MethodObj)
+
+#if defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)
+#define P8DB(arg0, arg1, arg2) P8XH (0, arg1) P8XH (1, arg0) sleep(arg2)
+#else
+#define P8DB(arg0, arg1, arg2)
+#endif
+
+External(PCI_SCOPE, DeviceObj)
+External(SG_ULT_RP_NUM, DeviceObj)
+External(DGPUPCH_SCOPE, DeviceObj)
+External(IGPU_SCOPE, DeviceObj)
+External(DGPUPCH_SCOPE._ADR, DeviceObj)
+External(IGPU_SCOPE._DSM, MethodObj)
+External(DGPUPCH_SCOPE.SGST, MethodObj)
+External(DGPUPCH_SCOPE.SGON, MethodObj)
+External(DGPUPCH_SCOPE.SGOF, MethodObj)
+External(DGPUPCH_SCOPE.SGPI, MethodObj)
+External(DGPUPCH_SCOPE.SGPO, MethodObj)
+External(\DSEL)
+External(\ESEL)
+External(\SSEL)
+External(\PSEL)
+External(\HLRS)
+External(\PWEN)
+External(\SGMD)
+External(\SGFL)
+External(\SSMP)
+External(\PWOK)
+
+#include <NVdGPUPCH.ASL> // Include DGPU device namespace
+#include <NViGPUPCH.ASL> // Include NVHG DSM calls
+#include <NViGDmiscPCH.ASL> // Include misc event callback methods
+#if NV_VENTURA_SUPPORT == 1
+#include <NvVenturaPCH.ASL> // Include Ventura support
+#endif
+#if NV_GPS_SUPPORT == 1
+#include <NvGPSPCH.ASL> // Include GPS support
+#endif
+
+#if NV_GC6_SUPPORT == 1
+#include <NvGC6PCH.ASL> // Include GC6 support
+#endif
+
+Scope(SG_ULT_RP_NUM)
+{
+ Method(_STA,0,Serialized)
+ {
+ Return(0x000F)
+ }
+}
+Scope(PCI_SCOPE)
+{
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: WMI1
+//
+// Description: WMI MXM Mapper. ASL Device is used to acccess Mxm native method via WMI API
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Device(WMI1) // placed within PCI Bus scope parallel to iGPU
+ {
+ Name(_HID, "PNP0C14")
+ Name(_UID, "MXM2")
+
+ Name(_WDG, Buffer()
+ {
+ // Methods GUID {F6CB5C3C-9CAE-4ebd-B577-931EA32A2CC0}
+ 0x3C, 0x5C, 0xCB, 0xF6, 0xAE, 0x9C, 0xbd, 0x4e, 0xB5, 0x77, 0x93, 0x1E,
+ 0xA3, 0x2A, 0x2C, 0xC0,
+ 0x4D, 0x58, // Object ID "MX" = method "WMMX"
+ 1, // Instance Count
+ 0x02, // Flags (WMIACPI_REGFLAG_METHOD)
+
+ // NVHG_NOTIFY_POLICYCHANGE
+ // WMI Notify - Hybrid Policy Request D0
+ // GUID {921A2F40-0DC4-402d-AC18-B48444EF9ED2}
+ 0x40, 0x2F, 0x1A, 0x92, 0xC4, 0x0D, 0x2D, 0x40, 0xAC, 0x18, 0xB4, 0x84, 0x44, 0xEF, 0x9E, 0xD2,
+ 0xD0, 0x00, 0x01, 0x08,
+
+ // NVHG_NOTIFY_POLICYSET
+ // WMI Notify D9 - Hybrid Policy Set
+ // GUID {C12AD361-9FA9-4C74-901F-95CB0945CF3E}
+ 0x61, 0xD3, 0x2A, 0xC1, 0xA9, 0x9F, 0x74, 0x4C, 0x90, 0x1F, 0x95, 0xCB, 0x09, 0x45, 0xCF, 0x3E,
+ 0xD9, 0x00, 0x01, 0x08,
+
+ // NVHG_DISPLAY_SCALING
+ // Notify event DB - Display scaling change
+ // GUID {42848006-8886-490E-8C72-2BDCA93A8A09}
+ 0x06, 0x80, 0x84, 0x42, 0x86, 0x88, 0x0E, 0x49, 0x8C, 0x72, 0x2B, 0xDC, 0xA9, 0x3A, 0x8A, 0x09,
+ 0xDB, 0x00, 0x01, 0x08,
+
+ // NVHG_DISPLAY_HOTKEY, ACPI_NOTIFY_PANEL_SWITCH GUID
+ // Notify event 80 (fixed) - Hot-Key, use _DGS, _DCS etc.
+ // GUID {E06BDE62-EE75-48F4-A583-B23E69ABF891}
+ 0x62, 0xDE, 0x6B, 0xE0, 0x75, 0xEE, 0xF4, 0x48, 0xA5, 0x83, 0xB2, 0x3E, 0x69, 0xAB, 0xFB, 0x91,
+ 0x80, 0x00, 0x01, 0x08,
+
+ // NVHG_DISPLAY_HOTplug, ACPI_NOTIFY_DEVICE_HOTPLUG
+ // Notify event 81 (fixed) - Hot-Plug, query _DCS
+ // GUID {3ADEBD0F-0C5F-46ED-AB2E-04962B4FDCBC}
+ 0x0F, 0xBD, 0xDe, 0x3A, 0x5F, 0x0C, 0xED, 0x46, 0xAB, 0x2E, 0x04, 0x96, 0x2B, 0x4F, 0xDC, 0xBC,
+ 0x81, 0x00, 0x01, 0x08,
+
+ // NVHG_BRIGHTNESS_INC, ACPI_NOTIFY_INC_BRIGHTNESS_HOTKEY
+ // Notify event 86 (fixed) - Backlight Increase
+ // GUID {1E519311-3E75-4208-B05E-EBE17E3FF41F}
+ 0x11, 0x93, 0x51, 0x1E, 0x75, 0x3E, 0x08, 0x42, 0xB0, 0x5E, 0xEB, 0xE1, 0x7E, 0x3F, 0xF4, 0x1F,
+ 0x86, 0x00, 0x01, 0x08,
+
+ // NVHG_BRIGHTNESS_DEC, ACPI_NOTIFY_DEC_BRIGHTNESS_HOTKEY
+ // Notify event 87 (fixed) - Backlight Decrease
+ // GUID {37F85341-4418-4F24-8533-38FFC7295542}
+ 0x41, 0x53, 0xF8, 0x37, 0x18, 0x44, 0x24, 0x4F, 0x85, 0x33, 0x38, 0xFF, 0xC7, 0x29, 0x55, 0x42,
+ 0x87, 0x00, 0x01, 0x08,
+
+ // MOF data {05901221-D566-11d1-B2F0-00A0C9062910}
+ 0x21, 0x12, 0x90, 0x05, 0x66, 0xd5, 0xd1, 0x11, 0xb2, 0xf0,
+ 0x00, 0xa0, 0xc9, 0x06, 0x29, 0x10,
+ 0x58, 0x4D, // Object ID "XM"
+ 1, // Instance Count = 1
+ 0x00 // Flags
+ }
+ ) // End of _WDG
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: WMMX
+//
+// Description: WMI Method execution tunnel. MXM Native methods are called via WMMX index.
+//
+// Input:
+// Arg1: Integer GPU index. 0x10-iGPU, 0x0-0xf - dGPU
+//
+// Output:
+// Buffer specific to the funcion being called
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(WMMX, 3)
+ {
+
+ //Arg1 = 0x10 indicates iGPU, 0x0~0x0F for dgpu
+ CreateDwordField(Arg2, 0, FUNC) // Get the function name
+ If (LEqual(FUNC, 0x4D53445F)) // "_DSM"
+ {
+ If (LGreaterEqual(SizeOf(Arg2), 28))
+ {
+ CreateField(Arg2, 0, 128, MUID)
+ CreateDwordField(Arg2, 16, REVI)
+ CreateDwordField(Arg2, 20, SFNC)
+ CreateField(Arg2, 0xe0, 0x20, XRG0)
+
+ If(LNotEqual(Arg1,0x10))
+ {
+ If (CondRefOf(IGPU_SCOPE._DSM)) // common with dGPU DSM functions
+ {
+ Return(IGPU_SCOPE._DSM(MUID, REVI, SFNC, XRG0))
+ }
+ }
+ }
+ }
+
+ ElseIf (LEqual(FUNC, 0x584D584D)) // "MXMX"
+ {
+ CreateDWordField(Arg2, 8, XRG1)
+ If (LEqual(Arg1, 0x10))
+ {
+ Return(IGPU_SCOPE.MXMX(XRG1))
+ }
+ Else
+ {
+ Return(DGPUPCH_SCOPE.MXMX(XRG1))
+ }
+ }
+
+ ElseIf (LEqual(FUNC, 0x5344584D)) // "MXDS"
+ {
+ CreateDWordField(Arg2, 8, XRG2)
+ If (LEqual(Arg1, 0x10))
+ {
+ Return(IGPU_SCOPE.MXDS(XRG2))
+ }
+ Else
+ {
+ Return(DGPUPCH_SCOPE.MXDS(XRG2))
+ }
+ }
+ Return(0)
+ } // End of WMMX
+
+ Name(WQXM, Buffer()
+ {
+ 0x46,0x4F,0x4D,0x42,0x01,0x00,0x00,0x00,0x8B,0x02,0x00,0x00,0x0C,0x08,0x00,0x00,
+ 0x44,0x53,0x00,0x01,0x1A,0x7D,0xDA,0x54,0x18,0xD2,0x83,0x00,0x01,0x06,0x18,0x42,
+ 0x10,0x05,0x10,0x8A,0xE6,0x80,0x42,0x04,0x92,0x43,0xA4,0x30,0x30,0x28,0x0B,0x20,
+ 0x86,0x90,0x0B,0x26,0x26,0x40,0x04,0x84,0xBC,0x0A,0xB0,0x29,0xC0,0x24,0x88,0xFA,
+ 0xF7,0x87,0x28,0x09,0x0E,0x25,0x04,0x42,0x12,0x05,0x98,0x17,0xA0,0x5B,0x80,0x61,
+ 0x01,0xB6,0x05,0x98,0x16,0xE0,0x18,0x92,0x4A,0x03,0xA7,0x04,0x96,0x02,0x21,0xA1,
+ 0x02,0x94,0x0B,0xF0,0x2D,0x40,0x3B,0xA2,0x24,0x0B,0xB0,0x0C,0x23,0x02,0x8F,0x82,
+ 0xA1,0x71,0x68,0xEC,0x30,0x2C,0x13,0x4C,0x83,0x38,0x8C,0xB2,0x91,0x45,0x60,0xDC,
+ 0x4E,0x05,0xC8,0x15,0x20,0x4C,0x80,0x78,0x54,0x61,0x34,0x07,0x45,0xE0,0x42,0x63,
+ 0x64,0x40,0xC8,0xA3,0x00,0xAB,0xA3,0xD0,0xA4,0x12,0xD8,0xBD,0x00,0x8D,0x02,0xB4,
+ 0x09,0x70,0x28,0x40,0xA1,0x00,0x6B,0x18,0x72,0x06,0x21,0x5B,0xD8,0xC2,0x68,0x50,
+ 0x80,0x45,0x14,0x8D,0xE0,0x2C,0x2A,0x9E,0x93,0x50,0x02,0xDA,0x1B,0x82,0xF0,0x8C,
+ 0xD9,0x18,0x9E,0x10,0x83,0x54,0x86,0x21,0x88,0xB8,0x11,0x8E,0xA5,0xFD,0x41,0x10,
+ 0xF9,0xAB,0xD7,0xB8,0x1D,0x69,0x34,0xA8,0xB1,0x26,0x38,0x76,0x8F,0xE6,0x84,0x3B,
+ 0x17,0x20,0x7D,0x6E,0x02,0x39,0xBA,0xD3,0xA8,0x73,0xD0,0x64,0x78,0x0C,0x2B,0xC1,
+ 0x7F,0x80,0x4F,0x01,0x78,0xD7,0x80,0x9A,0xFE,0xC1,0x33,0x41,0x70,0xA8,0x21,0x7A,
+ 0xD4,0xE1,0x4E,0xE0,0xBC,0x8E,0x84,0x41,0x1C,0xD1,0x71,0x63,0x67,0x75,0x32,0x07,
+ 0x5D,0xAA,0x00,0xB3,0x07,0x00,0x0D,0x2E,0xC1,0x69,0x9F,0x49,0xE8,0xF7,0x80,0xF3,
+ 0xE9,0x79,0x6C,0x6C,0x10,0xA8,0x91,0xF9,0xFF,0x0F,0xED,0x41,0x9E,0x56,0xCC,0x90,
+ 0xCF,0x02,0x87,0xC5,0xC4,0x1E,0x19,0xE8,0x78,0xC0,0x7F,0x00,0x78,0x34,0x88,0xF0,
+ 0x66,0xE0,0xF9,0x9A,0x60,0x50,0x08,0x39,0x19,0x0F,0x4A,0xCC,0xF9,0x80,0xCC,0x25,
+ 0xC4,0x43,0xC0,0x31,0xC4,0x08,0x7A,0x46,0x45,0x23,0x6B,0x22,0x3E,0x03,0x78,0xDC,
+ 0x96,0x05,0x42,0x09,0x0C,0xEC,0x73,0xC3,0x3B,0x84,0x61,0x71,0xA3,0x09,0xEC,0xF3,
+ 0x85,0x05,0x0E,0x0A,0x05,0xEB,0xBB,0x42,0xCC,0xE7,0x81,0xE3,0x3C,0x60,0x0B,0x9F,
+ 0x28,0x01,0x3E,0x24,0x8F,0x06,0xDE,0x20,0xE1,0x5B,0x3F,0x02,0x10,0xE0,0x27,0x06,
+ 0x13,0x58,0x1E,0x30,0x7A,0x94,0xF6,0x2B,0x00,0x21,0xF8,0x8B,0xC5,0x53,0xC0,0xEB,
+ 0x40,0x84,0x63,0x81,0x29,0x72,0x6C,0x68,0x78,0x7E,0x70,0x88,0x1E,0xF5,0x5C,0xC2,
+ 0x1F,0x4D,0x94,0x53,0x38,0x1C,0x1F,0x39,0x8C,0x10,0xFE,0x49,0xE3,0xC9,0xC3,0x9A,
+ 0xEF,0x00,0x9A,0xD2,0x5B,0xC0,0xFB,0x83,0x47,0x80,0x11,0x20,0xE1,0x68,0x82,0x89,
+ 0x7C,0x3A,0x01,0xD5,0xFF,0xFF,0x74,0x02,0xB8,0xBA,0x01,0x14,0x37,0x6A,0x9D,0x49,
+ 0x7C,0x2C,0xF1,0xAD,0xE4,0xBC,0x43,0xC5,0x7F,0x93,0x78,0x3A,0xF1,0x34,0x1E,0x4C,
+ 0x42,0x44,0x89,0x18,0x21,0xA2,0xEF,0x27,0x46,0x08,0x15,0x31,0x6C,0xA4,0x37,0x80,
+ 0xE7,0x13,0xE3,0x84,0x08,0xF4,0x74,0xC2,0x42,0x3E,0x34,0xA4,0xE1,0x74,0x02,0x50,
+ 0xE0,0xFF,0x7F,0x3A,0x81,0x1F,0xF5,0x74,0x82,0x1E,0xAE,0x4F,0x19,0x18,0xE4,0x03,
+ 0xF2,0xA9,0xC3,0xF7,0x1F,0x13,0xF8,0x78,0xC2,0x45,0x1D,0x4F,0x50,0xA7,0x07,0x1F,
+ 0x4F,0xD8,0x19,0xE1,0x2C,0x1E,0x03,0x7C,0x3A,0xC1,0xDC,0x13,0x7C,0x3A,0x01,0xDB,
+ 0x68,0x60,0x1C,0x4F,0xC0,0x77,0x74,0xC1,0x1D,0x4F,0xC0,0x30,0x18,0x18,0xE7,0x13,
+ 0xE0,0x31,0x5E,0xDC,0x31,0xC0,0x43,0xE0,0x03,0x78,0xDC,0x38,0x3D,0x2B,0x9D,0x14,
+ 0xF2,0x24,0xC2,0x07,0x85,0x39,0xB0,0xE0,0x14,0xDA,0xF4,0xA9,0xD1,0xA8,0x55,0x83,
+ 0x32,0x35,0xCA,0x34,0xA8,0xD5,0xA7,0x52,0x63,0xC6,0xCE,0x19,0x0E,0xF8,0x10,0xD0,
+ 0x89,0xC0,0xF2,0x9E,0x0D,0x02,0xB1,0x0C,0x0A,0x81,0x58,0xFA,0xAB,0x45,0x20,0x0E,
+ 0x0E,0xA2,0xFF,0x3F,0x88,0x23,0xD2,0x0A,0xC4,0xFF,0x7F,0x7F
+ }
+ ) // End of WQXM
+ } // End of WMI1 Device
+ } // end scope PCI0
+} // end SSDT
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvVenturaPCH.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvVenturaPCH.asl
new file mode 100644
index 0000000..f89191e
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/NvVenturaPCH.asl
@@ -0,0 +1,521 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/NvVenturaPCH.asl 1 1/15/13 6:03a Joshchou $
+//
+// $Revision: 1 $
+//
+// $Date: 1/15/13 6:03a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/NvVenturaPCH.asl $
+//
+// 1 1/15/13 6:03a Joshchou
+// [TAG] EIP107237
+// [Category] Improvement
+// [Description] Create componet for SG support on PCH
+// [Files] SgUltNvidia.cif
+// NVdGPUPCH.asl
+// NViGPUPCH.asl
+// NViGDmiscPCH.asl
+// OpSSDTPCH.asl
+// NvVenturaPCH.asl
+// NvGPSPCH.asl
+// NvSSDTPCH.asl
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+//
+
+//
+// 2 10/05/10 7:14p Alexp
+// 1. Added debug macro to be able to insert check points in target ASL
+// code
+// 2. Reuse NVdGPU.asl file to build OpSSDT for Optimus and NvSSDT for
+// MUXed SG targets.
+// NvOptimus.asl no longer required
+//
+// 1 9/17/10 1:21p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgNvidia.cif;
+// NvSSDT.asl; NVdGPU.asl;NViGPU.asl;NViGDmisc
+// OpSSDT.asl;NvOptimus.asl;NvVenture.asl
+//
+// 1 6/08/10 3:45p Alexp
+//
+//**********************************************************************
+// (Ventura+)>
+EXTERNAL(\_PR.CPU0, DeviceObj)
+EXTERNAL(\_PR.CPU1, DeviceObj)
+EXTERNAL(\_PR.CPU2, DeviceObj)
+EXTERNAL(\_PR.CPU3, DeviceObj)
+//> Andy+ for ClarksField -- 8 processors
+EXTERNAL(\_PR.CPU4, DeviceObj)
+EXTERNAL(\_PR.CPU5, DeviceObj)
+EXTERNAL(\_PR.CPU6, DeviceObj)
+EXTERNAL(\_PR.CPU7, DeviceObj)
+//<
+External(\_PR.CPU0._PSS, BuffObj)
+External(\_PR.CPU0._TSS, BuffObj)
+
+External(\_PR.CPU0._PPC, IntObj)
+External(\_PR.CPU1._PPC, IntObj)
+External(\_PR.CPU2._PPC, IntObj)
+External(\_PR.CPU3._PPC, IntObj)
+//> Andy+ for ClarksField -- 8 processors
+External(\_PR.CPU4._PPC, IntObj)
+External(\_PR.CPU5._PPC, IntObj)
+External(\_PR.CPU6._PPC, IntObj)
+External(\_PR.CPU7._PPC, IntObj)
+//<
+External(\_PR.CPU0._TPC, IntObj)
+External(\_PR.CPU1._TPC, IntObj)
+External(\_PR.CPU2._TPC, IntObj)
+External(\_PR.CPU3._TPC, IntObj)
+//> Andy+ for ClarksField -- 8 processors
+External(\_PR.CPU4._TPC, IntObj)
+External(\_PR.CPU5._TPC, IntObj)
+External(\_PR.CPU6._TPC, IntObj)
+External(\_PR.CPU7._TPC, IntObj)
+//<
+Scope(PCI_SCOPE){
+
+ Name(VEN, "VENACPI 2009-Nov-23 14:56:05") // MCPACPIP build time stamp.
+
+} // end of Scope
+
+Scope (DGPUPCH_SCOPE)
+{
+ // value used to notify iGPU
+
+ Name(VSTS, 1) // Ventura Status
+ Name(THBG, 50000) // Thermal Budget
+ Name(PSCP, 0) // P-State capacity, mainly for s/w debugging
+ Name(TBUD, 0x88B8) // Thermal Budget
+// Name(PBCM, 0)
+
+ // Called by EC to notify thermal budget/status change
+ // Arg0 is one of SPB_EC_ values
+ // Arg1 is an object reference
+ Method (THCH, 2, NotSerialized)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ case ( 0x03)
+ {
+ // VSTS needs to be updated before notification
+ Store(DeRefOf(Arg1), VSTS)
+ Notify(DGPUPCH_SCOPE, 0xC0)
+ }
+ case ( 0x01)
+ {
+ // THBG needs to be updated before notification
+ Store(DeRefOf(Arg1), THBG)
+ Notify(DGPUPCH_SCOPE, 0xC1)
+ }
+ }
+ }
+
+ // Wrapper to call Method(SPB)
+ Method (SPB2, 2, NotSerialized)
+ {
+ Store( Buffer() {0x00, 0x00, 0x00, 0x00}, Local0 )
+ CreateDwordField(Local0, 0, LLLL)
+ Store( Arg1, LLLL )
+ Return( SPB(0x00, 0x101, Arg0, Local0) )
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: SPB
+//
+// Description: Called from _DSM -Device Specific Method for dGPU device.
+// Implement Ventura specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// Ventura DSM_GUID 95DB88FD-940A-4253-A446-70CE0504AEDF
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (SPB, 4, NotSerialized)
+ {
+
+ Store("------- SPB DSM --------", Debug)
+ // Only Interface Revision 0x0101 is supported
+ If (LNotEqual(Arg1, 0x101))
+ {
+ Return(0x80000002)
+ }
+
+ // (Arg2) Sub-Function
+ Switch (ToInteger(Arg2))
+ {
+ case (0x00)
+ {
+ Name(FMSK, Buffer(0x8)
+ {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ })
+ Store(Buffer(0x8)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }, Local0)
+ Divide(Zero, 0x8, Local2, Local1)
+ // Local1 is Quotient, Local2 is Remainder
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x20, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x21, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x22, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x23, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x24, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x2A, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ // mask out specific functions
+ Store( SizeOf(Local0), Local1)
+ While( LNotEqual(Local1, 0) ) {
+ Decrement(Local1)
+ Store( DeRefOf(Index(FMSK, Local1)), Local2)
+ And( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1) )
+ }
+
+ Return(Local0)
+ }
+
+ // Unit is mWAT
+ case(0x20)
+ {
+ Store(TBUD, Local1)
+ //failsafe to clear ventura status bit
+ And(Local1, 0xFFFFF, Local1)
+ // Just return SPB status for now (bit[0]=1 SPB enabled)
+// If(CondRefOf(PBCM,Local0)){ // Make sure this object is present.
+// If(PBCM){
+// // Software/EC have another chance to disable ventura through VSTS
+// If(LNotEqual(VSTS, 0)) {
+// Or( Local1, 0x40000000, Local1 )
+// }
+// }
+// }
+ Return(Local1)
+ }
+
+ case(0x21)
+ {
+ Return(\_PR.CPU0._PSS)
+ }
+
+ case(0x22)
+ {
+ CreateByteField(Arg3, 0, PCAP)
+
+ Store(PCAP, PSCP)
+ // \_PR.CPU0._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU0, 0x80)
+
+ If(CondRefOf(\_PR.CPU1._PPC, Local0)) {
+ // \_PR.CPU1._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU1, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU2._PPC, Local0)) {
+ // \_PR.CPU2._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU2, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU3._PPC, Local0)) {
+ // \_PR.CPU3._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU3, 0x80)
+ }
+
+//> Andy+ for ClarksField -- 8 processors
+ If(CondRefOf(\_PR.CPU4._PPC, Local0)) {
+ // \_PR.CPU4._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU4, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU5._PPC, Local0)) {
+ // \_PR.CPU5._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU5, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU6._PPC, Local0)) {
+ // \_PR.CPU6._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU6, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU7._PPC, Local0)) {
+ // \_PR.CPU7._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU7, 0x80)
+ }
+//<
+
+ Return(PCAP)
+ }
+
+ case( 0x23)
+ {
+ Return(PSCP)
+ }
+
+ case(0x24)
+ {
+ CreateField(Arg3, 0, 20, THBG)
+ CreateField(Arg3, 30, 1, DDVE)
+ }
+ case(0x2a)
+ {
+ Return(SSNR(Arg3))
+ }
+ } // end of switch
+
+ Return(0x80000002)
+ } // end SPB
+
+ // Ventura Sensor parameters header structure
+ Name(SBHS, Buffer(0x8) {})
+ CreateDWordField(SBHS, 0, VERV)
+ CreateDWordField(SBHS, 4, NUMS)
+
+ // Ventura CPU Sensor structure
+ Name(SSCP, Buffer(44) {})
+ CreateDWordField(SSCP, 4, CSNT)
+ CreateDWordField(SSCP, 8, CPTI)
+ CreateDWordField(SSCP, 12, CICA)
+ CreateDWordField(SSCP, 16, CIRC)
+ CreateDWordField(SSCP, 20, CICV)
+ CreateDWordField(SSCP, 24, CIRA)
+ CreateDWordField(SSCP, 28, CIAV)
+ CreateDWordField(SSCP, 32, CIEP)
+ CreateDWordField(SSCP, 36, CPPF)
+ CreateDWordField(SSCP, 40, CSNR)
+
+ // Ventura GPU Sensor structure
+ Name(SSGP, Buffer(44) {})
+ CreateDWordField(SSGP, 4, GSNT)
+ CreateDWordField(SSGP, 8, GPTI)
+ CreateDWordField(SSGP, 12, GICA)
+ CreateDWordField(SSGP, 16, GIRC)
+ CreateDWordField(SSGP, 20, GICV)
+ CreateDWordField(SSGP, 24, GIRA)
+ CreateDWordField(SSGP, 28, GIAV)
+ CreateDWordField(SSGP, 32, GIEP)
+ CreateDWordField(SSGP, 36, GPPF)
+ CreateDWordField(SSGP, 40, GSNR)
+
+ // Ventura CPU Parameters Structure
+ Name(SCPP, Buffer(72) {})
+ CreateDWordField(SCPP, 0, VRV1)
+ CreateDWordField(SCPP, 4, VCAP)
+ CreateDWordField(SCPP, 8, VCCP)
+ CreateDWordField(SCPP, 12, VCDP)
+ CreateDWordField(SCPP, 16, VCEP)
+ CreateDWordField(SCPP, 20, VCGP)
+ CreateDWordField(SCPP, 24, VCHP)
+ CreateDWordField(SCPP, 28, VCXP)
+ CreateDWordField(SCPP, 32, VCYP)
+ CreateDWordField(SCPP, 36, VCZP)
+ CreateDWordField(SCPP, 40, VCKP)
+ CreateDWordField(SCPP, 44, VCMP)
+ CreateDWordField(SCPP, 48, VCNP)
+ CreateDWordField(SCPP, 52, VCAL)
+ CreateDWordField(SCPP, 56, VCBE)
+ CreateDWordField(SCPP, 60, VCGA)
+ CreateDWordField(SCPP, 64, VCPP)
+ CreateDWordField(SCPP, 68, VCDE)
+
+// Ventura GPU Parameters Structure
+ Name(SGPP, Buffer(40) {})
+ CreateDWordField(SGPP, 0, VRV2)
+ CreateDWordField(SGPP, 4, VGWP)
+ CreateDWordField(SGPP, 8, VGPP)
+ CreateDWordField(SGPP, 12, VGQP)
+ CreateDWordField(SGPP, 16, VGRP)
+ CreateDWordField(SGPP, 20, VGAP)
+ CreateDWordField(SGPP, 24, VGBP)
+ CreateDWordField(SGPP, 28, VGCP)
+ CreateDWordField(SGPP, 32, VGDP)
+ CreateDWordField(SGPP, 36, VGDE)
+
+ Method(SSNR, 1)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ case (0x00)
+ {
+ // Populate Header Structure
+ Store(0x00010000, VERV)
+ Store(0x02, NUMS)
+ Return(SBHS)
+ }
+ case (0x01)
+ {
+ Store(0x00010000, VRV1)
+ Store(0x3E8, VCAP) //VEN_CPU_PARAM_A_CK 0x3E8
+ Store(0x2EE, VCCP) //VEN_CPU_PARAM_C_CK 0x2EE
+ Store(0x2EE, VCDP) //VEN_CPU_PARAM_D_CK 0x2EE
+ Store(0x2EE, VCEP) //VEN_CPU_PARAM_E_CK 0x2EE
+ Store(0x79e, VCGP) //VEN_CPU_PARAM_G_CK 0x79e
+ Store(0x2bc, VCHP) //VEN_CPU_PARAM_H_CK 0x2bc
+ Store(0x258, VCXP) //VEN_CPU_PARAM_X_CK 0x258
+ Store(0x0fa, VCYP) //VEN_CPU_PARAM_Y_CK 0x0fa
+ Store(0x1f4, VCZP) //VEN_CPU_PARAM_Z_CK 0x1f4
+ Store(0x000, VCKP) //VEN_CPU_PARAM_K_CK 0x000
+ Store(0x000, VCMP) //VEN_CPU_PARAM_M_CK 0x000
+ Store(0x000, VCNP) //VEN_CPU_PARAM_N_CK 0x000
+ Store(0x000, VCPP) //VEN_CPU_PARAM_P_CK 0x000
+ Store(0x421, VCAL) //VEN_CPU_PARAM_AL_CK 0x421
+ Store(0x708, VCBE) //VEN_CPU_PARAM_BE_CK 0x708
+ Store(0x016, VCGA) //VEN_CPU_PARAM_GA_CK 0x016
+ Store(0x001, VCDE) //VEN_CPU_PARAM_DEL_CK 0x001
+/* Clarksfield 8 CPU
+ Store(0x3E8, VCAP)
+ Store(0x258, VCCP)
+ Store(0x258, VCDP)
+ Store(0x258, VCEP)
+ Store(0x2CF, VCGP)
+ Store(0x311, VCHP)
+ Store(0x136, VCXP)
+ Store(0x118, VCYP)
+ Store(0x19A, VCZP)
+ Store(0x001, VCKP)
+ Store(0x001, VCMP)
+ Store(0x001, VCNP)
+ Store(0x000, VCPP)
+ Store(0x36B, VCAL)
+ Store(0x13C, VCBE)
+ Store(0x019, VCGA)
+ Store(0x001, VCDE)
+end Clarksfield 8CPUs*/
+
+ Return(SCPP)
+ }
+ case (0x02)
+ {
+ Store(0x00010000, VRV2)
+ Store(0x3E8, VGWP)
+ Store(0x2EE, VGPP)
+ Store(0x2EE, VGQP)
+ Store(0x2EE, VGRP)
+ Store(0x001, VGAP)
+ Store(0x1F4, VGBP)
+ Store(0x000, VGCP)
+ Store(0x000, VGDP)
+ Store(0x001, VGDE)
+/* Clarksfield 8 CPU
+ Store(0x3E8, VGBP)
+ Store(0x001, VGCP)
+ Store(0x001, VGDP)
+ Store(0x000, VGDE)
+end Clarksfield 8CPUs*/
+ Return(SGPP)
+ }
+ case (0x03)
+ {
+ // The below sensor parameter values for GPU and CPU
+ // are board specific. To support for ventura, fill
+ // the SSCP and SSGP structures
+
+ // Populate CPU Sensor values
+ Store(0x0, Index(SSCP, 0)) // Indicate CPU sensor
+ Store(0x00, CSNT)
+ Store(0x01, CPTI)
+ Store(0x84, CICA) // 0x80
+ Store(0x00, CIRC)
+ Store(0x27FF, CICV)
+ Store(0x05, CIRA)
+ Store(0xA000, CIAV)
+ Store(0x03, CIEP)
+ Store(0x0F, CPPF)
+ Store(0x04, CSNR)
+
+ // Populate GPU Sensor values
+ Store(0x1, Index(SSGP, 0)) // Indicate GPU sensor
+ Store(0x00, GSNT)
+ Store(0x01, GPTI)
+ Store(0x8C, GICA) // 0x8A
+ Store(0x00, GIRC)
+ Store(0x27FF, GICV)
+ Store(0x05, GIRA)
+ Store(0xA000, GIAV)
+ Store(0x03, GIEP)
+ Store(0x0F, GPPF)
+ Store(0x04, GSNR)
+
+ Return(Concatenate(SSCP, SSGP))
+ }
+
+ } //switch end
+
+ Return(0x80000002)
+ }
+} // end DGPUPCH_SCOPE scope
+
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/OpSSDTPCH.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/OpSSDTPCH.asl
new file mode 100644
index 0000000..39ae4c7
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/OpSSDTPCH.asl
@@ -0,0 +1,292 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/OpSSDTPCH.asl 4 7/16/13 5:13a Joshchou $
+//
+// $Revision: 4 $
+//
+// $Date: 7/16/13 5:13a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/OpSSDTPCH.asl $
+//
+// 4 7/16/13 5:13a Joshchou
+// [TAG] None
+// [Category] New Feature
+// [Description] Add _DSW method to support MSHybrid.
+//
+// 3 2/21/13 5:42a Joshchou
+// [TAG] EIP106524
+// [Category] New Feature
+// [Description] Support GC6 function for Optimus
+//
+// 2 2/07/13 3:02a Joshchou
+//
+// 1 1/15/13 6:03a Joshchou
+// [TAG] EIP107237
+// [Category] Improvement
+// [Description] Create componet for SG support on PCH
+// [Files] SgUltNvidia.cif
+// NVdGPUPCH.asl
+// NViGPUPCH.asl
+// NViGDmiscPCH.asl
+// OpSSDTPCH.asl
+// NvVenturaPCH.asl
+// NvGPSPCH.asl
+// NvSSDTPCH.asl
+//
+// 5 12/22/11 6:31a Alanlin
+// Declared "defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)"
+//
+//
+// 3 12/02/11 12:40a Alanlin
+// [TAG] EIP75359
+// [Category] Improvement
+// [Description] Report _STA asl method to PCIe root port for nVidia
+// GPU.
+//
+// 2 10/14/11 2:59a Alanlin
+// [TAG] EIP64451
+// [Category] New Feature
+// [Description] Optimus GPS feature update
+// [Files] NvSSDT.asl
+// NViGPU.asl
+// OpSSDT.asl
+// NvGPS.asl
+// SgNvidia.cif
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+//
+//
+// 6 3/17/11 6:17p Alexp
+// Optimus:Add code to preserve HD AudioCodec enable flag in CMOS
+//
+// 5 11/12/10 1:26p Alexp
+// rename ELCT to ELCL in order to avoid name conflict with Intel's ref
+// code in SgDGPU.asl
+//
+// 4 10/06/10 3:34p Alexp
+// Include defines for different Nvidia GUID functions. Helps to control
+// inclusion of peices of ASL depending on type of desired SG mode
+//
+// 3 10/05/10 7:14p Alexp
+// 1. Added debug macro to be able to insert check points in target ASL
+// code
+// 2. Reuse NVdGPU.asl file to build OpSSDT for Optimus and NvSSDT for
+// MUXed SG targets.
+// NvOptimus.asl no longer required
+//
+// 2 9/17/10 3:22p Alexp
+// remove test comments
+//
+// 1 9/17/10 1:21p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgNvidia.cif;
+// NvSSDT.asl; NVdGPU.asl;NViGPU.asl;NViGDmisc
+// OpSSDT.asl;NvOptimus.asl;NvVenture.asl
+//
+//**********************************************************************
+
+DefinitionBlock (
+ "NvOpt.aml",
+ "SSDT",
+ 1,
+ "OptRef",
+ "OptTabl",
+ 0x1000
+ ) {
+
+#define OPTIMUS_DSM_GUID 1
+//#define NBCI_DSM_GUID 1
+
+External(P8XH, MethodObj)
+#if defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)
+#define P8DB(arg0, arg1, arg2) P8XH (0, arg1) P8XH (1, arg0) sleep(arg2)
+#else
+#define P8DB(arg0, arg1, arg2)
+#endif
+
+
+External(PCI_SCOPE, DeviceObj)
+External(SG_ULT_RP_NUM, DeviceObj)
+External(DGPUPCH_SCOPE, DeviceObj)
+External(IGPU_SCOPE, DeviceObj)
+External(DGPUPCH_SCOPE._ADR, DeviceObj)
+External(IGPU_SCOPE._DSM, MethodObj)
+External(DGPUPCH_SCOPE.SGST, MethodObj)
+External(DGPUPCH_SCOPE.SGON, MethodObj)
+External(DGPUPCH_SCOPE.SGOF, MethodObj)
+External(DGPUPCH_SCOPE.SGPI, MethodObj)
+External(DGPUPCH_SCOPE.SGPO, MethodObj)
+External(\DSEL)
+External(\ESEL)
+External(\SSEL)
+External(\PSEL)
+External(\HLRS)
+External(\PWEN)
+External(\PWOK)
+External(\SGMD)
+External(\SGFL)
+External(\SSMP)
+
+#include <NVdGPUPCH.ASL> // Include DGPU device namespace
+#include <NViGPUPCH.ASL> // Include NVHG DSM calls
+//#include <NViGDmiscPCH.ASL> // Include misc event callback methods
+
+#if NV_VENTURA_SUPPORT == 1
+#include <NvVenturaPCH.ASL> // Include Ventura support
+#endif
+#if NV_GPS_SUPPORT == 1
+#include <NvGPSPCH.ASL> // Include GPS support
+#endif
+
+#if NV_GC6_SUPPORT == 1
+#include <NvGC6PCH.ASL> // Include GC6 support
+#endif
+
+Scope(SG_ULT_RP_NUM)
+{
+ Method(_DSW, 3, NotSerialized)
+ {
+ If(Arg1)
+ {
+ Store("RP05 -_DSW call ", Debug)
+ }
+ Else
+ {
+ If(LAnd(Arg0, Arg2))
+ {
+ Store("RP05 -_DSW call-1 ", Debug)
+ }
+ Else
+ {
+ Store("RP05 -_DSW call-2 ", Debug)
+ }
+ }
+ }
+}
+
+ Scope(PCI_SCOPE)
+ {
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: WMI1
+//
+// Description: WMI MXM Mapper. ASL Device is used to acccess Nv Optimus native method via WMI API
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Device(WMI1) // placed within PCI Bus scope parallel to iGPU
+ {
+ Name(_HID, "PNP0C14")
+ Name(_UID, "OPT1")
+
+ Name(_WDG, Buffer()
+ {
+ // Methods GUID {F6CB5C3C-9CAE-4ebd-B577-931EA32A2CC0}
+ 0x3C, 0x5C, 0xCB, 0xF6, 0xAE, 0x9C, 0xbd, 0x4e, 0xB5, 0x77, 0x93, 0x1E,
+ 0xA3, 0x2A, 0x2C, 0xC0,
+ 0x4D, 0x58, // Object ID "MX" = method "WMMX"
+ 1, // Instance Count
+ 0x02, // Flags (WMIACPI_REGFLAG_METHOD)
+ }) // End of _WDG
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: WMMX
+//
+// Description: WMI Method execution tunnel. MXM Native methods are called via WMMX index.
+//
+// Input:
+// Arg1: Integer GPU index. 0x10-iGPU, 0x100+PCIe Bus number for the GPU
+//
+// Output:
+// Buffer specific to the funcion being called
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(WMMX, 3)
+ {
+
+ //Arg1 = 0x10 indicates iGPU, 0x100+PCIe Bus number for the GPU
+ //
+ CreateDwordField(Arg2, 0, FUNC) // Get the function name
+
+ If (LEqual(FUNC, 0x534F525F)) // "_ROM"
+ {
+ If (LGreaterEqual(SizeOf(Arg2), 8))
+ {
+ CreateDwordField(Arg2, 4, ARGS)
+ CreateDwordField(Arg2, 8, XARG)
+ Return(DGPUPCH_SCOPE._ROM(ARGS, XARG))
+ }
+ }
+
+ If (LEqual(FUNC, 0x4D53445F)) // "_DSM"
+ {
+ If (LGreaterEqual(SizeOf(Arg2), 28))
+ {
+ CreateField(Arg2, 0, 128, MUID)
+ CreateDwordField(Arg2, 16, REVI)
+ CreateDwordField(Arg2, 20, SFNC)
+ CreateField(Arg2, 0xe0, 0x20, XRG0)
+
+// If(LNotEqual(Arg1,0x10))
+// {
+ If (CondRefOf(IGPU_SCOPE._DSM)) // common with dGPU DSM functions
+ {
+ Return(IGPU_SCOPE._DSM(MUID, REVI, SFNC, XRG0))
+ }
+// }
+ }
+ }
+ Return(0)
+ } // End of WMMX
+ } // End of WMI1 Device
+ } // end scope PCI0
+} // end SSDT
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2010, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgTpvPCH.cif b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgTpvPCH.cif
new file mode 100644
index 0000000..27b1157
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgTpvPCH.cif
@@ -0,0 +1,12 @@
+<component>
+ name = "SgTpvPCH"
+ category = ModulePart
+ LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\AcpiTables\SgTpvPCH"
+ RefName = "SgTpvPCH"
+[files]
+"SgTpvPCH.sdl"
+"SgTpvPCH.mak"
+[parts]
+"AtiSGULT"
+"nVidiaSGULT"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgTpvPCH.mak b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgTpvPCH.mak
new file mode 100644
index 0000000..02d9298
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgTpvPCH.mak
@@ -0,0 +1,132 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/SgTpvPCH.mak 2 6/02/13 8:14a Joshchou $
+#
+# $Revision: 2 $
+#
+# $Date: 6/02/13 8:14a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPCH/SgTpvPCH.mak $
+#
+# 2 6/02/13 8:14a Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Change IASL compiler path to
+# $(ACPIPLATFORM_ASL_COMPILER) in SharkBay project.
+#
+# 1 1/15/13 6:01a Joshchou
+# [TAG] EIP107237
+# [Category] Improvement
+# [Description] Create componet for SG support on PCH
+# [Files] SgTpvPCH.cif
+# SgTpvPCH.sdl
+# SgTpvPCH.mak
+#
+# 3 11/20/12 3:48a Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Create Token for OEM clone
+#
+# 2 9/09/12 11:01p Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Tpv module support for sharkbay.
+# [Files] OEMSSDT.mak
+# OEMSSDT.asl
+# OEMNVdGPU.asl
+# OEMNViGPU.asl
+# OEMNViGDmisc.asl
+# OEMNvVentura.asl
+# OEMNvGPS.asl
+# OEMSSDT.cif
+#
+# 1 12/12/11 9:10p Alanlin
+#
+#
+#
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name: OEMSSDT.mak
+#
+# Description: MAke file to build Aptio ACPI ASL components
+#
+#
+#<AMI_FHDR_END>
+#*************************************************************************
+SGPCHASL: $(BUILD_DIR)\SGTPVPCHssdt.ffs
+
+
+#-----------------------------------------------------------------------------
+# SG SSDT ACPI Tables
+#-----------------------------------------------------------------------------
+!IF "$(ACPIPLATFORM_ASL_COMPILER)"==""
+!ERROR It is an invalid path, please check your ASL compiler path.
+!ENDIF
+
+IASL = $(ACPIPLATFORM_ASL_COMPILER)
+#-----------------------------------------------------------------------
+$(BUILD_DIR)\OpSSDTPCH.aml $(BUILD_DIR)\NvSSDTPCH.aml $(BUILD_DIR)\AtiSSDTPCH.aml: $(BUILD_DIR)\OpSSDTPCH.asl $(BUILD_DIR)\NvSSDTPCH.asl $(BUILD_DIR)\AtiSSDTPCH.asl
+ $(SILENT)$(IASL) -p $@ $*.asl
+
+$(BUILD_DIR)\OpSSDTPCH.sec $(BUILD_DIR)\NvSSDTPCH.sec $(BUILD_DIR)\ATIssdtPCH.sec: $(BUILD_DIR)\OpSSDTPCH.aml $(BUILD_DIR)\NvSSDTPCH.aml $(BUILD_DIR)\AtiSSDTPCH.aml
+ $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW
+
+#Note. Expand the package with multiple SG SSDT tables.
+# DXE phase will load the tables depending on present Mxm Gfx card
+# and update Aml contents if provided in AcpiTables.c
+$(BUILD_DIR)\SGTPVPCHssdt.ffs: $(BUILD_DIR)\OpSSDTPCH.sec $(BUILD_DIR)\NvSSDTPCH.sec $(BUILD_DIR)\AtiSSDTPCH.sec
+ $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\SGTPVPCHssdt.pkg
+
+PACKAGE.INF
+[.]
+BASE_NAME = SgTpvPCHACPI
+FFS_FILEGUID = 9B65FE7C-855E-43cc-A170-A2A685F3655F
+FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM
+FFS_ATTRIB_CHECKSUM = TRUE
+
+IMAGE_SCRIPT =
+{
+ Compress (dummy) {
+ $(PROJECT_DIR)\$(BUILD_DIR)\OpSSDTPCH.sec
+ $(PROJECT_DIR)\$(BUILD_DIR)\NvSSDTPCH.sec
+ $(PROJECT_DIR)\$(BUILD_DIR)\AtiSSDTPCH.sec
+ }
+}
+<<KEEP
+#-----------------------------------------------------------------------#
+# Process SG asl files
+#-----------------------------------------------------------------------#
+$(BUILD_DIR)\OpSSDTPCH.asl $(BUILD_DIR)\NvSSDTPCH.asl $(BUILD_DIR)\AtiSSDTPCH.asl : $(INTEL_OPSSDTPCH_ASL_FILE) $(INTEL_NVSSDTPCH_ASL_FILE) $(INTEL_ATISSDTPCH_ASL_FILE)
+ $(CP) /I$(SG_TPVPCH_DIR) /FItoken.h /C $(SG_TPVPCH_DIR)\$(@F) > $@
+# include the token.h if needed to check for SDL flags
+# /FItoken.h
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgTpvPCH.sdl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgTpvPCH.sdl
new file mode 100644
index 0000000..665005f
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgTpvPCH.sdl
@@ -0,0 +1,53 @@
+TOKEN
+ Name = "SgTpvPCH_SUPPORT"
+ Value = "1"
+ Help = "Add an OEM SSDT for discrete VGA card. When Primarydisplay = Auto or PEG, the system can report OEM SSDT talbes for AMD or nVidia dGPU VGA card."
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+ Master = Yes
+End
+
+TOKEN
+ Name = "DGPUPCH_SCOPE"
+ Value = "\_SB.PCI0.RP0$(SG_ULT_RPNum).PEGP"
+ Help = "PLATFORM PORTING!!! Update iGPU and dGPU device names as defined in SB/NB.SDL"
+ TokenType = Expression
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "INTEL_OPSSDTPCH_ASL_FILE"
+ Value = "$(SG_TPVPCH_DIR)\OpSSDTPCH.asl"
+ TokenType = Expression
+ TargetMAK = Yes
+End
+
+TOKEN
+ Name = "INTEL_NVSSDTPCH_ASL_FILE"
+ Value = "$(SG_TPVPCH_DIR)\NvSSDTPCH.asl"
+ TokenType = Expression
+ TargetMAK = Yes
+End
+
+TOKEN
+ Name = "INTEL_ATISSDTPCH_ASL_FILE"
+ Value = "$(SG_TPVPCH_DIR)\AtiSSDTPCH.asl"
+ TokenType = Expression
+ TargetMAK = Yes
+End
+
+PATH
+ Name = "SG_TPVPCH_DIR"
+End
+
+MODULE
+ Help = "Includes SgTpvPEG.mak to Project"
+ File = "SgTpvPCH.mak"
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\SGTPVPCHssdt.ffs"
+ Parent = "FV_MAIN"
+ InvokeOrder = AfterParent
+End
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgUltAti.cif b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgUltAti.cif
new file mode 100644
index 0000000..803c483
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgUltAti.cif
@@ -0,0 +1,11 @@
+<component>
+ name = "AtiUlt"
+ category = ModulePart
+ LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\AcpiTables\SgTpvPCH"
+ RefName = "AtiSGULT"
+[files]
+"AtiSSDTPCH.asl"
+"ATdGPUPCH.asl"
+"ATiGPUPCH.asl"
+"ATiGDmiscPCH.asl"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgUltNvidia.cif b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgUltNvidia.cif
new file mode 100644
index 0000000..d9c2f85
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPCH/SgUltNvidia.cif
@@ -0,0 +1,15 @@
+<component>
+ name = "nVidiaUlt"
+ category = ModulePart
+ LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\AcpiTables\SgTpvPCH"
+ RefName = "nVidiaSGULT"
+[files]
+"NVdGPUPCH.asl"
+"NViGPUPCH.asl"
+"NViGDmiscPCH.asl"
+"OpSSDTPCH.asl"
+"NvVenturaPCH.asl"
+"NvGPSPCH.asl"
+"NvSSDTPCH.asl"
+"NvGC6PCH.asl"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/ATdGPU.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/ATdGPU.asl
new file mode 100644
index 0000000..d4cce5d
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/ATdGPU.asl
@@ -0,0 +1,204 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/ATdGPU.asl 1 1/15/13 5:58a Joshchou $
+//
+// $Revision: 1 $
+//
+// $Date: 1/15/13 5:58a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/ATdGPU.asl $
+//
+// 1 1/15/13 5:58a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Create componet for SG support on PEG
+// [Files] SgAti.cif
+// AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+//
+// 2 9/09/12 11:02p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+// SgAti.cif
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgAti.cif
+// AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+//
+//
+// 2 10/05/10 7:09p Alexp
+// Added debug macro to be able to insert include check points in target
+// ASL code
+//
+// 1 9/17/10 1:20p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgAti.cif;
+// AtiSSDT.asl; ATdGPU.asl;ATiGPU.asl;ATiGDmisc
+//
+// 1 6/08/10 3:45p Alexp
+//
+// 1 6/03/10 2:54p Alexp
+//
+// 10 4/29/10 11:42a Alexp
+// updated ASL names for Mxm power control and switching from GPIO to
+// functional names. E.g. old- PO16 to new-MRST etc.
+//
+// 9 4/02/10 5:06p Alexp
+// Change per Calpella SG BIOS spec 1.03:
+// - add link control register
+// - add WiDi display
+//
+// 8 1/11/10 4:03p Alexp
+// Added Nvidia Optimus Gfx support
+//
+// 7 12/08/09 10:20a Alexp
+// Per BWG 1.2 Added code to save/restore Endpoint Link Contol Register
+// during power cycle of DGPU
+//
+// 6 10/06/09 1:27p Alexp
+// replaced Alias definitions with actual device name scopes for PEG
+// display devices
+//
+// 5 10/05/09 5:35p Alexp
+// updated asl code for Ati and Nvidia according to Calpella SG BWG 1.1
+//
+// 4 8/21/09 4:45p Alexp
+// Updated Nvidia and ATI SG code to match latest Intel Calpella Acpi
+// reference code from Intel code drop v#68 and Ati SG BWG
+// SG Asl code. Made PEG PCIe MMIO base address dependent on
+// PCIE_BASE_ADDRESS SDL token. Before it was hardwired in ASL code which
+// caused SG logic to fail in Mxm & SG Label 005
+//
+// 3 8/20/09 7:08p Alexp
+// upgraded Ati and Nvidia SSDT Asl files to match latest Acpi code drop
+// #68
+//
+// 1 7/16/09 11:17a Alexp
+// Added SG support for AMD ATI Gfx adaptors
+//**********************************************************************
+Scope(DGPU_SCOPE)
+{
+// OperationRegion (PEGR, PCI_Config, 0, 0x100)
+// Field(PEGR, DWordAcc, Lock, Preserve)
+// {
+// Offset(0x4C),
+// SSID, 32,
+// }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _ON
+//
+// Description: dGPU power ON control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_ON,0,Serialized)
+ {
+ SGON() // OEM Mxm Power On
+
+ //Set the SSID for the ATI MXM
+// Store(MXM_SSVID_DID, SSID)
+
+ //Ask OS to do a PnP rescan
+ Notify(PEG_SCOPE,0)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _OFF
+//
+// Description: dGPU power OFF control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_OFF,0,Serialized)
+ {
+ SGOF() // OEM Mxm Power On
+
+ //Ask OS to do a PnP rescan
+ Notify(PEG_SCOPE,0)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _STA
+//
+// Description: Returns curent dGPU power/presence state
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_STA,0,Serialized)
+ {
+ Return(SGST()) // OEM Mxm Power status
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _INI
+//
+// Description: dGPU Init control method. Used to force dGPU _ADR to return proper PCI address
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+// Method (_INI)
+// {
+// should already be set by now...
+//// Store(MXM_SSVID_DID, SSID) //Set the SSID for the ATI MXM
+// Store(0x0, DGPU_SCOPE._ADR) //make sure PEGP address returns 0x00000000
+// }
+
+} // end Scope(DGPU_SCOPE)
+
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/ATiGDmisc.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/ATiGDmisc.asl
new file mode 100644
index 0000000..f8ab4dd
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/ATiGDmisc.asl
@@ -0,0 +1,302 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/ATiGDmisc.asl 1 1/15/13 5:58a Joshchou $
+//
+// $Revision: 1 $
+//
+// $Date: 1/15/13 5:58a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/ATiGDmisc.asl $
+//
+// 1 1/15/13 5:58a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Create componet for SG support on PEG
+// [Files] SgAti.cif
+// AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+//
+// 2 9/09/12 11:02p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+// SgAti.cif
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgAti.cif
+// AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+//
+//
+// 4 3/17/11 6:18p Alexp
+// cleaned up the code.
+//
+// 3 11/12/10 1:25p Alexp
+// Change IDAB method: invoke IGD_SCOPE.IDAB is defined there
+//
+// 2 10/05/10 7:09p Alexp
+// Added debug macro to be able to insert include check points in target
+// ASL code
+//
+// 1 9/17/10 1:20p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgAti.cif;
+// AtiSSDT.asl; ATdGPU.asl;ATiGPU.asl;ATiGDmisc
+//
+// 1 6/08/10 3:45p Alexp
+//
+// 1 6/03/10 2:54p Alexp
+//
+// 4 10/05/09 5:35p Alexp
+// updated asl code for Ati and Nvidia according to Calpella SG BWG 1.1
+//
+// 3 8/20/09 7:08p Alexp
+// upgraded Ati and Nvidia SSDT Asl files to match latest Acpi code drop
+// #68
+//
+// 1 7/16/09 11:17a Alexp
+// Added SG support for AMD ATI Gfx adaptors
+//**********************************************************************
+
+External(DSEN)
+External(IGPU_SCOPE.AINT, MethodObj)
+External(DGPU_SCOPE.DD02)
+External(IGPU_SCOPE.IDAB, MethodObj)
+
+//Do not remove this function.
+Method(IDAB, 0, Serialized)
+{
+ If (CondRefOf(IGPU_SCOPE.IDAB))
+ {
+ IGPU_SCOPE.IDAB()
+ }
+}
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HGAS
+//
+// Description: HG Adaptor select, notify
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HGAS) // HG Adaptor Select
+{
+ // Toggle GFX Adapter.
+ Store(1,IGPU_SCOPE.PXGS)
+ Notify(IGPU_SCOPE,0x81)
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HBRT
+//
+// Description: Send backlight notifications to the DGPU LFP device
+// This is required for Win7 and is backward compatible with Vista
+//
+// Input: Arg0 - 4 - Brightnes Down, 3- Up
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HBRT, 1 , Serialized)
+{
+
+ If(And(4,DSEN)) //Note: DSEN variable is expected to be set by IGD miniport only.
+ {
+ If(LEqual(Arg0,4))
+ {
+ Notify(DGPU_SCOPE.DD02,0x87) //Note: DD02 is hardcoded as the LFP device in intelgfx.asl
+ }
+ If(LEqual(Arg0,3))
+ {
+ Notify(DGPU_SCOPE.DD02,0x86)
+ }
+ }
+
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HPFS
+//
+// Description: Panel Fitting Hot Key
+//
+// Input: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HPFS, 0, Serialized) //Panel Fitting Hot Key
+{
+ If(LNotEqual(IGPU_SCOPE.GSTP,1))
+ {
+
+ //
+ // HG Handling of Panel Fitting Switch
+ //
+ If(LEqual(IGPU_SCOPE.AGXA,0))
+ {
+ IGPU_SCOPE.AINT(2, 0)
+ }
+ Else
+ {
+ Store(1,IGPU_SCOPE.EMDR)
+
+ //
+ // Expansion Mode toggling
+ //
+ If(LEqual(IGPU_SCOPE.EXPM,2))
+ {
+ Store(0,IGPU_SCOPE.EXPM)
+ }
+ Else
+ {
+ Increment(IGPU_SCOPE.EXPM)
+ }
+ Notify(IGPU_SCOPE,0x81)
+ }
+ }
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HNOT
+//
+// Description: Notification handler for Switchable graphics. Called from GNOT()
+//
+// Input: Arg0 = Current event type:
+// 1 = display switch
+// 2 = lid
+// 3 = dock (!!!!!Calpella ref code, Method(GDCK)sends 4 for Dock notifications )
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method (HNOT, 1, Serialized)
+{
+
+ Switch(ToInteger(Arg0))
+ {
+ case(1) //Display Switch event
+ {
+ If(LNotEqual(IGPU_SCOPE.GSTP,1))
+ {
+ //
+ // HG Handling of Display Switch Event
+ //
+ // Muxless?
+ If(LEqual(SGMD,0x2))
+ {
+ If(LEqual(IGPU_SCOPE.AGXA,0))
+ {
+ Notify(IGPU_SCOPE,0x80)
+ }
+
+ If(LEqual(IGPU_SCOPE.AGXA,1))
+ {
+ Notify(DGPU_SCOPE,0x80)
+ }
+ }
+ Else
+ {
+ Store(1,IGPU_SCOPE.DSWR)
+ Notify(IGPU_SCOPE,0x81)
+ }
+ }
+ }
+ case (2) //Lid switch event
+ {
+ // Muxless?
+ If(LEqual(SGMD,0x2))
+ {
+ If(LEqual(IGPU_SCOPE.AGXA,0))
+ {
+ Notify(IGPU_SCOPE,0x80)
+ }
+
+ If(LEqual(IGPU_SCOPE.AGXA,1))
+ {
+ Notify(DGPU_SCOPE,0x80)
+ }
+ }
+ Else
+ {
+ Notify(IGPU_SCOPE,0x80) //Placeholder for LID event
+ }
+ }
+// case (3) //Dock event
+ case (4) //Dock event
+ {
+ // Muxless?
+ If(LEqual(SGMD,0x2))
+ {
+ If(LEqual(IGPU_SCOPE.AGXA,0))
+ {
+ Notify(IGPU_SCOPE,0x80)
+ }
+
+ If(LEqual(IGPU_SCOPE.AGXA,1))
+ {
+ Notify(DGPU_SCOPE,0x80)
+ }
+ }
+ Else
+ {
+ Notify(IGPU_SCOPE,0x80) //Placeholder for handling dock event
+ }
+ }
+ Default
+ {
+ Notify(IGPU_SCOPE,0x80)
+ }
+
+ }
+
+}
+
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/ATiGPU.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/ATiGPU.asl
new file mode 100644
index 0000000..19548a3
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/ATiGPU.asl
@@ -0,0 +1,1359 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/ATiGPU.asl 5 7/16/13 5:19a Joshchou $
+//
+// $Revision: 5 $
+//
+// $Date: 7/16/13 5:19a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/ATiGPU.asl $
+//
+// 5 7/16/13 5:19a Joshchou
+// [TAG] None
+// [Category] New Feature
+// [Description] Enable falg bit14 of ATPX Function 1 to support
+// MSHybrid.
+//
+// 4 6/05/13 5:13a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Increase the size of RBUF to support hybrid Vbios.
+// Improve some code for support PX5.6.
+// Add notification for customer call from EC event.
+//
+// 3 3/21/13 3:50a Joshchou
+// [TAG] EIP105607
+// [Category] Spec Update
+// [Severity] Important
+// [Description] Update for support PX5.6
+//
+// 2 2/21/13 5:46a Joshchou
+// [TAG] EIP107720
+// [Category] Spec Update
+// [Severity] Minor
+// [Description] Add ATIF function 15 sample code for reference.
+//
+// 1 1/15/13 5:58a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Create componet for SG support on PEG
+// [Files] SgAti.cif
+// AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+//
+// 3 11/20/12 3:44a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Comment some unused External
+//
+// 2 9/09/12 11:02p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+// SgAti.cif
+//
+// 3 12/06/11 2:14a Alanlin
+// [TAG] EIP76148
+// [Category] New Feature
+// [Description] PX 5.0 feature updated
+//
+// 2 7/14/11 5:39a Alanlin
+// [TAG] EIP64370
+// [Category] Bug Fix
+// [Severity] Important
+// [Symptom] Screen can't be displayed after install ATI SG driver
+// [RootCause] ASL method return value is incorrect.
+// [Solution] Return correct value to driver.
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgAti.cif
+// AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+//
+//
+// 5 3/17/11 6:18p Alexp
+// cleaned up the code.
+//
+// 4 1/03/11 12:26p Alexp
+// [TAG] EIP47451
+// [Category] Improvement
+// [Description] fixed checkpoint display in ATRM method
+// [Files] atidgpu.asl
+//
+// 3 11/12/10 1:23p Alexp
+// rename ELCT to ELCL in order to avoid name conflict with Intel's ref
+// code in SgDGPU.asl
+//
+// 2 10/05/10 7:09p Alexp
+// Added debug macro to be able to insert include check points in target
+// ASL code
+//
+// 1 9/17/10 1:20p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgAti.cif;
+// AtiSSDT.asl; ATdGPU.asl;ATiGPU.asl;ATiGDmisc
+//
+// 2 6/08/10 4:21p Alexp
+//
+// 1 6/08/10 3:46p Alexp
+//
+// 1 6/08/10 3:45p Alexp
+//
+// 1 6/03/10 2:56p Alexp
+//
+// 8 4/29/10 11:42a Alexp
+// updated ASL names for Mxm power control and switching from GPIO to
+// functional names. E.g. old- PO16 to new-MRST etc.
+//
+// 7 4/02/10 5:06p Alexp
+// Change per Calpella SG BIOS spec 1.03:
+// - add link control register
+// - add WiDi display
+//
+// 6 12/08/09 10:20a Alexp
+// Per BWG 1.2 Added code to save/restore Endpoint Link Contol Register
+// during power cycle of DGPU
+//
+// 5 10/05/09 5:35p Alexp
+// updated asl code for Ati and Nvidia according to Calpella SG BWG 1.1
+//
+// 4 8/21/09 4:45p Alexp
+// Updated Nvidia and ATI SG code to match latest Intel Calpella Acpi
+// reference code from Intel code drop v#68 and Ati SG BWG
+// SG Asl code. Made PEG PCIe MMIO base address dependent on
+// PCIE_BASE_ADDRESS SDL token. Before it was hardwired in ASL code which
+// caused SG logic to fail in Mxm & SG Label 005
+//
+// 1 7/16/09 11:17a Alexp
+// Added SG support for AMD ATI Gfx adaptors
+//
+//
+//**********************************************************************
+External(\ECON, IntObj) // Embedded Controller Availability Flag.
+External(PCI_SCOPE.LPCB.H_EC.LSTE)
+External(MXD1)
+External(MXD2)
+External(MXD3)
+External(MXD4)
+External(MXD5)
+External(MXD6)
+External(MXD7)
+External(MXD8)
+
+External(NXD1)
+External(NXD2)
+External(NXD3)
+External(NXD4)
+External(NXD5)
+External(NXD6)
+External(NXD7)
+External(NXD8)
+
+External(AMDA)
+External(SGMD)
+External(SGFL)
+//External(PXFX)
+//External(PXDY)
+External(PXFD)
+
+Scope (IGPU_SCOPE)
+{
+/*
+ Method(_INI,0)
+ {
+// Init all scratch pad fields if not already done so in OpRegion Init
+ }
+*/
+
+//<AMI_SHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: APXM
+//
+// Description: AMD PowerExpress OperationRegion.
+// OpRegion address (AMDA)is defined in IDG Nvs OpRegion
+//
+//-------------------------------------------------------------------------
+//<AMI_SHDR_END>
+ OperationRegion(APXM,SystemMemory,AMDA,0x20400)
+ Field(APXM, AnyAcc, NoLock, Preserve)
+ {
+ // OpRegion Header
+
+ APSG, 0x80, // (000h) Signature-"AMD--PowerXpress".
+ APSZ, 0x20, // (010h) OpRegion Size.
+ APVR, 0x20, // (014h) OpRegion Version.
+
+ // OpRegion Data
+ APXA, 0x20, // PX opregion address
+ RVBS, 0x20, // PX Runtime VBIOS image size
+ NTLE, 0x10, // Total number of toggle list entries
+ TLE1, 0x10, // The display combinations in the list...
+ TLE2, 0x10,
+ TLE3, 0x10,
+ TLE4, 0x10,
+ TLE5, 0x10,
+ TLE6, 0x10,
+ TLE7, 0x10,
+ TLE8, 0x10,
+ TLE9, 0x10,
+ TL10, 0x10,
+ TL11, 0x10,
+ TL12, 0x10,
+ TL13, 0x10,
+ TL14, 0x10,
+ TL15, 0x10,
+ TGXA, 0x10, // Target GFX adapter as notified by ATPX function 5
+ AGXA, 0x10, // Active GFX adapter as notified by ATPX function 6
+ GSTP, 0x08, // GPU switch transition in progress
+ DSWR, 0x08, // Display switch request
+ SPSR, 0x08, // System power source change request
+ DCFR, 0x08, // Display configuration change request
+ EMDR, 0x08, // Expansion mode change request
+ PXGS, 0x08, // PowerXpress graphics switch toggle request
+ CACD, 0x10, // Currently active displays
+ CCND, 0x10, // Currently connected displays
+ NACD, 0x10, // Next active displays
+ EXPM, 0x08, // Expansion Mode
+ TLSN, 0x10, // Toggle list sequence index
+ ELCL, 0x10, // Endpoint Link Contol Register Value
+ // for ATRM (_ROM equivalent) data
+ RBF1, 0x40000, // 0x8000 bytes in bits
+ RBF2, 0x40000, // 0x8000 bytes in bits
+ RBF3, 0x40000, // 0x8000 bytes in bits
+ RBF4, 0x40000 // 0x8000 bytes in bits
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: ADPM
+//
+// Description: ADPM -> ATPX Fn 8 Digital port mux mode
+//
+// Input:
+// Arg0 : Integer User selected option (via., setup 0 -> Shared, 1 -> iGPU Only, 2 -> dGPU Only)
+// Arg1 : 1 -> iGPU connector record, 2->dgpu connector record
+//
+// Output:
+// Flag value for ATPX Fn 8.
+// Bit0-> display can be driven by the GPU
+// Bit1-> HPD can be detected by the GPU
+// Bit2-> AUX/DDC can be driven by the GPU
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(ADPM, 2, Serialized)
+ {
+ Store(0, Local1)
+
+ // AUX/DDC Mux settings
+ ShiftRight(Arg0, 16, Local0)
+
+ if(LEqual(Arg1, 1)) // If iGPU connector record
+ {
+ Or (And(Local0, 0x1), Local1, Local1)
+ }
+ else // If dGPU connector record
+ {
+ Or (ShiftRight(And(Local0, 0x2),1), Local1, Local1)
+ }
+ ShiftLeft(Local1, 1, Local1)
+
+
+ // HPD Mux settings
+ ShiftRight(Arg0, 24, Local0)
+
+ if(LEqual(Arg1, 1)) // If iGPU connector record
+ {
+ Or (And(Local0, 0x1), Local1, Local1)
+ }
+ else // If dGPU connector record
+ {
+ Or (ShiftRight(And(Local0, 0x2),1), Local1, Local1)
+ }
+ ShiftLeft(Local1, 1, Local1)
+
+
+ // Display Mux settings
+ ShiftRight(Arg0, 8, Local0)
+
+ if(LEqual(Arg1, 1)) // If iGPU connector record
+ {
+ Or (And(Local0, 0x1), Local1, Local1)
+ }
+ else // If dGPU connector record
+ {
+ Or (ShiftRight(And(Local0, 0x2),1), Local1, Local1)
+ }
+
+ Return (Local1)
+
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: ATPX
+//
+// Description: ATI PowerXpress (PX) Contrl Method: Revision 0.19
+// PX specific Control Method used by integrated graphics
+// or discrete graphics driver on PX enabled platforms.
+//
+// Input:
+// Arg0: Integer Function code.
+// Arg1: Buffer Parameter buffer, 256 bytes
+//
+// Output:
+// Returns Buffer 256 bytes
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(ATPX,2,Serialized)
+ {
+ P8DB(0xA1, Arg0, 2000)
+ //
+ // Function 0: Verify PowerXpress Interface
+ //
+ // Returns the PX interface version and
+ // functions supported by PX System BIOS
+ //
+ If(LEqual(Arg0,0))
+ {
+ Name(TMP1,Buffer(256) {0x00})
+ CreateWordField ( TMP1, 0, F0SS)
+ CreateWordField ( TMP1, 2, F0IV)
+ CreateDwordField( TMP1, 4, F0SF)
+
+ Store(0x0008,F0SS)
+ Store(0x0001,F0IV)
+ Store(0x000000BF,F0SF)
+
+ // For Muxless: Support only Fun1, Fun2, Fun5 and Fun6
+ If(LEqual(SGMD,0x2))
+ {
+
+ Store(0x00000033,F0SF)
+/*
+ If (LEqual(PXDY, 0x01)) { // PX Dynamic Mode Switch Enabled
+ And(F0SF, 0xFFFFFFFD, F0SF) // Don't support PX02
+ }
+ If (LAnd(LEqual(PXDY, 0x01), // Support both Dynamic and Fixed PX switch
+ LEqual(PXFX, 0x01))) {
+ Or(F0SF, 0x2, F0SF) // Support PX02
+ }
+*/
+ }
+
+ Return(TMP1)
+ }
+
+ //
+ // Function 1: Get PowerXpress Parameters
+ //
+ // Returns various PX related platform parameters
+ //
+ If(LEqual(Arg0,1))
+ {
+ Name(TMP2,Buffer(256) {0x00})
+ CreateWordField ( TMP2, 0, F1SS)
+ CreateDwordField ( TMP2, 2, F1VM)
+ CreateDwordField( TMP2, 6, F1FG)
+ Store(0x000A,F1SS) //Structure size of return package
+ Store(0x00007FFF,F1VM) // Bit[14:0]Mask used for valid bit fields
+
+ // Bit0: LVDS I2C is accessible to both graphics controllers.
+ // Bit1: CRT1 I2C is accessible to both graphics controllers.
+ // Bit2: DVI1 I2C is accessible to both graphics controllers.
+ // Bit3: CRT1 RGB signals are multiplexed.
+ // Bit4: TV1 signals are multiplexed.
+ // Bit5: DFP1 signals are multiplexed.
+ // Bit6: Indicates that a separate multiplexer control for I2C/Aux/HPD exists.
+ // Bit7: Indicates that a "dynamic" PX scheme is supported.
+ // Bit8: Reserved.
+ // Bit9: Indicates that "fixed" scheme is not supported, if set to one.
+ // Bit10: Indicates that full dGPU power off in gdynamich scheme is supported, if set to one.
+ // Bit11: Indicates that discrete graphics must be powerd on while a monitor is connected to discrete graphics connector,if set to one
+ // Bit12: Indicates that discrete graphics can drive display outpurs(local dGPU displays are supported),if set to one
+ // Bit13: Indicates that long idle detection is disabled ,if set to one
+ // Bit14: Indicates that Windows Blue "Hybrid Graphics" is required(supported),if set to one
+ // Bits[31:15]: Reserved (must be zero).
+
+ // For Muxless: Set BIT7 for dynamic" PX scheme is supported
+ If(LEqual(SGMD,0x2))
+ {
+ Store(0x00000280,F1FG) // BACO Mode under the Dynamic Scheme
+
+ If(LEqual(PXFD,0x1))
+ {
+ Store(0x00005E80,F1FG) // dGPU Power off under the Dynamic Scheme
+ }
+ }
+ Else
+ {
+ // For Muxed: Set BIT6 to Indicates that a separate multiplexer control for I2C/Aux/HPD exists
+ // and is controlled by function 4 (Monitor I2C Control).
+ Store(0x00000040,F1FG) // Actual PX parameters field
+ }
+
+ Return(TMP2)
+ }
+
+ //
+ // Function 2: Power Control
+ //
+ // Powers on/off the discrete graphics
+ //
+ If(LEqual(Arg0,2))
+ {
+ CreateWordField(Arg1,0,FN2S)
+ CreateByteField(Arg1,2,DGPR)
+
+ If(LEqual(DGPR,0)) // Powers off discrete graphics
+ {
+ DGPU_SCOPE._OFF()
+ }
+ If(LEqual(DGPR,1)) // Powers on discrete graphics
+ {
+ DGPU_SCOPE._ON()
+ }
+ Return(0)
+ }
+
+ //
+ // Function 3: Display Multiplexer Control
+ //
+ // Controls display multiplexers
+ //
+ If(LEqual(Arg0,3))
+ {
+ CreateWordField(Arg1,0,FN3S)
+ CreateWordField(Arg1,2,SDMG)
+
+ // Display Multiplexer Control
+ If(LEqual(SDMG,0)) // Switch Display Muxes to iGFX
+ {
+ DGPU_SCOPE.SGPO(DSEL, 0)
+ }
+ If(LEqual(SDMG,1)) // Switch Display Muxes to dGFX
+ {
+ DGPU_SCOPE.SGPO(SSEL, 1)
+ }
+
+ Return(0)
+ }
+
+ //
+ // Function 4: Monitor I2C Control
+ //
+ // Controls monitor I2C lines
+ //
+ If(LEqual(Arg0,4))
+ {
+ CreateWordField(Arg1,0,FN4S)
+ CreateWordField(Arg1,2,SIMG)
+
+ // I2C Multiplexer Control
+ If(LEqual(SIMG,0)) // Switch I2C Muxes to iGFX
+ {
+ DGPU_SCOPE.SGPO(ESEL, 0)
+ }
+ If(LEqual(SIMG,1)) // Switch I2C Muxes to dGFX
+ {
+ DGPU_SCOPE.SGPO(ESEL, 1)
+ }
+
+ Return(0)
+ }
+
+ //
+ // Function 5: Graphics Device Switch Start Notification
+ //
+ // Notifies SBIOS that GFX device switch process has been started
+ //
+ If(LEqual(Arg0,5))
+ {
+ CreateWordField(Arg1,0,FN5S)
+ CreateWordField(Arg1,2,TGFX)
+ Store(TGFX,TGXA)
+ Store(1,GSTP)
+
+ Return(0)
+ }
+
+ //
+ // Function 6: Graphics Device Switch End Notification
+ //
+ // Notifies SBIOS that GFX device switch process has been completed
+ //
+ If(LEqual(Arg0,6))
+ {
+ CreateWordField(Arg1,0,FN6S)
+ CreateWordField(Arg1,2,AGFX)
+ Store(AGFX,AGXA)
+ Store(0,GSTP)
+
+ Return(0)
+ }
+
+ //
+ // Function 8: Get Display Connectors mapping
+ //
+ If(LEqual(Arg0,8))
+ {
+ Name(TMP3,Buffer(256) {
+ 0x0e,0x00, //Number of reported display connectors
+ 0x46,0x00, //Total Connector structure size in bytes (num of structures * structure size)
+ 0x07,0x01,0x00,0x00,0x01, //Connector structure 1 - CRT on iGPU
+ 0x07,0x01,0x01,0x00,0x01, //Connector structure 2 - CRT on dGPU
+ 0x05,0x00,0x00,0x00,0x04, //Connector structure 3 - LFP on iGPU
+ 0x05,0x00,0x01,0x10,0x01, //Connector structure 4 - LFP on dGPU
+
+ // Digital port mapping on EC4
+ //
+ // Intel ATI EC4 output
+ // Port B -> Port B DP
+ // Port C -> Port C HDMI
+ // Port D -> Port D DP
+ //
+
+ 0x07,0x03,0x00,0x00,0x03, //Connector structure 5 - DisplayPort_B on iGPU
+ 0x07,0x03,0x01,0x10,0x02, //Connector structure 6 - DP on dGPU (MXM port B on EC4)
+ 0x07,0x07,0x00,0x01,0x03, //Connector structure 7 - HDMI/DVI dongle on port B
+ 0x07,0x07,0x01,0x10,0x02, //Connector structure 8 - HDMI/DVI dongle on dGPU (MXM port B on EC4)
+ 0x07,0x09,0x00,0x02,0x03, //Connector structure 9 - HDMI_C on iGPU
+ 0x07,0x09,0x01,0x20,0x02, //Connector structure 10 - HDMI on dGPU (MXM port C on EC4)
+ 0x07,0x0a,0x00,0x03,0x03, //Connector structure 11 - DisplayPort_D on iGPU
+ 0x07,0x0a,0x01,0x30,0x02, //Connector structure 12 - DP on dGPU (MXM port B. Not routed to EC4)
+ 0x07,0x0b,0x00,0x04,0x03, //Connector structure 13 - HDMI/DVI dongle on port D
+ 0x07,0x0b,0x01,0x30,0x02, //Connector structure 14 - HDMI/DVI dongle on dGPU (MXM port B. Not routed to EC4)
+ 0x07,0x0C,0x00,0x06,0x03, //Connector structure 15 - Place holder for Intel Wireless Display
+ })
+
+ CreateWordField (TMP3, 0, ATNO)
+ CreateWordField (TMP3, 2, ATSZ)
+
+ //Modify the display, HPD and Aux/DDC flag in the connector structure based on iGPU Digital port setup option
+
+ //Connector structure 3 - LFP on iGPU
+ Store(ADPM(MXD2, 1), Index(TMP3, 14))
+
+ //Connector structure 4 - LFP on dGPU
+ Store(ADPM(MXD2, 1), Index(TMP3, 19))
+
+ //Connector structure 5 - DisplayPort_B on iGPU
+ Store(ADPM(MXD3, 1), Index(TMP3, 24))
+
+ //Connector structure 6 - DP on dGPU
+ Store(ADPM(MXD3, 2), Index(TMP3, 29))
+
+ //Connector structure 7 - HDMI/DVI dongle on port B
+ Store(ADPM(MXD4, 1), Index(TMP3, 34))
+
+ //Connector structure 8 - HDMI/DVI dongle on dGPU
+ Store(ADPM(MXD4, 2), Index(TMP3, 39))
+
+ //Connector structure 9 - HDMI_C on iGPU
+ Store(ADPM(MXD5, 1), Index(TMP3, 44))
+
+ //Connector structure 10 - HDMI on dGPU
+ Store(ADPM(MXD5, 2), Index(TMP3, 49))
+
+ //Connector structure 11 - DisplayPort_D on iGPU
+ Store(ADPM(MXD6, 1), Index(TMP3, 54))
+
+ //Connector structure 12 - DP on dGPU
+ Store(ADPM(MXD6, 2), Index(TMP3, 59))
+
+ //Connector structure 13 - HDMI/DVI dongle on port D
+ Store(ADPM(MXD7, 1), Index(TMP3, 64))
+
+ //Connector structure 14 - HDMI/DVI dongle on dGPU
+ Store(ADPM(MXD7, 2), Index(TMP3, 69))
+
+ If(And(SGFL, 0x01))
+ {
+ Store(Add(ATNO, 0x1), ATNO)
+ Store(Add(ATSZ, 0x5), ATSZ)
+ }
+
+ Return(TMP3)
+ }
+
+ Return(0) //End of ATPX
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: ATRM
+//
+// Description: ATI PowerXpress (PX) get ROM Method: Revision 0.19
+// PX specific Control Method used by discrete graphics driver
+// on PX enabled platforms to get a runtime modified copy of
+// the discrete graphics device ROM data (Video BIOS).
+//
+// Input:
+// Arg0: Integer Offset of the graphics device ROM data
+// Arg1: Integer Size of the buffer to fill in (up to 4K)
+//
+// Output:
+// Buffer Buffer of requested video ROM bytes
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(ATRM,2,Serialized)
+ {
+ Store(Arg0,Local0)
+ Store(Arg1,Local1)
+
+ P8DB(0x44, ShiftRight(Local0, 8), 1000)
+
+ If(LGreater(Local1,0x1000))
+ {
+ Store(0x1000,Local1)
+ }
+ If(LGreater(Local0,0x10000))
+ {
+ Return(Buffer(Local1){0})
+ }
+ If(LGreater(Local0,RVBS))
+ {
+ Return(Buffer(Local1){0})
+ }
+// If (LGreater (Add (Local0, Local1), RVBS))
+// {
+// Store (0x00, Local0)
+// }
+
+ Multiply(Local1,0x08,Local3)
+ Name(ROM1,Buffer(0x8000){0})
+ Name(ROM2,Buffer(Local1){0})
+
+ If(LLess(Local0, 0x8000)){
+ Store(RBF1, ROM1)
+ }
+ ElseIf(LLess(Local0, 0x10000)){
+ Subtract(Local0,0x8000,Local0)
+ Store(RBF2, ROM1)
+ }
+ ElseIf(LLess(Local0, 0x18000)){
+ Subtract(Local0,0x10000,Local0)
+ Store(RBF3, ROM1)
+ }
+ ElseIf(LLess(Local0, 0x20000)){
+ Subtract(Local0,0x18000,Local0)
+ Store(RBF4, ROM1)
+ }
+ Multiply(Local0,0x08,Local2)
+ CreateField(ROM1,Local2,Local3,TMPB)
+ Store(TMPB,ROM2)
+ Return(ROM2)
+
+ }
+ //
+ // INDL : Initialize Global Next active device list.
+ //
+ // Argments : None.
+ //
+ // returns : None.
+ //
+ Method(INDL, 0, Serialized)
+ {
+ Store(0, NXD1)
+ Store(0, NXD2)
+ Store(0, NXD3)
+ Store(0, NXD4)
+ Store(0, NXD5)
+ Store(0, NXD6)
+ Store(0, NXD7)
+ Store(0, NXD8)
+ }
+ //
+ // SNXD -> Set Next active device.
+ //
+ // Arg0 : Display vector of devices that will be activated
+ //
+ // Returns : None.
+ //
+ Method(SNXD, 1, Serialized)
+ {
+ INDL()
+
+ Store(Arg0, Local0)
+ If(And(Local0, ShiftLeft(1, 1))) // 1-> BIT1 CRT1
+ {
+ Store(1, NXD1) // NXD1 -> CRT
+ }
+ If(And(Local0, ShiftLeft(1, 0))) // 0 -> BIT2 LCD1
+ {
+ Store(1, NXD2) // NXD2 -> LCD
+ }
+ If(And(Local0, ShiftLeft(1, 3))) // 3 -> BIT3 DFP1 (DP_B)
+ {
+ Store(1, NXD3) // NXD3 -> Display port B
+ }
+ If(And(Local0, ShiftLeft(1, 7))) // 7 -> BIT7 DFP2 (HDMI_B)
+ {
+ Store(1, NXD4) // NXD4 -> HDMI B
+ }
+ If(And(Local0, ShiftLeft(1, 9))) // 9 -> BIT9 DFP3 (HDMI_C)
+ {
+ Store(1, NXD5) // NXD5 -> HDMI C
+ }
+ If(And(Local0, ShiftLeft(1, 10))) // 10 -> BIT10 DFP4 (DP_D)
+ {
+ Store(1, NXD6) // NXD6 -> Display port D
+ }
+ If(And(Local0, ShiftLeft(1, 11))) // 11 -> BIT11 DFP5 (HDMI_D)
+ {
+ Store(1, NXD7) // NXD7 -> HDMI D
+ }
+
+ //NXD8 is not used since there are only 7 entries in _DOD
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: ATIF
+//
+// Description: ATI GFX Interface.Provides ATI specific GFX functionality on mobile platforms.
+//
+// Input:
+// Arg0: Integer Function code.
+// Arg1: Package Parameter buffer, 256 bytes
+//
+//
+// Output:
+// Returns Buffer, 256 bytes
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(ATIF,2,Serialized)
+ {
+ P8DB(0xAF, Arg0, 2000)
+
+ //
+ // Function 0: Verify Interface
+ //
+ // Returns the interface version and
+ // functions/notifications supported by System BIOS
+ //
+ If(LEqual(Arg0,0))
+ {
+ Name(TMP0,Buffer(256) {0x00})
+ CreateWordField (TMP0, 0, F0SS)
+ CreateWordField (TMP0, 2, F0IV)
+ CreateDwordField (TMP0, 4, F0SN)
+ CreateDwordField (TMP0, 8, F0SF)
+
+ // Size of return structure=12
+ Store(0x000C,F0SS)
+
+ // Interface version
+ Store(0x0001,F0IV)
+
+ // Supported Notifications Mask
+ Store(0x00000041,F0SN) // Display switch request and PowerXpress graphics switch toggle request supported
+// Store(0x00000001,F0SN) //<Overriding as per edited ATIF spec 0.22- only display switch request supported>>
+
+ //Supported Functions Bit Vector
+ Store(0x00000007,F0SF)
+
+ /*
+ // For Muxless: No ATIF Fn supported
+ If(LEqual(SGMD,0x2))
+ {
+ Store(0x00000000,F0SN)
+ Store(0x00000000,F0SF)
+ }
+ */
+ Return(TMP0)
+ }
+
+ //
+ // Function 1: Get System Parameters
+ //
+ // Returns various system parameters
+ //
+ If(LEqual(Arg0,1))
+ {
+ Name(TMP1,Buffer(256) {0x0})
+ CreateWordField (TMP1, 0, F1SS)
+ CreateDwordField (TMP1, 2, F1VF)
+ CreateDwordField (TMP1, 6, F1FG)
+
+ // Size of return structure=10
+ Store(0x000A, F1SS)
+
+ // Valid Fields Mask
+ Store(0x00000003,F1VF)
+
+ // Flags
+ Store(0x00000001,F1FG) // Notify (VGA, 0x81) is used as a general purpose notification
+ Return(TMP1)
+ }
+
+ //
+ // Function 2: Get System BIOS Requests
+ //
+ // Reports pending system BIOS requests
+ //
+ // Invoked whenever driver receives Notify(VGA,0x81) and
+ // the Notify is designated as a general purpose notification
+ // in the function "Get System Parameters"
+ //
+ If(LEqual(Arg0,2))
+ {
+ CreateBitField(PSBR, 0, PDSW) // Display switch request
+ CreateBitField(PSBR, 1, PEXM) // Expansion mode request
+ CreateBitField(PSBR, 2, PTHR) // Thermal state change request
+ CreateBitField(PSBR, 3, PFPS) // Forced power state change request
+ CreateBitField(PSBR, 4, PSPS) // System power state change request
+ CreateBitField(PSBR, 5, PDCC) // Display configuration change request
+ CreateBitField(PSBR, 6, PXPS) // PowerXpress? graphics controller switch request
+ CreateBitField(PSBR, 7, PBRT) // Panel brightness change request //[ODM_Change]2012/08/20 AMD GOP brightness2 WHQL fail.
+ CreateBitField(PSBR, 8, DCSC) // Panel brightness change request //[ODM_Change]2012/08/20 AMD GOP brightness2 WHQL fail.
+
+ CreateWordField(ATIB, 0, SSZE) // Structure size = 12
+ CreateDWordField(ATIB, 2, PSBI) // Pending System BIOS Requests
+ CreateByteField(ATIB, 6, EXPM) // Expansion Mode
+ CreateByteField(ATIB, 7, THRM) // Thermal State: Target Gfx controller
+ CreateByteField(ATIB, 8, THID) // Thermal State: State Id
+ CreateByteField(ATIB, 9, FPWR) // Forced Power State: Target Gfx controller
+ CreateByteField(ATIB, 10, FPID) // Forced Power State: State Id
+ CreateByteField(ATIB, 11, SPWR) // System Power Source
+ CreateByteField (ATIB, 12, BRTL) // Brightness Level //[ODM_Change]2012/08/20 AMD GOP brightness2 WHQL fail.
+
+ Store(13,SSZE)
+ Store(PSBR,PSBI)
+
+ IF(PDSW) {
+ Store(0,PDSW)
+ }
+
+ IF(PEXM) {
+ Store(0,EXPM)
+ Store(0,PEXM)
+ }
+
+ IF(PTHR) {
+ Store(0, THRM)
+ Store(0, THID)
+ Store(0, PTHR)
+ }
+
+ IF(PFPS) {
+ Store(0, PFPS)
+ }
+
+ IF(PSPS) {
+ Store(0, PSPS)
+ }
+
+ IF(PXPS) {
+ Store(0, PXPS)
+ }
+
+ IF(PBRT) {
+ Store(0, PBRT)
+ }
+
+ IF(DCSC) {
+ Store(0, DCSC )
+ }
+
+ Return(ATIB)
+ }
+
+ //
+ // Function 3: Select Active Displays
+ //
+ // Returns displays to be selected in reposnse to
+ // a display switch request notification
+ //
+ If(LEqual(Arg0,3))
+ {
+ Name(TMP3,Buffer(256) {0x0})
+ CreateWordField (TMP3, 0, F3SS)
+ CreateWordField (TMP3, 2, F3SD)
+ CreateWordField(Arg1,0,AI3S)
+ CreateWordField(Arg1,2,SLDS)
+ CreateWordField(Arg1,4,CODS)
+ Store(SLDS,CACD)
+ Store(CODS,CCND)
+
+ If (\ECON)
+ {
+ If(LEqual(PCI_SCOPE.LPCB.H_EC.LSTE,1))
+ {
+ Or(CCND,0x0001,CCND) // ATI does not send LFP as connected when not LFP is not active. This is as per design
+ }
+ }
+
+ // Size of return structure=4
+ Store(0x0004,F3SS)
+
+ // Next Displays to be Selected
+ // Populate next displays based on Currently Connected and Active displays and the Toggle List Index
+ // CCND, CACD, TLSN,
+ Store(CTOI(CACD),TLSN) // Get current toggle index based on currently Active display vector
+ Store(CACD, Local1) // Initialize Local1 to a safe value
+ Store(NTLE, Local0) // Total number of toggle list entries
+ While(Local0)
+ {
+ Store(NATL(TLSN),Local1) // Get the next combination from toggle list into Local1
+
+ If(LNotEqual(Local1, 0)) //If next toggle list entry is not empty, then
+ {
+ If(LEqual(And(Local1,CCND),Local1)) // If entries in the next combination are actually connected..
+ {
+ Store(1,Local0) // Exit since we got the next active list
+ }
+ }
+ Decrement(Local0) // Decrement toggle list sequence counter
+
+ Increment(TLSN) // Increment toggle list number to point to next active list
+ If(LGreater(TLSN, NTLE)) // If sequence index currently points to last entry....
+ {
+ Store(1,TLSN) // Roll-up to the start of the toggle list
+ }
+ }
+ SNXD(Local1) // Set the selected displays as the next active for _DGS
+ Store(Local1,NACD) // The next active toggle list - put it on Opregion
+ Store(NACD,F3SD) // Store it in the return buffer
+ Return(TMP3)
+ }
+
+//<Overriding as per edited ATIF spec 0.22- only Functions 0,1,2,3 supported>
+// //
+// // Function 5: Get TV Standard from CMOS
+// //
+// // Retrieves current TV standard
+// //
+// If(LEqual(Arg0,5))
+// {
+// Name(TMP5,Buffer(256) {0x0})
+// CreateWordField (TMP5, 0, F5SS)
+//
+// // Size of return structure
+// Store(0x0004,F5SS)
+//
+// // TV Standard Encoding Format
+// Store(0x00,Index(TMP5,2))
+//
+// // TV Standard
+// Store(TVSD,Index(TMP5,3))
+//
+// Return(TMP5)
+//
+// }
+ //
+// //
+// // Function 6: Set TV Standard in CMOS
+// //
+// // Records current TV standard in CMOS
+// //
+// If(LEqual(Arg0,6))
+// {
+// Name(TMP6,Buffer(256) {0x0})
+//
+// CreateWordField(Arg1,0,AI6S)
+// CreateByteField(Arg1,2,TSEF)
+// CreateByteField(Arg1,3,TVST)
+//
+// // Records current TV standard in CMOS
+// Store(TVST,TVSD)
+//
+// Return(TMP6)
+//
+// }
+//
+// //
+// // Function 7: Get Panel Expansion Mode from CMOS
+// //
+// // Retrieves built-in panel expansion mode
+// //
+// If(LEqual(Arg0,7))
+// {
+// Name(TMP7,Buffer(256) {0x0})
+// CreateWordField (TMP7, 0 , F7SS)
+//
+// // Size of return structure
+// Store(0x0003,F7SS)
+ //
+// // Expansion Mode
+// Store(EXPM,Index(TMP7,2))
+ //
+// Return(TMP7)
+ //
+// }
+ //
+// //
+// // Function 8: Set Panel Expansion Mode in CMOS
+// //
+// // Records built-in panel expansion mode in CMOS
+// //
+// If(LEqual(Arg0,8))
+// {
+// Name(TMP8,Buffer(256) {0x0})
+ //
+// CreateWordField(Arg1,0,AI8S)
+// CreateByteField(Arg1,2,EMCM)
+ //
+// // Record Expansion Mode in CMOS
+// Store(EMCM,EXPM)
+ //
+// Return(TMP8)
+// }
+ //
+// //
+// // Function 9: Get Selected Displays from CMOS
+// //
+// // Retrieves Selected Displays
+// //
+// If(LEqual(Arg0,9))
+// {
+// Name(TMP9,Buffer(256) {0x0})
+// CreateWordField (TMP5, 0, F9SS)
+// CreateWordField (TMP5, 2, F9SD)
+// CreateWordField (TMP5, 4, F9DV)
+ //
+// // Size of return structure
+// Store(0x0006,F9SS)
+ //
+// // Supported Displays Mask
+// Store(BSPD,F9SD)
+ //
+// // Selected Displays Vector
+// Store(And(BPSD,3),F9DV) // Only LFP, CRT supported by IGD in PX
+ //
+// Return(TMP9)
+// }
+ //
+// //
+// // Function 10: Set Selected Displays in CMOS
+// //
+// // Records Selected Displays in CMOS
+// //
+// If(LEqual(Arg0,0xA))
+// {
+// Name(TMPA,Buffer(256) {0x0})
+ //
+// CreateWordField(Arg1,0,AIAS)
+// CreateWordField(Arg1,2,SDCM)
+ //
+// // Records Selected Displays in CMOS
+// Store(And(SDCM,3),BPSD) // Only LFP, CRT supported by IGD in PX
+ //
+// Return(TMPA)
+// }
+ //
+// //
+// // Function 12: Thermal Change Notification
+// //
+// // GPU temperature threshold related function
+// //
+// If(LEqual(Arg0,0xC))
+// {
+// Name(TMPC,Package() {0xFFFF,0xFFFFFFFF,0xFF,0xFF,0xFF,0xFF})
+//
+// // Size of return structure
+// Store(0x000A,Index(TMPC,0))
+//
+// // Flags
+////<TO DO>check Store(0x00000003,Index(TMPC,1))
+//
+// // High Temperature Threshold
+////<TO DO>check Store(0x00,Index(TMPC,2))
+//
+// // Low Temperature Threshold
+////<TO DO>check Store(0x00,Index(TMPC,3))
+//
+// // Thermal State At High Temperature Threshold
+////<TO DO>check Store(0x00,Index(TMPC,4))
+//
+// // Thermal State At Low Temperature Threshold
+////<TO DO>check Store(0x00,Index(TMPC,5))
+//
+// Return(TMPC)
+// }
+ //
+// //
+// // Function 13: Temperature Change Notification
+// //
+// // GPU temperature threshold related function
+// //
+// If(LEqual(Arg0,0xD))
+// {
+// Name(TMPD,Package() {0xFFFF,0xFFFFFFFF,0xFF,0xFF,0xFF,0xFF})
+// CreateWordField(Arg1,0,AIDS)
+// CreateWordField(Arg1,2,TGCI)
+// CreateByteField(Arg1,4,CGPT)
+ //
+// Return(TMPD)
+// }
+ //
+ // Function 15: Get Graphics Device Types
+ //
+ // This function reports all graphics devices and XGP ports supported by a given platform
+ //
+ If(LEqual(Arg0,0xF))
+ {
+ Name(TMPF,Buffer(256) {0x0})
+ CreateWordField (TMPF, 0, FFND)
+ CreateWordField (TMPF, 2, FFDS)
+ CreateDwordField (TMPF, 4, FFFG)
+ CreateWordField (TMPF, 8, FFBS)
+ CreateWordField (TMPF, 10, FFDV)
+
+
+
+ Return(TMPF)
+ }
+
+
+
+ Return (0)
+ }
+ Name(ATIB, Buffer(0x100){})
+ Name(PSBR, Buffer(0x4){0x00}) // Pending System BIOS Requests. (these get cleared only when function 2 is called)
+ Name(SSPS, 0x00) // Save System Power Source
+ Method(AFN0, 0, Serialized)
+ {
+ CreateBitField(PSBR, 0, PDSW) // Display switch request
+ Store(One, PDSW) // Set the request to pending state
+ Notify(IGPU_SCOPE, 0x81) // Inform the display driver
+ }
+
+
+ Method(AFN4, 1, Serialized) // Arg0: System Power Source
+ {
+ Store(Arg0, Local0)
+ Store(SSPS, Local1)
+ Store(Local0, SSPS)
+ If(LEqual(Local0, Local1))
+ {
+ } Else
+ {
+ CreateBitField(PSBR,0x04,PSPS)
+ Store(One, PSPS)
+ Notify(IGPU_SCOPE, 0x81)
+ }
+ }
+
+ Method(AFN5, 0, Serialized)
+ {
+ CreateBitField(PSBR,0x05,PDCC)
+ Store(One, PDCC)
+ Notify(IGPU_SCOPE, 0x81)
+ }
+
+ Method(AFN6, 0, Serialized)
+ {
+ CreateBitField(PSBR, 6, PXPS) // PowerXpress graphics switch toggle request
+ Store(One, PXPS) // Set the request to pending state
+ Notify(IGPU_SCOPE, 0x81) // Inform the display driver
+ }
+
+ Method(AFN7, 1, Serialized) // Arg0: Panel Brightness: Backlight Level
+ {
+ CreateBitField(PSBR, 7, PBRT) // Brightness level change request
+ Store(One, PBRT) // Pending brightness level request
+
+ CreateByteField(ATIB, 12, BRTL) // Brightness Level
+ Store(Arg0, BRTL) // Brightness level
+ Notify(IGPU_SCOPE, 0x81)
+ }
+
+ Method(AFN8, 0, Serialized)
+ {
+ CreateBitField(PSBR, 8, DCSC) // Discrete GPU display connect state change request
+ Store(One, DCSC) // Pending brightness level request
+ Notify(IGPU_SCOPE, 0x81)
+ }
+
+ Method(CTOI,1)
+ {
+ If(LNotEqual(NTLE, Zero))
+ {
+ If(LEqual(TLE1, Arg0))
+ {
+ Return(1)
+ }
+ If(LEqual(TLE2, Arg0))
+ {
+ Return(2)
+ }
+ If(LEqual(TLE3, Arg0))
+ {
+ Return(3)
+ }
+ If(LEqual(TLE4, Arg0))
+ {
+ Return(4)
+ }
+ If(LEqual(TLE5, Arg0))
+ {
+ Return(5)
+ }
+ If(LEqual(TLE6, Arg0))
+ {
+ Return(6)
+ }
+ If(LEqual(TLE7, Arg0))
+ {
+ Return(7)
+ }
+ If(LEqual(TLE8, Arg0))
+ {
+ Return(8)
+ }
+ If(LEqual(TLE9, Arg0))
+ {
+ Return(9)
+ }
+ If(LEqual(TL10, Arg0))
+ {
+ Return(10)
+ }
+ If(LEqual(TL11, Arg0))
+ {
+ Return(11)
+ }
+ If(LEqual(TL12, Arg0))
+ {
+ Return(12)
+ }
+ If(LEqual(TL13, Arg0))
+ {
+ Return(13)
+ }
+ If(LEqual(TL14, Arg0))
+ {
+ Return(14)
+ }
+ If(LEqual(TL15, Arg0))
+ {
+ Return(15)
+ }
+ }
+ Return(1) //If no match, then set TLSN to 1
+ }
+
+ Method(NATL,1)
+ {
+ If(LNotEqual(NTLE, Zero))
+ {
+ If(LEqual(Arg0,1))
+ {
+ Return(TLE2)
+ }
+ If(LEqual(Arg0,2))
+ {
+ Return(TLE3)
+ }
+ If(LEqual(Arg0,3))
+ {
+ Return(TLE4)
+ }
+ If(LEqual(Arg0,4))
+ {
+ Return(TLE5)
+ }
+ If(LEqual(Arg0,5))
+ {
+ Return(TLE6)
+ }
+ If(LEqual(Arg0,6))
+ {
+ Return(TLE7)
+ }
+ If(LEqual(Arg0,7))
+ {
+ Return(TLE8)
+ }
+ If(LEqual(Arg0,8))
+ {
+ Return(TLE9)
+ }
+ If(LEqual(Arg0,9))
+ {
+ Return(TL10)
+ }
+ If(LEqual(Arg0,10))
+ {
+ Return(TL11)
+ }
+ If(LEqual(Arg0,11))
+ {
+ Return(TL12)
+ }
+ If(LEqual(Arg0,12))
+ {
+ Return(TL13)
+ }
+ If(LEqual(Arg0,13))
+ {
+ Return(TL14)
+ }
+ If(LEqual(Arg0,14))
+ {
+ Return(TL15)
+ }
+ If(LEqual(Arg0,15))
+ {
+ Return(TLE1)
+ }
+ }
+ Return(0)
+ }
+} // end PCI0.GFX0 scope
+
+
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/AtiSSDT.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/AtiSSDT.asl
new file mode 100644
index 0000000..5264ff1
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/AtiSSDT.asl
@@ -0,0 +1,143 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/AtiSSDT.asl 1 1/15/13 5:58a Joshchou $
+//
+// $Revision: 1 $
+//
+// $Date: 1/15/13 5:58a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/AtiSSDT.asl $
+//
+// 1 1/15/13 5:58a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Create componet for SG support on PEG
+// [Files] SgAti.cif
+// AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+//
+// 2 9/09/12 11:02p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+// SgAti.cif
+//
+// 2 12/22/11 6:36a Alanlin
+// Declared "defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)"
+//
+// 1 6/27/11 5:26a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgAti.cif
+// AtiSSDT.asl
+// ATdGPU.asl
+// ATiGPU.asl
+// ATiGDmisc.asl
+//
+//
+// 3 11/12/10 1:22p Alexp
+// include "token.h" inside the command line to CL preprocessor in
+// SgAcpiTable.mak
+//
+// 2 10/05/10 7:09p Alexp
+// Added debug macro to be able to insert include check points in target
+// ASL code
+//
+// 1 9/17/10 1:20p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgAti.cif;
+// AtiSSDT.asl; ATdGPU.asl;ATiGPU.asl;ATiGDmisc
+//
+// 1 6/08/10 3:45p Alexp
+//
+// 1 6/03/10 2:56p Alexp
+//
+// 1 7/16/09 11:17a Alexp
+// Added SG support for AMD ATI Gfx adaptors
+//
+//
+//**********************************************************************
+
+DefinitionBlock (
+ "Amd.aml",
+ "SSDT",
+ 1,
+ "AmdRef",
+ "AmdTabl",
+ 0x1000
+ ){
+
+External(P8XH, MethodObj)
+#if defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)
+#define P8DB(arg0, arg1, arg2) P8XH (0, arg1) P8XH (1, arg0) sleep(arg2)
+#else
+#define P8DB(arg0, arg1, arg2)
+#endif
+
+External(PCI_SCOPE, DeviceObj)
+External(PEG_SCOPE, DeviceObj)
+External(DGPU_SCOPE, DeviceObj)
+External(IGPU_SCOPE, DeviceObj)
+External(DGPU_SCOPE._ADR, DeviceObj)
+External(DGPU_SCOPE.SGST, MethodObj)
+External(DGPU_SCOPE.SGON, MethodObj)
+External(DGPU_SCOPE.SGOF, MethodObj)
+External(DGPU_SCOPE.SGPI, MethodObj)
+External(DGPU_SCOPE.SGPO, MethodObj)
+External(\DSEL)
+External(\ESEL)
+External(\SSEL)
+External(\PSEL)
+External(\HLRS)
+External(\PWEN)
+External(\PWOK)
+
+#include <ATdGPU.ASL> // Include dGPU device namespace
+#include <ATiGPU.ASL> // Include IGD _DSM and AMD ATIF/ATPM/ATRM methods
+#include <ATiGDmisc.ASL> // Include misc event callback methods
+
+} // end SSDT
+
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NVdGPU.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NVdGPU.asl
new file mode 100644
index 0000000..0359b5e
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NVdGPU.asl
@@ -0,0 +1,806 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NVdGPU.asl 4 3/21/13 3:55a Joshchou $
+//
+// $Revision: 4 $
+//
+// $Date: 3/21/13 3:55a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NVdGPU.asl $
+//
+// 4 3/21/13 3:55a Joshchou
+// [TAG] EIP115355
+// [Category] Bug Fix
+// [Severity] Minor
+// [Symptom] NV HD audio did not disable
+// [RootCause] 0x488 [25] is not disable.
+// [Solution] Clear this bit in _PS0 method and _on method.
+//
+// 3 2/21/13 5:35a Joshchou
+// [TAG] EIP106524
+// [Category] New Feature
+// [Description] Support GC6 function for Optimus.
+//
+// 2 2/07/13 3:12a Joshchou
+// [TAG] EIP111393
+// [Category] Bug Fix
+// [Severity] Minor
+// [Symptom] Shows Error Event ACPI (ID 10) in Win8 event viewer
+// [RootCause] We use PCI_CONFIG to save/restore registers.
+// [Solution] Change to use MMIO to save/restore registers.
+//
+// 1 1/15/13 5:58a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Create componet for SG support on PEG
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 7 12/22/12 2:32a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Update for SA RC 0.8.1.
+// Since RC has saved and restored registers,
+// do not have to save/restore register here.
+//
+// 6 12/12/12 4:20a Joshchou
+// [TAG] EIP108203
+// [Category] Bug Fix
+// [Severity] Important
+// [Symptom] Optimus function can not work normally
+//
+// 5 10/19/12 8:22a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Save/restore TC/VC remapping setting register
+// [Files] NVdGPU.asl
+//
+// 4 10/16/12 4:37a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] save/store PCIE NV PCI register from 0 to 256 byte by
+// Dword access while do _ON & OFF for NV SG
+// [Files] NVdGPU.asl
+//
+// 2 9/09/12 11:04p Joshchou
+// [TAG] EIPNone
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 6 12/26/11 4:59a Alanlin
+// 1.Change OperationRegion of BPCI access type from "AnyAcc" to
+// "DWordAcc" for nVidia VGA.
+//
+//
+// 4 12/22/11 6:28a Alanlin
+// [Category] Bug Fix
+// [Description] Fixed NV dGPU Driver has yellow mark when OS is Win7
+// x32.
+//
+// 3 12/02/11 5:36a Alanlin
+// [TAG] EIP75211
+// [Category] Improvement
+// [Description] 1.Following nVidia's suggestion to change
+// OperationRegion access type from "AnyAcc" to "DWordAcc" for nVidia new
+// chip.
+// 2.Changeing VBIOS size to 128k for _ROM method for nVidia chip.
+//
+// 2 10/06/11 11:08p Alanlin
+// [Category] Improvement
+// [Description] Fixed build error when MXM30_SUPPORT = 0.
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+//
+//
+// 7 3/17/11 6:17p Alexp
+// Optimus:Add code to preserve HD AudioCodec enable flag in CMOS
+//
+// 6 1/03/11 12:29p Alexp
+// [TAG] EIP50104
+// [Category] Improvement
+// [Description] optimize PCI context save/restore in DGPU._OFF() method
+// [Files] NVdGPU.asl
+//
+// 5 11/11/10 3:15p Alexp
+// Bug Fix: DGPU_SCOPE._ON - remove write to Link train bit field RETR
+// that was redefined in SgDGPU.asl
+// Optimization: Move Optimus _DSM functions to NviGPU.asl
+//
+// 4 10/08/10 1:49p Alexp
+// re-arrange check point messages
+//
+// 3 10/06/10 3:34p Alexp
+// Include defines for different Nvidia GUID functions. Helps to control
+// inclusion of peices of ASL depending on type of desired SG mode
+//
+// 2 10/05/10 7:14p Alexp
+// 1. Added debug macro to be able to insert check points in target ASL
+// code
+// 2. Reuse NVdGPU.asl file to build OpSSDT for Optimus and NvSSDT for
+// MUXed SG targets.
+// NvOptimus.asl no longer required
+//
+// 1 9/17/10 1:21p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgNvidia.cif;
+// NvSSDT.asl; NVdGPU.asl;NViGPU.asl;NViGDmisc
+// OpSSDT.asl;NvOptimus.asl;NvVenture.asl
+//
+//**********************************************************************
+// PEG Endpoint PCIe Base Address.
+External(EBAS)
+External(NVHA)
+
+#ifdef OPTIMUS_DSM_GUID
+Scope(PCI_SCOPE){
+
+ Name(OTM, "OTMACPI 2010-Mar-09 12:08:26") // OTMACPIP build time stamp.
+} // end of Scope
+#endif
+
+Scope(DGPU_SCOPE)
+{
+//<AMI_SHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: PCI2
+//
+// Description: For save/store PCIE NV PCI register from 0 to 256 byte by Dword access while do _ON & OFF
+//
+//-------------------------------------------------------------------------
+//<AMI_SHDR_END>
+ OperationRegion (PCI2, SystemMemory, EBAS, 0x500)
+ Field(PCI2, DWordAcc, Lock, Preserve)
+ {
+ Offset(0x4),
+ CMDR, 8,
+ VGAR, 2000,
+ Offset(0x48B),
+ , 1,
+ NHDA, 1,
+ }
+ Name(VGAB, Buffer(0xFA)
+ {
+ 0x00
+ })
+ Name(GPRF, Zero)
+
+//<AMI_SHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: NVHM
+//
+// Description: Nvidia NVHG (dGPU) OperationRegion
+// OpRegion address (NVHA)is defined in IDG Nvs OpRegion
+//
+//-------------------------------------------------------------------------
+//<AMI_SHDR_END>
+ OperationRegion(NVHM,SystemMemory, NVHA, 0x20400)
+ Field(NVHM, DWordAcc, NoLock, Preserve)
+ {
+ // OpRegion Header
+
+ NVSG, 0x80, // (000h) Signature-"NVSG".
+ NVSZ, 0x20, // (010h) OpRegion Size in KB.
+ NVVR, 0x20, // (014h) OpRegion Version.
+
+ // NVHG data
+
+ NVHO, 0x20, // (018h)NVHM opregion address
+ RVBS, 0x20, // (01Ch)NVIDIA VBIOS image size
+ // (020h)for _ROM
+ RBF1, 0x40000, // 0x8000 bytes in bits
+ RBF2, 0x40000, // 0x8000 bytes in bits
+ RBF3, 0x40000, // 0x8000 bytes in bits
+ RBF4, 0x40000, // 0x8000 bytes in bits
+ MXML, 0x20, // Mxm3 buffer length
+#if MXM30_SUPPORT
+ MXM3, MXM_ROM_MAX_SIZE_bits // MXM 3.0 Data buffer
+#else
+ MXM3, 0x640 // MXM 3.0 Data buffer
+#endif
+
+ }
+
+ Name(OPCE, 2) // Optimus Power-Control ENABLE
+ // 2: The platform should not power down the GPU subsystem
+ // in the _PS3 method (Default)
+ // 3: The platform should power down the GPU subsystem
+ // at the end of the _PS3 ACPI method
+
+ Name(DGPS, Zero)// Power State. dummy control field. Can be a GPIO in EC or PCH
+
+#ifdef OPTIMUS_DSM_GUID
+
+//If dGPU power control is available....
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _PSC
+//
+// Description: Curent dGPU power state, 0-D0, 3-D3, etc.
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Name(_PSC, Zero)
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _PS0
+//
+// Description: dGPU power ON control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(_PS0, 0, NotSerialized)
+ {
+ P8DB(0xB0, OPCE, 2000)
+ Store(0x0,NHDA) //NV HDMI audio did not need enable
+ Store(Zero, _PSC)
+ If(LNotEqual(DGPS, Zero))
+ {
+ _ON() // with Optimus w/a
+ Store(Zero, DGPS)
+ }
+ }
+
+ Method(_PS1, 0x0, NotSerialized)
+ {
+ Store(One, _PSC)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _PS3
+//
+// Description: dGPU power OFF control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(_PS3, 0, NotSerialized)
+ {
+ P8DB(0xB3, OPCE, 2000)
+ If(LEqual(OPCE, 0x3))
+ {
+ If(LEqual(DGPS, Zero))
+ {
+ _OFF() // w Optimus w/a
+ Store(One, DGPS)
+ }
+ Store(0x2, OPCE) // Reset NV GPU power down flag
+ }
+ Store(0x3, _PSC)
+ }
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _STA
+//
+// Description: dGPU power status.
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_STA,0x0)
+ {
+ Return(0x0F) // Always return DGPU is powered-ON
+ }
+
+#endif // OPTIMUS_DSM_GUID
+
+#if HYBRID_DSM_GUID || MXM_DSM_GUID
+// NON-OPTIMUS mode - MUXed
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _IRC
+//
+// Description: In-rush current
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+// Name(_IRC, 0)
+ Method(_IRC,0,Serialized)
+ {
+ Return(0x00)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _ON
+//
+// Description: dGPU power ON control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_ON,0,Serialized)
+ {
+ SGON() // OEM Mxm Power On
+ //Ask OS to do a PnP rescan
+ Notify(PEG_SCOPE,0)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _OFF
+//
+// Description: dGPU power OFF control method
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_OFF,0,Serialized)
+ {
+ SGOF() // OEM Mxm Power On
+
+ //Ask OS to do a PnP rescan
+ Notify(PEG_SCOPE,0)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _STA
+//
+// Description: Returns curent dGPU power/presence state
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_STA,0,Serialized)
+ {
+ Return(SGST()) // OEM Mxm Power status
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: MXMX
+//
+// Description: Display DDC Mux Control
+//
+// Input:
+// Arg0: Get/Set DDC/Aux Mux State
+// 0- Acquire DDC/Aux Mux on this GPU
+// 1- Release Mux from this GPU
+// 2- Get Mux state
+//
+// Output:
+// 0, Not Acquired.
+// if Arg0 = 0 or 1, Non-Zero return indicates success acquiring MUX
+// (and MUX has switched to this output)
+// if Arg0 = 2, Non-Zero return indicates MUX is currently set to this output
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (MXMX, 1, Serialized)
+ {
+ P8DB(0x99, Arg0, 2000)
+
+ If (LEqual (Arg0, 0))
+ {
+
+ //Acquire DDC/AUX mux
+ // No mutex implemented. No need to acquire mutex.
+ // Set mux to dGPU
+// SGPO(DSEL, 1)// dGPU_SELECT#
+ SGPO(ESEL, 1)// use EDID_SELECT# as Mutex flag
+ Return(1)
+ }
+
+ If (LEqual (Arg0, 1))
+ {
+
+ //Release DDC/AUX mux
+ // No mutex implemented. No need to release mutex.
+ // 2-way mux. Hence no need to do anything
+ Return(0x1)
+
+ }
+
+ If (LEqual (Arg0, 2))
+ {
+
+ //Get ddc/aux mux status for dGPU
+ Return(SGPI(ESEL))
+ }
+
+ Return(0x0) // mutex not acquired
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: MXDS
+//
+// Description: Display output MUX control
+//
+// Input:
+// Arg0:
+// 0 - Get Mux state
+// 1 - Set Display to active on this GPU
+// 2 - Set Backlight control to active on this GPU
+// 3 - Set Display & Backlight to active on this GPU
+//
+// Output:
+// If Arg0 = 0, Error = Display is not MUXed
+// Else return value of the state of the MUX
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(MXDS, 1, Serialized)
+ {
+ P8DB(0x9A, Arg0, 2000)
+
+ If(LEqual (Arg0, 0))
+ {
+ //Get display mux status for dGPU
+ return(SGPI(DSEL))
+ } else
+// If(LOr(LEqual (Arg0, 1), LEqual (Arg0, 2)))
+ {
+ //Set display mux to dgpu
+ SGPO(DSEL, 1) // dGPU_SELECT
+ SGPO(PSEL, 1) // dGPU_PWM_SELECT
+ }
+
+ Return (0)
+ }
+#endif // MXM && HYBRID
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _ROM
+//
+// Description: Video ROM data buffer
+//
+// Input:
+// Arg0: Integer Offset of the graphics device ROM data
+// Arg1: Integer Size of the buffer to fill in (up to 4K)
+//
+// Output:
+// Buffer Buffer of requested video ROM bytes
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_ROM,2)
+ {
+
+ Store (Arg0, Local0)
+ Store (Arg1, Local1)
+
+ P8DB(0x44, Local1, 100)
+// CreateWordField (RBF1, 2, RVBS) // Vbios image size
+// ShiftLeft(And(RVBS,0xff), 9, RVBS) // size in Bytes (* 512)
+
+ If (LGreater (Local1, 0x1000))
+ {
+ Store (0x1000, Local1)
+ }
+ If (LGreater (Local0, 0x20000))
+ {
+ Return(Buffer(Local1){0})
+ }
+// If (LGreater (Local0, RVBS))
+// {
+// Return(Buffer(Local1){0})
+// }
+//// If (LGreater (Add (Local0, Local1), RVBS))
+//// {
+//// Store (0x00, Local0)
+//// }
+
+ Multiply (Local1, 0x08, Local3)
+ Name (ROM1, Buffer (0x8000) {0})
+ Name (ROM2, Buffer (Local1) {0})
+
+ If(LLess(Local0, 0x8000)){
+ Store(RBF1, ROM1)
+ }
+ ElseIf(LLess(Local0, 0x10000)){
+ Subtract(Local0,0x8000,Local0)
+ Store(RBF2, ROM1)
+ }
+ ElseIf(LLess(Local0, 0x18000)){
+ Subtract(Local0,0x10000,Local0)
+ Store(RBF3, ROM1)
+ }
+ ElseIf(LLess(Local0, 0x20000)){
+ Subtract(Local0,0x18000,Local0)
+ Store(RBF4, ROM1)
+ }
+
+ Multiply (Local0, 0x08, Local2)
+ CreateField (ROM1, Local2, Local3, TMPB)
+ Store (TMPB, ROM2)
+ Return (ROM2)
+ }
+
+//
+// Check for Nvidia _DSM UUIDs
+//
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HDSM
+//
+// Description: Device Specific Methods for Hybrid dGPU (may be invoked from iGD as well)
+// Implements Mxm and SG specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// nVidia
+// MXM dGPU GUID :9D95A0A0-0060-4D48-B34D-7E5FEA129FD4
+//
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(HDSM, 4, SERIALIZED)
+ {
+
+#ifdef MXM_DSM_GUID
+
+ If(LEqual(Arg0, ToUUID("4004A400-917D-4cf2-B89C-79B62FD55665")))
+ {
+
+ P8DB(0xEE, Arg2, 1000)
+
+ Switch(ToInteger(Arg2))
+ {
+ //
+ // Function 0: MXM_FUNC_MXSS
+ //
+ case (0)
+ {
+ //Sub-Functions 0,16,24 are supported
+ Return(ToBuffer(0x01010001))
+ }
+
+ //
+ // Function 24: MXM_FUNC_MXMI
+ //
+ case (24)
+ {
+ Return(ToBuffer(0x300)) // MXM 1.101 defines revision as 0x300
+ // Return(ToBuffer(0x30)) // MXM 1.101 defines revision as 0x300
+ }
+
+ //
+ // Function 16: MXM_FUNC_MXMS
+ //
+ case (16)
+ {
+ If(LEqual (Arg1, 0x300)) // MXM 1.101 defines revision as 0x300
+ {
+#if MXM30_SUPPORT
+ // calculate true length of MXM block
+ CreateWordField(MXM3, 6, MXLN)
+ Add(MXLN, 8, Local0) // Add length of MXM header
+ CreateField(MXM3, 0, Local0, MXM)
+ Return(ToBuffer(MXM))
+#else
+ // ElkCreek 4 Mxm data structure
+ Name(MXM3, Buffer()
+ {
+ 0x4d, 0x58, 0x4d, 0x5f, 0x03, 0x00, 0x5d, 0x00,
+ 0x30, 0x11, 0xb8, 0xff, 0xf9, 0x3e, 0x00, 0x00,
+ 0x00, 0x00, 0x0a, 0xf0, 0xf9, 0x3e, 0x00, 0x00,
+ 0x60, 0xe9, 0xd0, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x60, 0x6a, 0xda, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x20, 0x2b, 0xe2, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x60, 0x6c, 0xea, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x20, 0x6a, 0xda, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x20, 0x6c, 0xea, 0xfe, 0xf9, 0x3e, 0x00, 0x00,
+ 0x01, 0x90, 0x01, 0x00, 0x03, 0x00, 0x90, 0x01,
+ 0x13, 0x00, 0x90, 0x01, 0xe5, 0x0d, 0x01, 0x01,
+ 0x01, 0x00, 0x00, 0x00, 0xe5, 0x0d, 0x01, 0x03,
+ 0x00, 0x90, 0xd8, 0x09, 0x11, 0x0a
+ })
+ Return(MXM3)
+#endif
+ }
+ }
+ } // switch
+ Return(0x80000002) //MXM_ERROR_UNSUPPORTED - FunctionCode or SubfunctionCode not supported
+ } // "4004A400-917D-4cf2-B89C-79B62FD55665"
+
+#endif // MXM_DSM_GUID
+
+ Return (0x80000001) //MXM_ERROR_UNSPECIFIED
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _DSM Device Specific Method for dGPU device
+//
+// Description: Implement Mxm and SG specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// MXM dGPU GUID :9D95A0A0-0060-4D48-B34D-7E5FEA129FD4
+// NBCI GUID :D4A50B75-65C7-46F7-BfB7-41514CEA0244
+// Ventura GUID :95DB88FD-940A-4253-A446-70CE0504AEDF
+// Optimus DSM_GUID :A486D8F8-0BDA-471B-A72B-6042A6B5BEE0
+//
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(_DSM,4,SERIALIZED)
+ {
+ CreateByteField (Arg0, 3, GUID)
+ P8DB(0xDD, GUID, 1000)
+ //
+ // Check for Nvidia _DSM UUIDs
+ //
+ // common _DSM for dGPU and iGPU: NBCI, SG DSM, Ventura
+ return(IGPU_SCOPE.HDSM(Arg0, Arg1, Arg2, Arg3))
+ }
+
+
+#ifdef OPTIMUS_DSM_GUID
+// TEST !!! TEST !!! TEST !!!!
+// NvOptimus should not be be using _ON and _OFF methods for power cycling
+// Used here for testing with Intel ElkCreek Mxm interposer
+//
+ Name(CTXT, Zero)// Save Context flag
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _ON
+//
+// Description: Optimus w/a for before dGPU _ON
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(_ON, 0, Serialized)
+ {
+ P8DB(0x01, 0x11, 2000)
+ // OEM Mxm Power status
+ SGON()
+
+// Nvidia Optimus driver w/a. Restore saved PCI context of PEG Video card
+// Skip restore resource if GPRF = 1
+ If(LNotEqual(GPRF, One))
+ {
+ Store(CMDR,local0)
+ Store(Zero, CMDR)
+ Store(VGAB, VGAR)
+ Store(0x06, CMDR)
+ Store(0x0,NHDA) //NV HDMI audio did not need enable
+ Store(local0,CMDR)
+ }
+
+// Store(1, RETR) // retrain PCI-E bus
+//+<
+// doesn't look like we need delay here...
+// Sleep(0x64)
+
+ Store(SWSMI_NVOEM_CMOS_R, SSMP) // Read CMOS:AudioCodec flag to AcpiNvs:SGFL
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: _OFF
+//
+// Description: Optimus w/a before dGPU _OFF
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+ Method(_OFF, 0, Serialized)
+ {
+
+ P8DB(0x0F, 0xFF, 2000)
+// store PCI context only once
+ If(LEqual(CTXT, Zero))
+ {
+// Nvidia Optimus driver w/a. Save PCI context of PEG Video card
+ //+ for GC6 , need to de-assert EC FB_CLAMP
+
+ //-
+ // Skip restore resource if GPRF = 1
+ If(LNotEqual(GPRF, One))
+ {
+ Store(VGAR, VGAB)
+
+ }
+//+<
+ Store(1, CTXT)
+ }
+
+ SGOF()
+
+ }
+#endif
+} // end Scope(DGPU_SCOPE)
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NViGDmisc.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NViGDmisc.asl
new file mode 100644
index 0000000..e81c4a6
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NViGDmisc.asl
@@ -0,0 +1,306 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NViGDmisc.asl 1 1/15/13 5:59a Joshchou $
+//
+// $Revision: 1 $
+//
+// $Date: 1/15/13 5:59a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NViGDmisc.asl $
+//
+// 1 1/15/13 5:59a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Create componet for SG support on PEG
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 2 9/09/12 11:04p Joshchou
+// [TAG] EIPNone
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+//
+//
+// 4 11/12/10 1:27p Alexp
+// Change IDAB method: invoke IGD_SCOPE.IDAB is it's defined
+//
+// 3 10/08/10 12:04p Alexp
+// code clean up: removed unused externs
+//
+// 2 10/05/10 7:14p Alexp
+// 1. Added debug macro to be able to insert check points in target ASL
+// code
+// 2. Reuse NVdGPU.asl file to build OpSSDT for Optimus and NvSSDT for
+// MUXed SG targets.
+// NvOptimus.asl no longer required
+//
+// 1 9/17/10 1:21p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgNvidia.cif;
+// NvSSDT.asl; NVdGPU.asl;NViGPU.asl;NViGDmisc
+// OpSSDT.asl;NvOptimus.asl;NvVenture.asl
+//
+// 1 6/08/10 3:45p Alexp
+//
+// 1 6/03/10 2:54p Alexp
+//
+// 6 10/05/09 5:35p Alexp
+// updated asl code for Ati and Nvidia according to Calpella SG BWG 1.1
+//
+// 5 8/20/09 7:08p Alexp
+// upgraded Ati and Nvidia SSDT Asl files to match latest Acpi code drop
+// #68
+//
+// 4 8/10/09 4:21p Alexp
+// changed with latest reference code from Intel MPG. not yet tested
+//
+// 3 7/16/09 11:17a Alexp
+// Added SG support for AMD ATI Gfx adaptors
+//
+//
+//**********************************************************************
+
+External(DSEN)
+External(IGPU_SCOPE.CDCK)
+External(DGPU_SCOPE.DD02)
+External(IGPU_SCOPE.IDAB, MethodObj)
+
+//Do not remove this function.
+Method(IDAB, 0, Serialized)
+{
+ If (CondRefOf(IGPU_SCOPE.IDAB))
+ {
+ IGPU_SCOPE.IDAB()
+ }
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HGAS
+//
+// Description: HG Adaptor select, notify
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HGAS) //HG Adaptor select
+{
+ //Stateless button/Hotkey supporting 3 states - Power Saver, Adaptive and Perf
+
+ Increment(IGPU_SCOPE.GPSS)
+ Mod(IGPU_SCOPE.GPSS, 3, IGPU_SCOPE.GPSS)
+
+ Store(1,IGPU_SCOPE.GPPO)
+ Store(1,IGPU_SCOPE.SGNC) //indicate 'policy select' change
+
+ Notify(IGPU_SCOPE, 0xD0)
+ Notify(PCI_SCOPE.WMI1, 0xD0) // Mirror Notify on WMI1
+
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HBRT
+//
+// Description: Send backlight notifications to the DGPU LFP device
+// This is required for Win7 and is backward compatible with Vista
+//
+// Input: Arg0 - 4 - Brightnes Down, 3- Up
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HBRT, 1 , Serialized)
+{
+ Store(Arg0,IGPU_SCOPE.DACE)
+
+ If(And(4,DSEN)) //Note: DSEN variable is expected to be set by IGD miniport only.
+ {
+ If(LEqual(Arg0,4))
+ {
+ Notify(DGPU_SCOPE.DD02,0x87) //Note: DD02 is hardcoded as the LFP device in intelgfx.asl
+ }
+ If(LEqual(Arg0,3))
+ {
+ Notify(DGPU_SCOPE.DD02,0x86)
+ }
+ }
+
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HPFS
+//
+// Description: Panel Fitting Hot Key
+//
+// Input: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HPFS, 0, Serialized) //Panel Fitting Hot Key
+{
+ //
+ // HG Handling of Panel Fitting Switch
+ //
+
+ Store(5,IGPU_SCOPE.DACE) // Indicate display scaling hot key event
+ Store(2,IGPU_SCOPE.SGNC) // Indicate platpolicy change
+
+ //
+ // Expansion Mode toggling
+ //
+ Increment(IGPU_SCOPE.GPSP)
+ Mod(IGPU_SCOPE.GPSP, 4 , IGPU_SCOPE.GPSP)
+
+ Notify(IGPU_SCOPE,0xDC)
+
+}
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HNOT
+//
+// Description: Notification handler for Switchable graphics. Called from GNOT()
+//
+// Input: Arg0 = Current event type:
+// 1 = display switch
+// 2 = lid
+// 3 = dock (!!!!!Acpi ref code, Method(GDCK)sends 4 for Dock notifications )
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method (HNOT, 1, Serialized)
+{
+ Switch(ToInteger(Arg0))
+ {
+ case(1) //Display Switch event
+ {
+ Store(3,IGPU_SCOPE.SGNC) // indicate 'Displaystatus' change
+ Store(1,IGPU_SCOPE.DACE)
+ Notify(IGPU_SCOPE, 0x80)
+ Notify(PCI_SCOPE.WMI1, 0x80) // Mirror Notify on WMI1
+ }
+
+ case (2) //Lid switch event
+ {
+ //Note: NV clarified that only LDES needs to be set
+ Store(1,IGPU_SCOPE.LDES)
+ Notify(IGPU_SCOPE, 0xDB)
+ Notify(PCI_SCOPE.WMI1, 0xDB) // Mirror Notify on WMI1
+ }
+// case (3) //Dock event
+ case (4) //Dock event (!!!Acpi ref code, Method(GDCK)sends 4 for Dock notifications)
+ {
+ Store(IGPU_SCOPE.CDCK, IGPU_SCOPE.DKST) // Store the current dock state
+ Notify(IGPU_SCOPE, 0x81)
+ Notify(PCI_SCOPE.WMI1, 0x81) // Mirror Notify on WMI1
+ }
+
+ Default
+ {
+ Notify(IGPU_SCOPE,0x80)
+ }
+
+ }
+
+}
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: CHPS
+//
+// Description: Shows current Hybrid Policy status on Port80 header
+// Adaptive -> 1, Save power -> 2 and High performance -> 3
+//
+// Input: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(CHPS)
+{
+ P8DB(0xEC, Add(IGPU_SCOPE.GPSS, 1), 2000)
+}
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HDOS
+//
+// Description: Check if the _DOS flag was set during the hot key handling
+//
+// Input: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+Method(HDOS, 0, Serialized)
+{
+ If(LEqual(IGPU_SCOPE.DOSF,1))
+ {
+ Store(1,IGPU_SCOPE.SGNC) // indicate 'policy select' change
+ Notify(IGPU_SCOPE,0xD0)
+ Notify(PCI_SCOPE.WMI1, 0xD0) // Mirror Notify on WMI1
+ Store(0, IGPU_SCOPE.DOSF) // Clear the DOSF
+ }
+}
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NViGPU.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NViGPU.asl
new file mode 100644
index 0000000..2410021
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NViGPU.asl
@@ -0,0 +1,1108 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NViGPU.asl 2 2/21/13 5:36a Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 2/21/13 5:36a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NViGPU.asl $
+//
+// 2 2/21/13 5:36a Joshchou
+// [TAG] EIP106524
+// [Category] New Feature
+// [Description] Support GC6 function for Optimus.
+//
+// 1 1/15/13 5:59a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Create componet for SG support on PEG
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 3 12/22/12 2:34a Joshchou
+// [TAG] None
+// [Category] Bug Fix
+// [Severity] Important
+// [Symptom] Sometimes boot to OS will BSOD on customer's platform.
+// [RootCause] The NVIG's structure dose not match with the real size.
+// [Solution] Fix the structure size.
+//
+// 2 9/09/12 11:04p Joshchou
+// [TAG] EIPNone
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 6 4/11/12 3:54a Alanlin
+// [TAG] EIP82808
+// [Category] Improvement
+// [Description] nVidia GPS function improvement.
+// [Files] Board\EM\SgTpv\AcpiTables\SgTpvAcpiTables.sdl
+// Board\EM\SgTpv\AcpiTables\NvGPS.asl
+// Board\EM\SgTpv\AcpiTables\NViGPU.asl
+//
+// 5 12/02/11 5:37a Alanlin
+// [TAG] EIP75211
+// [Category] Improvement
+// [Description] Following nVidia's suggestion to change OperationRegion
+// access type from "AnyAcc" to "DWordAcc" for nVidia new chip.
+//
+// 4 12/02/11 1:00a Alanlin
+// [TAG] EIP75359
+// [Category] Improvement
+// [Description] 1.Fixed \_SB_.PCI0.GFX0.HDSM method can't be
+// unassembled if use windebug utility to check it.
+// 2.Fixed _DSM sub function 0x1B will report "Unexpected argument type"
+// message if use windebug utility to check it.
+//
+// 2 10/14/11 2:59a Alanlin
+// [TAG] EIP64451
+// [Category] New Feature
+// [Description] Optimus GPS feature update
+// [Files] NvSSDT.asl
+// NViGPU.asl
+// OpSSDT.asl
+// NvGPS.asl
+// SgNvidia.cif
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+//
+//
+// 7 3/17/11 6:17p Alexp
+// Optimus:Add code to preserve HD AudioCodec enable flag in CMOS
+//
+// 6 11/12/10 1:28p Alexp
+// bring back the field ELCL to hold the Link Control register value. Not
+// used as it's overriden in SG Reference Code in SgDGPU.asl
+//
+// 5 11/11/10 3:15p Alexp
+// Optimization: bring Optimus _DSM functions from NvdGPU.asl
+//
+// 4 10/08/10 1:50p Alexp
+// re-arrange debug messages
+//
+// 3 10/06/10 3:34p Alexp
+// Include defines for different Nvidia GUID functions. Helps to control
+// inclusion of peices of ASL depending on type of desired SG mode
+//
+// 2 10/05/10 7:14p Alexp
+// 1. Added debug macro to be able to insert check points in target ASL
+// code
+// 2. Reuse NVdGPU.asl file to build OpSSDT for Optimus and NvSSDT for
+// MUXed SG targets.
+// NvOptimus.asl no longer required
+//
+// 1 9/17/10 1:21p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgNvidia.cif;
+// NvSSDT.asl; NVdGPU.asl;NViGPU.asl;NViGDmisc
+// OpSSDT.asl;NvOptimus.asl;NvVenture.asl
+//
+//**********************************************************************
+External(NVGA)
+
+External(NXD1)
+External(NXD2)
+External(NXD3)
+External(NXD4)
+External(NXD5)
+External(NXD6)
+External(NXD7)
+External(NXD8)
+External(DID1)
+External(DID2)
+External(DID3)
+External(DID4)
+External(DID5)
+External(DID6)
+External(DID7)
+External(DID8)
+
+Scope (IGPU_SCOPE)
+{
+
+ Method(_INI,0)
+ {
+ //DIDx values have been changed in MxmAcpiTables.c
+ //Port - D to be used for eDP only and not as DFP. Hence generating a new toggle list
+ Store(DID1, Index(TLPK,0)) // CRT
+ Store(DID2, Index(TLPK,2)) // LFP
+ Store(DID3, Index(TLPK,4)) // DP_B
+ Store(DID4, Index(TLPK,6)) // HDMI_B
+ Store(DID5, Index(TLPK,8)) // HDMI_C
+ Store(DID6, Index(TLPK,10)) // DP_D
+ Store(DID7, Index(TLPK,12)) // HDMI_D
+ Store(DID2, Index(TLPK,14)) // LFP+CRT
+ Store(DID1, Index(TLPK,15))
+ Store(DID2, Index(TLPK,17)) // LFP+DP_B
+ Store(DID3, Index(TLPK,18))
+ Store(DID2, Index(TLPK,20)) // LFP+HDMI_B
+ Store(DID4, Index(TLPK,21))
+ Store(DID2, Index(TLPK,23)) // LFP+HDMI_C
+ Store(DID5, Index(TLPK,24))
+ Store(DID2, Index(TLPK,26)) // LFP+DP_D
+ Store(DID6, Index(TLPK,27))
+ Store(DID2, Index(TLPK,29)) // LFP+HDMI_D
+ Store(DID7, Index(TLPK,30))
+ }
+
+//
+// MXMX method is dupplicated under GFX0 scope in INTELGFX.ASL
+// need to replace it with method in this file.
+//
+#ifndef OPTIMUS_DSM_GUID
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: MXMX
+//
+// Description: Display DDC Mux Control
+//
+// Input:
+// Arg0: Get/Set DDC/Aux Mux State
+// 0- Acquire DDC/Aux Mux on this GPU
+// 1- Release Mux from this GPU
+// 2- Get Mux state
+//
+// Output:
+// 0, Not Acquired.
+// if Arg0 = 0 or 1, Non-Zero return indicates success acquiring MUX
+// (and MUX has switched to this output)
+// if Arg0 = 2, Non-Zero return indicates MUX is currently set to this output
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (MXMX, 1, Serialized)
+ {
+ P8DB(0x77, Arg0, 2000)
+
+ If (LEqual (Arg0, 0))
+ {
+ //Acquire DDC/AUX mux
+ // No mutex implemented. No need to acquire mutex.
+ // Set mux to iGPU
+ DGPU_SCOPE.SGPO(DSEL, 0)
+ DGPU_SCOPE.SGPO(ESEL, 0) // use edid_select# as mutex flag
+
+ Return(0x1)
+ }
+
+ If (LEqual (Arg0, 1))
+ {
+ //Release DDC/AUX mux
+ // No mutex implemented. No need to release mutex.
+ // 2-way mux. Hence no need to do anything
+ Return(0x1)
+ }
+
+ If (LEqual (Arg0, 2))
+ {
+
+ //Get ddc/aux mux status for iGPU
+ Return(LNot(DGPU_SCOPE.SGPI(ESEL)))
+ }
+
+ Return(0x0) // mutex not acquired
+ }
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: MXDS
+//
+// Description: Display output MUX control
+//
+// Input:
+// Arg0:
+// 0 - Get Mux state
+// 1 - Set Display to active on this GPU
+// 2 - Set Backlight control to active on this GPU
+// 3 - Set Display & Backlight to active on this GPU
+//
+// Output:
+// If Arg0 = 0, Error = Display is not MUXed
+// Else return value of the state of the MUX
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(MXDS, 1, Serialized)
+ {
+ P8DB(0x7A, Arg0, 2000)
+
+ If(LEqual (Arg0, 0))
+ {
+ //Get display mux status for iGPU
+ return(LNot(DGPU_SCOPE.SGPI(DSEL)))
+ } else
+// If(LOr(LEqual (Arg0, 1), LEqual (Arg0, 2)))
+ {
+ //Set display mux to igpu
+ DGPU_SCOPE.SGPO(DSEL, 0)
+ DGPU_SCOPE.SGPO(PSEL, 0)
+ }
+
+ Return (0)
+ }
+
+#endif // OPTIMUS_DSM_GUID
+
+//<AMI_SHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: NVIG
+//
+// Description: Nvidia NVIG (iGPU) OperationRegion
+//
+//-------------------------------------------------------------------------
+//<AMI_SHDR_END>
+ OperationRegion(NVIG,SystemMemory,NVGA,0x45)
+ Field(NVIG, DWordAcc, NoLock, Preserve)
+ {
+ // OpRegion Header
+
+ NISG, 0x80, // (000h) Signature-"NVSG-IGD-DSM-VAR".
+ NISZ, 0x20, // (010h) OpRegion Size in KB.
+ NIVR, 0x20, // (014h) OpRegion Version.
+
+ // OpRegion Data
+ GPSS, 0x20, // Policy Selection Switch Status (Policy selection)
+ GACD, 0x10, // Active Displays
+ GATD, 0x10, // Attached Displays
+ LDES, 0x08, // Lid Event State
+ DKST, 0x08, // Dock State
+ DACE, 0x08, // Display ACPI event
+ DHPE, 0x08, // Display Hot-Plug Event
+ DHPS, 0x08, // Display Hot-Plug Status
+ SGNC, 0x08, // Notify Code (Cause of Notify(..,0xD0))
+ GPPO, 0x08, // Policy Override (Temporary ASL variables)
+ USPM, 0x08, // Update Scaling Preference Mask (Temporary ASL variable)
+ GPSP, 0x08, // Panel Scaling Preference
+ TLSN, 0x08, // Toggle List Sequence Number
+ DOSF, 0x08, // Flag for _DOS
+ ELCL, 0x10, // Endpoint Link Contol Register Value
+ }
+
+ // Toggle List Package
+ Name(TLPK,Package()
+ {
+ //fix this toggle list. DIDx values have been changed in MxmAcpiTables.c
+ 0xFFFFFFFF, 0x2C, // CRT
+ 0xFFFFFFFF, 0x2C, // LFP
+ 0xFFFFFFFF, 0x2C, // DP_B
+ 0xFFFFFFFF, 0x2C, // HDMI_B
+ 0xFFFFFFFF, 0x2C, // HDMI_C
+ 0xFFFFFFFF, 0x2C, // DP_D
+ 0xFFFFFFFF, 0x2C, // HDMI_D
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+CRT
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+DP_B
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+HDMI_B
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+HDMI_C
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+DP_D
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+HDMI_D
+
+ })
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: INDL
+//
+// Description: Initialize Global Next active device list.
+//
+// Input: None
+//
+// Output: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(INDL, 0, Serialized)
+ {
+ Store(0, NXD1)
+ Store(0, NXD2)
+ Store(0, NXD3)
+ Store(0, NXD4)
+ Store(0, NXD5)
+ Store(0, NXD6)
+ Store(0, NXD7)
+ Store(0, NXD8)
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: SND1
+//
+// Description: Set Next active device for a single device
+//
+// Input:
+// Arg0 : Device ID of the device that's to be set as next active device.
+//
+// Output: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(SND1, 1, Serialized)
+ {
+ If(LEqual(Arg0, DID1))
+ {
+ Store(1, NXD1)
+ }
+ If(LEqual(Arg0, DID2))
+ {
+ Store(1, NXD2)
+ }
+ If(LEqual(Arg0, DID3))
+ {
+ Store(1, NXD3)
+ }
+ If(LEqual(Arg0, DID4))
+ {
+ Store(1, NXD4)
+ }
+ If(LEqual(Arg0, DID5))
+ {
+ Store(1, NXD5)
+ }
+ If(LEqual(Arg0, DID6))
+ {
+ Store(1, NXD6)
+ }
+ If(LEqual(Arg0, DID7))
+ {
+ Store(1, NXD7)
+ }
+ If(LEqual(Arg0, DID8))
+ {
+ Store(1, NXD8)
+ }
+
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: SNXD
+//
+// Description: Set Next active device
+//
+// Input:
+// Arg0 TLSN
+//
+// Output: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(SNXD, 1, Serialized)
+ {
+ INDL()
+
+ //
+ // Locate the toggle table entry corresponding to TLSN value
+ // Toggle list entries are separated by 0x2C.
+ //
+
+ Store(1, Local0) // Local0 to track entries. Point to the first entry (TLSN starts from 1)
+ Store(0, Local1) // Local1 to track elements inside the TLPK package (ACPI IDs and '0x2C')
+
+ while(LLess(Local0, Arg0)) // TLSN start from 1!!
+ {
+ if(LEqual(DeRefOf(Index(TLPK,Local1)), 0x2C))
+ {
+ Increment(Local0)
+ }
+ Increment(Local1)
+
+ }
+
+ SND1(DeRefOf(Index(TLPK, Local1))) // 1 st ACPI ID in the entry corresponding to TLSN
+ Increment(Local1)
+ if(LNotEqual(DeRefOf(Index(TLPK,Local1)), 0x2C)) // Check for separator
+ {
+ SND1(DeRefOf(Index(TLPK, Local1))) // 2 nd ACPI ID in the entry corresponding to TLSN
+ }
+
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: CTOI
+//
+// Description: Convert _DOD indices-> MDTL index
+//
+// Input:
+// Arg 0 is the currently active display list
+//
+// Output: None
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(CTOI,1, Serialized)
+ {
+ Switch(ToInteger(Arg0)) //Arg 0 is the currently active display list
+ {
+ //_DOD indices-> MDTL index
+ case(0x1) {Return(1)} //CRT
+ case(0x2) {Return(2)} //LFP
+ case(0x4) {Return(3)} //DP_B
+ case(0x8) {Return(4)} //HDMI_B
+ case(0x10) {Return(5)} //HDMI_C
+ case(0x20) {Return(6)} //DP_D
+ case(0x40) {Return(7)} //HDMI_D
+ case(0x3) {Return(8)} //LFP+CRT
+ case(0x6) {Return(9)} //LFP+DP_B
+ case(0xA) {Return(10)} //LFP+HDMI_B
+ case(0x12) {Return(11)} //LFP+HDMI_C
+ case(0x22) {Return(12)} //LFP+DP_D
+ case(0x42) {Return(13)} //LFP+HDMI_D
+ Default {Return(1)}
+ }
+ }
+
+// Check for Nvidia _DSM UUIDs
+//
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: HDSM
+//
+// Description: Device Specific Methods for Hybrid GPU (may be invoked from dGP and iGD)
+// Implements Mxm and SG specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// nVidia
+// SG dGPU GUID :9D95A0A0-0060-4D48-B34D-7E5FEA129FD4
+// NBCI GUID :D4A50B75-65C7-46F7-BfB7-41514CEA0244
+// Ventura GUID :95DB88FD-940A-4253-A446-70CE0504AEDF
+// Optimus DSM_GUID :A486D8F8-0BDA-471B-A72B-6042A6B5BEE0
+//
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(HDSM, 4, SERIALIZED)
+ {
+
+#if NV_VENTURA_SUPPORT == 1
+ //SPB_DSM_GUID {95DB88FD-940A-4253-A446-70CE0504AEDF}
+//x if(CMPB(Arg0, Buffer(){0xFD,0x88,0xDB,0x95,0x0A,0x94,0x53,0x42,0xA4,0x46,0x70,0xCE,0x05,0x04,0xAE,0xDF}))
+ If(LEqual(Arg0, ToUUID("95DB88FD-940A-4253-A446-70CE0504AEDF")))
+ {
+ return ( DGPU_SCOPE.SPB(Arg0, Arg1, Arg2, Arg3))
+ }
+#endif
+
+#if NV_GPS_SUPPORT == 1
+ //SPB_DSM_GUID {A3132D01-8CDA-49BA-A52E-BC9D46DF6B81}
+//x if(CMPB(Arg0, Buffer(){0x01, 0x2D, 0x13, 0xA3, 0xDA, 0x8C, 0xBA, 0x49,0xA5, 0x2E, 0xBC, 0x9D, 0x46, 0xDF, 0x6B, 0x81}))
+ If(LEqual(Arg0, ToUUID("A3132D01-8CDA-49BA-A52E-BC9D46DF6B81")))
+ {
+ return ( DGPU_SCOPE.GPS(Arg0, Arg1, Arg2, Arg3))
+ }
+#endif
+
+#if NV_GC6_SUPPORT == 1
+ If(LEqual(Arg0, ToUUID("CBECA351-067B-4924-9CBD-B46B00B86F34")))
+ {
+ return ( DGPU_SCOPE.NGC6(Arg0, Arg1, Arg2, Arg3))
+ }
+#endif
+
+#if HYBRID_DSM_GUID || NBCI_DSM_GUID || OPTIMUS_DSM_GUID
+
+ Name(SGCI, 0) // SG Common Interface
+ Name(NBCI, 0) // Notebok Common Interface
+ Name(OPCI, 0) // Optimus Common Interface
+ Name(BUFF, 0) // Buff Parameter
+
+// Hybrid Graphics Methods supported only if MUXed mode is selected
+#ifdef HYBRID_DSM_GUID
+ If(LEqual(Arg0, ToUUID("9D95A0A0-0060-4D48-B34D-7E5FEA129FD4")))
+ {
+ Store(1, SGCI)
+ }
+#endif
+// NBCI Methods can be querried in botd MUXed and MUXless modes
+#ifdef NBCI_DSM_GUID
+ if(LEqual(Arg0, ToUUID("D4A50B75-65C7-46F7-BfB7-41514CEA0244")))
+ {
+ Store(1, NBCI)
+ }
+#endif
+// Optimus Methods can be querried in botd MUXed and MUXless modes
+#ifdef OPTIMUS_DSM_GUID
+ If(LEqual(Arg0, ToUUID("A486D8F8-0BDA-471B-A72B-6042A6B5BEE0")))
+ {
+ Store(1, OPCI)
+ }
+#endif
+
+ If(LOr(OPCI, LOr( SGCI, NBCI)) )
+ {
+
+ P8DB(0xEE, Arg2, 1000)
+
+ if(OPCI) {
+ if(LNotEqual(Arg1, 0x100)) {
+ Return(0x80000002)
+ }
+ }
+ else { // NBCI & SGCI
+ If(LNotEqual(Arg1,0x0102))
+ {
+ Return(0x80000002)
+ }
+ }
+ //
+ // Function 0: NVSG_FUNC_SUPPORT - Return Supported Functions
+ //
+ // Returns:
+ // SGCI: Functions 0-6,18 are supported
+ // NBCI: Functions 0,4-6,18 are supported
+ // OPCI: Functions 0,5,6,12,13,16,17,26,27
+ //
+ If(LEqual(Arg2,0))
+ {
+ if(SGCI){
+ Return(Buffer(){0x7F, 0x00, 0x04, 0x00})
+ } else {
+ if(NBCI){
+ Return(Buffer(){0x73, 0x00, 0x04, 0x00})
+ }
+ else {
+ if(OPCI){
+ //Sub-Functions 0,16,17,26 are supported
+ // Return(ToBuffer(0x04030001))
+ //Sub-Functions 0,5, 6, 12, 13, 16, 17, 26,27 are supported
+ // Return(ToBuffer(0x0c031861))
+ // Follow nVidia's suggetion, Optimus displayless platform has no used for other sub-functions.
+ #if NV_OPTIMUS_DISPLAYLESS == 1
+ Return(Buffer(){0x01, 0x00, 0x03, 0x04})
+ #else
+ Return(Buffer(){0x61, 0x18, 0x03, 0x0C})
+ #endif
+ //Sub-Functions 0,16 26,27 are supported
+// Return(ToBuffer(0x0c010001))
+
+ }
+ }
+ }
+ }
+
+ //
+ // Function 1: NVSG_FUNC_CAP
+ //
+ // Returns the capabilities of the Switchable Graphics
+ // implementation on the platform
+ //
+ If(LEqual(Arg2,1))
+ {
+ Name (TEMP, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TEMP,0,STS0)
+ if(SGCI){
+ // Return status (bit0-1 Hybrid enabled) and indicate Hybrid power On/Off
+
+ // 0 HG Enable Status = 1
+ // 1 GPU Output MUX Capabilities= 1
+ // 2 GPU Policy Selector Capabilities = 1
+ // 3-4 GPU Control Status = 3
+ // 5 GPU Reset Control = 1
+ // 6 MUX'ed Hot-Plug Capabilities = 0
+ // 7 MUX'ed DDC/AUX Capabilities = 1
+ // 8-10 Notify Codes
+ // 0= Not a Notify(0xD0)
+ // 1= POLICYSELECT change
+ // 2= PLATPOLICY change
+ // 3= DISPLAYSTATUS change
+ // 11-12 EC Notify code
+ // 14-15 Eject Capabilities = 0
+ // 16 Mux'd backlight cap = 0
+ // 17-23 Hybrid EC version = 0
+ // 24-26 HG capability = 3 (Power saver & Boost performance)
+ // 27-28 HG switch = 1 (hot-key or stateless button)
+ // 29 Fasl LCD swithing = 0
+ // 31 = 0
+
+ // Switchable caps
+ Or(STS0,0x0B0000BF,STS0)
+
+ // Switchable Notify Code (Cause of Notify(..,0xD0))
+ Or(STS0,ShiftLeft(SGNC,8,SGNC),STS0)
+ } else {
+ // NBCI
+ // 0..3 Reserved=00
+ // 4 Aux Power States
+ // 6:5 LID State Event
+ // 0= Use the event List to determine support
+ // 1= Force use of Generic Hot-Plug Notify(0x81)
+ // 2= Force use of Specific Lid Event, e.g. Notify (0xDB)
+ // 3= Reserved for future use
+ // 7:8 LID State Enumeration
+ // 0= Use _DCS under _LCD device(default)
+ // 1= Provides status DISPLAYSTATUS Bit[4], for single pannel systems only(recommended)
+ // 2,3= Reserved
+ // 9 Dock State Enumerartion
+ // 0= Doesn't have a Dock(or _DCS under device reflects attachments-via-dock (default)
+ // 1= Provides dock status info via DISPLAYSTATUS Bit[5] (recommended)
+ // 10:30 Reserved
+ // 31 = 0
+
+ // use all defaults for now
+ Or(STS0,0x00000,STS0)
+ }
+ return(TEMP)
+ }
+
+ //
+ // Function 2: NVSG_FUNC_SELECTOR
+ //
+ // Returns device preference between iGPU and dGPU
+ //
+ If(LEqual(Arg2,2))
+ {
+ Name (TMP1, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TMP1,0,STS1)
+
+ //Ignore bits[6:5] since we are not supporting Switchable enable/disable policy selection
+ //Only Switchable policy selection is supported via CAS+F6 hotkey
+
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(DerefOf(Index(Arg3,0)), Local0)
+ ToInteger(Arg3, Local0)
+ And(Local0, 0x1F, Local0)
+
+ If(And(Local0,0x10)) //If Switchable policy update bit is set
+ {
+ And(Local0,0xF,Local0)
+ Store(Local0,GPSS)
+ Notify(IGPU_SCOPE,0xD9) //Broadcast "policy completed" notification
+ Notify(PCI_SCOPE.WMI1, 0xD9) // Mirror Notify on WMI1
+
+ }
+ Else
+ {
+ And(Local0,0xF,Local0)
+ If(LEqual(GPPO,1))
+ {
+ // Retrieve the setting from NVS
+ Store(GPSS,Local0)
+ Or(Local0,0x10,Local0)
+ Store(0,GPPO)
+ }
+ }
+
+ Or(STS1,Local0,STS1)
+
+ Return(TMP1)
+ }
+
+ //
+ // Function 3: NVSG_FUNC_POWERCONTROL
+ //
+ // Allows control of dGPU power methods from the iGPU
+ //
+ If(LEqual(Arg2,3))
+ {
+ Name (TMP2, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TMP2,0,STS2)
+
+ // GPU Power Control
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(DerefOf(Index(Arg3,0)), Local0)
+ ToInteger(Arg3, Local0)
+ And(Local0, 0x3, Local0)
+
+ If(LEqual(Local0,0))
+ {
+ DGPU_SCOPE.SGST()
+ }
+
+ If(LEqual(Local0,1))
+ {
+ DGPU_SCOPE.SGON()
+ }
+
+ If(LEqual(Local0,2))
+ {
+ DGPU_SCOPE.SGOF()
+ }
+
+ //dGPU_PWROK is not working. Using dGPU_PWR_EN# instead as w/a
+ //Or(STS2,DGPU_SCOPE.MPOK,STS2)
+ If(LEqual(DGPU_SCOPE.SGST(), 0xF))
+ {
+ Or(STS2,0x1,STS2)
+ }
+ //else do nothing since STS2 is already 0
+ Return(TMP2)
+ }
+
+ //
+ // Function 4: NVSG_FUNC_PLATPOLICY
+ //
+ // Sets or Returns the current System Policy settings
+ //
+ If(LEqual(Arg2,4))
+ {
+
+// common for SGCI and NBCI
+ Name (TMP3, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TMP3,0,STS3)
+
+ // Panel Scaling Preference
+
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(DerefOf(Index(Arg3,0)), Local0)
+ ToInteger(Arg3, Local0)
+ Store(Local0, Local1)
+ ShiftRight(Local0, 16, Local0)
+ And(Local0, 0x1, USPM)
+
+ ShiftRight(Local1, 13, Local1)
+ And(Local1, 0x3, Local1)
+
+
+ If(LNotEqual(Local1,GPSP))
+ {
+ If(LEqual(USPM,1))
+ {
+ Store(Local1,GPSP)
+ }
+ Else
+ {
+ // Retrieve the setting from NVS
+ Store(GPSP,Local1)
+ Or(STS3,0x8000,STS3) // Set Panel Scaling override
+ }
+ }
+ Or(STS3,ShiftLeft(Local1,13),STS3)
+
+
+ Return(TMP3)
+ }
+
+ //
+ // Function 5: NVSG_FUNC_DISPLAYSTATUS
+ //
+ // Sets or Returns the current display detection,
+ // hot-key toggle sequence
+ //
+ If(LEqual(Arg2,5))
+ {
+// common for SGCI and NBCI
+ Name (TMP4, Buffer () {0x00, 0x00, 0x00, 0x00})
+ CreateDwordField(TMP4,0,STS4)
+
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(Derefof(Index(Arg3,0)), Local0) //Store input field in local0
+ ToInteger(Arg3, Local0)
+
+ // Next Combination Sequence
+
+ If(And(Local0,0x80000000)) //If Bit31 is set
+ {
+ Store(And(ShiftRight(Local0,25),0x1F),TLSN)
+
+ If(And(Local0,0x40000000)) //If Bit30 is set
+ {
+ Store(1,DOSF)
+ }
+ }
+
+ // Display Mask for Attached and Active Displays
+
+ If(And(Local0,0x01000000)) //If Bit24 is set
+ {
+ Store(And(ShiftRight(Local0,12),0xFFF),GACD)
+ Store(And(Local0,0xFFF),GATD)
+
+ //Get current toggle list index based on currently active display list
+ Store(CTOI(GACD),TLSN)
+ Increment(TLSN)
+
+ If(LGreater(TLSN, 13)) //For Huron River ,13 is the number of entries in the toggle list
+ {
+ Store(1, TLSN)
+ }
+
+ SNXD(TLSN) //This is optional for NV SG
+ }
+
+ // Display Hot-Plug Event/Status
+ Or(STS4,ShiftLeft(DHPE,21),STS4)
+ Or(STS4,ShiftLeft(DHPS,20),STS4)
+
+ // Toggle Sequence number
+ Or(STS4,ShiftLeft(TLSN,8),STS4)
+
+ // Dock State
+ Or(STS4,ShiftLeft(DKST,5),STS4)
+
+ // Lid Event State
+ Or(STS4,ShiftLeft(LDES,4),STS4)
+
+ // Display ACPI Event(SGCI only)
+ Or(STS4,DACE,STS4)
+
+ Store(0,LDES)
+ Store(0,DHPS)
+ Store(0,DHPE)
+ Store(0,DACE)
+
+ Return(TMP4)
+ }
+
+ //
+ // Function 6: NVSG_FUNC_MDTL - Returns Hot-Key display switch toggle sequence
+ //
+ // Returns:
+ // Returns Hot-Key display switch toggle sequence
+ //
+ If(LEqual(Arg2,6))
+ {
+// common for SGCI and NBCI
+ Return(TLPK)
+ }
+ //
+ // Function 16:
+ //
+ If(LEqual(Arg2,16))
+ {
+ CreateWordField(Arg3, 2, USRG) // Object type signature passed in by driver.
+ Name(OPVK, Buffer()
+ {
+ // Key below is for Emerald Lake Fab2 platform
+ // Customer need to ask NVIDIA PM to get the key
+ // Customer need to put the key in between labels "// key start -" and
+ // "// key end -". Please consult NVIDIA PM if any issues
+ //148597456985Genuine NVIDIA Certified Optimus Ready Motherboard for 736019_MIRc
+ // Key start -
+ 0xE4,0x42,0x5F,0x14,0x36,0x26,0x16,0x37,0x4B,0x56,0xE6,0x00,0x00,0x00,0x01,0x00,
+ 0x31,0x34,0x38,0x35,0x39,0x37,0x34,0x35,0x36,0x39,0x38,0x35,0x47,0x65,0x6E,0x75,
+ 0x69,0x6E,0x65,0x20,0x4E,0x56,0x49,0x44,0x49,0x41,0x20,0x43,0x65,0x72,0x74,0x69,
+ 0x66,0x69,0x65,0x64,0x20,0x4F,0x70,0x74,0x69,0x6D,0x75,0x73,0x20,0x52,0x65,0x61,
+ 0x64,0x79,0x20,0x4D,0x6F,0x74,0x68,0x65,0x72,0x62,0x6F,0x61,0x72,0x64,0x20,0x66,
+ 0x6F,0x72,0x20,0x37,0x33,0x36,0x30,0x31,0x39,0x5F,0x4D,0x49,0x52,0x63,0x20,0x20,
+ 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x2D,0x20,0x3C,0x34,0x27,0x21,0x58,0x29,
+ 0x57,0x27,0x58,0x20,0x27,0x25,0x59,0x5D,0x31,0x29,0x3A,0x2A,0x26,0x39,0x59,0x43,
+ 0x56,0x3B,0x58,0x56,0x58,0x3D,0x59,0x4E,0x3B,0x3A,0x35,0x44,0x25,0x42,0x5A,0x48,
+ 0x55,0x3A,0x58,0x4C,0x25,0x48,0x54,0x21,0x35,0x4B,0x4D,0x37,0x2C,0x3C,0x20,0x2D,
+ 0x20,0x43,0x6F,0x70,0x79,0x72,0x69,0x67,0x68,0x74,0x20,0x32,0x30,0x31,0x30,0x20,
+ 0x4E,0x56,0x49,0x44,0x49,0x41,0x20,0x43,0x6F,0x72,0x70,0x6F,0x72,0x61,0x74,0x69,
+ 0x6F,0x6E,0x20,0x41,0x6C,0x6C,0x20,0x52,0x69,0x67,0x68,0x74,0x73,0x20,0x52,0x65,
+ 0x73,0x65,0x72,0x76,0x65,0x64,0x2D,0x31,0x34,0x38,0x35,0x39,0x37,0x34,0x35,0x36,
+ 0x39,0x38,0x35,0x28,0x52,0x29,
+ //Copyright 2010 NVIDIA Corporation All Rights Reserved-148597456985(R)
+ // Key end -
+ })
+ If(LEqual(USRG, 0x564B)) { // 'VK' for Optimus Validation Key Object.
+ Return(OPVK)
+ }
+ Return(Zero)
+ }
+ //
+ // Function 17 NVOP_FUNC_GETALLOBJECTS
+ //
+ If(LEqual(Arg2,17))
+
+ {
+ Return(Zero)
+ }
+ //
+ // Function 18: NVSG_FUNC_GETEVENTLIST
+ //
+ // Returns:
+ // Returns list of notifiers and their meanings
+ //
+ If(LEqual(Arg2,18))
+ {
+// common for SGCI and NBCI
+ return(Package(){
+ 0xD0, ToUUID("921A2F40-0DC4-402d-AC18-B48444EF9ED2"), // Policy request
+ 0xD9, ToUUID("C12AD361-9FA9-4C74-901F-95CB0945CF3E"), // Policy set
+ 0xDB, ToUUID("42848006-8886-490E-8C72-2BDCA93A8A09"), // Display scaling
+
+ 0xEF, ToUUID("B3E485D2-3CC1-4B54-8F31-77BA2FDC9EBE"), // Policy change
+ 0xF0, ToUUID("360d6fb6-1d4e-4fa6-b848-1be33dd8ec7b"), // Display status
+
+ // unfinished list of events. we do not need this Func18 unless event notifiers differ from standard ones defined in BWG.
+ })
+ }
+ //
+ // Function 26: NVOP_FUNC_OPTIMUSCAPS
+ //
+ If(LEqual(Arg2,26))
+ {
+ // On Input
+ //Bit25-24 Power Control Enable
+ // 2-Platform should not power down GPU in the _PS3 method(default)
+ // 3-Platform should power down GPU in the _PS3 method(default)
+ // Bit0 No flag upd present in this call (SBIOS returns curent status)
+ //
+ CreateField(Arg3,24,2,OMPR)
+ CreateField(Arg3,0,1,FLCH)
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET 1:1
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET_SBIOS 0x00000000
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET_DRIVER 0x00000001
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN 2:2
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN_FALSE 0x00000000
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN_TRUE 0x00000001
+ CreateField(Arg3,One,One,DVSR)
+ CreateField(Arg3,0x02,One,DVSC)
+ If(ToInteger(FLCH))
+ {
+ Store(OMPR, DGPU_SCOPE.OPCE) // Optimus Power Control Enable - From DD
+ }
+ // On return
+ // Bit 24:26 Capabilities
+ // 0: No special platf cap
+ // 1: Platform has dynamic GPU power control
+ // Bit6 GPU Display Hot Plug NEW Optimus BWG v02
+ // Bit4:3 Current GPU Control status
+ // 0: GPU is powered off
+ // 1: GPU is powered on and enabled
+ // 2: reserved
+ // 3: GPU Power has stabilized
+ // Bit0
+ // 0:Optimus Disabled
+ // 1:Optimus Enabled
+ Store(Buffer(4) {0, 0, 0, 0}, Local0)
+ CreateField(Local0,0,1,OPEN)
+ CreateField(Local0,3,2,CGCS)
+ CreateField(Local0,6,1,SHPC)
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL 8:8
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL_SBIOS 0x00000000
+ //#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL_DRIVER 0x00000001
+ CreateField(Local0,0x08,One,SNSR)
+ CreateField(Local0,24,3,DGPC) // DGPC - Default: No Dynamic GPU Power Control
+ CreateField(Local0,27,2,HDAC) // HDAC - HD Audio Codec Cap
+
+ Store(One, OPEN) // Optimus Enabled
+
+ Store(One, SHPC) // GPU Display Hotplug Supported
+ Store(0x2, HDAC) // HDA BIOS control Supported
+
+ Store(One, DGPC) // Dynamic GPU Power Control Available
+ //if (NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN is set)
+ //{
+ // GPRF = NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET
+ //}
+ //NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL = GPRF
+ If(ToInteger(DVSC))
+ {
+ If(ToInteger(DVSR))
+ {
+ Store(One, DGPU_SCOPE.GPRF)
+ }
+ Else
+ {
+ Store(Zero, DGPU_SCOPE.GPRF)
+ }
+ }
+ Store(DGPU_SCOPE.GPRF, SNSR)
+ If(LNotEqual(DGPU_SCOPE.SGST(), 0))
+ {
+ Store(0x3, CGCS) // Current GPU Control status
+ }
+ Return(Local0)
+
+ }//case (26)
+ //
+ // Function 27: NVOP_FUNC_OPTIMUSFLAGS
+ //
+ If(LEqual(Arg2,27))
+ {
+ //bugbug:Proxy is sending Arg3 as Buffer and not package!
+ //ToInteger(Derefof(Index(Arg3,0)), Local0) //Store input field in local0
+ ToInteger(Arg3, Local0)
+// Store(Arg3, Local0)
+// CreateField(Local0,0,1,OPFL)
+// CreateField(Local0,1,1,OPVL)
+ If(And(Local0,0x00000002))
+ {
+ Store(Zero, BUFF)
+ If(And(Local0,0x00000001))
+ {
+ Store(One, BUFF)
+ }
+ }
+ And(SGFL, Not(0x2), SGFL)
+ Or(SGFL, ShiftLeft(BUFF,1), SGFL)
+ Store(SWSMI_NVOEM_CMOS_W, SSMP) // Set Audio Codec flag to CMOS
+ Return(Local0)
+ }
+ // FunctionCode or SubFunctionCode not supported
+ Return(0x80000002) // OTHER ARGUMENTS NOT SUPPORTED
+ }
+#endif // common scope for Hybrid/Nbci/Optimus
+
+ // Check for common with dGPU _DSM UUIDs
+// return (DGPU_SCOPE.HDSM(Arg0, Arg1, Arg2, Arg3))
+ Return (0x80000001)
+ }
+} // end PCI0.GFX0 scope
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvGC6.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvGC6.asl
new file mode 100644
index 0000000..55cd3f6
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvGC6.asl
@@ -0,0 +1,363 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2013, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NvGC6.asl 1 2/21/13 5:32a Joshchou $Revision:
+//
+// $Date: 2/21/13 5:32a $Log:
+//
+//
+//
+//**********************************************************************
+External(\_SB.PCI0.LPCB.H_EC, DeviceObj)
+
+External(\_SB.PCI0.PEG0.LNKD)
+External(\_SB.PCI0.PEG0.LNKS)
+External(DGPU_SCOPE.TGPC, MethodObj)
+
+#define JT_REVISION_ID 0x00000103 // Revision number
+#define JT_FUNC_SUPPORT 0x00000000 // Function is supported?
+#define JT_FUNC_CAPS 0x00000001 // Capabilities
+#define JT_FUNC_POWERCONTROL 0x00000003 // dGPU Power Control
+#define JT_FUNC_PLATPOLICY 0x00000004 // Platform Policy
+#define JT_FUNC_DISPLAYSTATUS 0x00000005 // Query the Display Hot-Key
+#define JT_FUNC_MDTK 0x00000006 // Display Hot-Key Toggle List
+
+//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+//!!!!!!!Note:This Asl Code is sample code for reference,should be modified it by different board design!!!!!!!!!!
+//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+Scope(\_SB.PCI0.LPCB.H_EC)
+{
+ // Nvidia recommneded to use EC IO for SBIOS to communicate GC6 entry/exit to EC,
+ // Use EC RAM is polling mechanism and might cause the longer delay time for GC6 T1/T2 timing.
+ // Here we just use EC RAM for example, pleae use EC IO access for production solution.
+ OperationRegion(ECF3,EmbeddedControl,0,0xFF)
+ Field(ECF3, ByteAcc, Lock, Preserve)
+ {
+ Offset(0xF0), // assume GC6 control flags located at offset 0xE0
+ EC6I, 1, // EC flag to prepare GC6 entry
+ EC6O, 1, // EC flag to prepare GC6 exit
+ FBST, 1, // the state of FB_CLAMP
+ }
+ Mutex(GC6M, 0)
+ Method(ECNV, 1, NotSerialized)
+ {
+ Acquire(GC6M, 0xFFFF)
+ If(LEqual(Arg0, Zero))
+ {
+ Store(One, EC6I)
+ }
+ If(LEqual(Arg0, One))
+ {
+ Store(One, EC6O)
+ }
+ Release(GC6M)
+ }
+
+ Method(_Q60, 0, NotSerialized) // for GC6 entry Q-event
+ {
+ Store("------- GC6I-SCI _Q event --------", Debug)
+ CreateField(DGPU_SCOPE.TGPC,0x0A,0x2,PRGE) // PRGE : PCIe Root Power GC6 Enter Sequence
+ If(LEqual(ToInteger(PRGE), 0x0)) // DAGC : Link Disable after GC6 Entry complete & before GPU Power Down
+ {
+ Store(One,\_SB.PCI0.PEG0.LNKD) // PCIE link disabling.
+ }
+
+ DGPU_SCOPE.SGPO(HLRS, 0) // dGPU RST# to low
+ DGPU_SCOPE.SGPO(PWEN, 0) // dGPU PWN Enable to low
+
+ If(LEqual(ToInteger(PRGE), 0x2)) // DAGP : Link Disable after GC6 Entry & GPU Power down is complete
+ {
+ Store(One, \_SB.PCI0.PEG0.LNKD) // PCIE link disabling.
+ }
+ }
+ Method(_Q61, 0, NotSerialized) // for GC6 exit Q-event
+ {
+ Store("------- GC6O-SCI _Q event --------",Debug)
+ }
+}
+
+Scope (DGPU_SCOPE)
+{
+ Name(TGPC, Buffer(0x04)
+ {
+ 0x00
+ }
+ )
+
+ Method(GC6I, 0, Serialized)
+ {
+ Store("<<< GC6I >>>", Debug)
+ CreateField(TGPC,0x06,0x2,ECOC) // NOC: Notify on complete: Reserve
+ CreateField(TGPC,0x0A,0x2,PRGE) // PRGE : PCIe Root Power GC6 Enter Sequence
+ If(Lor(LEqual(ToInteger(PRGE), 0x3), LEqual(ToInteger(PRGE), 0x1))) // DBGS : Link Disable before GC6 Entry starts (E0)
+ {
+ Store(One, \_SB.PCI0.PEG0.LNKD) // PCIE link disabling.
+ }
+ \_SB.PCI0.LPCB.H_EC.ECNV (0) // notify EC to prepare GC6 entry.
+ }
+
+ Method(GC6O, 0, Serialized)
+ {
+ Store("<<< GC6O >>>", Debug)
+ CreateField(TGPC,0x06,0x2,ECOC) // NOC: Notify on complete: Reserve
+ CreateField(TGPC,0x08,0x2,PRGX) // PRGX : PCIe Root Power GC6 Exit Sequence
+ If(LEqual(ToInteger(PRGX), Zero)) // EBPG : Link Enable before GPU Power-On & GC6 Exit begins (X0)
+ {
+ Store(Zero, \_SB.PCI0.PEG0.LNKD) // PCIE link enabling
+ }
+ DGPU_SCOPE.SGPO(HLRS, 0) // dGPU RST# is low
+ DGPU_SCOPE.SGPO(PWEN, 1) // dGPU PWR Enable is high
+ //+ Todo - need to addd more delay to make sure all power rail is ready and stable
+ // if you have PWR_OK to check, please check PWR_OK instead of delay here
+ //....................
+ //-
+ // GC6 T5 1.5ms
+ Store(Zero, Local0) // Delay by Stall(0x32) *30 times.= 1.5ms , you can add more if you don't think 1.5ms is good enough
+ While(LLess(Local0, 0x1E))
+ {
+ Add(Local0, One, Local0)
+ Stall(0x32)
+ }
+ DGPU_SCOPE.SGPO(HLRS, 1) // dGPU RST# is high
+ If(LEqual(ToInteger(PRGX), 0x3)) // EAPG : Link Enable after GPU Power-On Reset, but before GC6 Exit begins
+ {
+ Store(Zero, \_SB.PCI0.PEG0.LNKD) // PCIE link enabling
+ }
+
+ // Haswell UTL has no LNKS register, please remove it from Haswell platform
+ While(LLess(\_SB.PCI0.PEG0.LNKS, 0x07))
+ {
+ Sleep(One)
+ }
+ \_SB.PCI0.LPCB.H_EC.ECNV (1) // notify EC to prepare GC6 exit.
+ }
+
+ Method(GETS, 0, Serialized)
+ {
+ If(LEqual(DGPU_SCOPE.SGPI(PWEN), One)) // dGPU PWR Enable is high
+ {
+ Store("<<< GETS() return 0x1 >>>", Debug)
+ Return(One)// GC6 - dGPU on
+ }
+ Else
+ {
+ If(LEqual(\_SB.PCI0.LPCB.H_EC.FBST, One)) // FB_CLAMP asserted.
+ {
+ Store("<<< GETS() return 0x3 >>>", Debug)
+ Return(0x03)// GC6 - dGPU off, FB On, w/ FB_CLAMP asserted
+ }
+ Else
+ {
+ Store("<<< GETS() return 0x2 >>>", Debug)
+ Return(0x02)// GC6 - dGPU & FB Powered off
+ }
+ }
+ }
+
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: NGC6
+//
+// Description: Called from _DSM -Device Specific Method for dGPU device.
+// Implement Ventura specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// Ventura DSM_GUID CBECA351-067B4924-9CBDB46B00B86F34
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (NGC6, 4, NotSerialized)
+ {
+
+ Store("------- GC6 DSM --------", Debug)
+ // Only Interface Revision 0x0100 is supported
+ If (LLess(Arg1, 0x100))
+ {
+ Return(0x80000001)
+ }
+
+ // (Arg2) Sub-Function
+ Switch (ToInteger(Arg2))
+ {
+ //
+ // Function 0:
+ //
+ case (JT_FUNC_SUPPORT)
+ {
+ Return(Buffer(0x04)
+ {
+ 0x1B, 0x00, 0x00, 0x00
+ })
+ }
+ //
+ // Function 1:
+ //
+ case (JT_FUNC_CAPS)
+ {
+
+ Name(JTB1, Buffer(0x4)
+ {
+ 0x00
+ })
+ CreateField(JTB1,Zero,One,JTEN)
+ CreateField(JTB1,One,0x02,SREN)
+ CreateField(JTB1,0x03,0x03,PLPR)
+ CreateField(JTB1,0x06,0x02,FBPR)
+ CreateField(JTB1,0x08,0x02,GUPR)
+ CreateField(JTB1,0x0A,One,GC6R)
+ CreateField(JTB1,0x0B,One,PTRH)
+ CreateField(JTB1,0x14,0x0C,JTRV)
+ Store(One, JTEN) // JT enable
+ Store(One, GC6R) // GC6 integrated ROM
+ Store(One, PTRH) // No SMI Handler
+ Store(One, SREN) // Disable NVSR
+ Store(JT_REVISION_ID, JTRV) // JT rev
+
+ Return(JTB1)
+ }
+ //
+ // Function 2:
+ //
+ case(0x00000002)
+ {
+ Store("GPS fun 19", Debug)
+ return(arg3)
+ }
+ //
+ // Function 3:
+ //
+ case(0x00000003)
+ {
+ CreateField(Arg3,Zero,0x03,GUPC)
+ CreateField(Arg3,0x04,One,PLPC)
+ Name(JTB3, Buffer(0x04)
+ {
+ 0x00
+ })
+ CreateField(JTB3,Zero,0x03,GUPS)
+ CreateField(JTB3,0x03,One,GPGS) // dGPU Power status
+ CreateField(JTB3,0x07,One,PLST)
+ If(LEqual(ToInteger(GUPC), One)) // EGNS
+ {
+ Store(Arg3,TGPC) // Store GC6 control input for GC6I GC6O
+ GC6I()
+ Store(One, PLST)
+ }
+ Else
+ {
+ If(LEqual(ToInteger(GUPC), 0x02)) // EGIS
+ {
+ Store(Arg3,TGPC) // Store GC6 control input for GC6I GC6O
+ GC6I()
+ If(LEqual(ToInteger(PLPC), Zero))
+ {
+ Store(Zero, PLST)
+ }
+ }
+ Else
+ {
+ If(LEqual(ToInteger(GUPC), 0x03)) // XGXS
+ {
+ Store(Arg3,TGPC) // Store GC6 control input for GC6I GC6O
+ GC6O()
+ If(LNotEqual(ToInteger(PLPC), Zero))
+ {
+ Store(Zero, PLST)
+ }
+ }
+ Else
+ {
+ If(LEqual(ToInteger(GUPC), 0x04)) // XGIS
+ {
+ Store(Arg3,TGPC) // Store GC6 control input for GC6I GC6O
+ GC6O()
+ If(LNotEqual(ToInteger(PLPC), Zero))
+ {
+ Store(Zero, PLST)
+ }
+ }
+ Else
+ {
+ If(LEqual(ToInteger(GUPC), Zero))
+ {
+ Store(GETS(), GUPS)
+ If(LEqual(ToInteger(GUPS), 0x01))
+ {
+ Store(One, GPGS) // dGPU power status is Power OK
+ }
+ Else
+ {
+ Store(Zero, GPGS) // dGPU power status is Power off
+ }
+ }
+ Else
+ {
+ If(LEqual(ToInteger(GUPC), 0x6)) // XLCM
+ {
+ //+ De-assert FB_CLAMP
+
+ //-
+ }
+ }
+ }
+ }
+ }
+ }
+ Return(JTB3)
+ }
+ //
+ // Function 4:
+ //
+ case(JT_FUNC_PLATPOLICY)
+ {
+ Return(0x80000002)
+ }
+
+ } // end of switch
+
+ Return(0x80000002)
+ } // end NGC6
+
+
+} // end DGPU_SCOPE scope
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2013, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvGPS.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvGPS.asl
new file mode 100644
index 0000000..9fcec38
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvGPS.asl
@@ -0,0 +1,356 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NvGPS.asl 1 1/15/13 5:59a Joshchou $
+//
+// $Revision: 1 $
+//
+// $Date: 1/15/13 5:59a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NvGPS.asl $
+//
+// 1 1/15/13 5:59a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Create componet for SG support on PEG
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 2 9/09/12 11:05p Joshchou
+// [TAG] EIPNone
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 2 4/11/12 3:52a Alanlin
+// [TAG] EIP82808
+// [Category] Improvement
+// [Description] nVidia GPS function improvement.
+// [Files] Board\EM\SgTpv\AcpiTables\SgTpvAcpiTables.sdl
+// Board\EM\SgTpv\AcpiTables\NvGPS.asl
+// Board\EM\SgTpv\AcpiTables\NViGPU.asl
+//
+// 1 10/14/11 2:56a Alanlin
+//
+//
+//**********************************************************************
+External(\_PR.CPU0._PSS, BuffObj)
+
+External(\_PR.CPU0._PPC, IntObj)
+External(\_PR.CPU1._PPC, IntObj)
+External(\_PR.CPU2._PPC, IntObj)
+External(\_PR.CPU3._PPC, IntObj)
+External(\_PR.CPU4._PPC, IntObj)
+External(\_PR.CPU5._PPC, IntObj)
+External(\_PR.CPU6._PPC, IntObj)
+External(\_PR.CPU7._PPC, IntObj)
+External(\_SB.PCI0.LPCB.H_EC.GTVR) // CPU GT VR (IMVP) Temperature
+External(\_PR.CPU0._TSS, MethodObj)
+External(\_PR.CPU0._PTC, MethodObj)
+
+#define GPS_REVISION_ID 0x00000100 // Revision number
+#define GPS_ERROR_SUCCESS 0x00000000 // Generic Success
+#define GPS_ERROR_UNSPECIFIED 0x00000001 // Generic unspecified error code
+#define GPS_ERROR_UNSUPPORTED 0x00000002 // Sub-Function not supported
+
+#define GPS_FUNC_SUPPORT 0x00000000 // Bit list of supported functions
+#define GPS_FUNC_GETCALLBACKS 0x00000013 // Get system requested callback
+#define GPS_FUNC_PSHARESTATUS 0x00000020 // Get system requested Power Steering Setting
+#define GPS_FUNC_GETPSS 0x00000021 // Get _PSS object
+#define GPS_FUNC_SETPPC 0x00000022 // Set _PCC object
+#define GPS_FUNC_GETPPC 0x00000023 // Get _PCC object
+#define GPS_FUNC_PSHAREPARAMS 0x0000002A // Get sensor information and capabilities
+
+Scope(PCI_SCOPE){
+
+ Name(GPS, "GPSACPI 2012-Aug-12 14:56:05") // MCPACPIP build time stamp.
+
+} // end of Scope
+
+Scope (DGPU_SCOPE)
+{
+
+Name(PSAP, Zero)
+ Name(ECBF, Buffer(20) {})
+ CreateDWordField(ECBF, 0, EDS1)
+ CreateDWordField(ECBF, 4, EDS2)
+ CreateDWordField(ECBF, 8, EDS3)
+ CreateDWordField(ECBF, 12, EDS4)
+ CreateDWordField(ECBF, 16, EPDT)
+
+ Name(GPSP, Buffer(36) {})
+ CreateDWordField(GPSP, 0, RETN)
+ CreateDWordField(GPSP, 4, VRV1)
+ CreateDWordField(GPSP, 8, TGPU)
+ CreateDWordField(GPSP, 12, PDTS)
+ CreateDWordField(GPSP, 16, SFAN)
+ CreateDWordField(GPSP, 20, SKNT)
+ CreateDWordField(GPSP, 24, CPUE)
+ CreateDWordField(GPSP, 28, TMP1)
+ CreateDWordField(GPSP, 32, TMP2)
+
+Name(NLIM, 0) //set one flag for GPS_EVENT_STATUS_CHANGE 1: will update parameter: 0 just call function 0x1c _PCONTROL
+
+ Name(PSCP, 0) // P-State capacity, mainly for s/w debugging
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: GPS
+//
+// Description: Called from _DSM -Device Specific Method for dGPU device.
+// Implement Ventura specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// Ventura DSM_GUID A3132D01-8CDA-49BA-A52E-BC9D46DF6B81
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (GPS, 4, NotSerialized)
+ {
+
+ Store("------- GPS DSM --------", Debug)
+ // Only Interface Revision 0x0100 is supported
+ If (LNotEqual(Arg1, 0x100))
+ {
+ Return(0x80000002)
+ }
+
+ P8DB(0xDD, Arg2, 1000)
+ // (Arg2) Sub-Function
+ Switch (ToInteger(Arg2))
+ {
+
+ case (GPS_FUNC_SUPPORT)
+ {
+
+ Name(FMSK, Buffer(0x8)
+ {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ })
+ Store(Buffer(0x8)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }, Local0)
+ Divide(GPS_FUNC_SUPPORT, 0x8, Local2, Local1)
+ // Local1 is Quotient, Local2 is Remainder
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_GETCALLBACKS, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_PSHARESTATUS, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_GETPSS, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_SETPPC, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_GETPPC, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(GPS_FUNC_PSHAREPARAMS, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+
+ // mask out specific functions
+ Store( SizeOf(Local0), Local1)
+ While( LNotEqual(Local1, 0) ) {
+ Decrement(Local1)
+ Store( DeRefOf(Index(FMSK, Local1)), Local2)
+ And( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1) )
+ }
+
+ Return(Local0)
+ }
+ //
+ // Function 19: GPS_FUNC_GETCALLBACKS,
+ //
+ case(GPS_FUNC_GETCALLBACKS)
+ {
+ Store("GPS fun 19", Debug)
+ return(arg3)
+ }
+ //
+ // Function 32: GPS_FUNC_PSHARESTATUS,
+ //
+ case(GPS_FUNC_PSHARESTATUS)
+ {
+ Store("GPS fun 20", Debug)
+
+ Name(RET1, Zero)
+ CreateBitField(Arg3,24,NRIT) //new request new IGP turbo state(bit 24 is valid)
+ CreateBitField(Arg3,25,NRIS) //request new IGP turbo state
+ if (NRIS){
+ if(NRIT){
+ Or(RET1, 0x01000000, RET1)
+ }else
+ {
+ //help disable IGP turbo boost
+ And(RET1, 0xFeFFFFFF, RET1)
+ }
+ }
+ Or(RET1, 0x40000000, RET1) // if this machine support GPS
+
+ if(NLIM){
+ Or(RET1, 0x00000001, RET1) // if NLIM falg is set, set bit0 =1
+ }
+
+ Return(RET1)
+ }
+ //
+ // Function 33: GPS_FUNC_GETPSS, Get CPU _PSS structure
+ //
+ case(GPS_FUNC_GETPSS)
+ {
+ Return(\_PR.CPU0._PSS)
+ }
+ //
+ // Function 34: GPS_FUNC_SETPPC, Set current CPU _PPC limit
+ //
+ case(GPS_FUNC_SETPPC)
+ {
+ CreateBYTEField(Arg3, 0, PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU0, 0x80)
+ store(PCAP, PSAP)
+ Return(PCAP)
+ }
+ //
+ // Function 35: GPS_FUNC_GETPPC, Get current CPU _PPC limit
+ //
+ case(GPS_FUNC_GETPPC)
+ {
+ Return(PSAP)
+ }
+
+ case(0x25)
+ {
+ Store("GPS fun 25", Debug)
+ return(\_PR_.CPU0._TSS)
+ }
+ case(0x26)
+ {
+ Store("GPS fun 26", Debug)
+ CreateDWordField(Arg3, Zero, TCAP)
+ Store(TCAP, \_PR_.CPU0._PTC)
+ Notify(\_PR_.CPU0, 0x80)
+ return(TCAP) }
+ //
+ // Function 42: GPS_FUNC_PSHAREPARAMS, Get Power Steering platform parameters
+ //
+ case(GPS_FUNC_PSHAREPARAMS)
+ {
+ Store("GPS fun 2a", Debug)
+
+ CreateBYTEField(Arg3,0,PSH0)
+ CreateBYTEField(Arg3,1,PSH1)
+ CreateBitField(Arg3,8,GPUT)
+ CreateBitField(Arg3,9,CPUT)
+ CreateBitField(Arg3,10,FANS)
+ CreateBitField(Arg3,11,SKIN)
+ CreateBitField(Arg3,12,ENGR)
+ CreateBitField(Arg3,13,SEN1)
+ CreateBitField(Arg3,14,SEN2)
+
+ switch (PSH0){
+ case(0){
+ if(CPUT){
+ store(0x00000200, RETN)
+ Or(RETN, PSH0, RETN)
+ // Please return CPU or EC tempture to PDTS
+ store(\_SB.PCI0.LPCB.H_EC.GTVR,PDTS)
+ }
+ return(GPSP)
+ } //case(0)
+
+ case(1){
+ store(0x00000300, RETN) //need to return CPU and GPU status bits for Querytype1
+ Or(RETN, PSH0, RETN)
+ store(1000,PDTS)
+ return(GPSP)
+ } //case(1)
+
+ case(2){
+ store(0x0102, RETN) //RETN[0:3] need to be the same as input argument, bit8 is GPU temp status bit
+ store(0x00000000, VRV1)
+ store(0x00000000, TGPU)
+ store(0x00000000, PDTS)
+ store(0x00000000, SFAN)
+ store(0x00000000, CPUE)
+ store(0x00000000, SKNT)
+ store(0x00000000, TMP1)
+ store(0x00000000, TMP2)
+ return(GPSP)
+ } //case(2)
+ } // PSH0 of switch
+
+ }
+ } // end of switch
+
+ Return(0x80000002)
+ } // end GPS
+
+
+} // end DGPU_SCOPE scope
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvSSDT.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvSSDT.asl
new file mode 100644
index 0000000..4f4673e
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvSSDT.asl
@@ -0,0 +1,391 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NvSSDT.asl 2 2/21/13 5:37a Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 2/21/13 5:37a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NvSSDT.asl $
+//
+// 2 2/21/13 5:37a Joshchou
+// [TAG] EIP106524
+// [Category] New Feature
+// [Description] Support GC6 function for Optimus.
+//
+// 1 1/15/13 5:58a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Create componet for SG support on PEG
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 2 9/09/12 11:04p Joshchou
+// [TAG] EIPNone
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 5 12/22/11 6:31a Alanlin
+// Declared "defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)"
+//
+//
+// 3 12/02/11 12:38a Alanlin
+// [TAG] EIP75359
+// [Category] Improvement
+// [Description] Report _STA asl method to PCIe root port for nVidia
+// GPU.
+//
+// 2 10/14/11 2:59a Alanlin
+// [TAG] EIP64451
+// [Category] New Feature
+// [Description] Optimus GPS feature update
+// [Files] NvSSDT.asl
+// NViGPU.asl
+// OpSSDT.asl
+// NvGPS.asl
+// SgNvidia.cif
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+//
+//
+// 5 3/17/11 6:17p Alexp
+// Optimus:Add code to preserve HD AudioCodec enable flag in CMOS
+//
+// 4 11/12/10 1:25p Alexp
+// rename ELCT to ELCL in order to avoid name conflict with Intel's ref
+// code in SgDGPU.asl
+//
+// 3 10/06/10 3:34p Alexp
+// Include defines for different Nvidia GUID functions. Helps to control
+// inclusion of peices of ASL depending on type of desired SG mode
+//
+// 2 10/05/10 7:14p Alexp
+// 1. Added debug macro to be able to insert check points in target ASL
+// code
+// 2. Reuse NVdGPU.asl file to build OpSSDT for Optimus and NvSSDT for
+// MUXed SG targets.
+// NvOptimus.asl no longer required
+//
+// 1 9/17/10 1:21p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgNvidia.cif;
+// NvSSDT.asl; NVdGPU.asl;NViGPU.asl;NViGDmisc
+// OpSSDT.asl;NvOptimus.asl;NvVenture.asl
+//
+//
+//**********************************************************************
+
+DefinitionBlock (
+ "Nvidia.aml",
+ "SSDT",
+ 1,
+ "NvdRef",
+ "NvdTabl",
+ 0x1000
+ ) {
+
+#define HYBRID_DSM_GUID 1
+#define MXM_DSM_GUID 1
+//#define NBCI_DSM_GUID 1
+
+External(P8XH, MethodObj)
+
+#if defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)
+#define P8DB(arg0, arg1, arg2) P8XH (0, arg1) P8XH (1, arg0) sleep(arg2)
+#else
+#define P8DB(arg0, arg1, arg2)
+#endif
+
+External(PCI_SCOPE, DeviceObj)
+External(PEG_SCOPE, DeviceObj)
+External(DGPU_SCOPE, DeviceObj)
+External(IGPU_SCOPE, DeviceObj)
+External(DGPU_SCOPE._ADR, DeviceObj)
+External(IGPU_SCOPE._DSM, MethodObj)
+External(DGPU_SCOPE.SGST, MethodObj)
+External(DGPU_SCOPE.SGON, MethodObj)
+External(DGPU_SCOPE.SGOF, MethodObj)
+External(DGPU_SCOPE.SGPI, MethodObj)
+External(DGPU_SCOPE.SGPO, MethodObj)
+External(\DSEL)
+External(\ESEL)
+External(\SSEL)
+External(\PSEL)
+External(\HLRS)
+External(\PWEN)
+External(\PWOK)
+External(\SGMD)
+External(\SGFL)
+External(\SSMP)
+
+
+#include <NVdGPU.ASL> // Include DGPU device namespace
+#include <NViGPU.ASL> // Include NVHG DSM calls
+#include <NViGDmisc.ASL> // Include misc event callback methods
+#if NV_VENTURA_SUPPORT == 1
+#include <NvVentura.ASL> // Include Ventura support
+#endif
+#if NV_GPS_SUPPORT == 1
+#include <NvGPS.ASL> // Include GPS support
+#endif
+#if NV_GC6_SUPPORT == 1
+#include <NvGC6.ASL> // Include GC6 support
+#endif
+
+Scope(PEG_SCOPE)
+{
+ Method(_STA,0,Serialized)
+ {
+ Return(0x000F)
+ }
+}
+Scope(PCI_SCOPE)
+{
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: WMI1
+//
+// Description: WMI MXM Mapper. ASL Device is used to acccess Mxm native method via WMI API
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Device(WMI1) // placed within PCI Bus scope parallel to iGPU
+ {
+ Name(_HID, "PNP0C14")
+ Name(_UID, "MXM2")
+
+ Name(_WDG, Buffer()
+ {
+ // Methods GUID {F6CB5C3C-9CAE-4ebd-B577-931EA32A2CC0}
+ 0x3C, 0x5C, 0xCB, 0xF6, 0xAE, 0x9C, 0xbd, 0x4e, 0xB5, 0x77, 0x93, 0x1E,
+ 0xA3, 0x2A, 0x2C, 0xC0,
+ 0x4D, 0x58, // Object ID "MX" = method "WMMX"
+ 1, // Instance Count
+ 0x02, // Flags (WMIACPI_REGFLAG_METHOD)
+
+ // NVHG_NOTIFY_POLICYCHANGE
+ // WMI Notify - Hybrid Policy Request D0
+ // GUID {921A2F40-0DC4-402d-AC18-B48444EF9ED2}
+ 0x40, 0x2F, 0x1A, 0x92, 0xC4, 0x0D, 0x2D, 0x40, 0xAC, 0x18, 0xB4, 0x84, 0x44, 0xEF, 0x9E, 0xD2,
+ 0xD0, 0x00, 0x01, 0x08,
+
+ // NVHG_NOTIFY_POLICYSET
+ // WMI Notify D9 - Hybrid Policy Set
+ // GUID {C12AD361-9FA9-4C74-901F-95CB0945CF3E}
+ 0x61, 0xD3, 0x2A, 0xC1, 0xA9, 0x9F, 0x74, 0x4C, 0x90, 0x1F, 0x95, 0xCB, 0x09, 0x45, 0xCF, 0x3E,
+ 0xD9, 0x00, 0x01, 0x08,
+
+ // NVHG_DISPLAY_SCALING
+ // Notify event DB - Display scaling change
+ // GUID {42848006-8886-490E-8C72-2BDCA93A8A09}
+ 0x06, 0x80, 0x84, 0x42, 0x86, 0x88, 0x0E, 0x49, 0x8C, 0x72, 0x2B, 0xDC, 0xA9, 0x3A, 0x8A, 0x09,
+ 0xDB, 0x00, 0x01, 0x08,
+
+ // NVHG_DISPLAY_HOTKEY, ACPI_NOTIFY_PANEL_SWITCH GUID
+ // Notify event 80 (fixed) - Hot-Key, use _DGS, _DCS etc.
+ // GUID {E06BDE62-EE75-48F4-A583-B23E69ABF891}
+ 0x62, 0xDE, 0x6B, 0xE0, 0x75, 0xEE, 0xF4, 0x48, 0xA5, 0x83, 0xB2, 0x3E, 0x69, 0xAB, 0xFB, 0x91,
+ 0x80, 0x00, 0x01, 0x08,
+
+ // NVHG_DISPLAY_HOTplug, ACPI_NOTIFY_DEVICE_HOTPLUG
+ // Notify event 81 (fixed) - Hot-Plug, query _DCS
+ // GUID {3ADEBD0F-0C5F-46ED-AB2E-04962B4FDCBC}
+ 0x0F, 0xBD, 0xDe, 0x3A, 0x5F, 0x0C, 0xED, 0x46, 0xAB, 0x2E, 0x04, 0x96, 0x2B, 0x4F, 0xDC, 0xBC,
+ 0x81, 0x00, 0x01, 0x08,
+
+ // NVHG_BRIGHTNESS_INC, ACPI_NOTIFY_INC_BRIGHTNESS_HOTKEY
+ // Notify event 86 (fixed) - Backlight Increase
+ // GUID {1E519311-3E75-4208-B05E-EBE17E3FF41F}
+ 0x11, 0x93, 0x51, 0x1E, 0x75, 0x3E, 0x08, 0x42, 0xB0, 0x5E, 0xEB, 0xE1, 0x7E, 0x3F, 0xF4, 0x1F,
+ 0x86, 0x00, 0x01, 0x08,
+
+ // NVHG_BRIGHTNESS_DEC, ACPI_NOTIFY_DEC_BRIGHTNESS_HOTKEY
+ // Notify event 87 (fixed) - Backlight Decrease
+ // GUID {37F85341-4418-4F24-8533-38FFC7295542}
+ 0x41, 0x53, 0xF8, 0x37, 0x18, 0x44, 0x24, 0x4F, 0x85, 0x33, 0x38, 0xFF, 0xC7, 0x29, 0x55, 0x42,
+ 0x87, 0x00, 0x01, 0x08,
+
+ // MOF data {05901221-D566-11d1-B2F0-00A0C9062910}
+ 0x21, 0x12, 0x90, 0x05, 0x66, 0xd5, 0xd1, 0x11, 0xb2, 0xf0,
+ 0x00, 0xa0, 0xc9, 0x06, 0x29, 0x10,
+ 0x58, 0x4D, // Object ID "XM"
+ 1, // Instance Count = 1
+ 0x00 // Flags
+ }
+ ) // End of _WDG
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: WMMX
+//
+// Description: WMI Method execution tunnel. MXM Native methods are called via WMMX index.
+//
+// Input:
+// Arg1: Integer GPU index. 0x10-iGPU, 0x0-0xf - dGPU
+//
+// Output:
+// Buffer specific to the funcion being called
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(WMMX, 3)
+ {
+
+ //Arg1 = 0x10 indicates iGPU, 0x0~0x0F for dgpu
+ CreateDwordField(Arg2, 0, FUNC) // Get the function name
+ If (LEqual(FUNC, 0x4D53445F)) // "_DSM"
+ {
+ If (LGreaterEqual(SizeOf(Arg2), 28))
+ {
+ CreateField(Arg2, 0, 128, MUID)
+ CreateDwordField(Arg2, 16, REVI)
+ CreateDwordField(Arg2, 20, SFNC)
+ CreateField(Arg2, 0xe0, 0x20, XRG0)
+
+ If(LNotEqual(Arg1,0x10))
+ {
+ If (CondRefOf(IGPU_SCOPE._DSM)) // common with dGPU DSM functions
+ {
+ Return(IGPU_SCOPE._DSM(MUID, REVI, SFNC, XRG0))
+ }
+ }
+ }
+ }
+
+ ElseIf (LEqual(FUNC, 0x584D584D)) // "MXMX"
+ {
+ CreateDWordField(Arg2, 8, XRG1)
+ If (LEqual(Arg1, 0x10))
+ {
+ Return(IGPU_SCOPE.MXMX(XRG1))
+ }
+ Else
+ {
+ Return(DGPU_SCOPE.MXMX(XRG1))
+ }
+ }
+
+ ElseIf (LEqual(FUNC, 0x5344584D)) // "MXDS"
+ {
+ CreateDWordField(Arg2, 8, XRG2)
+ If (LEqual(Arg1, 0x10))
+ {
+ Return(IGPU_SCOPE.MXDS(XRG2))
+ }
+ Else
+ {
+ Return(DGPU_SCOPE.MXDS(XRG2))
+ }
+ }
+ Return(0)
+ } // End of WMMX
+
+ Name(WQXM, Buffer()
+ {
+ 0x46,0x4F,0x4D,0x42,0x01,0x00,0x00,0x00,0x8B,0x02,0x00,0x00,0x0C,0x08,0x00,0x00,
+ 0x44,0x53,0x00,0x01,0x1A,0x7D,0xDA,0x54,0x18,0xD2,0x83,0x00,0x01,0x06,0x18,0x42,
+ 0x10,0x05,0x10,0x8A,0xE6,0x80,0x42,0x04,0x92,0x43,0xA4,0x30,0x30,0x28,0x0B,0x20,
+ 0x86,0x90,0x0B,0x26,0x26,0x40,0x04,0x84,0xBC,0x0A,0xB0,0x29,0xC0,0x24,0x88,0xFA,
+ 0xF7,0x87,0x28,0x09,0x0E,0x25,0x04,0x42,0x12,0x05,0x98,0x17,0xA0,0x5B,0x80,0x61,
+ 0x01,0xB6,0x05,0x98,0x16,0xE0,0x18,0x92,0x4A,0x03,0xA7,0x04,0x96,0x02,0x21,0xA1,
+ 0x02,0x94,0x0B,0xF0,0x2D,0x40,0x3B,0xA2,0x24,0x0B,0xB0,0x0C,0x23,0x02,0x8F,0x82,
+ 0xA1,0x71,0x68,0xEC,0x30,0x2C,0x13,0x4C,0x83,0x38,0x8C,0xB2,0x91,0x45,0x60,0xDC,
+ 0x4E,0x05,0xC8,0x15,0x20,0x4C,0x80,0x78,0x54,0x61,0x34,0x07,0x45,0xE0,0x42,0x63,
+ 0x64,0x40,0xC8,0xA3,0x00,0xAB,0xA3,0xD0,0xA4,0x12,0xD8,0xBD,0x00,0x8D,0x02,0xB4,
+ 0x09,0x70,0x28,0x40,0xA1,0x00,0x6B,0x18,0x72,0x06,0x21,0x5B,0xD8,0xC2,0x68,0x50,
+ 0x80,0x45,0x14,0x8D,0xE0,0x2C,0x2A,0x9E,0x93,0x50,0x02,0xDA,0x1B,0x82,0xF0,0x8C,
+ 0xD9,0x18,0x9E,0x10,0x83,0x54,0x86,0x21,0x88,0xB8,0x11,0x8E,0xA5,0xFD,0x41,0x10,
+ 0xF9,0xAB,0xD7,0xB8,0x1D,0x69,0x34,0xA8,0xB1,0x26,0x38,0x76,0x8F,0xE6,0x84,0x3B,
+ 0x17,0x20,0x7D,0x6E,0x02,0x39,0xBA,0xD3,0xA8,0x73,0xD0,0x64,0x78,0x0C,0x2B,0xC1,
+ 0x7F,0x80,0x4F,0x01,0x78,0xD7,0x80,0x9A,0xFE,0xC1,0x33,0x41,0x70,0xA8,0x21,0x7A,
+ 0xD4,0xE1,0x4E,0xE0,0xBC,0x8E,0x84,0x41,0x1C,0xD1,0x71,0x63,0x67,0x75,0x32,0x07,
+ 0x5D,0xAA,0x00,0xB3,0x07,0x00,0x0D,0x2E,0xC1,0x69,0x9F,0x49,0xE8,0xF7,0x80,0xF3,
+ 0xE9,0x79,0x6C,0x6C,0x10,0xA8,0x91,0xF9,0xFF,0x0F,0xED,0x41,0x9E,0x56,0xCC,0x90,
+ 0xCF,0x02,0x87,0xC5,0xC4,0x1E,0x19,0xE8,0x78,0xC0,0x7F,0x00,0x78,0x34,0x88,0xF0,
+ 0x66,0xE0,0xF9,0x9A,0x60,0x50,0x08,0x39,0x19,0x0F,0x4A,0xCC,0xF9,0x80,0xCC,0x25,
+ 0xC4,0x43,0xC0,0x31,0xC4,0x08,0x7A,0x46,0x45,0x23,0x6B,0x22,0x3E,0x03,0x78,0xDC,
+ 0x96,0x05,0x42,0x09,0x0C,0xEC,0x73,0xC3,0x3B,0x84,0x61,0x71,0xA3,0x09,0xEC,0xF3,
+ 0x85,0x05,0x0E,0x0A,0x05,0xEB,0xBB,0x42,0xCC,0xE7,0x81,0xE3,0x3C,0x60,0x0B,0x9F,
+ 0x28,0x01,0x3E,0x24,0x8F,0x06,0xDE,0x20,0xE1,0x5B,0x3F,0x02,0x10,0xE0,0x27,0x06,
+ 0x13,0x58,0x1E,0x30,0x7A,0x94,0xF6,0x2B,0x00,0x21,0xF8,0x8B,0xC5,0x53,0xC0,0xEB,
+ 0x40,0x84,0x63,0x81,0x29,0x72,0x6C,0x68,0x78,0x7E,0x70,0x88,0x1E,0xF5,0x5C,0xC2,
+ 0x1F,0x4D,0x94,0x53,0x38,0x1C,0x1F,0x39,0x8C,0x10,0xFE,0x49,0xE3,0xC9,0xC3,0x9A,
+ 0xEF,0x00,0x9A,0xD2,0x5B,0xC0,0xFB,0x83,0x47,0x80,0x11,0x20,0xE1,0x68,0x82,0x89,
+ 0x7C,0x3A,0x01,0xD5,0xFF,0xFF,0x74,0x02,0xB8,0xBA,0x01,0x14,0x37,0x6A,0x9D,0x49,
+ 0x7C,0x2C,0xF1,0xAD,0xE4,0xBC,0x43,0xC5,0x7F,0x93,0x78,0x3A,0xF1,0x34,0x1E,0x4C,
+ 0x42,0x44,0x89,0x18,0x21,0xA2,0xEF,0x27,0x46,0x08,0x15,0x31,0x6C,0xA4,0x37,0x80,
+ 0xE7,0x13,0xE3,0x84,0x08,0xF4,0x74,0xC2,0x42,0x3E,0x34,0xA4,0xE1,0x74,0x02,0x50,
+ 0xE0,0xFF,0x7F,0x3A,0x81,0x1F,0xF5,0x74,0x82,0x1E,0xAE,0x4F,0x19,0x18,0xE4,0x03,
+ 0xF2,0xA9,0xC3,0xF7,0x1F,0x13,0xF8,0x78,0xC2,0x45,0x1D,0x4F,0x50,0xA7,0x07,0x1F,
+ 0x4F,0xD8,0x19,0xE1,0x2C,0x1E,0x03,0x7C,0x3A,0xC1,0xDC,0x13,0x7C,0x3A,0x01,0xDB,
+ 0x68,0x60,0x1C,0x4F,0xC0,0x77,0x74,0xC1,0x1D,0x4F,0xC0,0x30,0x18,0x18,0xE7,0x13,
+ 0xE0,0x31,0x5E,0xDC,0x31,0xC0,0x43,0xE0,0x03,0x78,0xDC,0x38,0x3D,0x2B,0x9D,0x14,
+ 0xF2,0x24,0xC2,0x07,0x85,0x39,0xB0,0xE0,0x14,0xDA,0xF4,0xA9,0xD1,0xA8,0x55,0x83,
+ 0x32,0x35,0xCA,0x34,0xA8,0xD5,0xA7,0x52,0x63,0xC6,0xCE,0x19,0x0E,0xF8,0x10,0xD0,
+ 0x89,0xC0,0xF2,0x9E,0x0D,0x02,0xB1,0x0C,0x0A,0x81,0x58,0xFA,0xAB,0x45,0x20,0x0E,
+ 0x0E,0xA2,0xFF,0x3F,0x88,0x23,0xD2,0x0A,0xC4,0xFF,0x7F,0x7F
+ }
+ ) // End of WQXM
+ } // End of WMI1 Device
+ } // end scope PCI0
+} // end SSDT
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvVentura.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvVentura.asl
new file mode 100644
index 0000000..ec6a303
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/NvVentura.asl
@@ -0,0 +1,546 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NvVentura.asl 1 1/15/13 5:59a Joshchou $
+//
+// $Revision: 1 $
+//
+// $Date: 1/15/13 5:59a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/NvVentura.asl $
+//
+// 1 1/15/13 5:59a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Create componet for SG support on PEG
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 2 9/09/12 11:05p Joshchou
+// [TAG] EIPNone
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+//
+
+//
+// 2 10/05/10 7:14p Alexp
+// 1. Added debug macro to be able to insert check points in target ASL
+// code
+// 2. Reuse NVdGPU.asl file to build OpSSDT for Optimus and NvSSDT for
+// MUXed SG targets.
+// NvOptimus.asl no longer required
+//
+// 1 9/17/10 1:21p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgNvidia.cif;
+// NvSSDT.asl; NVdGPU.asl;NViGPU.asl;NViGDmisc
+// OpSSDT.asl;NvOptimus.asl;NvVenture.asl
+//
+// 1 6/08/10 3:45p Alexp
+//
+//**********************************************************************
+// (Ventura+)>
+EXTERNAL(\_PR.CPU0, DeviceObj)
+EXTERNAL(\_PR.CPU1, DeviceObj)
+EXTERNAL(\_PR.CPU2, DeviceObj)
+EXTERNAL(\_PR.CPU3, DeviceObj)
+//> Andy+ for ClarksField -- 8 processors
+EXTERNAL(\_PR.CPU4, DeviceObj)
+EXTERNAL(\_PR.CPU5, DeviceObj)
+EXTERNAL(\_PR.CPU6, DeviceObj)
+EXTERNAL(\_PR.CPU7, DeviceObj)
+//<
+External(\_PR.CPU0._PSS, BuffObj)
+External(\_PR.CPU0._TSS, BuffObj)
+
+External(\_PR.CPU0._PPC, IntObj)
+External(\_PR.CPU1._PPC, IntObj)
+External(\_PR.CPU2._PPC, IntObj)
+External(\_PR.CPU3._PPC, IntObj)
+//> Andy+ for ClarksField -- 8 processors
+External(\_PR.CPU4._PPC, IntObj)
+External(\_PR.CPU5._PPC, IntObj)
+External(\_PR.CPU6._PPC, IntObj)
+External(\_PR.CPU7._PPC, IntObj)
+//<
+External(\_PR.CPU0._TPC, IntObj)
+External(\_PR.CPU1._TPC, IntObj)
+External(\_PR.CPU2._TPC, IntObj)
+External(\_PR.CPU3._TPC, IntObj)
+//> Andy+ for ClarksField -- 8 processors
+External(\_PR.CPU4._TPC, IntObj)
+External(\_PR.CPU5._TPC, IntObj)
+External(\_PR.CPU6._TPC, IntObj)
+External(\_PR.CPU7._TPC, IntObj)
+//<
+Scope(PCI_SCOPE){
+
+ Name(VEN, "VENACPI 2009-Nov-23 14:56:05") // MCPACPIP build time stamp.
+
+} // end of Scope
+
+Scope (DGPU_SCOPE)
+{
+ // value used to notify iGPU
+
+ Name(VSTS, 1) // Ventura Status
+ Name(THBG, 50000) // Thermal Budget
+ Name(PSCP, 0) // P-State capacity, mainly for s/w debugging
+ Name(TBUD, 0x88B8) // Thermal Budget
+// Name(PBCM, 0)
+
+ // Called by EC to notify thermal budget/status change
+ // Arg0 is one of SPB_EC_ values
+ // Arg1 is an object reference
+ Method (THCH, 2, NotSerialized)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ case ( 0x03)
+ {
+ // VSTS needs to be updated before notification
+ Store(DeRefOf(Arg1), VSTS)
+ Notify(DGPU_SCOPE, 0xC0)
+ }
+ case ( 0x01)
+ {
+ // THBG needs to be updated before notification
+ Store(DeRefOf(Arg1), THBG)
+ Notify(DGPU_SCOPE, 0xC1)
+ }
+ }
+ }
+
+ // Wrapper to call Method(SPB)
+ Method (SPB2, 2, NotSerialized)
+ {
+ Store( Buffer() {0x00, 0x00, 0x00, 0x00}, Local0 )
+ CreateDwordField(Local0, 0, LLLL)
+ Store( Arg1, LLLL )
+ Return( SPB(0x00, 0x101, Arg0, Local0) )
+ }
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: SPB
+//
+// Description: Called from _DSM -Device Specific Method for dGPU device.
+// Implement Ventura specific callback functions
+//
+// Input:
+// Arg0: UUID Unique function identifier.
+// Ventura DSM_GUID 95DB88FD-940A-4253-A446-70CE0504AEDF
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (0 = Return Supported Functions)
+// Arg3: Package Parameters
+//
+// Output:
+// Sub-function 0 and unsupported function calls always returns a buffer.
+// Other subfunctions may return a buffer or a package as defined in the function.
+// When a single DWord is returned the following values have special meaning,
+// controlled by reserved Bit31 as follows:
+// MXM_ERROR_SUCCESS 0x00000000 Success
+// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code
+// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not
+// supported by this system
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method (SPB, 4, NotSerialized)
+ {
+
+ Store("------- SPB DSM --------", Debug)
+ // Only Interface Revision 0x0101 is supported
+ If (LNotEqual(Arg1, 0x101))
+ {
+ Return(0x80000002)
+ }
+
+ // (Arg2) Sub-Function
+ Switch (ToInteger(Arg2))
+ {
+ case (0x00)
+ {
+ Name(FMSK, Buffer(0x8)
+ {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ })
+ Store(Buffer(0x8)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }, Local0)
+ Divide(Zero, 0x8, Local2, Local1)
+ // Local1 is Quotient, Local2 is Remainder
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x20, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x21, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x22, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x23, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x24, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ Divide(0x2A, 8, Local2, Local1)
+ ShiftLeft(0x01, Local2, Local2)
+ Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
+
+ // mask out specific functions
+ Store( SizeOf(Local0), Local1)
+ While( LNotEqual(Local1, 0) ) {
+ Decrement(Local1)
+ Store( DeRefOf(Index(FMSK, Local1)), Local2)
+ And( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1) )
+ }
+
+ Return(Local0)
+ }
+
+ // Unit is mWAT
+ case(0x20)
+ {
+ Store(TBUD, Local1)
+ //failsafe to clear ventura status bit
+ And(Local1, 0xFFFFF, Local1)
+ // Just return SPB status for now (bit[0]=1 SPB enabled)
+// If(CondRefOf(PBCM,Local0)){ // Make sure this object is present.
+// If(PBCM){
+// // Software/EC have another chance to disable ventura through VSTS
+// If(LNotEqual(VSTS, 0)) {
+// Or( Local1, 0x40000000, Local1 )
+// }
+// }
+// }
+ Return(Local1)
+ }
+
+ case(0x21)
+ {
+ Return(\_PR.CPU0._PSS)
+ }
+
+ case(0x22)
+ {
+ CreateByteField(Arg3, 0, PCAP)
+
+ Store(PCAP, PSCP)
+ // \_PR.CPU0._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU0, 0x80)
+
+ If(CondRefOf(\_PR.CPU1._PPC, Local0)) {
+ // \_PR.CPU1._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU1, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU2._PPC, Local0)) {
+ // \_PR.CPU2._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU2, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU3._PPC, Local0)) {
+ // \_PR.CPU3._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU3, 0x80)
+ }
+
+//> Andy+ for ClarksField -- 8 processors
+ If(CondRefOf(\_PR.CPU4._PPC, Local0)) {
+ // \_PR.CPU4._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU4, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU5._PPC, Local0)) {
+ // \_PR.CPU5._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU5, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU6._PPC, Local0)) {
+ // \_PR.CPU6._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU6, 0x80)
+ }
+
+ If(CondRefOf(\_PR.CPU7._PPC, Local0)) {
+ // \_PR.CPU7._PPC(PCAP)
+ Store(PCAP, \_PR.CPU0._PPC)
+ Notify(\_PR.CPU7, 0x80)
+ }
+//<
+
+ Return(PCAP)
+ }
+
+ case( 0x23)
+ {
+ Return(PSCP)
+ }
+
+ case(0x24)
+ {
+ CreateField(Arg3, 0, 20, THBG)
+ CreateField(Arg3, 30, 1, DDVE)
+ }
+ case(0x2a)
+ {
+ Return(SSNR(Arg3))
+ }
+ } // end of switch
+
+ Return(0x80000002)
+ } // end SPB
+
+ // Ventura Sensor parameters header structure
+ Name(SBHS, Buffer(0x8) {})
+ CreateDWordField(SBHS, 0, VERV)
+ CreateDWordField(SBHS, 4, NUMS)
+
+ // Ventura CPU Sensor structure
+ Name(SSCP, Buffer(44) {})
+ CreateDWordField(SSCP, 4, CSNT)
+ CreateDWordField(SSCP, 8, CPTI)
+ CreateDWordField(SSCP, 12, CICA)
+ CreateDWordField(SSCP, 16, CIRC)
+ CreateDWordField(SSCP, 20, CICV)
+ CreateDWordField(SSCP, 24, CIRA)
+ CreateDWordField(SSCP, 28, CIAV)
+ CreateDWordField(SSCP, 32, CIEP)
+ CreateDWordField(SSCP, 36, CPPF)
+ CreateDWordField(SSCP, 40, CSNR)
+
+ // Ventura GPU Sensor structure
+ Name(SSGP, Buffer(44) {})
+ CreateDWordField(SSGP, 4, GSNT)
+ CreateDWordField(SSGP, 8, GPTI)
+ CreateDWordField(SSGP, 12, GICA)
+ CreateDWordField(SSGP, 16, GIRC)
+ CreateDWordField(SSGP, 20, GICV)
+ CreateDWordField(SSGP, 24, GIRA)
+ CreateDWordField(SSGP, 28, GIAV)
+ CreateDWordField(SSGP, 32, GIEP)
+ CreateDWordField(SSGP, 36, GPPF)
+ CreateDWordField(SSGP, 40, GSNR)
+
+ // Ventura CPU Parameters Structure
+ Name(SCPP, Buffer(72) {})
+ CreateDWordField(SCPP, 0, VRV1)
+ CreateDWordField(SCPP, 4, VCAP)
+ CreateDWordField(SCPP, 8, VCCP)
+ CreateDWordField(SCPP, 12, VCDP)
+ CreateDWordField(SCPP, 16, VCEP)
+ CreateDWordField(SCPP, 20, VCGP)
+ CreateDWordField(SCPP, 24, VCHP)
+ CreateDWordField(SCPP, 28, VCXP)
+ CreateDWordField(SCPP, 32, VCYP)
+ CreateDWordField(SCPP, 36, VCZP)
+ CreateDWordField(SCPP, 40, VCKP)
+ CreateDWordField(SCPP, 44, VCMP)
+ CreateDWordField(SCPP, 48, VCNP)
+ CreateDWordField(SCPP, 52, VCAL)
+ CreateDWordField(SCPP, 56, VCBE)
+ CreateDWordField(SCPP, 60, VCGA)
+ CreateDWordField(SCPP, 64, VCPP)
+ CreateDWordField(SCPP, 68, VCDE)
+
+// Ventura GPU Parameters Structure
+ Name(SGPP, Buffer(40) {})
+ CreateDWordField(SGPP, 0, VRV2)
+ CreateDWordField(SGPP, 4, VGWP)
+ CreateDWordField(SGPP, 8, VGPP)
+ CreateDWordField(SGPP, 12, VGQP)
+ CreateDWordField(SGPP, 16, VGRP)
+ CreateDWordField(SGPP, 20, VGAP)
+ CreateDWordField(SGPP, 24, VGBP)
+ CreateDWordField(SGPP, 28, VGCP)
+ CreateDWordField(SGPP, 32, VGDP)
+ CreateDWordField(SGPP, 36, VGDE)
+
+ Method(SSNR, 1)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ case (0x00)
+ {
+ // Populate Header Structure
+ Store(0x00010000, VERV)
+ Store(0x02, NUMS)
+ Return(SBHS)
+ }
+ case (0x01)
+ {
+ Store(0x00010000, VRV1)
+ Store(0x3E8, VCAP) //VEN_CPU_PARAM_A_CK 0x3E8
+ Store(0x2EE, VCCP) //VEN_CPU_PARAM_C_CK 0x2EE
+ Store(0x2EE, VCDP) //VEN_CPU_PARAM_D_CK 0x2EE
+ Store(0x2EE, VCEP) //VEN_CPU_PARAM_E_CK 0x2EE
+ Store(0x79e, VCGP) //VEN_CPU_PARAM_G_CK 0x79e
+ Store(0x2bc, VCHP) //VEN_CPU_PARAM_H_CK 0x2bc
+ Store(0x258, VCXP) //VEN_CPU_PARAM_X_CK 0x258
+ Store(0x0fa, VCYP) //VEN_CPU_PARAM_Y_CK 0x0fa
+ Store(0x1f4, VCZP) //VEN_CPU_PARAM_Z_CK 0x1f4
+ Store(0x000, VCKP) //VEN_CPU_PARAM_K_CK 0x000
+ Store(0x000, VCMP) //VEN_CPU_PARAM_M_CK 0x000
+ Store(0x000, VCNP) //VEN_CPU_PARAM_N_CK 0x000
+ Store(0x000, VCPP) //VEN_CPU_PARAM_P_CK 0x000
+ Store(0x421, VCAL) //VEN_CPU_PARAM_AL_CK 0x421
+ Store(0x708, VCBE) //VEN_CPU_PARAM_BE_CK 0x708
+ Store(0x016, VCGA) //VEN_CPU_PARAM_GA_CK 0x016
+ Store(0x001, VCDE) //VEN_CPU_PARAM_DEL_CK 0x001
+/* Clarksfield 8 CPU
+ Store(0x3E8, VCAP)
+ Store(0x258, VCCP)
+ Store(0x258, VCDP)
+ Store(0x258, VCEP)
+ Store(0x2CF, VCGP)
+ Store(0x311, VCHP)
+ Store(0x136, VCXP)
+ Store(0x118, VCYP)
+ Store(0x19A, VCZP)
+ Store(0x001, VCKP)
+ Store(0x001, VCMP)
+ Store(0x001, VCNP)
+ Store(0x000, VCPP)
+ Store(0x36B, VCAL)
+ Store(0x13C, VCBE)
+ Store(0x019, VCGA)
+ Store(0x001, VCDE)
+end Clarksfield 8CPUs*/
+
+ Return(SCPP)
+ }
+ case (0x02)
+ {
+ Store(0x00010000, VRV2)
+ Store(0x3E8, VGWP)
+ Store(0x2EE, VGPP)
+ Store(0x2EE, VGQP)
+ Store(0x2EE, VGRP)
+ Store(0x001, VGAP)
+ Store(0x1F4, VGBP)
+ Store(0x000, VGCP)
+ Store(0x000, VGDP)
+ Store(0x001, VGDE)
+/* Clarksfield 8 CPU
+ Store(0x3E8, VGBP)
+ Store(0x001, VGCP)
+ Store(0x001, VGDP)
+ Store(0x000, VGDE)
+end Clarksfield 8CPUs*/
+ Return(SGPP)
+ }
+ case (0x03)
+ {
+ // The below sensor parameter values for GPU and CPU
+ // are board specific. To support for ventura, fill
+ // the SSCP and SSGP structures
+
+ // Populate CPU Sensor values
+ Store(0x0, Index(SSCP, 0)) // Indicate CPU sensor
+ Store(0x00, CSNT)
+ Store(0x01, CPTI)
+ Store(0x84, CICA) // 0x80
+ Store(0x00, CIRC)
+ Store(0x27FF, CICV)
+ Store(0x05, CIRA)
+ Store(0xA000, CIAV)
+ Store(0x03, CIEP)
+ Store(0x0F, CPPF)
+ Store(0x04, CSNR)
+
+ // Populate GPU Sensor values
+ Store(0x1, Index(SSGP, 0)) // Indicate GPU sensor
+ Store(0x00, GSNT)
+ Store(0x01, GPTI)
+ Store(0x8C, GICA) // 0x8A
+ Store(0x00, GIRC)
+ Store(0x27FF, GICV)
+ Store(0x05, GIRA)
+ Store(0xA000, GIAV)
+ Store(0x03, GIEP)
+ Store(0x0F, GPPF)
+ Store(0x04, GSNR)
+
+ Return(Concatenate(SSCP, SSGP))
+ }
+
+ } //switch end
+
+ Return(0x80000002)
+ }
+} // end DGPU_SCOPE scope
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/OpSSDT.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/OpSSDT.asl
new file mode 100644
index 0000000..3fac84f
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/OpSSDT.asl
@@ -0,0 +1,281 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/OpSSDT.asl 4 7/16/13 5:23a Joshchou $
+//
+// $Revision: 4 $
+//
+// $Date: 7/16/13 5:23a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/OpSSDT.asl $
+//
+// 4 7/16/13 5:23a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Remove _STA method in the scope of root port because
+// it's not required.
+//
+//
+// 2 2/21/13 5:37a Joshchou
+// [TAG] EIP106524
+// [Category] New Feature
+// [Description] Support GC6 function for Optimus.
+//
+// 1 1/15/13 5:59a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Create componet for SG support on PEG
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 2 9/09/12 11:05p Joshchou
+// [TAG] EIPNone
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+// NvGPS.asl
+//
+// 5 12/22/11 6:31a Alanlin
+// Declared "defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)"
+//
+//
+// 3 12/02/11 12:40a Alanlin
+// [TAG] EIP75359
+// [Category] Improvement
+// [Description] Report _STA asl method to PCIe root port for nVidia
+// GPU.
+//
+// 2 10/14/11 2:59a Alanlin
+// [TAG] EIP64451
+// [Category] New Feature
+// [Description] Optimus GPS feature update
+// [Files] NvSSDT.asl
+// NViGPU.asl
+// OpSSDT.asl
+// NvGPS.asl
+// SgNvidia.cif
+//
+// 1 6/27/11 5:27a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgNvidia.cif
+// NvSSDT.asl
+// NVdGPU.asl
+// NViGPU.asl
+// NViGDmisc.asl
+// OpSSDT.asl
+// NvVentura.asl
+//
+//
+// 6 3/17/11 6:17p Alexp
+// Optimus:Add code to preserve HD AudioCodec enable flag in CMOS
+//
+// 5 11/12/10 1:26p Alexp
+// rename ELCT to ELCL in order to avoid name conflict with Intel's ref
+// code in SgDGPU.asl
+//
+// 4 10/06/10 3:34p Alexp
+// Include defines for different Nvidia GUID functions. Helps to control
+// inclusion of peices of ASL depending on type of desired SG mode
+//
+// 3 10/05/10 7:14p Alexp
+// 1. Added debug macro to be able to insert check points in target ASL
+// code
+// 2. Reuse NVdGPU.asl file to build OpSSDT for Optimus and NvSSDT for
+// MUXed SG targets.
+// NvOptimus.asl no longer required
+//
+// 2 9/17/10 3:22p Alexp
+// remove test comments
+//
+// 1 9/17/10 1:21p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgNvidia.cif;
+// NvSSDT.asl; NVdGPU.asl;NViGPU.asl;NViGDmisc
+// OpSSDT.asl;NvOptimus.asl;NvVenture.asl
+//
+//**********************************************************************
+
+DefinitionBlock (
+ "NvOpt.aml",
+ "SSDT",
+ 1,
+ "OptRef",
+ "OptTabl",
+ 0x1000
+ ) {
+
+#define OPTIMUS_DSM_GUID 1
+//#define NBCI_DSM_GUID 1
+
+External(P8XH, MethodObj)
+#if defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)
+#define P8DB(arg0, arg1, arg2) P8XH (0, arg1) P8XH (1, arg0) sleep(arg2)
+#else
+#define P8DB(arg0, arg1, arg2)
+#endif
+
+
+External(PCI_SCOPE, DeviceObj)
+External(PEG_SCOPE, DeviceObj)
+External(DGPU_SCOPE, DeviceObj)
+External(IGPU_SCOPE, DeviceObj)
+External(DGPU_SCOPE._ADR, DeviceObj)
+External(IGPU_SCOPE._DSM, MethodObj)
+External(DGPU_SCOPE.SGST, MethodObj)
+External(DGPU_SCOPE.SGON, MethodObj)
+External(DGPU_SCOPE.SGOF, MethodObj)
+External(DGPU_SCOPE.SGPI, MethodObj)
+External(DGPU_SCOPE.SGPO, MethodObj)
+External(\DSEL)
+External(\ESEL)
+External(\SSEL)
+External(\PSEL)
+External(\HLRS)
+External(\PWEN)
+External(\PWOK)
+External(\SGMD)
+External(\SGFL)
+External(\SSMP)
+
+#include <NVdGPU.ASL> // Include DGPU device namespace
+#include <NViGPU.ASL> // Include NVHG DSM calls
+//#include <NViGDmisc.ASL> // Include misc event callback methods
+
+#if NV_VENTURA_SUPPORT == 1
+#include <NvVentura.ASL> // Include Ventura support
+#endif
+#if NV_GPS_SUPPORT == 1
+#include <NvGPS.ASL> // Include GPS support
+#endif
+#if NV_GC6_SUPPORT == 1
+#include <NvGC6.ASL> // Include GC6 support
+#endif
+
+ Scope(PCI_SCOPE)
+ {
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: WMI1
+//
+// Description: WMI MXM Mapper. ASL Device is used to acccess Nv Optimus native method via WMI API
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Device(WMI1) // placed within PCI Bus scope parallel to iGPU
+ {
+ Name(_HID, "PNP0C14")
+ Name(_UID, "OPT1")
+
+ Name(_WDG, Buffer()
+ {
+ // Methods GUID {F6CB5C3C-9CAE-4ebd-B577-931EA32A2CC0}
+ 0x3C, 0x5C, 0xCB, 0xF6, 0xAE, 0x9C, 0xbd, 0x4e, 0xB5, 0x77, 0x93, 0x1E,
+ 0xA3, 0x2A, 0x2C, 0xC0,
+ 0x4D, 0x58, // Object ID "MX" = method "WMMX"
+ 1, // Instance Count
+ 0x02, // Flags (WMIACPI_REGFLAG_METHOD)
+ }) // End of _WDG
+
+//<AMI_PHDR_START>
+//------------------------------------------------------------------------
+//
+// Procedure: WMMX
+//
+// Description: WMI Method execution tunnel. MXM Native methods are called via WMMX index.
+//
+// Input:
+// Arg1: Integer GPU index. 0x10-iGPU, 0x100+PCIe Bus number for the GPU
+//
+// Output:
+// Buffer specific to the funcion being called
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+ Method(WMMX, 3)
+ {
+
+ //Arg1 = 0x10 indicates iGPU, 0x100+PCIe Bus number for the GPU
+ //
+ CreateDwordField(Arg2, 0, FUNC) // Get the function name
+
+ If (LEqual(FUNC, 0x534F525F)) // "_ROM"
+ {
+ If (LGreaterEqual(SizeOf(Arg2), 8))
+ {
+ CreateDwordField(Arg2, 4, ARGS)
+ CreateDwordField(Arg2, 8, XARG)
+ Return(DGPU_SCOPE._ROM(ARGS, XARG))
+ }
+ }
+
+ If (LEqual(FUNC, 0x4D53445F)) // "_DSM"
+ {
+ If (LGreaterEqual(SizeOf(Arg2), 28))
+ {
+ CreateField(Arg2, 0, 128, MUID)
+ CreateDwordField(Arg2, 16, REVI)
+ CreateDwordField(Arg2, 20, SFNC)
+ CreateField(Arg2, 0xe0, 0x20, XRG0)
+
+// If(LNotEqual(Arg1,0x10))
+// {
+ If (CondRefOf(IGPU_SCOPE._DSM)) // common with dGPU DSM functions
+ {
+ Return(IGPU_SCOPE._DSM(MUID, REVI, SFNC, XRG0))
+ }
+// }
+ }
+ }
+ Return(0)
+ } // End of WMMX
+ } // End of WMI1 Device
+ } // end scope PCI0
+} // end SSDT
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//****************************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgAti.cif b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgAti.cif
new file mode 100644
index 0000000..295726c
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgAti.cif
@@ -0,0 +1,11 @@
+<component>
+ name = "Ati"
+ category = ModulePart
+ LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\AcpiTables\SgTpvPEG"
+ RefName = "AtiSG"
+[files]
+"AtiSSDT.asl"
+"ATdGPU.asl"
+"ATiGPU.asl"
+"ATiGDmisc.asl"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgNvidia.cif b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgNvidia.cif
new file mode 100644
index 0000000..014f0f6
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgNvidia.cif
@@ -0,0 +1,15 @@
+<component>
+ name = "nVidia"
+ category = ModulePart
+ LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\AcpiTables\SgTpvPEG"
+ RefName = "nVidiaSG"
+[files]
+"NvSSDT.asl"
+"NVdGPU.asl"
+"NViGPU.asl"
+"NViGDmisc.asl"
+"OpSSDT.asl"
+"NvVentura.asl"
+"NvGPS.asl"
+"NvGC6.asl"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgTpvPEG.cif b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgTpvPEG.cif
new file mode 100644
index 0000000..2f84740
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgTpvPEG.cif
@@ -0,0 +1,12 @@
+<component>
+ name = "SgTpvPEG"
+ category = ModulePart
+ LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\AcpiTables\SgTpvPEG"
+ RefName = "SgTpvPEG"
+[files]
+"SgTpvPEG.sdl"
+"SgTpvPEG.mak"
+[parts]
+"AtiSG"
+"nVidiaSG"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgTpvPEG.mak b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgTpvPEG.mak
new file mode 100644
index 0000000..4536804
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgTpvPEG.mak
@@ -0,0 +1,131 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/SgTpvPEG.mak 2 6/02/13 8:13a Joshchou $
+#
+# $Revision: 2 $
+#
+# $Date: 6/02/13 8:13a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/SgTpvPEG/SgTpvPEG.mak $
+#
+# 2 6/02/13 8:13a Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Change IASL compiler path to
+# $(ACPIPLATFORM_ASL_COMPILER) in SharkBay project.
+#
+# 1 1/15/13 5:57a Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Create componet for SG ASL code support on PEG
+# [Files] SgTpvPEG.cif
+# SgTpvPEG.sdl
+# SgTpvPEG.mak
+#
+# 3 11/20/12 3:48a Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Create Token for OEM clone
+#
+# 2 9/09/12 11:01p Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Tpv module support for sharkbay.
+# [Files] OEMSSDT.mak
+# OEMSSDT.asl
+# OEMNVdGPU.asl
+# OEMNViGPU.asl
+# OEMNViGDmisc.asl
+# OEMNvVentura.asl
+# OEMNvGPS.asl
+# OEMSSDT.cif
+#
+# 1 12/12/11 9:10p Alanlin
+#
+#
+#
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name: OEMSSDT.mak
+#
+# Description: MAke file to build Aptio ACPI ASL components
+#
+#
+#<AMI_FHDR_END>
+#*************************************************************************
+SGPEGASL: $(BUILD_DIR)\SGTPVssdt.ffs
+
+#-----------------------------------------------------------------------------
+# SG SSDT ACPI Tables
+#-----------------------------------------------------------------------------
+!IF "$(ACPIPLATFORM_ASL_COMPILER)"==""
+!ERROR It is an invalid path, please check your ASL compiler path.
+!ENDIF
+
+IASL = $(ACPIPLATFORM_ASL_COMPILER)
+#-----------------------------------------------------------------------
+$(BUILD_DIR)\OpSSDT.aml $(BUILD_DIR)\NvSSDT.aml $(BUILD_DIR)\AtiSSDT.aml: $(BUILD_DIR)\OpSSDT.asl $(BUILD_DIR)\NvSSDT.asl $(BUILD_DIR)\AtiSSDT.asl
+ $(SILENT)$(IASL) -p $@ $*.asl
+
+$(BUILD_DIR)\OpSSDT.sec $(BUILD_DIR)\NvSSDT.sec $(BUILD_DIR)\ATIssdt.sec: $(BUILD_DIR)\OpSSDT.aml $(BUILD_DIR)\NvSSDT.aml $(BUILD_DIR)\AtiSSDT.aml
+ $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW
+
+#Note. Expand the package with multiple SG SSDT tables.
+# DXE phase will load the tables depending on present Mxm Gfx card
+# and update Aml contents if provided in AcpiTables.c
+$(BUILD_DIR)\SGTPVssdt.ffs: $(BUILD_DIR)\OpSSDT.sec $(BUILD_DIR)\NvSSDT.sec $(BUILD_DIR)\AtiSSDT.sec
+ $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\SGTPVssdt.pkg
+
+PACKAGE.INF
+[.]
+BASE_NAME = SgTpvACPI
+FFS_FILEGUID = 6A061113-FE54-4A07-A28E-0A69359EB069
+FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM
+FFS_ATTRIB_CHECKSUM = TRUE
+
+IMAGE_SCRIPT =
+{
+ Compress (dummy) {
+ $(PROJECT_DIR)\$(BUILD_DIR)\OpSSDT.sec
+ $(PROJECT_DIR)\$(BUILD_DIR)\NvSSDT.sec
+ $(PROJECT_DIR)\$(BUILD_DIR)\AtiSSDT.sec
+ }
+}
+<<KEEP
+#-----------------------------------------------------------------------#
+# Process SG asl files
+#-----------------------------------------------------------------------#
+$(BUILD_DIR)\OpSSDT.asl $(BUILD_DIR)\NvSSDT.asl $(BUILD_DIR)\AtiSSDT.asl : $(INTEL_OPSSDT_ASL_FILE) $(INTEL_NVSSDT_ASL_FILE) $(INTEL_ATISSDT_ASL_FILE)
+ $(CP) /I$(SG_TPVPEG_DIR) /FItoken.h /C $(SG_TPVPEG_DIR)\$(@F) > $@
+# include the token.h if needed to check for SDL flags
+# /FItoken.h
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgTpvPEG.sdl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgTpvPEG.sdl
new file mode 100644
index 0000000..b43b0dd
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/SgTpvPEG/SgTpvPEG.sdl
@@ -0,0 +1,53 @@
+TOKEN
+ Name = "SgTpvPEG_SUPPORT"
+ Value = "1"
+ Help = "Add an OEM SSDT for discrete VGA card. When Primarydisplay = Auto or PEG, the system can report OEM SSDT talbes for AMD or nVidia dGPU VGA card."
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+ Master = Yes
+End
+
+TOKEN
+ Name = "DGPU_SCOPE"
+ Value = "\_SB.PCI0.PEG0.PEGP"
+ Help = "PLATFORM PORTING!!! Update iGPU and dGPU device names as defined in SB/NB.SDL"
+ TokenType = Expression
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "INTEL_OPSSDT_ASL_FILE"
+ Value = "$(SG_TPVPEG_DIR)\OpSSDT.asl"
+ TokenType = Expression
+ TargetMAK = Yes
+End
+
+TOKEN
+ Name = "INTEL_NVSSDT_ASL_FILE"
+ Value = "$(SG_TPVPEG_DIR)\NvSSDT.asl"
+ TokenType = Expression
+ TargetMAK = Yes
+End
+
+TOKEN
+ Name = "INTEL_ATISSDT_ASL_FILE"
+ Value = "$(SG_TPVPEG_DIR)\AtiSSDT.asl"
+ TokenType = Expression
+ TargetMAK = Yes
+End
+
+PATH
+ Name = "SG_TPVPEG_DIR"
+End
+
+MODULE
+ Help = "Includes SgTpvPEG.mak to Project"
+ File = "SgTpvPEG.mak"
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\SGTPVssdt.ffs"
+ Parent = "FV_MAIN"
+ InvokeOrder = AfterParent
+End
diff --git a/Board/EM/SwitchableGraphics/SgTpv/MXM30/MXM30.cif b/Board/EM/SwitchableGraphics/SgTpv/MXM30/MXM30.cif
new file mode 100644
index 0000000..02fd8c4
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/MXM30/MXM30.cif
@@ -0,0 +1,18 @@
+<component>
+ name = "Sg nVidia API"
+ category = ModulePart
+ LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\MXM30"
+ RefName = "MXM_NBCI"
+[files]
+"MXM30.sdl"
+"MXM30.mak"
+"Mxm30Dxe.dxs"
+"Mxm30Dxe.c"
+"Mxm30Efi.c"
+"NBCIEfi.c"
+"MxmInt15.asm"
+"Mxm30ElkCreek4.mxm"
+"Mxm30ElkCreekIII.mxm"
+[parts]
+"MXM_Protocol"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SgTpv/MXM30/MXM30.mak b/Board/EM/SwitchableGraphics/SgTpv/MXM30/MXM30.mak
new file mode 100644
index 0000000..2ac9f97
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/MXM30/MXM30.mak
@@ -0,0 +1,161 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia API/MXM30.mak 2 9/09/12 11:12p Joshchou $
+#
+# $Revision: 2 $
+#
+# $Date: 9/09/12 11:12p $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia API/MXM30.mak $
+#
+# 2 9/09/12 11:12p Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Tpv module support for sharkbay.
+# [Files] MXM30.mak
+# Mxm30Dxe.dxs
+# Mxm30Dxe.c
+# Mxm30Efi.c
+# NBCIEfi.c
+# MxmInt15.asm
+# MXM30.cif
+#
+# 1 6/27/11 5:25a Alanlin
+# [TAG] EIP61848
+# [Category] New Feature
+# [Description] Initial check-in.Integrated SwitchableGraphics Intel
+# Reference code 0.6.0
+# [Files] MXM30.cif
+# MXM30.sdl
+# MXM30.mak
+# Mxm30Dxe.dxs
+# Mxm30Dxe.c
+# Mxm30Efi.c
+# NBCIEfi.c
+# MxmInt15.asm
+# Mxm30ElkCreek4.mxm
+# Mxm30ElkCreekIII.mxm
+#
+#
+# 2 9/23/10 1:04p Alexp
+# change the build target
+#
+# 1 9/17/10 1:15p Alexp
+# [TAG] EIP43103
+# [Category] Function Request
+# [Severity] Normal
+# [Symptom] Initial check-in of SgTPV module
+# [RootCause] Request to implement SG reference code .
+# [Solution] Initial check-in.
+# [Files]
+# Mxm30.cif;*.sdl;*.mak;
+# Mxm30Dxe.c;*.dxs
+# Mxm30efi.c
+# MxmInt15.asm
+# NbciEfi.c
+# Mxm30ElkCreek3(4).mxm
+#
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name: MXM30.mak
+#
+# Description: Make file to build Switchable Graphics MXM component
+#
+#<AMI_FHDR_END>
+#*************************************************************************
+SgTpv: MXM30
+
+MXM30 : $(BUILD_DIR)\MXM30.mak Mxm30DxeBin $(BUILD_DIR)\MXMdat.ffs
+
+$(BUILD_DIR)\MXM30.mak : $(MXM30_DIR)\MXM30.cif $(MXM30_DIR)\MXM30.mak $(BUILD_RULES)
+ $(CIF2MAK) $(MXM30_DIR)\MXM30.cif $(CIF2MAK_DEFAULTS)
+
+#--------------------------------------------------------------------------
+# 1.
+#--------------------------------------------------------------------------
+BUILD_MXM_DIR = $(BUILD_DIR)\$(MXM30_DIR)
+
+##SGDxeBin : $(BUILD_MXM_DIR)\Mxm30Efi.obj $(BUILD_MXM_DIR)\NbciEfi.obj
+#SGDxeBin : $(BUILD_MXM_DIR)\Mxm30Efi.obj
+
+##$(BUILD_MXM_DIR)\Mxm30Efi.obj $(BUILD_MXM_DIR)\NbciEfi.obj: $(MXM30_DIR)\Mxm30Efi.c $(MXM30_DIR)\NbciEfi.c
+#$(BUILD_MXM_DIR)\Mxm30Efi.obj: $(MXM30_DIR)\Mxm30Efi.c
+# $(CC) $(CFLAGS) $(MXM_INCLUDES) /I$(MXM30_DIR) /Fo$@ $(MXM30_DIR)\$(@F)
+
+MXM_DXE_OBJECTS = \
+$(BUILD_MXM_DIR)\Mxm30Dxe.obj\
+$(BUILD_MXM_DIR)\Mxm30Efi.obj\
+
+#$(BUILD_MXM_DIR)\Nbci.obj\
+
+MXM_INCLUDES= \
+ /I $(MXM30_DIR)\
+ /I$(CORE_DIR)\
+ $(INTEL_MPG_INCLUDES)\
+ $(INTEL_MCH_INCLUDES)\
+ $(INTEL_PCH_INCLUDES)\
+ /I$(NB_BOARD_DIR)\
+ /I$(SB_BOARD_DIR)
+
+Mxm30DxeBin : $(AMIDXELIB) $(AMICSPLib)
+ $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+ /f $(BUILD_DIR)\MXM30.mak all\
+ NAME=Mxm30Dxe\
+ MAKEFILE=$(BUILD_DIR)\MXM30.mak \
+ GUID=31A0B6EF-A400-4419-8327-0FB134AA59E7 \
+ ENTRY_POINT=MxmDriverEntryPoint\
+ DEPEX1=$(MXM30_DIR)\Mxm30Dxe.DXS DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+ "MY_INCLUDES=$(MXM_INCLUDES)"\
+ "OBJECTS=$(MXM_DXE_OBJECTS)"\
+ TYPE=RT_DRIVER\
+ COMPRESS=1
+
+#--------------------------------------------------------------------------
+# 2.
+#--------------------------------------------------------------------------
+$(BUILD_DIR)\MXMint15.obj: $(MXM30_DIR)\MXMint15.asm
+ $(ASM16) $(AFLAGS16) /Fo$(BUILD_DIR)\ $(MXM30_DIR)\$(@B).asm
+
+#--------------------------------------------------------------------------
+# 3.
+#---------------------------------------------------------------------------
+# Build Mxm block file. In case external utils want to update Mxm
+# Don't change the GUID. LocateMXMffs expects this GUID.
+#---------------------------------------------------------------------------
+$(BUILD_DIR)\MXMdat.ffs : $(MXM30_DIR)\$(MXM_FILE_NAME)
+ $(MAKE) /f Core\FFS.mak \
+ NAME=$(@B) \
+ BUILD_DIR=$(BUILD_DIR) SOURCE_DIR=$(MXM30_DIR) \
+ GUID=6707536E-46AF-42d3-8F6C-15F2F202C234 \
+ TYPE=EFI_FV_FILETYPE_FREEFORM \
+ BINFILE=$** FFSFILE=$@ COMPRESS=1 NAME=$(**B)
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/MXM30/MXM30.sdl b/Board/EM/SwitchableGraphics/SgTpv/MXM30/MXM30.sdl
new file mode 100644
index 0000000..9562308
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/MXM30/MXM30.sdl
@@ -0,0 +1,135 @@
+TOKEN
+ Name = "MXM30_SUPPORT"
+ Value = "1"
+ Help = "Main switch to enable MXM30 Legacy int15, Efi and Acpi interfaces"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Master = Yes
+End
+
+TOKEN
+ Name = "MXM_REVISION"
+ Value = "3"
+ Help = "1: Support MXM rev2.0, 2: Support MXM rev2.1, 3: Support MXM rev3.0."
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetMAK = Yes
+End
+
+TOKEN
+ Name = "MXM_REV_SUPPORTED"
+ Value = "30h"
+ Help = "the revision of the MXM software specification that is supported by the MXM module\Format is binary coded decimal, for example: 0x30 = 3.0, etc."
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "MXM_FUNC_SUPPORTED"
+ Value = "3"
+ Help = "the bit map of function list supported by the MXM module\Bit 0 = `1' MxmReturnSpecLevel method is required\Bit 1 = `1' MxmReturnStucture is also required"
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "NBCI_REVISION"
+ Value = "1"
+ Help = "1: Support NBCI rev1.1"
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetMAK = Yes
+End
+
+TOKEN
+ Name = "NBCI_REV_SUPPORTED"
+ Value = "11h"
+ Help = "the revision of the NBCI software specification that is supported by the NBCI module\Format is binary coded decimal, for example: 0x11 = 1.1, etc."
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "NBCI_FUNC_SUPPORTED"
+ Value = "3"
+ Help = "the bit map of function list supported by the Nbci module\Bit 0 = `1' NbciReturnSpecLevel method is required\Bit 1 = `1' NbciReturnStucture is also required"
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "MXM_ROM_MAX_SIZE"
+ Value = "200"
+ Help = "Max size of MXM module data structure"
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "MXM_ROM_MAX_SIZE_bits"
+ Value = "$(MXM_ROM_MAX_SIZE)*8"
+ Help = "Max size of MXM module data structure 1600"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "MXMOEM1_GUID"
+ Value = "{0x6707536e, 0x46af, 0x42d3, 0x8f, 0x6c, 0x15, 0xf2, 0xf2, 0x2, 0xc2, 0x34}"
+ Help = "MXM module FFS file"
+ TokenType = Expression
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "MXM_FILE_NAME"
+ Value = "Mxm30ElkCreek4.mxm"
+ Help = "MXM module file name"
+ TokenType = Expression
+ TargetMAK = Yes
+End
+
+PATH
+ Name = "MXM30_DIR"
+ Help = "Path to MXM30 Module in Project"
+End
+
+MODULE
+ Help = "Includes MXM30.mak to Project"
+ File = "MXM30.mak"
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\mxmint15.obj"
+ Parent = "CSM_OEMINT_OBJS"
+ Priority = 10
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "MXMINT15Proc"
+ Parent = "CsmOemInterrupts"
+ ProcID = 015h
+ SrcFile = "Board\em\mxm30\mxmint15.asm"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\Mxm30Dxe.ffs"
+ Parent = "FV_MAIN"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\MXMdat.ffs"
+ Parent = "FV_MAIN"
+ InvokeOrder = AfterParent
+End
+
diff --git a/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30Dxe.c b/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30Dxe.c
new file mode 100644
index 0000000..83ec3e6
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30Dxe.c
@@ -0,0 +1,377 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia API/Mxm30Dxe.c 2 9/09/12 11:12p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:12p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia API/Mxm30Dxe.c $
+//
+// 2 9/09/12 11:12p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] MXM30.mak
+// Mxm30Dxe.dxs
+// Mxm30Dxe.c
+// Mxm30Efi.c
+// NBCIEfi.c
+// MxmInt15.asm
+// MXM30.cif
+//
+// 3 4/11/12 4:06a Alanlin
+// Nvidia Optimus support when CSM module is disabled or CSM is never on
+// setup menu.
+//
+// 2 12/12/11 9:19p Alanlin
+// [TAG] EIP74169
+// [Category] Improvement
+// [Description] Add OEMSSDT module part. Token "SGOEMSSDT_SUPPORT" to
+// create OEM SSDT for discrete VGA card.
+// When Primarydisplay = Auto or PEG, it can report OEM SSDT talbes for
+// AMD or nVidia dGPU VGA card.
+//
+// 1 6/27/11 5:25a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] MXM30.cif
+// MXM30.sdl
+// MXM30.mak
+// Mxm30Dxe.dxs
+// Mxm30Dxe.c
+// Mxm30Efi.c
+// NBCIEfi.c
+// MxmInt15.asm
+// Mxm30ElkCreek4.mxm
+// Mxm30ElkCreekIII.mxm
+//
+//
+// 2 9/23/10 1:04p Alexp
+// comment out unused BDS callback defines
+//
+// 1 9/17/10 1:16p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// Mxm30.cif;*.sdl;*.mak;
+// Mxm30Dxe.c;*.dxs
+// Mxm30efi.c
+// MxmInt15.asm
+// NbciEfi.c
+// Mxm30ElkCreek3(4).mxm
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name: Mxm30DXE.c
+//
+// Description: This file contains the etry point of EFI MXM30 Support driver
+// The function istalls MXM EFI, Legacy and Acpi interfaces if
+// enabled in Setup
+// Installs Acpi Tables for Switchable Graphics
+//
+// Notes: MAKE SURE NO PEI OR DXE SPECIFIC CODE IS NEEDED
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+#include <Token.h>
+#include <AmiDxeLib.h>
+#include <DXE.h>
+#include "SB.h"
+#include "Setup.h"
+#include <Protocol\Mxm30.h>
+#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1)
+#include <AmiLoadCsmPolicy.h>
+#endif
+
+#if ( defined(CSM_SUPPORT) && (CSM_SUPPORT != 0) )
+#include <Protocol\LegacyBios.h>
+#include <Protocol\LegacyRegion.h>
+#include <Protocol\LegacyBiosExt.h>
+#endif
+#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1)
+AMI_OPROM_POLICY_PROTOCOL *gAmiOpRomPolicyProtocol = NULL;
+EFI_GUID gAmiOpromPolicyProtocolGuid = AMI_OPROM_POLICY_PROTOCOL_GUID;
+#endif
+
+extern EFI_BOOT_SERVICES *pBS;
+extern EFI_RUNTIME_SERVICES *pRS;
+
+VOID *gMxmLegMemAddr = NULL;
+UINTN gMxmLegMemSize = 0;
+
+//#define BDS_ALL_DRIVERS_CONNECTED_PROTOCOL_GUID \
+// {0xdbc9fd21, 0xfad8, 0x45b0, 0x9e, 0x78, 0x27, 0x15, 0x88, 0x67, 0xcc, 0x93}
+
+//EFI_EVENT mMxmEvent;
+//VOID *mMxmReg;
+//EFI_GUID gBdsAllDriversConnectedProtocolGuid = BDS_ALL_DRIVERS_CONNECTED_PROTOCOL_GUID;
+
+// extern functions
+EFI_STATUS MXM30Interfaces (EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTable);
+//EFI_STATUS NBCIInterfaces (EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTable);
+
+#if ( defined(CSM_SUPPORT) && (CSM_SUPPORT != 0) )
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: UpdateInt15MxMData
+//
+// Description: Get the address of MXM data buffer in legacy bios region
+//
+// Input: EFI_LEGACY_BIOS_PROTOCOL *LegacyBiosProtocol;
+//
+//
+// Output: EFI_STATUS
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS
+UpdateInt15MxmSISData (
+ IN EFI_LEGACY_BIOS_PROTOCOL *LegacyBiosProtocol
+)
+{
+ EFI_STATUS Status;
+ UINT32 Addr16;
+ EFI_IA32_REGISTER_SET RegSet;
+ UINT32 *ivt = (UINT32*)0;
+
+ // Get the Data Pointer to MXM Structure within Int15 MXM handler
+ MemSet(&RegSet, sizeof (EFI_IA32_REGISTER_SET), 0);
+ RegSet.X.AX = 0x5f80;
+ RegSet.X.BX = 0xFF01;
+ RegSet.X.CX = EFI30_DataBlockID;
+ RegSet.X.ES = 0;
+ RegSet.X.DI = 0;
+ Addr16 = ivt[0x15];
+ Status = LegacyBiosProtocol->FarCall86 (LegacyBiosProtocol,
+ (UINT16)(Addr16 >> 16),
+ (UINT16)Addr16,
+ &RegSet, 0, 0);
+ Status = (RegSet.X.AX == 0x5F80 || RegSet.X.ES == 0)? EFI_UNSUPPORTED : EFI_SUCCESS;
+ ASSERT_EFI_ERROR(Status);
+
+// return updated address
+ gMxmLegMemAddr = (UINT8*)((RegSet.X.ES << 4) + (RegSet.X.DI));
+
+// TO DO. Expand the routine to obtain the address of _DOD buffer(MXM Int15 5f80, Func 9)
+
+ return Status;
+}
+#endif
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: MxmDriverEntryPoint
+//
+// Description: Entry point of EFI MXM Support driver. The function istalls
+// 1. Install MXM protocol;
+// 2. Update data structure to be passed to Int15 binary
+// must support multiple MXM data modules. Dependent on controller's handle
+// Load MXM data block <1Mb area.
+// a. Copy MXM Structure below 1MB
+// 1. Allocate Legacy mem space for MXM dat <1MB
+// OR
+// 2. Update the MXM data by the pointer returned by Int15 5F80 Func01(default)
+// b. Update the pointer to MXM data in EFI Protocol API
+// c. Create an ACPI SSDT table and copy MXM block there (ASL MXM logic must handle different MXM modules...)
+//
+// Input: EFI_HANDLE ImageHandle,
+// EFI_SYSTEM_TABLE *SystemTable
+//
+// Output: EFI_STATUS
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS
+MxmDriverEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ SETUP_DATA SetupData;
+ EFI_GUID SetupGuid = SETUP_GUID;//SYSTEM_CONFIGURATION_GUID;
+ EFI_GUID EfiMxmStructGuid = MXMOEM1_GUID;
+// MXM_STRUCT_HDR *MxmHdr;
+
+#if ( defined(CSM_SUPPORT) && (CSM_SUPPORT != 0) )
+ EFI_LEGACY_BIOS_EXT_PROTOCOL *BiosExtensions = NULL;
+ EFI_LEGACY_BIOS_PROTOCOL *LegacyBiosProtocol = NULL;
+#endif
+ VOID *MxmData;
+ UINTN ImageSize, Size;
+#if ( defined(CSM_SUPPORT) && (CSM_SUPPORT != 0) )
+ UINT32 LockUnlockAddr, LockUnlockSize;
+#endif
+ EFI_STATUS CsmOptOutStatus = EFI_SUCCESS;
+
+ InitAmiLib(ImageHandle, SystemTable);
+ TRACE((-1, "==============MxmDriverEntryPoint============\n"));
+ //
+ // Check if the module is enabled in Setup; if not - return EFI_UNSUPPORTED
+ //
+ Size = sizeof(SETUP_DATA);
+ Status = pRS->GetVariable(L"Setup",
+ &SetupGuid,
+ NULL,
+ &Size,
+ &SetupData);
+ if (EFI_ERROR(Status)) return Status;
+
+ // Check to see if Primary Display is set to enable SG
+ //
+ if ((SetupData.PrimaryDisplay == 1)|| //PEG
+ (SetupData.PrimaryDisplay == 3)|| //AUTO
+ (SetupData.PrimaryDisplay == 4)) //SG
+ { }
+ else
+ return EFI_UNSUPPORTED;
+#if ( defined(CSM_SUPPORT) && (CSM_SUPPORT != 0) )
+ #if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1)
+ CsmOptOutStatus = pBS->LocateProtocol(&gAmiOpromPolicyProtocolGuid, NULL, &gAmiOpRomPolicyProtocol);
+ #endif
+ if (!EFI_ERROR(CsmOptOutStatus)){
+ Status = pBS->LocateProtocol(&gEfiLegacyBiosProtocolGuid, NULL, &LegacyBiosProtocol);
+ if (EFI_ERROR(Status)) return Status;
+
+ Status = pBS->LocateProtocol(&gEfiLegacyBiosExtProtocolGuid, NULL, &BiosExtensions);
+ if (EFI_ERROR(Status)) return Status;
+ }
+#endif
+// TBD. Proper Mxm structure block can be loaded based on matching dGPU's PCI Dev`ice/Vendor ID with the file Guid
+// e.g. EfiMxmStructGuid = Nvidia Mxm, AMD Mxm etc.
+// Also, multiple Mxm structure can be loaded if design supports 2 or more Mxm cards plugged in simultaneusly
+// Latter scenario will require MxmInt15.asm changes
+
+ Status = LoadFile(&EfiMxmStructGuid, &MxmData, &ImageSize);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) return Status;
+ // just in case we'll need to change MXM data
+ // MxmHdr = (MXM_STRUCT_HDR*)MxmData;
+ // if(Strcmp(MxmHdr->Sig,"*MXM_"))
+ // return EFI_UNSUPPORTED;
+
+ gMxmLegMemAddr = (UINT8*)0xE0000;
+ Size = 0x20000;
+
+#if ( defined(CSM_SUPPORT) && (CSM_SUPPORT != 0) )
+ if (!EFI_ERROR(CsmOptOutStatus)){
+ BiosExtensions->UnlockShadow(
+ (UINT8*)gMxmLegMemAddr, Size,
+ &LockUnlockAddr, &LockUnlockSize);
+ }
+#endif
+
+ gMxmLegMemAddr = MxmData;
+ // Int15 may update gMxmLegMemAddr
+#if ( defined(CSM_SUPPORT) && (CSM_SUPPORT != 0) )
+ if (!EFI_ERROR(CsmOptOutStatus)){
+ // will copy MXM struct to the address returned by Int15 5F80, Func01
+ Status = UpdateInt15MxmSISData(LegacyBiosProtocol);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+/*
+#else
+ //
+ // Allocate MXM and E000:0 area
+ //
+ Address = 0xE0000;
+ Status = pBS->AllocatePages (
+ AllocateAddress,
+ EfiBootServicesCode,
+ ImageSize,
+ &gMxmLegMemAddr);
+#endif
+*/
+ if (EFI_ERROR(Status)) {
+ BiosExtensions->LockShadow(LockUnlockAddr, LockUnlockSize);
+ return Status;
+ }
+
+ gMxmLegMemSize = ImageSize;
+ //
+ // Copy the image into the shadow.
+ //
+ pBS->CopyMem(gMxmLegMemAddr, MxmData, gMxmLegMemSize);
+
+ BiosExtensions->LockShadow(LockUnlockAddr, LockUnlockSize);
+
+ } // (!EFI_ERROR(CsmOptOutStatus))
+#endif // ( defined(CSM_SUPPORT) && (CSM_SUPPORT != 0) )
+// Install NBCI & MXM3_EFI_PROTOCOL only if Primary Display is set to enable SG
+#if SGOEMSSDT_SUPPORT
+ if ((SetupData.PrimaryDisplay == 4) || (SetupData.PrimaryDisplay == 1) || (SetupData.PrimaryDisplay == 3)) //SG
+#else
+ if (SetupData.PrimaryDisplay == 4) //SG
+#endif
+ {
+
+// Install NBCI_EFI_PROTOCOL, Int15 5F80 handle
+// Status = NBCIInterfaces(ImageHandle, SystemTable);
+// Install MXM_EFI_PROTOCOL, Int15 5F80 handle
+ Status = MXM30Interfaces(ImageHandle, SystemTable);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR(Status)) return Status;
+
+// wait till Mxm PEG Card is enumerated in BDS
+/*
+ Status = RegisterProtocolCallback(
+ &gBdsAllDriversConnectedProtocolGuid,
+ // Function is linked from MxmAcpiTable.c. Contains OEM implementation for Mxm Acpi table load
+ LoadAcpiTables,
+ NULL,
+ &mMxmEvent,
+ &mMxmReg
+ );
+
+*/
+ }
+ return Status;
+}
+
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30Dxe.dxs b/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30Dxe.dxs
new file mode 100644
index 0000000..a4ef880
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30Dxe.dxs
@@ -0,0 +1,105 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia API/Mxm30Dxe.dxs 2 9/09/12 11:12p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:12p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia API/Mxm30Dxe.dxs $
+//
+// 2 9/09/12 11:12p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] MXM30.mak
+// Mxm30Dxe.dxs
+// Mxm30Dxe.c
+// Mxm30Efi.c
+// NBCIEfi.c
+// MxmInt15.asm
+// MXM30.cif
+//
+// 2 4/11/12 4:07a Alanlin
+// Nvidia Optimus support when CSM module is disabled or CSM is never on
+// setup menu.
+//
+// 1 6/27/11 5:25a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] MXM30.cif
+// MXM30.sdl
+// MXM30.mak
+// Mxm30Dxe.dxs
+// Mxm30Dxe.c
+// Mxm30Efi.c
+// NBCIEfi.c
+// MxmInt15.asm
+// Mxm30ElkCreek4.mxm
+// Mxm30ElkCreekIII.mxm
+//
+//
+// 1 9/17/10 1:16p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// Mxm30.cif;*.sdl;*.mak;
+// Mxm30Dxe.c;*.dxs
+// Mxm30efi.c
+// MxmInt15.asm
+// NbciEfi.c
+// Mxm30ElkCreek3(4).mxm
+//
+// 2 6/03/10 3:08p Alexp
+//
+// 1 6/03/10 2:54p Alexp
+//
+//**********************************************************************
+#include <Token.h>
+#include <protocol\PciRootBridgeIo.h>
+#include <protocol\AcpiSupport.h>
+#if ( defined(CSM_SUPPORT) && (CSM_SUPPORT != 0) )
+#include <Protocol\CsmPlatform.h>
+#endif
+
+DEPENDENCY_START
+#if ( defined(CSM_SUPPORT) && (CSM_SUPPORT != 0) )
+ AMI_CSM_DRIVER_STARTED_GUID AND
+#endif
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID AND
+ EFI_ACPI_SUPPORT_GUID
+DEPENDENCY_END
+
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//**************************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30Efi.c b/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30Efi.c
new file mode 100644
index 0000000..b0aa207
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30Efi.c
@@ -0,0 +1,425 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia API/Mxm30Efi.c 2 9/09/12 11:12p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:12p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia API/Mxm30Efi.c $
+//
+// 2 9/09/12 11:12p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] MXM30.mak
+// Mxm30Dxe.dxs
+// Mxm30Dxe.c
+// Mxm30Efi.c
+// NBCIEfi.c
+// MxmInt15.asm
+// MXM30.cif
+//
+// 1 6/27/11 5:25a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] MXM30.cif
+// MXM30.sdl
+// MXM30.mak
+// Mxm30Dxe.dxs
+// Mxm30Dxe.c
+// Mxm30Efi.c
+// NBCIEfi.c
+// MxmInt15.asm
+// Mxm30ElkCreek4.mxm
+// Mxm30ElkCreekIII.mxm
+//
+//
+// 1 9/17/10 1:16p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// Mxm30.cif;*.sdl;*.mak;
+// Mxm30Dxe.c;*.dxs
+// Mxm30efi.c
+// MxmInt15.asm
+// NbciEfi.c
+// Mxm30ElkCreek3(4).mxm
+//
+// 1 6/08/10 3:43p Alexp
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name: Mxm30Efi.c
+//
+// Description: This file installs
+// 1)Mxm EFI protocol
+// 2)Mxm Legacy Int15 and
+// 3)Acpi interfaces for Switchable Graphics
+//
+// Notes: MAKE SURE NO PEI OR DXE SPECIFIC CODE IS NEEDED
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+#include <Token.h>
+#include <AmiDxeLib.h>
+#include <DXE.h>
+
+#include <Protocol\Mxm30.h>
+
+extern EFI_BOOT_SERVICES *pBS;
+extern EFI_RUNTIME_SERVICES *pRS;
+
+// Defined in Mxm30Dxe.c
+extern VOID *gMxmLegMemAddr;
+extern UINTN gMxmLegMemSize;
+/////////////////////////////////////////
+// MXM EFI PROTOCOL PROTOTYPES //
+/////////////////////////////////////////
+
+EFI_STATUS MxmReturnSpecLevel (
+ IN MXM3_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 usStructSize,
+ IN OUT CHAR8 *pucRevisionLevel,
+ OUT UINTN *puSupportFuncs
+);
+
+EFI_STATUS MxmReturnStructure (
+ IN MXM3_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 *usStructSize,
+ IN CHAR16 usDataBlockID,
+ OUT CHAR8 **pMxmStruct
+);
+
+EFI_STATUS MxmSelectOutputDevice (
+ IN MXM3_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 usStructSize,
+ IN EFI_HANDLE ChildHandle,
+ IN CHAR8 ucOutputSetting
+);
+
+EFI_STATUS MxmCheckOutputDevice (
+ IN MXM3_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 usStructSize,
+ IN EFI_HANDLE ChildHandle,
+ OUT CHAR8 ucDisplayAvailable
+);
+
+MXM3_EFI_PROTOCOL Mxm30Protocol = {
+ MxmReturnSpecLevel,
+ MxmReturnStructure,
+ MxmSelectOutputDevice,
+ MxmCheckOutputDevice
+};
+
+////////////////////////////////
+// MXM EFI PROTOCOL FUNCTIONS //
+////////////////////////////////
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: MxmReturnSpecLevel
+//
+// Description: Caller provides pointer to location, which on call contains the Module requested Spec Revision
+// Level, and which on exit, will contain the Platform's preferred Revision Level and Bit Field of
+// supported functions.
+//
+// Input: UINT8 *This
+// EFI_HANDLE ControllerHandle
+// UCHAR16 usStructSize
+//
+// Output: EFI_STATUS =
+// EFI_SUCCESS, EFI_UNSUPPORTED, EFI_INVALID_PARAMETER, EFI_BUFFER_TOO_SMALL
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+// Where the integer value passed in uSupportFuncs indicates supported functions:
+// Bit 0 = `1' (this method is required)
+// Bit 1 = `1' (MxmReturnStucture is also required)
+// Bit 2 = `1' if MxmSelectOutputDevice is supported, `0' if not
+// Bit 3 = `1' if MxmCheckOutputDevice is supported, `0' if not
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS MxmReturnSpecLevel (
+ IN MXM3_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 usStructSize,
+ IN OUT CHAR8 *pucRevisionLevel,
+ OUT UINTN *puSupportFuncs
+){
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ *pucRevisionLevel = EFI30_DataBlockID;
+ *puSupportFuncs = EFI30_SupportFuncs;
+
+ return Status;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: MxmReturnStructure
+//
+// Description: Caller provides expected MXM Interface Revision Level and a pointer which,
+// on return will contain the MXM structure.
+//
+// Input: UINT8 *This
+// EFI_HANDLE ControllerHandle
+// UCHAR16 usStructSize
+//
+// Output: EFI_STATUS =
+// EFI_SUCCESS, EFI_UNSUPPORTED, EFI_INVALID_PARAMETER, EFI_BUFFER_TOO_SMALL
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+// ControllerHandle - used to differentiate which MXM module is being referenced.
+// This is the EFI handle for the PCI device. ChildHandle where used, is the output device (the display).
+// usStructSize - set to the size of the supplied buffer by the caller, and on return should contain the
+// actual size of the structure. If the structure is larger than the buffer, EFI_BUFFER_TOO_SMALL
+// should be returned as the status of the call
+// usDataBlockID - Identifier for the data block to return. To obtain the MXM information structure, use usDataBlockID[0..7] to specify the revision
+// of the MXM software specification that is supported by the MXM module.Format is binary coded decimal, for example: 0030h = 3.0, etc.
+// To obtain an additional vendor specific data block, use lower 8 bits to specify an identifier in the range 0x80-0x8F.
+// If the system BIOS does not contain MXM Graphics Module Software Specification Version 3.0 such a data block, it should return an error.
+// Graphics vendors should not assume a specific assignment within this range - the SBIOS can store
+// the data for different vendors in any order in the 0x80-0x8F identifier range
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS MxmReturnStructure (
+ IN MXM3_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 *usStructSize,
+ IN CHAR16 usDataBlockID,
+ OUT CHAR8 **pMxmStruct
+){
+ EFI_STATUS Status = EFI_SUCCESS;
+// Only supports Rev 3.0
+ if(usDataBlockID != EFI30_DataBlockID)
+ return EFI_UNSUPPORTED;
+
+// TO DO: calculate the offset within *pMxmStruct by comparing the DevID in the MXM Header with given controller handle DevID
+ *pMxmStruct = gMxmLegMemAddr;
+ *usStructSize = (CHAR16)gMxmLegMemSize;
+
+ return Status;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: MxmSelectOutputDevice
+//
+// Description: Select Output Device Channel.
+// Caller provides the handle of the target adapter, the handle of the display and the output setting
+//
+// Input: UINT8 *This
+// EFI_HANDLE ControllerHandle
+// UCHAR16 usStructSize
+//
+// Output: EFI_STATUS =
+// EFI_SUCCESS, EFI_UNSUPPORTED, EFI_INVALID_PARAMETER, EFI_BUFFER_TOO_SMALL
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+// Where the value passed in ucOutputSetting may indicate one of the following actions:
+// 0 - Acquire shared Display DDC
+// 1 - Enable this Display Output
+// 3 - Enable this Display - Both Output and DDC
+// 4 - Release shared Display DDC
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS MxmSelectOutputDevice (
+ IN MXM3_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 usStructSize,
+ IN EFI_HANDLE ChildHandle,
+ IN CHAR8 ucOutputSetting
+){
+
+ return EFI_UNSUPPORTED;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: MxmCheckOutputDevice
+//
+// Description: Check Availability of Output Device. Caller provides the handle of
+// the target adapter and the handle of the display
+//
+// Input: UINT8 *This
+// EFI_HANDLE ControllerHandle
+// UCHAR16 usStructSize
+//
+// Output: EFI_STATUS =
+// EFI_SUCCESS, EFI_UNSUPPORTED, EFI_INVALID_PARAMETER, EFI_BUFFER_TOO_SMALL
+// UCHAR8 ucDisplayAvailable
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes: The returned value ucDisplayAvailable will be one of the following values:
+// 0 - Connector is currently available
+// 1 - Connector is not currently available
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS MxmCheckOutputDevice (
+ IN MXM3_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 usStructSize,
+ IN EFI_HANDLE ChildHandle,
+ OUT CHAR8 ucDisplayAvailable
+){
+
+ return EFI_UNSUPPORTED;
+}
+
+///////////////////////////////////////
+// END of MXM EFI PROTOCOL FUNCTIONS //
+///////////////////////////////////////
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: LoadFile
+//
+// Description: Reads the file with the given GUID.
+//
+// Input:
+// IN EFI_GUID *Guid,
+// IN VOID **Buffer
+// IN UINTN *BufferSize
+//
+// Output:
+// EFI_STATUS
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS LoadFile(
+ EFI_GUID *Guid,
+ VOID **Buffer,
+ UINTN *BufferSize
+)
+{
+ EFI_STATUS Status;
+ UINTN NumHandles;
+ EFI_HANDLE *HandleBuffer;
+ EFI_FIRMWARE_VOLUME_PROTOCOL *Fv;
+ UINT32 FvStatus;
+ UINTN i;
+ EFI_GUID EfiFVProtocolGuid = EFI_FIRMWARE_VOLUME_PROTOCOL_GUID;
+
+ *Buffer = 0;
+ *BufferSize = 0;
+
+ Status = pBS->LocateHandleBuffer(ByProtocol,&EfiFVProtocolGuid,NULL,&NumHandles,&HandleBuffer);
+ if (EFI_ERROR(Status)) return Status;
+
+ for (i = 0; i < NumHandles; ++i) {
+ Status = pBS->HandleProtocol(HandleBuffer[i],&EfiFVProtocolGuid,&Fv);
+ if (EFI_ERROR(Status)) continue;
+ Status = Fv->ReadSection(Fv,Guid,EFI_SECTION_RAW,0,Buffer,BufferSize,&FvStatus);
+ if (Status == EFI_SUCCESS) break;
+ }
+
+ pBS->FreePool(HandleBuffer);
+ return Status;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: MXM30Interfaces
+//
+// Description: Entry point of EFI MXM Support driver. The function istalls
+// 1. Install MXM protocol;
+// 2. Update data structure to be passed to Int15 binary
+// must support multiple MXM data modules. Dependent on controller's handle
+// Load MXM data block <1Mb area.
+// a. Copy MXM Structure below 1MB
+// 1. Allocate Legacy mem space for MXM dat <1MB
+// OR
+// 2. Update the MXM data by the pointer returned by Int15 5F80 Func01(default)
+// b. Update the pointer to MXM data in EFI Protocol API
+// c. Create an ACPI SSDT table and copy MXM block there (ASL MXM logic must handle different MXM modules...)
+//
+// Input: EFI_HANDLE ImageHandle,
+// EFI_SYSTEM_TABLE *SystemTable
+//
+// Output: EFI_STATUS
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS
+MXM30Interfaces (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ EFI_GUID gEfiMxm3ProtocolGuid = MXM3_EFI_GUID;
+
+ Status = pBS->InstallProtocolInterface (
+ &ImageHandle,
+ &gEfiMxm3ProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &Mxm30Protocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30ElkCreek4.mxm b/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30ElkCreek4.mxm
new file mode 100644
index 0000000..a5712b1
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30ElkCreek4.mxm
Binary files differ
diff --git a/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30ElkCreekIII.mxm b/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30ElkCreekIII.mxm
new file mode 100644
index 0000000..3eebd74
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/MXM30/Mxm30ElkCreekIII.mxm
Binary files differ
diff --git a/Board/EM/SwitchableGraphics/SgTpv/MXM30/MxmInt15.asm b/Board/EM/SwitchableGraphics/SgTpv/MXM30/MxmInt15.asm
new file mode 100644
index 0000000..ad7ea06
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/MXM30/MxmInt15.asm
@@ -0,0 +1,553 @@
+
+ TITLE MXMINT15.ASM -- OEM INTERRUPT IMPLEMENTATION
+
+;**********************************************************************
+;**********************************************************************
+;** **
+;** (C)Copyright 1985-2012, American Megatrends, Inc. **
+;** **
+;** All Rights Reserved. **
+;** **
+;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+;** **
+;** Phone: (770)-246-8600 **
+;** **
+;**********************************************************************
+;**********************************************************************
+;**********************************************************************
+; $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia API/MxmInt15.asm 2 9/09/12 11:12p Joshchou $
+;
+; $Revision: 2 $
+;
+; $Date: 9/09/12 11:12p $
+;**********************************************************************
+; Revision History
+; ----------------
+; $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia API/MxmInt15.asm $
+;
+; 2 9/09/12 11:12p Joshchou
+; [TAG] None
+; [Category] Improvement
+; [Description] Tpv module support for sharkbay.
+; [Files] MXM30.mak
+; Mxm30Dxe.dxs
+; Mxm30Dxe.c
+; Mxm30Efi.c
+; NBCIEfi.c
+; MxmInt15.asm
+; MXM30.cif
+;
+; 1 6/27/11 5:25a Alanlin
+; [TAG] EIP61848
+; [Category] New Feature
+; [Description] Initial check-in.Integrated SwitchableGraphics Intel
+; Reference code 0.6.0
+; [Files] MXM30.cif
+; MXM30.sdl
+; MXM30.mak
+; Mxm30Dxe.dxs
+; Mxm30Dxe.c
+; Mxm30Efi.c
+; NBCIEfi.c
+; MxmInt15.asm
+; Mxm30ElkCreek4.mxm
+; Mxm30ElkCreekIII.mxm
+;
+;
+; 1 9/17/10 1:16p Alexp
+; [TAG] EIP43103
+; [Category] Function Request
+; [Severity] Normal
+; [Symptom] Initial check-in of SgTPV module
+; [RootCause] Request to implement SG reference code .
+; [Solution] Initial check-in.
+; [Files]
+; Mxm30.cif;*.sdl;*.mak;
+; Mxm30Dxe.c;*.dxs
+; Mxm30efi.c
+; MxmInt15.asm
+; NbciEfi.c
+; Mxm30ElkCreek3(4).mxm
+;
+; 2 6/03/10 3:07p Alexp
+;
+; 1 6/03/10 2:54p Alexp
+;
+;
+;**********************************************************************
+INCLUDE Token.equ
+.386p
+
+CSMOEM_CSEG SEGMENT PARA PUBLIC 'CODE' USE16
+ ASSUME cs:CSMOEM_CSEG, ds:CSMOEM_CSEG
+
+OldIntHandler LABEL DWORD
+ IntSegSav dw 0
+ IntOfsSav dw 0
+
+;<AMI_FHDR_START>
+;---------------------------------------------------------------------------
+;
+; Name: MXMINT15Proc
+;
+; Description: MXM INT15 function implememtation
+; + nVidia's NBCI Int15 supplement functions
+;
+;---------------------------------------------------------------------------
+;<AMI_FHDR_END>
+
+MXMINT15Proc PROC NEAR PUBLIC
+
+ cmp ax, 5f80h
+ je igd_mxmcall
+; cmp ax, 5f14h ; NVidia Vbios is calling this method. Keeping it commented out since the call is not documented
+; je igd_misccall
+ jmp DWORD PTR cs:[OldIntHandler]
+
+;;igd_misccall:
+;; Output Spec Support Level
+;; BX = 078Fh, Get Miscellaneous Status
+; cmp bx, 078fh
+; jne notSupported
+;; CL = Bit map of dock, lid and AC status:
+;; Bits 7 - 3 = Reserved
+;; Bit 2 = 0, no AC power
+;; = 1, AC power active
+;; Bit 1 = 0, lid open
+;; = 1, lid closed
+;; Bit 0 = 0, not docked
+;; = 1, docked
+; mov cl, 00000100b ; Bitmap of supported functions.
+; jmp short mxmExit
+
+igd_mxmcall:
+
+; MXM rev3.0 <=9
+; NBCI <=9
+; Optimus 13
+ cmp bl, 13
+ ja short notSupported
+
+ push si
+ movzx si, bl
+ shl si, 1
+ stc ; default->not supported
+ call WORD PTR cs:[mxmFuncTable+si] ; Call this function.
+ pop si
+ jc short notSupported
+mxmExit:
+
+ mov ax, 05fh
+
+notSupported:
+; sti
+ clc
+ retf 0002
+; iret
+
+MXMINT15Proc ENDP
+
+mxmFuncTable::
+ DW OFFSET mxmInt15Fun0
+ DW OFFSET mxmInt15Fun1
+ DW OFFSET mxmInt15Fun2
+ DW OFFSET mxmInt15Fun3
+ DW OFFSET mxmInt15Fun4
+ DW OFFSET mxmnotSupported ; mxmInt15Fun5
+ DW OFFSET mxmnotSupported ; mxmInt15Fun6
+ DW OFFSET mxmInt15Fun7
+ DW OFFSET mxmInt15Fun8
+ DW OFFSET mxmInt15Fun9
+ DW OFFSET mxmnotSupported ; mxmInt15FunA
+ DW OFFSET mxmnotSupported ; mxmInt15FunB
+ DW OFFSET mxmnotSupported ; mxmInt15FunC
+ DW OFFSET mxmInt15FunD ; OptimusInt15FunD
+
+mxmDODTable:: ; table must be consistent with _DOD method return in ASL
+ DD 80000100h ; CRT
+ DD 80000400h ; LVDS
+ DD 80006300h ; DP_B
+ DD 80008301h ; dP->HDMI B interop dongle
+ DD 80008302h ; dP->HDMI C interop dongle
+ DD 80006303h ; DP_D
+
+DODCount EQU (($ - mxmDODTable) / 4)
+
+mxmFunc4String::
+ DB 'MXM 3.0 VBIOS: AMI Int15 5F80 Interface', 0dh, 0ah, 0
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+; Procedure: mxmnotSupported
+; Input:
+; Output:
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+mxmnotSupported PROC NEAR
+ ret
+mxmnotSupported ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+; Procedure: mxmInt15Fun0
+; Description: Function 0 Output Specification Support Level
+; Input:
+; AX = 5F80h ; MXM2.0, MXM2.1, MXM3.0
+; BL = 00h ; MXM2.0, MXM2.1, MXM3.0
+; BH = Adapter Index ; MXM2.0, MXM2.1
+; 0 = Primary MXM adapter (default) ; MXM2.0, MXM2.1
+; 1 = Secondary MXM adapter ; MXM2.0, MXM2.1
+; BH = FFh ; MXM3.0
+; EBX[31:16] = Adapter ID ; MXM3.0
+; Bits [31:24] Bus ; MXM3.0
+; Bits [23:19] Device ; MXM3.0
+; Bits [18:16] Function ; MXM3.0
+; CL = Revision of the MXM software specification that is supported by the MXM module ; MXM2.0, MXM2.1
+; Format is binary coded decimal, for example:
+; 10h = 1.0, 11h = 1.1, 20h = 2.0, etc.
+; CX = Revision of the MXM software specification that is supported by the MXM module. ; MXM3.0
+; Format is binary coded decimal, for example: 0030h = 3.0, etc
+; CX = 'OP' 4F50h Optimus Interface
+; CX = 'NB' 4E42h NBCI Interface
+; Output:
+; AX = 005Fh to indicate that the system bios supports this function ; MXM2.0, MXM2.1, MXM3.0
+; BL = Revision of the MXM software specification that is supported by the system ; MXM2.0, MXM2.1, MXM3.0
+; Format is binary coded decimal, for example:
+; 10h = 1.0, 11h = 1.1, 20h = 2.0, etc.
+; CX = MXM functions supported ; MXM2.0, MXM2.1, MXM3.0
+; Bit 0 = 1
+; Bit 1 = 1 if Function 1 is supported, 0 if not supported ; MXM2.0, MXM2.1, MXM3.0
+; Bit 2 = 1 if Function 2 is supported, 0 if not supported ; MXM2.0, MXM2.1, MXM3.0
+; Bit 3 = 1 if Function 3 is supported, 0 if not supported ; MXM2.0, MXM2.1, MXM3.0
+; Bit 4 = 1 if Function 4 is supported, 0 if not supported ; MXM2.1, MXM3.0
+; Bit 7 = 1 if Function 7 is supported, 0 if not supported ; MXM3.0
+; Bit 8 = 1 if Function 8 is supported, 0 if not supported ; MXM3.0
+; Bit 9 = 1 if Function 9 is supported, 0 if not supported ; MXM3.0
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+mxmInt15Fun0 PROC NEAR
+; Check signature if Optimus, Mxm or NBCI
+ cmp cx, 'OP'
+ je OptimusFun1
+; MXM rev3.0
+ mov bl, 030h ; Support 3.0
+ mov cx, 0000010011b ; Support funcion 0,1,4
+ jmp short @F
+; mov cx, 1100001011b ; Support funcion 0,1,3,8,9
+; mov cx, 11 0001 1011b ; Support funcion 0,1,3,4,8,9
+; mov cx, 1110011111b ; Support funcion 0,1,2,3,4,7,8,9.
+OptimusFun1:
+ mov bl, 011h ; rev 1.1
+ mov cx, 2001h ; Support funcion 0,13
+@@:
+ clc
+ ret
+mxmInt15Fun0 ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+; Procedure: mxmInt15Fun1
+; Description: Function 1 Output a Pointer to the MXM Structure
+; Input:
+; AX = 5F80h ; MXM2.0, MXM2.1, MXM3.0
+; BL = 01h ; MXM2.0, MXM2.1, MXM3.0
+; BH = FFh ; MXM3.0
+; EBX[31:16] = Adapter ID ; MXM3.0
+; Bits [31:24] Bus ; MXM3.0
+; Bits [23:19] Device ; MXM3.0
+; Bits [18:16] Function ; MXM3.0
+; CL = Revision of the MXM software specification that is supported by the MXM module ; MXM2.0, MXM2.1
+; CX = Identifier for the data block to return ; MXM3.0
+; Output:
+; AX = 005Fh to indicate that the system bios supports this function ; MXM2.0, MXM2.1, MXM3.0
+; BX = Vendor ID of data block if CX = 0x80-0x8F, else 0. ; MXM3.0
+; ES:DI = Pointer to the MXM structure in real mode memory (< 1MB) ; MXM2.0, MXM2.1, MXM3.0
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+mxmInt15Fun1 PROC NEAR
+
+; MXM rev3.0
+ mov di, OFFSET mxm30Struc
+ cmp cl, 030h ; Assume this DI for 3.0 MXM.
+ jz short returnMxmStruc
+
+ jmp short exit
+
+returnMxmStruc:
+ mov bx, 0
+ mov ax, cs ; Get ES for MXM structure.
+ mov es, ax
+ clc
+exit:
+ ret
+mxmInt15Fun1 ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+; Procedure: mxmInt15Fun2
+; Description: Function 2 Output a Pointer to the EDID Structure for the Internal Panel
+; Input:
+; AX = 5F80h ; MXM2.0, MXM2.1, MXM3.0
+; BL = 02h ; MXM2.0, MXM2.1, MXM3.0
+; BH = Adapter Index ; MXM2.0, MXM2.1
+; 0 = Primary MXM adapter (default)
+; 1 = Secondary MXM adapter
+; BH = FFh ; MXM3.0
+; EBX[31:16] = Adapter ID ; MXM3.0
+; Bits [31:24] Bus
+; Bits [23:19] Device
+; Bits [18:16] Function
+; EDX = Display device identifier (32-bit value as used in _DOD) ; MXM3.0
+; Output:
+; AX = 005Fh to indicate that the system bios supports this function ; MXM2.0, MXM2.1, MXM3.0
+; BL = EDID structures returned ; MXM2.1, MXM3.0
+; 00 = 128byte EDID 1.3 followed by a 128byte DI-EXT block.
+; 02 = 128byte EDID 1.3 structure only
+; ES:DI = Pointer to the EDID structure in real mode memory (< 1MB) ; MXM2.0, MXM2.1, MXM3.0
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+mxmInt15Fun2 PROC NEAR
+ ret
+mxmInt15Fun2 ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+; Procedure: mxmInt15Fun3
+; Description: Function 3 Select Output Device Channel
+; Input:
+; AX = 5F80h ; MXM2.0, MXM2.1, MXM3.0
+; BL = 03h ; MXM2.0, MXM2.1, MXM3.0
+; BH = Adapter Index ; MXM2.0, MXM2.1
+; 0 = Primary MXM adapter (default)
+; 1 = Secondary MXM adapter
+; BH = FFh ; MXM3.0
+; EBX[31:16] = Adapter ID ; MXM3.0
+; Bits [31:24] Bus
+; Bits [23:19] Device
+; Bits [18:16] Function
+; CL = Selection ; MXM2.0, MXM2.1, MXM3.0
+; 0 - Acquire shared Display DDC
+; 1 - Display Output
+; 3 - Both
+; 4 - Release shared Display DDC
+; CH = Device index (range 0 - 7) ; MXM2.0, MXM2.1
+; according to the order in which the MXM Output Device Structure
+; for this device appears in the MXM Data Structure.
+; EDX = Display device identifier (32-bit value as used in _DOD) ; MXM3.0
+; Output:
+; AX = 005Fh to indicate that the SBIOS supports this function ; MXM2.0, MXM2.1, MXM3.0
+; BL For CL=0 the SBIOS shall return a 0h if the mutex was successfully acquired. ; MXM2.0, MXM2.1, MXM3.0
+; When non-zero the mutex was not aquired.
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+mxmInt15Fun3 PROC NEAR
+;; mov bl, 0 ; Display DDC acquired
+;; mov cl, 0 ; Display DDC acquired
+ mov bl, cl ; temp fix. actual mutex lock implementation is needed
+ clc
+ ret
+mxmInt15Fun3 ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+; Procedure: mxmInt15Fun4
+; Description: Function 4 Boot Message
+; Input:
+; AX = 5F80h ; MXM2.1, MXM3.0
+; BL = 04h ; MXM2.1, MXM3.0
+; Output:
+; AX = 005Fh to indicate that the SBIOS supports this function ; MXM2.1, MXM3.0
+; BL = Mode If zero then the Pointer is a (zero-terminated) Sign-On Text String. ; MXM2.1
+; BX = Mode If zero then the Pointer is a (zero-terminated) Sign-On Text String. ; MXM3.0
+; ES:DI = Pointer String/Image in real mode memory (< 1MB). ; MXM2.1, MXM3.0
+; A zero length string indicates the normal sign-on message should be suppressed
+; e.g. to support a graphical splash screen.
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+mxmInt15Fun4 PROC NEAR
+; Note. Nvidia Vbios replaces normal Vbios POST messages with the boot string
+ mov di, OFFSET mxmFunc4String
+ mov bx, 0
+ mov ax, cs ; Get ES for MXM structure.
+ mov es, ax
+ clc
+ ret
+mxmInt15Fun4 ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+; Procedure: mxmInt15Fun7
+; Description: Function 7 Returns a Pointer to the VBIOS Image for ROM-Less Adapters
+; Input:
+; AX = 5F80h ; MXM3.0
+; BL = 07h ; MXM3.0
+; BH = FFh ; MXM3.0
+; EBX[31:16] = Adapter ID ; MXM3.0
+; Bits [31:24] Bus
+; Bits [23:19] Device
+; Bits [18:16] Function
+; Output:
+; AX = 005Fh to indicate that the SBIOS supports this function ; MXM3.0
+; ES:DI = Pointer to the requested VBIOS image in real mode memory (< 1MB). ; MXM3.0
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+mxmInt15Fun7 PROC NEAR
+ ret
+mxmInt15Fun7 ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+; Procedure: mxmInt15Fun8
+; Description: Function 8 Check Availability of Output Device
+; Input:
+; AX = 5F80h ; MXM3.0
+; BL = 08h ; MXM3.0
+; BH = FFh ; MXM3.0
+; EBX[31:16] = Adapter ID ; MXM3.0
+; Bits [31:24] Bus
+; Bits [23:19] Device
+; Bits [18:16] Function
+; EDX = Display device identifier (32-bit value as used in _DOD) ; MXM3.0
+; Output:
+; AX = 005Fh to indicate that the SBIOS supports this function ; MXM3.0
+; BL = Available ; MXM3.0
+; BL = 0 indicates the connector is currently available.
+; BL = 1 indicates the connector is not currently available
+; and no display detection should occur on it.
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+mxmInt15Fun8 PROC NEAR
+
+ cmp bh, 0ffh
+ jne invalidDOD
+ mov si, 0
+ mov cx, DODCount ; no of entries
+@@: cmp edx, DWORD PTR cs:[mxmDODTable+si] ; Call this function.
+ je goodDOD
+ add si, 4 ; dword offset
+ loop @B
+
+invalidDOD:
+ stc ; default->not supported
+ mov bl, 1 ; connector is not currently available
+ ret
+
+goodDOD:
+ mov bl, 0 ; connector is available
+ clc
+ ret
+mxmInt15Fun8 ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+; Procedure: mxmInt15Fun9
+; Description: Function 9 Identify Output Devices
+; Input:
+; AX = 5F80h ; MXM3.0
+; BL = 09h ; MXM3.0
+; BH = 00h ; MXM3.0
+; Output:
+; AX = 005Fh to indicate that the SBIOS supports this function; MXM3.0
+; BL = Number of entries in table. ; MXM3.0
+; ES:DI = Pointer to the table. ; MXM3.0
+; This is a table of 32-bit values identical to the buffer returned by _DOD. ; MXM3.0
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+mxmInt15Fun9 PROC NEAR
+
+ cmp bh, 0
+ jne invalidFunc9
+ mov di, OFFSET mxmDODTable
+ mov bl, DODCount ; number of entries
+ mov ax, cs
+ mov es, ax
+ clc
+invalidFunc9:
+ ret
+mxmInt15Fun9 ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+; Procedure: mxmInt15FunD
+; Description: Optimus: Discrete graphics subsystem power control
+; Input:
+; AX = 5F80h
+; BL = 0Dh
+; BH = FFh
+; EBX[31:16] = Adapter ID
+; Bits [31:24] Bus
+; Bits [23:19] Device
+; Bits [18:16] Function
+; CL = Request GPU subsystem state (0 = Powered off/1 = Powered on)
+; Output:
+; AX = 005Fh to indicate that the system bios supports this function and it completed successfully
+; BL = GPU power state which has been set
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+mxmInt15FunD PROC NEAR
+;!!!! EmeraldLake specific
+ mov dx, 0538h ; DX = mux register
+ cmp cl, 0
+ je dGPU_off
+ cmp cl, 1
+ je dGPU_on
+ ret
+
+dGPU_off:
+ in eax, dx
+ or eax, 00400000h
+ out dx, eax
+ mov bl, cl
+ jmp short OK_FuncD
+
+dGPU_on:
+ in eax, dx
+ and eax, NOT (00400000h)
+ out dx, eax
+ mov bl, cl
+;!!!! EmeraldLake specific
+
+OK_FuncD:
+ clc
+ ret
+mxmInt15FunD ENDP
+
+ PUBLIC mxmStrucSrart
+mxmStrucSrart:
+
+;----------------------------------------------------------------------------
+; MXM rev3.0 data structure
+;----------------------------------------------------------------------------
+mxm30Struc:
+; include MXM30.INC ; First SIS is for first MXM in single MXM config (instance index 0)
+ MxmTbl db MKF_MXM_ROM_MAX_SIZE dup (0dbh)
+
+ PUBLIC mxmStrucEnd
+mxmStrucEnd:
+
+
+CSMOEM_CSEG ENDS
+END
+
+
+;**********************************************************************
+;**********************************************************************
+;** **
+;** (C)Copyright 1985-2012, American Megatrends, Inc. **
+;** **
+;** All Rights Reserved. **
+;** **
+;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+;** **
+;** Phone: (770)-246-8600 **
+;** **
+;**********************************************************************
+;**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/MXM30/NBCIEfi.c b/Board/EM/SwitchableGraphics/SgTpv/MXM30/NBCIEfi.c
new file mode 100644
index 0000000..eeaf289
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/MXM30/NBCIEfi.c
@@ -0,0 +1,367 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia API/NBCIEfi.c 2 9/09/12 11:12p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:12p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia API/NBCIEfi.c $
+//
+// 2 9/09/12 11:12p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] MXM30.mak
+// Mxm30Dxe.dxs
+// Mxm30Dxe.c
+// Mxm30Efi.c
+// NBCIEfi.c
+// MxmInt15.asm
+// MXM30.cif
+//
+// 1 6/27/11 5:25a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] MXM30.cif
+// MXM30.sdl
+// MXM30.mak
+// Mxm30Dxe.dxs
+// Mxm30Dxe.c
+// Mxm30Efi.c
+// NBCIEfi.c
+// MxmInt15.asm
+// Mxm30ElkCreek4.mxm
+// Mxm30ElkCreekIII.mxm
+//
+//
+// 1 9/17/10 1:16p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// Mxm30.cif;*.sdl;*.mak;
+// Mxm30Dxe.c;*.dxs
+// Mxm30efi.c
+// MxmInt15.asm
+// NbciEfi.c
+// Mxm30ElkCreek3(4).mxm
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name: NBCIEfi.c
+//
+// Description: This file installs
+// Nbci EFI protocol
+//
+// Notes: MAKE SURE NO PEI OR DXE SPECIFIC CODE IS NEEDED
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+#include <Token.h>
+#include <AmiDxeLib.h>
+#include <DXE.h>
+
+#include <Protocol\NBCI.h>
+
+extern EFI_BOOT_SERVICES *pBS;
+extern EFI_RUNTIME_SERVICES *pRS;
+
+// Defined in Mxm30Dxe.c
+extern VOID *gMxmLegMemAddr;
+extern UINTN gMxmLegMemSize;
+/////////////////////////////////////////
+// Nbci EFI PROTOCOL PROTOTYPES //
+/////////////////////////////////////////
+
+EFI_STATUS NbciReturnSpecLevel (
+ IN NBCI_EFI_PROTOCOL *This,
+ IN OUT CHAR8 *pucRevisionLevel,
+ OUT UINTN *puSupportFuncs
+);
+
+EFI_STATUS NbciReturnStructure (
+ IN NBCI_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 usStructSize,
+ IN CHAR16 usDataBlockID,
+ OUT CHAR8 *pNbciStruct
+);
+
+EFI_STATUS NbciSelectOutputDevice (
+ IN NBCI_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 usStructSize,
+ IN EFI_HANDLE ChildHandle,
+ IN CHAR8 ucOutputSetting
+);
+
+EFI_STATUS NbciCheckOutputDevice (
+ IN NBCI_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 usStructSize,
+ IN EFI_HANDLE ChildHandle,
+ OUT CHAR8 ucDisplayAvailable
+);
+
+NBCI_EFI_PROTOCOL NBCIProtocol = {
+ NbciReturnSpecLevel,
+ NbciReturnStructure,
+ NbciSelectOutputDevice,
+ NbciCheckOutputDevice
+};
+
+// Auxilary Functions. Defined in Mxm30Efi.c
+EFI_STATUS UpdateInt15MxmSISData (
+ IN EFI_LEGACY_BIOS_PROTOCOL *LegacyBiosProtocol
+);
+
+////////////////////////////////
+// Nbci EFI PROTOCOL FUNCTIONS //
+////////////////////////////////
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: NbciReturnSpecLevel
+//
+// Description: Caller provides pointer to location, which on call contains the Module requested Spec Revision
+// Level, and which on exit, will contain the Platform's preferred Revision Level and Bit Field of
+// supported functions.
+//
+// Input:
+// CHAR8 *pucRevisionLevel
+// UINTN *puSupportFuncs
+//
+// Output: EFI_STATUS =
+// EFI_SUCCESS, EFI_UNSUPPORTED, EFI_INVALID_PARAMETER, EFI_BUFFER_TOO_SMALL
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+// Where the integer value passed in uSupportFuncs indicates supported functions:
+// Bit 0 = `1' (this method is required)
+// Bit 1 = `1' (NbciReturnStucture is also required)
+// Bit 2 = `1' if NbciSelectOutputDevice is supported, `0' if not
+// Bit 3 = `1' if NbciCheckOutputDevice is supported, `0' if not
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS NbciReturnSpecLevel (
+ IN NBCI_EFI_PROTOCOL *This,
+ IN OUT CHAR8 *pucRevisionLevel,
+ OUT UINTN *puSupportFuncs
+){
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ *pucRevisionLevel = EFI_NBCI_DataBlockID;
+ *puSupportFuncs = EFI_NBCI_SupportFuncs;
+
+ return Status;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: NbciReturnStructure
+//
+// Description: Caller provides expected Nbci Interface Revision Level and a pointer which,
+// on return will contain the Nbci structure.
+//
+// Input: UINT8 *This
+// EFI_HANDLE ControllerHandle
+// UCHAR16 usStructSize
+//
+// Output: EFI_STATUS =
+// EFI_SUCCESS, EFI_UNSUPPORTED, EFI_INVALID_PARAMETER, EFI_BUFFER_TOO_SMALL
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+// ControllerHandle - used to differentiate which Nbci module is being referenced.
+// This is the EFI handle for the PCI device. ChildHandle where used, is the output device (the display).
+// usStructSize - set to the size of the supplied buffer by the caller, and on return should contain the
+// actual size of the structure. If the structure is larger than the buffer, EFI_BUFFER_TOO_SMALL
+// should be returned as the status of the call
+// usDataBlockID - Identifier for the data block to return. To obtain the Nbci information structure, use usDataBlockID[0..7] to specify the revision
+// of the Nbci software specification that is supported by the Nbci module.Format is binary coded decimal, for example: 0030h = 3.0, etc.
+// To obtain an additional vendor specific data block, use lower 8 bits to specify an identifier in the range 0x80-0x8F.
+// If the system BIOS does not contain Nbci Graphics Module Software Specification Version 3.0 such a data block, it should return an error.
+// Graphics vendors should not assume a specific assignment within this range - the SBIOS can store
+// the data for different vendors in any order in the 0x80-0x8F identifier range
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS NbciReturnStructure (
+ IN NBCI_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 *usStructSize,
+ IN CHAR16 usDataBlockID,
+ OUT CHAR8 **pNbciStruct
+){
+ EFI_STATUS Status = EFI_SUCCESS;
+// Only supports Rev 3.0
+ if(usDataBlockID != EFI_NBCI_DataBlockID)
+ return EFI_UNSUPPORTED;
+
+ UpdateInt15MxmSISData(This);
+
+// TO DO: calculate the offset within *pNbciStruct by comparing the DevID in the Nbci Header with given controller handle DevID
+ *pNbciStruct = (CHAR8*)gMxmLegMemAddr;
+ *usStructSize = (CHAR16)gMxmLegMemSize;
+
+ return Status;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: NbciSelectOutputDevice
+//
+// Description: Select Output Device Channel.
+// Caller provides the handle of the target adapter, the handle of the display and the output setting
+//
+// Input: UINT8 *This
+// EFI_HANDLE ControllerHandle
+// UCHAR16 usStructSize
+//
+// Output: EFI_STATUS =
+// EFI_SUCCESS, EFI_UNSUPPORTED, EFI_INVALID_PARAMETER, EFI_BUFFER_TOO_SMALL
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+// Where the value passed in ucOutputSetting may indicate one of the following actions:
+// 0 - Acquire shared Display DDC
+// 1 - Enable this Display Output
+// 3 - Enable this Display - Both Output and DDC
+// 4 - Release shared Display DDC
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS NbciSelectOutputDevice (
+ IN NBCI_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 usStructSize,
+ IN EFI_HANDLE ChildHandle,
+ IN CHAR8 ucOutputSetting
+){
+
+ return EFI_UNSUPPORTED;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: NbciCheckOutputDevice
+//
+// Description: Check Availability of Output Device. Caller provides the handle of
+// the target adapter and the handle of the display
+//
+// Input: UINT8 *This
+// EFI_HANDLE ControllerHandle
+// UCHAR16 usStructSize
+//
+// Output: EFI_STATUS =
+// EFI_SUCCESS, EFI_UNSUPPORTED, EFI_INVALID_PARAMETER, EFI_BUFFER_TOO_SMALL
+// UCHAR8 ucDisplayAvailable
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes: The returned value ucDisplayAvailable will be one of the following values:
+// 0 - Connector is currently available
+// 1 - Connector is not currently available
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS NbciCheckOutputDevice (
+ IN NBCI_EFI_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN OUT CHAR16 usStructSize,
+ IN EFI_HANDLE ChildHandle,
+ OUT CHAR8 ucDisplayAvailable
+){
+
+ return EFI_UNSUPPORTED;
+}
+
+///////////////////////////////////////
+// END of Nbci EFI PROTOCOL FUNCTIONS //
+///////////////////////////////////////
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: NBCIInterfaces
+//
+// Description: Common entry point to install:
+// 1. Install Nbci protocol;
+//
+// Input: EFI_HANDLE ImageHandle
+//
+// Output: EFI_STATUS
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS
+NBCIInterfaces (
+ IN EFI_HANDLE ImageHandle
+)
+{
+ EFI_STATUS Status;
+ EFI_GUID gEfiNBCIProtocolGuid = NBCI_EFI_GUID;
+
+// Install NBCI_EFI_PROTOCOL
+ Status = pBS->InstallProtocolInterface (
+ &ImageHandle,
+ &gEfiNbciProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &NBCIProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.asl b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.asl
new file mode 100644
index 0000000..93eabab
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.asl
@@ -0,0 +1,79 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia Optimus SMM/NvOptimusSMM.asl 2 9/09/12 11:07p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:07p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia Optimus SMM/NvOptimusSMM.asl $
+//
+// 2 9/09/12 11:07p Joshchou
+// [TAG] EIPNone
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] NvOptimusSMM.mak
+// NvOptimusSMM.c
+// NvOptimusSMM.dxs
+// NvOptimusSMM.ssp
+// NvOptimusSMM.asl
+// NvOptimusSMM.cif
+//
+//**********************************************************************
+External(DGPU_SCOPE.OPTF)
+
+Scope(\_SB.PCI0.LPCB.EC0) {
+ Method(_Q4F) {
+
+ If(LEqual(HMIS, one))
+ {
+ Store(0, DGPU_SCOPE.OPTF)
+ }
+ else
+ {
+ Store(1, DGPU_SCOPE.OPTF)
+ }
+ Notify(PEG_SCOPE,0x81)
+
+ }
+
+ OperationRegion(ECIS, EmbeddedControl, 0, 0xFF) // dummy
+
+ Field(ECIS, ByteAcc, Lock, Preserve) {
+
+ offset(0x78), //
+ , 6,
+ HMIS, 1, // 1 : hdmi plug in, 0 : out
+ }
+
+}
+
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.c b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.c
new file mode 100644
index 0000000..85a894c
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.c
@@ -0,0 +1,223 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia Optimus SMM/NvOptimusSMM.c 3 10/16/12 4:25a Joshchou $
+//
+// $Revision: 3 $
+//
+// $Date: 10/16/12 4:25a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia Optimus SMM/NvOptimusSMM.c $
+//
+// 3 10/16/12 4:25a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Update for SA and ACPI RC 0.7.1
+// [Files] NvOptimusSmm.c
+//
+// 2 9/09/12 11:07p Joshchou
+// [TAG] EIPNone
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] NvOptimusSMM.mak
+// NvOptimusSMM.c
+// NvOptimusSMM.dxs
+// NvOptimusSMM.ssp
+// NvOptimusSMM.asl
+// NvOptimusSMM.cif
+//
+//**********************************************************************
+#include "Efi.h"
+#include "token.h"
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+#include <Protocol\SmmSwDispatch.h>
+#include <Protocol\SmmBase.h>
+#include <CmosAccess.h>
+#include <Core\EM\CmosManager\CmosManager.h>
+
+#include <SaGlobalNvsArea\SaGlobalNvsArea.h>
+
+
+SYSTEM_AGENT_GLOBAL_NVS_AREA *mSaGlobalNvsAreaPtr = NULL;
+extern EFI_BOOT_SERVICES *pBS;
+//
+// GUID Definitions
+//
+EFI_GUID mSwDispatchProtocolGuid = EFI_SMM_SW_DISPATCH_PROTOCOL_GUID;
+EFI_GUID gSmmCmosServiceProtocolGuid = EFI_SMM_CMOS_ACCESS_GUID;
+EFI_GUID gSaGlobalNvsAreaProtocolGuid = SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL_GUID;
+
+EFI_CMOS_MANAGER_INTERFACE *CmosManager=NULL ;
+VOID NvCmosFunction (EFI_HANDLE DispatchHandle,EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext );
+VOID NvCmosFunction1 (EFI_HANDLE DispatchHandle,EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext );
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: NvCmosFunction
+//
+// Description: Write AcpiNvs->AudioCodec to CMOS:AudioCodec.
+//
+// Input:EFI_HANDLE DispatchHandle,
+// EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
+//
+// Output:
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+VOID NvCmosFunction (
+ IN EFI_HANDLE DispatchHandle,
+ IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext )
+{
+ UINT8 CheckPoint;
+
+ CheckPoint = (mSaGlobalNvsAreaPtr->SgFeatureList & 0x2) >> 1; // dGPUAudioCodec flag bit2
+ CmosManager->Access.Write(&CmosManager->Access, CMOS_OEM_NVSWSMI_CODE, CheckPoint);
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: NvCmosFunction1
+//
+// Description: Read CMOS:AudioCodec to AcpiNvs->AudioCodec.
+//
+// Input: EFI_HANDLE DispatchHandle,
+// EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
+//
+// Output:
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+VOID NvCmosFunction1 (
+ IN EFI_HANDLE DispatchHandle,
+ IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext )
+{
+ UINT8 CheckPoint;
+
+ CmosManager->Access.Read(&CmosManager->Access, CMOS_OEM_NVSWSMI_CODE,&CheckPoint);
+ mSaGlobalNvsAreaPtr->SgFeatureList |= (CheckPoint & 1) << 1; // dGPUAudioCodec flag bit2
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: InSmmFunction
+//
+// Description: InSmmFunction
+//
+// Input:
+//
+// Output:
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS InSmmFunction (EFI_HANDLE ImageHandle,EFI_SYSTEM_TABLE *SystemTable )
+{
+ EFI_STATUS Status;
+ SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL *SaGlobalNvsAreaProtocol;
+ EFI_SMM_SW_DISPATCH_PROTOCOL *SwDispatch;
+ EFI_SMM_SW_DISPATCH_CONTEXT NvSwSmiContext = {SWSMI_NVOEM_CMOS_W};
+ EFI_SMM_SW_DISPATCH_CONTEXT NvSwSmiContext1 = {SWSMI_NVOEM_CMOS_R};
+ EFI_HANDLE SwHandle;
+
+ UINT8 CheckPoint;
+
+
+ Status = pBS->LocateProtocol ( &mSwDispatchProtocolGuid, NULL, &SwDispatch );
+ ASSERT_EFI_ERROR(Status);
+ //
+ // Locate the Global NVS Protocol.
+ //
+ Status = pBS->LocateProtocol (&gSaGlobalNvsAreaProtocolGuid, NULL, &SaGlobalNvsAreaProtocol);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ mSaGlobalNvsAreaPtr = SaGlobalNvsAreaProtocol->Area;
+ TRACE((-1,"AcpiNvs Addr->SgFeatureList = %X\n", &mSaGlobalNvsAreaPtr->SgFeatureList));
+
+ LOCATE_CMOS_ACCESS_SMM_PROTOCOL(Status, CmosManager);
+
+ if (CmosManager != NULL)
+ {
+ Status = SwDispatch->Register( SwDispatch, NvCmosFunction, &NvSwSmiContext, &SwHandle);
+ Status = SwDispatch->Register( SwDispatch, NvCmosFunction1, &NvSwSmiContext1, &SwHandle);
+// Init dGPUAudioCodec flag
+ CmosManager->Access.Read(&CmosManager->Access,CMOS_OEM_NVSWSMI_CODE,&CheckPoint);
+ mSaGlobalNvsAreaPtr->SgFeatureList |= (CheckPoint & 1) << 1; // dGPUAudioCodec flag bit2
+ }
+
+ return Status;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: NvSwSmiEntry
+//
+// Description: NvSwSmiEntry
+//
+// Input: EFI_HANDLE ImageHandle,
+// EFI_SYSTEM_TABLE *SystemTable
+//
+// Output:
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS NvSwSmiEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable )
+{
+ InitAmiLib(ImageHandle,SystemTable);
+
+ return InitSmmHandler( ImageHandle, SystemTable, InSmmFunction, NULL );
+}
+
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.cif b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.cif
new file mode 100644
index 0000000..db24ffb
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.cif
@@ -0,0 +1,13 @@
+<component>
+ name = "Sg nVidia Optimus SMM"
+ category = ModulePart
+ LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\NvOptimusSMM\"
+ RefName = "NvOptimusSMM"
+[files]
+"NvOptimusSMM.sdl"
+"NvOptimusSMM.mak"
+"NvOptimusSMM.c"
+"NvOptimusSMM.dxs"
+"NvOptimusSMM.ssp"
+"NvOptimusSMM.asl"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.dxs b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.dxs
new file mode 100644
index 0000000..1b47f48
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.dxs
@@ -0,0 +1,65 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia Optimus SMM/NvOptimusSMM.dxs 2 9/09/12 11:07p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:07p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia Optimus SMM/NvOptimusSMM.dxs $
+//
+// 2 9/09/12 11:07p Joshchou
+// [TAG] EIPNone
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] NvOptimusSMM.mak
+// NvOptimusSMM.c
+// NvOptimusSMM.dxs
+// NvOptimusSMM.ssp
+// NvOptimusSMM.asl
+// NvOptimusSMM.cif
+//
+//**********************************************************************
+
+//#include "EfiDepex.h"
+#include <Protocol\SmmBase.h>
+#include "protocol\SmmSwDispatch.h"
+#include <CmosAccess.h>
+#include <Protocol\GlobalNvsArea\GlobalNvsArea.h>
+
+DEPENDENCY_START
+ EFI_SMM_CMOS_ACCESS_GUID AND
+ EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID AND
+ EFI_SMM_BASE_PROTOCOL_GUID AND
+ EFI_SMM_SW_DISPATCH_PROTOCOL_GUID
+DEPENDENCY_END
+
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.mak b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.mak
new file mode 100644
index 0000000..2ab5deb
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.mak
@@ -0,0 +1,109 @@
+#**********************************************************************
+#**********************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#**********************************************************************
+#**********************************************************************
+
+#**********************************************************************
+# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia Optimus SMM/NvOptimusSMM.mak 3 10/16/12 4:26a Joshchou $
+#
+# $Revision: 3 $
+#
+# $Date: 10/16/12 4:26a $
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia Optimus SMM/NvOptimusSMM.mak $
+#
+# 3 10/16/12 4:26a Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Update for SA and ACPI RC 0.7.1
+# [Files] NvOptimusSMM.mak
+#
+# 2 9/09/12 11:07p Joshchou
+# [TAG] EIPNone
+# [Category] Improvement
+# [Description] Tpv module support for sharkbay.
+# [Files] NvOptimusSMM.mak
+# NvOptimusSMM.c
+# NvOptimusSMM.dxs
+# NvOptimusSMM.ssp
+# NvOptimusSMM.asl
+# NvOptimusSMM.cif
+#
+# 1 6/27/11 5:26a Alanlin
+# [TAG] EIP61848
+# [Category] New Feature
+# [Description] Initial check-in.Integrated SwitchableGraphics Intel
+# Reference code 0.6.0
+# [Files] NvOptimusSMM.cif
+# NvOptimusSMM.sdl
+# NvOptimusSMM.mak
+# NvOptimusSMM.c
+# NvOptimusSMM.dxs
+# NvOptimusSMM.ssp
+# NvOptimusSMM.asl
+#
+#
+# 1 3/17/11 6:14p Alexp
+#
+#**********************************************************************
+#<AMI_FHDR_START>
+#
+# Name: NvOptimusSMM.mak
+#
+# Description:
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+SgTpv : NvOptimusSMM
+
+NvOptimusSMM : $(BUILD_DIR)\NvOptimusSMM.mak NvOptimusSMMBin
+
+$(BUILD_DIR)\NvOptimusSMM.mak : $(NvOptimusSMM_DIR)\$(@B).cif $(NvOptimusSMM_DIR)\$(@B).mak $(BUILD_RULES)
+ $(CIF2MAK) $(NvOptimusSMM_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+NvOptimusSMM_INCLUDES=\
+ $(INTEL_MPG_INCLUDES)\
+ $(ACPI_PLATFORM_INCLUDES)\
+ /DTIANO_RELEASE_VERSION=$(TIANO_RELEASE_VERSION)\
+ /I $(INTEL_SA_PROTOCOL_LIB_DIR)\
+
+# /I$(NvOptimusSMM_DIR) \
+# $(PROJECT_INCLUDES)\
+# $(Foundation_INCLUDES)\
+# /FIinclude\CompilerDirective.h\
+
+NvOptimusSMMBin :$(AMIDXELIB) $(INTEL_SA_PROTOCOL_LIB)
+ $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+ /f $(BUILD_DIR)\NvOptimusSMM.mak all\
+ GUID=8A4E8240-74F8-4024-AE2B-B39221C9FA59\
+ "MY_INCLUDES= $(NvOptimusSMM_INCLUDES)"\
+ DEPEX1=$(NvOptimusSMM_DIR)\NvOptimusSMM.dxs\
+ ENTRY_POINT=NvSwSmiEntry \
+ TYPE=BS_DRIVER \
+ COMPRESS=1\
+
+# OBJECTS="$(BUILD_DIR)\$(NvOptimusSMM_DIR)\NvOptimusSMM.obj" \
+#**********************************************************************
+#**********************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#**********************************************************************
+#**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.sdl b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.sdl
new file mode 100644
index 0000000..c77f960
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.sdl
@@ -0,0 +1,67 @@
+TOKEN
+ Name = "NvOptimusSMM_SUPPORT"
+ Value = "1"
+ Help = "Main switch to enable NvOptimusSMM support in Project"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ Master = Yes
+End
+
+TOKEN
+ Name = "SWSMI_NVOEM_CMOS_W"
+ Value = "0xB6"
+ Help = "Value to be written into SMI command register \to write AcpiNvs->AudioCodec to CMOS"
+ TokenType = Integer
+ TargetH = Yes
+ Range = "0-0xff"
+End
+
+TOKEN
+ Name = "SWSMI_NVOEM_CMOS_R"
+ Value = "0xB7"
+ Help = "Value to be written into SMI command register \to write CMOS:AudioCodec to AcpiNvs->AudioCodec"
+ TokenType = Integer
+ TargetH = Yes
+ Range = "0-0xff"
+End
+
+TOKEN
+ Name = "CMOS_NVOEM_OFFSET"
+ Value = "0x74"
+ Help = "select fixed Offset in CMOS. By default the offset is assigned by CmosManager, see NvOptimus.ssp"
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetH = Yes
+End
+
+PATH
+ Name = "NvOptimusSMM_DIR"
+End
+
+MODULE
+ Help = "Includes NvOptimusSMM.mak to Project"
+ File = "NvOptimusSMM.mak"
+End
+
+#ELINK
+# Name = "$(NvOptimusSMM_DIR)\NvOptimusSMM.asl"
+# Parent = "GENERIC_ACPI_ASL"
+# InvokeOrder = AfterParent
+# Disable = Yes
+#End
+
+ELINK
+ Name = "$(BUILD_DIR)\NvOptimusSMM.ffs"
+ Parent = "$(BUILD_DIR)\SaInitDxe.ffs"
+ InvokeOrder = BeforeParent
+# Parent = "FV_MAIN"
+# InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "$(NvOptimusSMM_DIR)\NvOptimusSMM.SSP"
+ Parent = "ADDON_SSP_FILES"
+ InvokeOrder = AfterParent
+End
+
diff --git a/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.ssp b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.ssp
new file mode 100644
index 0000000..09c17e9
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/NvOptimusSMM/NvOptimusSMM.ssp
@@ -0,0 +1,59 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia Optimus SMM/NvOptimusSMM.ssp 2 9/09/12 11:07p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:07p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg nVidia Optimus SMM/NvOptimusSMM.ssp $
+//
+// 2 9/09/12 11:07p Joshchou
+// [TAG] EIPNone
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] NvOptimusSMM.mak
+// NvOptimusSMM.c
+// NvOptimusSMM.dxs
+// NvOptimusSMM.ssp
+// NvOptimusSMM.asl
+// NvOptimusSMM.cif
+//
+//**********************************************************************
+
+NvramField (CMOS_OEM_NVSWSMI_CODE)
+ OptionBits = 1
+ Default = 1
+ Checksum = NO
+// Location = MKF_CMOS_NVOEM_OFFSET, 0FFh
+EndNvramField
+
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/SgTpv.cif b/Board/EM/SwitchableGraphics/SgTpv/SgTpv.cif
new file mode 100644
index 0000000..263df51
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/SgTpv.cif
@@ -0,0 +1,20 @@
+<component>
+ name = "Sg TPV"
+ category = ModulePart
+ LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\"
+ RefName = "SgTpv"
+[files]
+"SgTpv.sdl"
+"SgTpv.mak"
+"SgTpvPei.c"
+"SgTpvPei.dxs"
+"SgTpvDxe.c"
+"SgTpvDxe.dxs"
+[parts]
+"MXM_NBCI"
+"NvOptimusSMM"
+"SgTpvAcpiTables"
+"SgTpvAcpiS3Save"
+[dependOn]
+"SwitchableGraphics"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SgTpv/SgTpv.mak b/Board/EM/SwitchableGraphics/SgTpv/SgTpv.mak
new file mode 100644
index 0000000..5094a83
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/SgTpv.mak
@@ -0,0 +1,266 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012 American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/SgTpv.mak 5 1/15/13 5:00a Joshchou $
+#
+# $Revision: 5 $
+#
+# $Date: 1/15/13 5:00a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/SgTpv.mak $
+#
+# 5 1/15/13 5:00a Joshchou
+# [TAG] EIP107237
+# [Category] New Feature
+# [Description] Support SG function on ULT platform.
+#
+# 4 12/18/12 6:20a Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Update for SA RC 081
+#
+# 3 9/24/12 8:27a Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Update for Reference Code v0.70
+# [Files] SgTpv.mak
+#
+# 2 9/09/12 11:15p Joshchou
+# [TAG] EIPNone
+# [Category] New Feature
+# [Description] Tpv module support for sharkbay.
+# [Files] SgTpv.sdl
+# SgTpv.mak
+# SgTpvPei.c
+# SgTpvPei.dxs
+# SgTpvDxe.c
+# SgTpvDxe.dxs
+# SgTpv.cif
+#
+# 1 6/27/11 5:25a Alanlin
+# [TAG] EIP61848
+# [Category] New Feature
+# [Description] Initial check-in.Integrated SwitchableGraphics Intel
+# Reference code 0.6.0
+# [Files] SgTpv.cif
+# SgTpv.sdl
+# SgTpv.mak
+# SgTpvPei.c
+# SgTpvPei.dxs
+# SgTpvDxe.c
+# SgTpvDxe.dxs
+#
+#
+# 3 12/07/10 3:13p Alexp
+# SgTpvPeiBin build rule: replace EDK_DEFAULTS with EDKIIGLUE_DEFAULTS
+# macro.
+# Fixes the build error if project includes Rules.mak without
+# modifications file.
+#
+# 2 11/12/10 1:57p Alexp
+#
+# 1 9/17/10 1:12p Alexp
+# [TAG] EIP43103
+# [Category] Function Request
+# [Severity] Normal
+# [Symptom] Initial check-in of SgTPV module
+# [RootCause] Request to implement SG reference code .
+# [Solution] Initial check-in.
+# [Files]
+# SgTpv.cif;*.sdl;*.mak;
+# SgTpvPei.c;*.dxs;
+# SgTpvDxe.c;*.dxs
+#
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name: SgTpv.mak
+#
+# Description:
+# Make file to build Switchable Graphics module for Third Party Gfx vendors
+#
+#<AMI_FHDR_END>
+#*************************************************************************
+SwitchableGraphics: SgTpv
+
+SgTpv : $(BUILD_DIR)\SgTpv.mak SgTpvDxeBin SgTpvPeiBin
+
+$(BUILD_DIR)\SgTpv.mak : $(SgTpv_DIR)\$(@B).cif $(SgTpv_DIR)\$(@B).mak $(BUILD_RULES)
+ $(CIF2MAK) $(SgTpv_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+BUILD_SGTPV_DIR = $(BUILD_DIR)\$(SgTpv_DIR)
+
+################################################################################
+# PEI
+################################################################################
+SgTpv_PEI_OBJECTS = \
+$(BUILD_SGTPV_DIR)\SGTpvPei.obj
+
+SgTpvPei_INCLUDES=\
+ $(EDK_INCLUDES)\
+ $(PROJECT_INCLUDES)\
+ $(INTEL_MCH_INCLUDES)\
+ $(INTEL_MCH_INCLUDES)\SaDataHob\
+ $(INTEL_MCH_INCLUDES)\SaPlatformPolicy\
+ $(EdkIIGlueLib_INCLUDES)\
+ $(SwitchableGraphics_INCLUDES)\
+ /I$(NB_BOARD_DIR)\
+ /I$(SgTpv_DIR)
+
+SgTpvPei_DEFINES=\
+ /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=SgTpvPeiInit"\
+ /D __EDKII_GLUE_BASE_LIB__ \
+ /D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+ /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+ /D __EDKII_GLUE_PEI_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+ /D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \
+ /D __EDKII_GLUE_PEI_SERVICES_LIB__ \
+ /D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__
+
+SgTpvPei_LIBS=\
+ $(SaGuidLib_LIB)\
+ $(INTEL_SA_PPI_LIB)\
+ $(IntelPchPpiLib_LIB)\
+ $(EDKFRAMEWORKPPILIB) \
+ $(BUILD_DIR)\IA32\EdkIIGlueBaseLib.lib\
+ $(EdkIIGlueBaseLibIA32_LIB)\
+ $(EdkIIGlueBaseIoLibIntrinsic_LIB) \
+ $(BUILD_DIR)\IA32\EdkIIGluePeiDebugLibReportStatusCode.lib\
+ $(BUILD_DIR)\IA32\EdkIIGluePeiReportStatusCodeLib.lib\
+ $(BUILD_DIR)\IA32\EdkIIGluePeiServicesLib.lib\
+ $(BUILD_DIR)\IA32\EdkIIGluePeiMemoryAllocationLib.lib\
+ $(BUILD_DIR)\IA32\EdkIIGlueBasePciLibPciExpress.lib\
+
+# $(EdkIIGlueBasePciLibPciExpress_LIB) \
+# $(EdkIIGluePeiMemoryAllocationLib_LIB) \
+# $(EdkIIGluePeiServicesLib_LIB) \
+# $(EdkIIGluePeiReportStatusCodeLib_LIB) \
+# $(EdkIIGluePeiDxeDebugLibReportStatusCode_LIB) \
+
+# $(EdkIIGlueBaseIoLibIntrinsic_LIB)\
+
+# $(EdkIIGlueBaseMemoryLib_LIB)\
+
+# $(EdkIIGluePeiDebugLibReportStatusCode_LIB)\
+
+# $(PEILIB)
+
+# $(SwitchableGraphicsPei_LIBS)
+
+SgTpvPeiBin : $(SgTpvPei_LIBS)
+ $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+ /f $(BUILD_DIR)\SgTpv.mak all\
+ "MY_INCLUDES=$(SgTpvPei_INCLUDES)"\
+ "MY_DEFINES=$(SgTpvPei_DEFINES)"\
+ OBJECTS="$(SgTpv_PEI_OBJECTS)" \
+ NAME=SgTpvPei\
+ MAKEFILE=$(BUILD_DIR)\SgTpv.mak\
+ GUID=0E2DAF63-8A4F-4026-A899-DE2D7F46E5EC\
+ ENTRY_POINT=_ModuleEntryPoint\
+ TYPE=PEIM \
+ EDKIIModule=PEIM\
+ DEPEX1=$(SgTpv_DIR)\SgTpvPei.dxs\
+ DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX\
+ COMPRESS=0
+
+################################################################################
+# DXE
+################################################################################
+SgTpv_DXE_OBJECTS = \
+$(BUILD_SGTPV_DIR)\SGTpvDxe.obj
+
+SgTpvDxe_INCLUDES=\
+ $(EDK_INCLUDES) \
+ $(MISCFRAMEWORK_INCLUDES)\
+ $(EDK_SOURCE_INCLUDES)\
+ $(INTEL_MCH_INCLUDES)\
+ $(INTEL_MCH_INCLUDES)\SaDataHob\
+ $(INTEL_MCH_INCLUDES)\SaPlatformPolicy\
+ $(INTEL_PCH_INCLUDES)\
+ $(INTEL_MPG_INCLUDES)\
+ $(IndustryStandard_INCLUDES)\
+ $(EdkIIGlueLib_INCLUDES)\
+ $(ACPI_PLATFORM_INCLUDES)\
+ $(PROJECT_CPU_INCLUDES)\
+ /I$(SgTpv_DIR)\
+ /I$(INTEL_SYSTEM_AGENT_DIR)\SaInit\
+ /I$(EDK_SOURCE)\Foundation\Efi\Include\
+
+# $(SwitchableGraphics_INCLUDES)\
+
+
+
+SgTpvDxe_LIBS=\
+ $(EDKPROTOCOLLIB)\
+ $(EDKFRAMEWORKPROTOCOLLIB)\
+ $(EFISCRIPTLIB)\
+ $(EFIDRIVERLIB)\
+ $(EdkIIGlueBaseIoLibIntrinsic_LIB)\
+ $(BUILD_DIR)\IA32\EdkIIGlueBaseLib.lib\
+ $(EdkIIGlueBaseMemoryLib_LIB)\
+!IF "$(x64_BUILD)"=="1"
+ $(EdkIIGlueBaseLibX64_LIB)\
+!ELSE
+ $(EdkIIGlueBaseLibIA32_LIB)\
+!ENDIF
+ $(EdkIIGlueEdkDxeRuntimeDriverLib_LIB)\
+ $(EdkIIGlueDxeMemoryAllocationLib_LIB)\
+ $(EdkIIGlueDxeReportStatusCodeLib_LIB)\
+ $(EdkIIGlueDxeServicesTableLib_LIB)\
+ $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\
+ $(EdkIIGlueUefiBootServicesTableLib_LIB)\
+ $(EdkIIGlueUefiLib_LIB)\
+ $(EdkIIGlueDxeHobLib_LIB)\
+ $(INTEL_SA_PROTOCOL_LIB)\
+ $(SaGuidLib_LIB)\
+ $(IntelMpgProtocolLib_LIB)\
+ $(EdkIIGlueBasePciExpressLib_LIB)\
+ $(EdkIIGlueBasePciLibPciExpress_LIB)\
+ $(CpuPlatformLib_LIB)\
+ $(PchPlatformSmmLib_LIB)\
+
+ #$(EdkIIGlueBaseLib_LIB)\
+
+
+SgTpvDxeBin : $(SgTpvDxe_LIBS)
+ $(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS)\
+ /f $(BUILD_DIR)\SgTpv.mak all\
+ GUID=3FE57AC2-C675-46B1-8458-AC6206588424\
+ NAME=SgTpvDxe\
+ MAKEFILE=$(BUILD_DIR)\SgTpv.mak\
+ "MY_INCLUDES = $(SgTpvDxe_INCLUDES)" \
+ OBJECTS="$(SgTpv_DXE_OBJECTS)" \
+ ENTRY_POINT=SgTpvDxeEntryPoint\
+ TYPE=BS_DRIVER\
+ EDKIIModule=DXEDRIVER\
+ DEPEX1=$(SgTpv_DIR)\SgTpvDxe.dxs\
+ DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+ COMPRESS=1
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012 American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/SgTpv.sdl b/Board/EM/SwitchableGraphics/SgTpv/SgTpv.sdl
new file mode 100644
index 0000000..41b10af
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/SgTpv.sdl
@@ -0,0 +1,40 @@
+TOKEN
+ Name = SgTpv_SUPPORT
+ Value = "1"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Master = Yes
+ Help = "Main switch to enable SgTpv support in Project"
+End
+
+TOKEN
+ Name = "EFI_PEI_END_OF_SG_TPV_PPI_GUID"
+ Value = "{0xc81aa794, 0xdf62, 0x4a39, 0xaf, 0xf6, 0xa6, 0x8c, 0x9, 0xe2, 0x3b, 0xdd}"
+ Help = "End of SG TPV PPI GUID"
+ TokenType = Expression
+ TargetH = Yes
+End
+
+PATH
+ Name = SgTpv_DIR
+ Help = "Path to SgTpv Module in Project"
+End
+
+MODULE
+ Help = "Includes SgTpv.mak to Project"
+ File = "SgTpv.mak"
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\SgTpvPei.ffs"
+ Parent = "$(BUILD_DIR)\SaInitPeim.ffs"
+ InvokeOrder = BeforeParent
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\SgTpvDxe.ffs"
+ Parent = "$(BUILD_DIR)\SaInitDxe.ffs"
+ InvokeOrder = BeforeParent
+End \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/SgTpvDxe.c b/Board/EM/SwitchableGraphics/SgTpv/SgTpvDxe.c
new file mode 100644
index 0000000..d3f8465
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/SgTpvDxe.c
@@ -0,0 +1,260 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/SgTpvDxe.c 4 5/13/14 4:44a Joshchou $
+//
+// $Revision: 4 $
+//
+// $Date: 5/13/14 4:44a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/SgTpvDxe.c $
+//
+// 4 5/13/14 4:44a Joshchou
+// [TAG] EIP167034
+// [Category] Improvement
+// [Description] Review the variable's attribute.
+//
+// 3 1/15/13 5:02a Joshchou
+// [TAG] EIP107237
+// [Category] New Feature
+// [Description] Support SG function on ULT platform.
+//
+// 2 9/09/12 11:15p Joshchou
+// [TAG] EIPNone
+// [Category] New Feature
+// [Description] Tpv module support for sharkbay.
+// [Files] SgTpv.sdl
+// SgTpv.mak
+// SgTpvPei.c
+// SgTpvPei.dxs
+// SgTpvDxe.c
+// SgTpvDxe.dxs
+// SgTpv.cif
+//
+// 2 12/06/11 2:15a Alanlin
+// [TAG] EIP76248
+// [Category] New Feature
+// [Description] PX 5.0 feature updated
+//
+// 1 6/27/11 5:25a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgTpv.cif
+// SgTpv.sdl
+// SgTpv.mak
+// SgTpvPei.c
+// SgTpvPei.dxs
+// SgTpvDxe.c
+// SgTpvDxe.dxs
+//
+//
+// 2 9/24/10 5:37p Alexp
+// [TAG] EIP43103 --> fix CPU exception error by checking if
+// endpoint bus is enabled in PEG root bridge
+//
+// 1 9/17/10 1:12p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgTpv.cif;*.sdl;*.mak;
+// SgTpvPei.c;*.dxs;
+// SgTpvDxe.c;*.dxs
+//
+// 2 6/16/10 5:07p Alexp
+//
+// 1 6/10/10 4:22p Alexp
+//
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name: SgTpvDXE.c
+//
+// Description: This file contains the etry point of SgTpv Support driver
+//
+// Notes: MAKE SURE NO PEI OR DXE SPECIFIC CODE IS NEEDED
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+#include "EfiScriptLib.h"
+#endif
+
+#include <Token.h>
+#include <SetupDataDefinition.h>
+#include "SaAccess.h"
+
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+#include "PchRegsPcie.h"
+
+#include EFI_PROTOCOL_PRODUCER (SaPlatformPolicy)
+
+#define AMD_VID 0x1002
+#define NVIDIA_VID 0x10DE
+#define SETUP_GUID { 0xEC87D643, 0xEBA4, 0x4BB5, 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 }
+SETUP_DATA SetupDataBuffer;
+CPU_FAMILY CpuFamilyId;
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: SgTpvDxeEntryPoint
+//
+// Description: Entry point of EFI SG Support driver.
+//
+// Input: EFI_HANDLE ImageHandle,
+// EFI_SYSTEM_TABLE *SystemTable
+//
+// Output: EFI_STATUS
+//
+// Modified:
+//
+// Referrals:
+//
+// Notes:
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS
+SgTpvDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy;
+ UINT8 EndpointBus;
+ EFI_GUID gSetupGuid = SETUP_GUID;
+ UINTN VariableSize = 0;
+ UINT8 RootPortDev;
+ UINT8 RootPortFun;
+ UINT32 Attributes = 0;
+
+
+ EfiInitializeDriverLib (ImageHandle, SystemTable);
+ CpuFamilyId = GetCpuFamily();
+ //
+ // Locate the SG Policy Protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gDxePlatformSaPolicyGuid,
+ NULL,
+ &DxePlatformSaPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Update SG DXE Policy -
+ //
+
+ // 1 = Load secondary display device VBIOS; 0 = Do not load
+ //
+ DxePlatformSaPolicy->VbiosConfig->LoadVbios = LOADVBIOS;
+ DxePlatformSaPolicy->VbiosConfig->VbiosSource = VBIOSSOURCE;
+ DxePlatformSaPolicy->VbiosConfig->ExecuteVbios = EXECUTEVBIOS;
+#if (defined(SGOEMSSDT_SUPPORT) && (SGOEMSSDT_SUPPORT != 0))
+ DxePlatformSaPolicy->VbiosConfig->ExecuteVbios = 0;
+#endif
+
+ //
+ // Endpoint Base Addresses and Capability Structure Offsets for ASL usage
+ //
+
+ if (CpuFamilyId == EnumCpuHswUlt) {
+ /// For SwitchableGraphics support the dGPU is present on PCH RootPort
+ RootPortDev = PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS;
+ RootPortFun = SG_ULT_PORT_FUNC;
+ } else {
+ /// Assume: For SwitchableGraphics support the dGPU is present on PEG RootPort by default
+ RootPortDev = SA_PEG10_DEV_NUM;
+ RootPortFun = SA_PEG10_FUN_NUM;
+ }
+
+ //EndpointBus = McD1PciCfg8 (PCI_SBUS);
+ EndpointBus = MmPci8 (0, 0, RootPortDev, RootPortFun, PCI_SBUS);
+
+ if (EndpointBus != 0xff &&
+ McDevFunPciCfg16 (EndpointBus, 0, 0, PCI_VID) == NVIDIA_VID)
+ {
+ DxePlatformSaPolicy->VbiosConfig->ExecuteVbios = 0;
+ }
+
+ VariableSize = sizeof (SETUP_DATA);
+ Status = gRT->GetVariable (
+ L"Setup",
+ &gSetupGuid,
+ &Attributes,
+ &VariableSize,
+ &SetupDataBuffer
+ );
+ DEBUG ((EFI_D_ERROR, "SgTpvDxeEntryPoint Attributes = %x\n",Attributes));
+
+
+#if (defined(CSM_SUPPORT) && (CSM_SUPPORT != 0))
+ #if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1)
+ if ((SetupDataBuffer.CsmLaunchPolicy == 0) || (SetupDataBuffer.BootOptionFilter == 2))
+ {DxePlatformSaPolicy->VbiosConfig->ExecuteVbios = 0;}
+ #endif
+#else
+ DxePlatformSaPolicy->VbiosConfig->ExecuteVbios = 0;
+#endif
+// if (SetupDataBuffer.PrimaryDisplay == 4)
+// {
+ if (EndpointBus != 0xff &&
+ McDevFunPciCfg16 (EndpointBus, 0, 0, PCI_VID) == AMD_VID)
+ {
+ SetupDataBuffer.TPVCardCheck = 1;
+ } else
+ SetupDataBuffer.TPVCardCheck = 0;
+
+ Status = gRT->SetVariable (
+ L"Setup",
+ &gSetupGuid,
+ Attributes,
+ sizeof(SETUP_DATA),
+ &SetupDataBuffer
+ );
+// } // SetupDataBuffer.PrimaryDisplay == 4
+
+ return Status;
+}
+
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/SgTpvDxe.dxs b/Board/EM/SwitchableGraphics/SgTpv/SgTpvDxe.dxs
new file mode 100644
index 0000000..4513007
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/SgTpvDxe.dxs
@@ -0,0 +1,88 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/SgTpvDxe.dxs 2 9/09/12 11:15p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:15p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/SgTpvDxe.dxs $
+//
+// 2 9/09/12 11:15p Joshchou
+// [TAG] EIPNone
+// [Category] New Feature
+// [Description] Tpv module support for sharkbay.
+// [Files] SgTpv.sdl
+// SgTpv.mak
+// SgTpvPei.c
+// SgTpvPei.dxs
+// SgTpvDxe.c
+// SgTpvDxe.dxs
+// SgTpv.cif
+//
+// 1 6/27/11 5:25a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgTpv.cif
+// SgTpv.sdl
+// SgTpv.mak
+// SgTpvPei.c
+// SgTpvPei.dxs
+// SgTpvDxe.c
+// SgTpvDxe.dxs
+//
+// 2 3/30/11 10:27p Alanlin
+//
+// 1 9/17/10 1:12p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgTpv.cif;*.sdl;*.mak;
+// SgTpvPei.c;*.dxs;
+// SgTpvDxe.c;*.dxs
+//
+//**********************************************************************
+
+#include "EfiDepex.h"
+#include EFI_PROTOCOL_DEPENDENCY (SaPlatformPolicy)
+#include EFI_PROTOCOL_DEPENDENCY (PciIo)
+
+DEPENDENCY_START
+ DXE_PLATFORM_SA_POLICY_GUID AND
+ EFI_PCI_IO_PROTOCOL_GUID
+DEPENDENCY_END
+
+
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//**************************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SgTpv/SgTpvPei.c b/Board/EM/SwitchableGraphics/SgTpv/SgTpvPei.c
new file mode 100644
index 0000000..beb41c9
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/SgTpvPei.c
@@ -0,0 +1,266 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/SgTpvPei.c 4 10/30/13 6:42a Joshchou $
+//
+// $Revision: 4 $
+//
+// $Date: 10/30/13 6:42a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/SgTpvPei.c $
+//
+// 4 10/30/13 6:42a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] system assert after clear nvram,and we have give it
+// value,so do not assert
+//
+// 3 2/07/13 2:58a Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Install a PPI for broadcasting OEM.
+//
+// 2 9/09/12 11:15p Joshchou
+// [TAG] EIPNone
+// [Category] New Feature
+// [Description] Tpv module support for sharkbay.
+// [Files] SgTpv.sdl
+// SgTpv.mak
+// SgTpvPei.c
+// SgTpvPei.dxs
+// SgTpvDxe.c
+// SgTpvDxe.dxs
+// SgTpv.cif
+//
+// 3 12/06/11 2:33a Alanlin
+// [TAG] EIP76248
+// [Category] New Feature
+// [Description] PX 5.0 feature updated.
+//
+// 2 10/14/11 2:54a Alanlin
+// [TAG] EIP72054
+// [Category] Improvement
+// [Description] SgTpv is not compatible with SETUP_DATA_LAYOUT_OVERRIDE
+// in core > 4.6.4.1
+// [Files] Board\EM\SgTpv\SgTpvPei.c
+//
+// 1 6/27/11 5:25a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgTpv.cif
+// SgTpv.sdl
+// SgTpv.mak
+// SgTpvPei.c
+// SgTpvPei.dxs
+// SgTpvDxe.c
+// SgTpvDxe.dxs
+//
+//
+// 5 3/17/11 6:12p Alexp
+// 1. Add nNvOptimusSMM module part
+// 2. cleaned up SgTpvPei.c
+// 3. Optimus:Add code to preserve HD AudioCodec enable flag in CMOS
+//
+// 4 11/12/10 1:08p Alexp
+// Update to match Intel HR SwitchableGraphics Reference Code Version
+// 1.00
+// Code to set SSID for IGD moved to SgPei.c
+//
+// 3 9/30/10 2:51p Alexp
+// [TAG] EIP43103 ---> Set IGD SSID/SVID based on the SG mode
+//
+// 2 9/21/10 5:23p Alexp
+// [TAG] EIP43103 ---> re-arranged include statements
+//
+// 1 9/17/10 1:12p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgTpv.cif;*.sdl;*.mak;
+// SgTpvPei.c;*.dxs;
+// SgTpvDxe.c;*.dxs
+//
+//
+//**********************************************************************
+
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name: SgTpvPEI.c
+//
+// Description: This file contains the PEI SG Entry point SgPei_Init.
+// The function updates SG Policy settings
+//
+// Notes: MAKE SURE NO PEI OR DXE SPECIFIC CODE IS NEEDED
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+
+#include <Token.h>
+
+#define SETUP_GUID { 0xEC87D643, 0xEBA4, 0x4BB5, 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 }
+
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGluePeim.h"
+#include "EdkIIGlueIoLib.h"
+#endif
+
+#include "Pei.h"
+
+#include "SaAccess.h"
+
+#include EFI_PPI_DEPENDENCY (Variable)
+#include EFI_PPI_DEPENDENCY (SaPlatformPolicy)
+#include EFI_GUID_DEFINITION (SaDataHob)
+
+static EFI_GUID gSetupGuid = SETUP_GUID;
+
+#include <SetupDataDefinition.h>
+
+EFI_GUID guidEndOfSgTpvPei = EFI_PEI_END_OF_SG_TPV_PPI_GUID;
+
+static EFI_PEI_PPI_DESCRIPTOR EndOfSgTpvPpiList[] =
+{
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &guidEndOfSgTpvPei, NULL
+ }
+};
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: SgTpvPeiInit
+//
+// Description: This function is the entry point for this PEI.
+//
+// Input: FfsHeader Pointer to the FFS file header
+// PeiServices Pointer to the PEI services table
+//
+// Output: Return Status based on errors that occurred while waiting for
+// time to expire.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS
+EFIAPI
+SgTpvPeiInit (
+ IN EFI_FFS_FILE_HEADER *FfsHeader,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE_PPI *VariableServices;
+ UINTN VariableSize;
+ SETUP_DATA SetupData;
+
+ SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi;
+ EFI_GUID gSaPlatformPolicyPpiGuid = SA_PLATFORM_POLICY_PPI_GUID;
+
+DEBUG ((EFI_D_ERROR, "==============SgTpvPeiInit==========\n"));
+ //
+ // Locate Variable Ppi
+ //
+ Status = (*PeiServices)->LocatePpi(PeiServices,
+ &gPeiReadOnlyVariablePpiGuid,
+ 0,
+ NULL,
+ &VariableServices);
+
+ //
+ // Make sure we have a PPI, if not, just return.
+ //
+ if (!VariableServices) {
+ return EFI_UNSUPPORTED;
+ }
+ VariableSize = sizeof(SETUP_DATA);
+ //
+ // Get Setup Variable
+ //
+ Status = VariableServices->PeiGetVariable (
+ PeiServices,
+ L"Setup",
+ &gSetupGuid,
+ NULL,
+ &VariableSize,
+ &SetupData);
+
+ if (EFI_ERROR(Status))
+ return Status;
+
+ //
+ // Get platform policy settings through the SgPlatformPolicy PPI
+ //
+ Status = (**PeiServices).LocatePpi (
+ PeiServices,
+ &gSaPlatformPolicyPpiGuid,
+ 0,
+ NULL,
+ &SaPlatformPolicyPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // GPIO Assigned from policy
+ //
+
+ //
+ // Initialzie the Platform Configuration
+ //
+
+ //
+ // Switchable Graphics mode set as MUXED (By default)
+ //
+ if( SetupData.PrimaryDisplay == 4 ) {
+ SaPlatformPolicyPpi->PlatformData->SgMode = SetupData.SgMuxMode;
+ SaPlatformPolicyPpi->PlatformData->PXFixedDynamicMode = SetupData.PX_FIXED_DYNAMIC_MODE;
+
+ } else if ((SetupData.PrimaryDisplay == 1) || (SetupData.PrimaryDisplay == 3)) { // PEG || Auto
+
+ SaPlatformPolicyPpi->PlatformData->SgMode = 3;//SgModeDgpu;
+
+ } else if (SetupData.PrimaryDisplay == 0) { // IGFX
+ //
+ // In IGFX only mode mode set Switchable Gfx mode as Disabled
+ //
+ SaPlatformPolicyPpi->PlatformData->SgMode = SgModeDisabled;
+ }
+
+ //
+ // Set SSID/SVID for IGD in SG mode only
+ //
+ SaPlatformPolicyPpi->PlatformData->SgSubSystemId = (UINT16)((SG_MUXLESS_SSVID_DID >> 16 )& 0xFFFF);
+ (*PeiServices)->InstallPpi(PeiServices,EndOfSgTpvPpiList);
+ return Status;
+}
+
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SgTpv/SgTpvPei.dxs b/Board/EM/SwitchableGraphics/SgTpv/SgTpvPei.dxs
new file mode 100644
index 0000000..d19e0fc
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SgTpv/SgTpvPei.dxs
@@ -0,0 +1,85 @@
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//****************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/SgTpvPei.dxs 2 9/09/12 11:15p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:15p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/SgTpvPei.dxs $
+//
+// 2 9/09/12 11:15p Joshchou
+// [TAG] EIPNone
+// [Category] New Feature
+// [Description] Tpv module support for sharkbay.
+// [Files] SgTpv.sdl
+// SgTpv.mak
+// SgTpvPei.c
+// SgTpvPei.dxs
+// SgTpvDxe.c
+// SgTpvDxe.dxs
+// SgTpv.cif
+//
+// 1 6/27/11 5:25a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SgTpv.cif
+// SgTpv.sdl
+// SgTpv.mak
+// SgTpvPei.c
+// SgTpvPei.dxs
+// SgTpvDxe.c
+// SgTpvDxe.dxs
+//
+//
+// 1 9/17/10 1:12p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of SgTPV module
+// [RootCause] Request to implement SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SgTpv.cif;*.sdl;*.mak;
+// SgTpvPei.c;*.dxs;
+// SgTpvDxe.c;*.dxs
+//
+//**********************************************************************
+
+#include "EfiDepex.h"
+#include EFI_PPI_DEPENDENCY (SaPlatformPolicy)
+
+DEPENDENCY_START
+ SA_PLATFORM_POLICY_PPI_GUID
+DEPENDENCY_END
+
+
+//****************************************************************************
+//****************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone (770)-246-8600 **
+//** **
+//****************************************************************************
+//**************************************************************************** \ No newline at end of file
diff --git a/Board/EM/SwitchableGraphics/SwitchableGraphics.chm b/Board/EM/SwitchableGraphics/SwitchableGraphics.chm
new file mode 100644
index 0000000..768e160
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SwitchableGraphics.chm
Binary files differ
diff --git a/Board/EM/SwitchableGraphics/SwitchableGraphics.cif b/Board/EM/SwitchableGraphics/SwitchableGraphics.cif
new file mode 100644
index 0000000..2350167
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SwitchableGraphics.cif
@@ -0,0 +1,14 @@
+<component>
+ name = "SwitchableGraphics"
+ category = eModule
+ LocalRoot = "Board\EM\SwitchableGraphics\"
+ RefName = "SwitchableGraphics"
+[files]
+"SwitchableGraphics.sdl"
+"SwitchableGraphics.mak"
+"SwitchableGraphics.sd"
+"SwitchableGraphics.uni"
+"SwitchableGraphics.chm"
+[parts]
+"SgTpv"
+<endComponent>
diff --git a/Board/EM/SwitchableGraphics/SwitchableGraphics.mak b/Board/EM/SwitchableGraphics/SwitchableGraphics.mak
new file mode 100644
index 0000000..e2ab8a0
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SwitchableGraphics.mak
@@ -0,0 +1,100 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/SwitchableGraphics.mak 2 9/09/12 11:26p Joshchou $
+#
+# $Revision: 2 $
+#
+# $Date: 9/09/12 11:26p $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/SwitchableGraphics.mak $
+#
+# 2 9/09/12 11:26p Joshchou
+# [TAG] None
+# [Category] Improvement
+# [Description] Tpv module support for sharkbay.
+# [Files] SwitchableGraphics.sdl
+# SwitchableGraphics.mak
+# SwitchableGraphics.sd
+# SwitchableGraphics.uni
+# SwitchableGraphics.chm
+# SwitchableGraphics.cif
+#
+# 1 6/27/11 5:13a Alanlin
+# [TAG] EIP61848
+# [Category] New Feature
+# [Description] Initial check-in.Integrated SwitchableGraphics Intel
+# Reference code 0.6.0
+# [Files] SwitchableGraphics.cif
+# SwitchableGraphics.sdl
+# SwitchableGraphics.mak
+# SwitchableGraphics.sd
+# SwitchableGraphics.uni
+#
+#
+# 4 9/17/10 3:21p Alexp
+#
+# [TAG] EIP43103
+# [Category] Function Request
+# [Severity] Normal
+# [Symptom] Initial check-in of iIntel Switchable Graphics module
+# [RootCause] Request to implement Intel Huron River SG reference code .
+# [Solution] Initial check-in.
+# [Files]
+# SwitchableGraphics.cif; *.chm; *.sdl; *.mak; *.sd;*.uni
+#
+#
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name: SwitchableGraphics.mak
+#
+# Description: Makfile for SG Setup menu.
+#
+#
+#<AMI_FHDR_END>
+#*************************************************************************
+all : SwitchableGraphics
+
+SwitchableGraphics: $(BUILD_DIR)\SwitchableGraphics.mak
+
+$(BUILD_DIR)\SwitchableGraphics.mak : $(SwitchableGraphics_DIR)\SwitchableGraphics.cif $(SwitchableGraphics_DIR)\SwitchableGraphics.mak $(BUILD_RULES)
+ $(CIF2MAK) $(SwitchableGraphics_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+#---------------------------------------------------------------------------
+# Create Sg Setup Screen(s)
+#---------------------------------------------------------------------------
+SetupSdbs : SwitchableGraphicsSDB
+
+SwitchableGraphicsSDB : $(BUILD_DIR)\SwitchableGraphics.mak
+ $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+ /f $** all\
+ TYPE=SDB NAME=SwitchableGraphics STRING_CONSUMERS=$(SwitchableGraphics_DIR)\SwitchableGraphics.sd
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/SwitchableGraphics/SwitchableGraphics.sd b/Board/EM/SwitchableGraphics/SwitchableGraphics.sd
new file mode 100644
index 0000000..5bb4cf4
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SwitchableGraphics.sd
@@ -0,0 +1,216 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/SwitchableGraphics.sd 2 9/09/12 11:26p Joshchou $
+//
+// $Revision: 2 $
+//
+// $Date: 9/09/12 11:26p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/SwitchableGraphics.sd $
+//
+// 2 9/09/12 11:26p Joshchou
+// [TAG] None
+// [Category] Improvement
+// [Description] Tpv module support for sharkbay.
+// [Files] SwitchableGraphics.sdl
+// SwitchableGraphics.mak
+// SwitchableGraphics.sd
+// SwitchableGraphics.uni
+// SwitchableGraphics.chm
+// SwitchableGraphics.cif
+//
+// 3 1/30/12 6:46a Alanlin
+// [TAG] EIP81672
+// [Category] New Feature
+// [Description] SwitchableGraphics setting goto define.
+// [Files] SwitchableGraphics.sd
+//
+// 2 12/06/11 2:24a Alanlin
+// [TAG] EIP76248
+// [Category] New Feature
+// [Description] PX 5.0 feature updated
+//
+// 1 6/27/11 5:13a Alanlin
+// [TAG] EIP61848
+// [Category] New Feature
+// [Description] Initial check-in.Integrated SwitchableGraphics Intel
+// Reference code 0.6.0
+// [Files] SwitchableGraphics.cif
+// SwitchableGraphics.sdl
+// SwitchableGraphics.mak
+// SwitchableGraphics.sd
+// SwitchableGraphics.uni
+//
+//
+// 1 9/17/10 1:46p Alexp
+// [TAG] EIP43103
+// [Category] Function Request
+// [Severity] Normal
+// [Symptom] Initial check-in of iIntel Switchable Graphics module
+// [RootCause] Request to implement Intel Huron River SG reference code .
+// [Solution] Initial check-in.
+// [Files]
+// SwitchableGraphics.cif; *.chm; *.sdl; *.mak; *.sd;*.uni
+//
+//
+//**********************************************************************
+
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name: SwitchableGraphics.sd
+//
+// Description: Switchable Graphics Setup page layout
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+
+#ifdef SETUP_DATA_DEFINITION
+/***********************************************************/
+/* Put NVRAM data definitions here.
+/* For example: UINT8 Data1;
+/* These definitions will be converted by the build process
+/* to a definitions of SETUP_DATA fields.
+/***********************************************************/
+ UINT8 SgMuxMode;
+// UINT8 PX_FIXED_MODE;
+// UINT8 PX_DYNAMIC_MODE;
+ UINT8 PX_FIXED_DYNAMIC_MODE;
+ UINT8 TPVCardCheck;
+#endif
+
+//---------------------------------------------------------------------------
+#if defined(VFRCOMPILE) && !defined(CONTROLS_ARE_DEFINED)
+#define CONTROL_DEFINITION
+#endif
+//---------------------------------------------------------------------------
+
+//**********************************************************************
+// ADVANCED - Onboard Devices Form
+//**********************************************************************
+#ifdef CONTROL_DEFINITION
+
+#define SG_ONEOF_SGMUXMODE\
+ oneof varid = SETUP_DATA.SgMuxMode,\
+ prompt = STRING_TOKEN(STR_SG_MODE),\
+ help = STRING_TOKEN(STR_SG_MODE_HELP),\
+ option text = STRING_TOKEN(STR_SG_MUXLESS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ endoneof;
+
+/*
+#define SG_ONEOF_PXFIXEDMODE\
+ oneof varid = SETUP_DATA.PX_FIXED_MODE,
+ prompt = STRING_TOKEN(STR_PX_FIXED_MODE),
+ help = STRING_TOKEN(STR_PX_FIXED_MODE_HELP),
+ option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = RESET_REQUIRED | DEFAULT | MANUFACTURING;
+ option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = RESET_REQUIRED;
+ endoneof;
+
+#define SG_ONEOF_PXDYNAMICMODE\
+ oneof varid = SETUP_DATA.PX_DYNAMIC_MODE,
+ prompt = STRING_TOKEN(STR_PX_DYNAMIC_MODE),
+ help = STRING_TOKEN(STR_PX_DYNAMIC_MODE_HELP),
+ option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = RESET_REQUIRED | DEFAULT | MANUFACTURING;
+ option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = RESET_REQUIRED;
+ endoneof;
+*/
+
+#define SG_ONEOF_PXFIXEDDYNAMICMODE\
+ oneof varid = SETUP_DATA.PX_FIXED_DYNAMIC_MODE,\
+ prompt = STRING_TOKEN(STR_PX_FIXED_DYNAMIC_MODE),\
+ help = STRING_TOKEN(STR_PX_FIXED_DYNAMIC_MODE_HELP),\
+ option text = STRING_TOKEN(STR_BACO_DYNAMIC_SCHEME), value = 0, flags = RESET_REQUIRED | DEFAULT | MANUFACTURING;\
+ option text = STRING_TOKEN(STR_DGPUOFF_DYNAMIC_SCHEME), value = 1, flags = RESET_REQUIRED;\
+ endoneof;
+
+#define SG_GOTO_SWITCHABLEGRAPHICS\
+ goto SG_FORM_ID, \
+ prompt = STRING_TOKEN(STR_SG_FORM),\
+ help = STRING_TOKEN(STR_SG_FORM_HELP);
+
+#endif // CONTROL_DEFINITION
+
+//---------------------------------------------------------------------------
+#ifdef CONTROLS_WITH_DEFAULTS
+ SG_ONEOF_SGMUXMODE
+/*
+ SG_ONEOF_PXFIXEDMODE
+ SG_ONEOF_PXDYNAMICMODE
+*/
+ SG_ONEOF_PXFIXEDDYNAMICMODE
+#endif // CONTROLS_WITH_DEFAULTS
+//---------------------------------------------------------------------------
+
+//**********************************************************************
+// Advanced - SwitchableGraphics Configuration Form
+//**********************************************************************
+
+#ifdef ADVANCED_FORM_SET
+
+ #ifndef SUPPRESS_GRAYOUT_ENDIF //old Core
+ #define SUPPRESS_GRAYOUT_ENDIF endif;
+ #endif
+
+ #ifdef FORM_SET_ITEM
+ // Define controls to be added to the main page of the formset
+
+ #endif
+
+ #ifdef FORM_SET_GOTO
+ // Define goto commands for the forms defined in this file
+ SG_GOTO_SWITCHABLEGRAPHICS
+ #endif
+
+ #ifdef FORM_SET_FORM
+ #ifndef SWITCHABLEGRAPHICS_FORM_SETUP
+ #define SWITCHABLEGRAPHICS_FORM_SETUP
+
+ // Define forms
+ form formid = AUTO_ID(SG_FORM_ID),
+ title = STRING_TOKEN(STR_SG_FORM);
+
+ // Define controls to be added to the main page of the formset
+
+ grayoutif NOT ideqval SETUP_DATA.PrimaryDisplay == 4;
+ SG_ONEOF_SGMUXMODE
+ endif;
+
+ suppressif NOT ideqval SETUP_DATA.PrimaryDisplay == 4 OR
+ ideqval SETUP_DATA.TPVCardCheck == 0;
+ SG_ONEOF_PXFIXEDDYNAMICMODE
+ endif;
+
+ endform;
+ #endif // SWITCHABLEGRAPHICS_FORM_SETUP
+ #endif // FORM_SET_FORM
+
+#endif // ADVANCED_FORM_SET
+
+
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/SwitchableGraphics/SwitchableGraphics.sdl b/Board/EM/SwitchableGraphics/SwitchableGraphics.sdl
new file mode 100644
index 0000000..125e8f3
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SwitchableGraphics.sdl
@@ -0,0 +1,155 @@
+TOKEN
+ Name = "AmiSgTPV_SUPPORT"
+ Value = "1"
+ Help = "Main switch to enable SwitchableGraphics TPV support in Project"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Master = Yes
+ Token = "SwitchableGraphics_SUPPORT" "=" "1"
+End
+
+TOKEN
+ Name = "SG_MUXLESS_SSVID_DID"
+ Value = "0x21118086"
+ Help = "SUBSYSTEM VENDOR & DEVICE ID. Using Intel iGPU"
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "LOADVBIOS"
+ Value = "1"
+ Help = "1 = Load secondary display device VBIOS; 0 = Do not load"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "EXECUTEVBIOS"
+ Value = "0"
+ Help = "0 = Do no execute\1 = Execute the secondary display device VBIOS (only if LoadVbios == 1)"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "VBIOSSOURCE"
+ Value = "1"
+ Help = "1 = secondary display device VBIOS Source is PCI Card\0 = secondary display device VBIOS Source is FW Volume"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "SGMUXDID1"
+ Value = "0x00030301"
+ Help = "CRT Display; SGMUXDID format\0x|<HPD Mux> |<Aux Mux>|<Disp Mux>|<Port Type>|\0x|31 24|23 16|15 8|7 0|\HPD/Aux/Disp Mux: 1 = iGPU Only, 2 = dGPU Only, 3 = Shared"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "SGMUXDID2"
+ Value = "0x00030302"
+ Help = "LFP Display"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "SGMUXDID3"
+ Value = "0x03030308"
+ Help = "DisplayPort_B Display"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "SGMUXDID4"
+ Value = "0x03030304"
+ Help = "HDMI_B Display"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "SGMUXDID5"
+ Value = "0x03030305"
+ Help = "HDMI_C Display"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "SGMUXDID6"
+ Value = "0x0303030A"
+ Help = "DisplayPort_D Display"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "SGMUXDID7"
+ Value = "0x00030306"
+ Help = "HDMI_D Display"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "SGMUXDID8"
+ Value = "0x00000000"
+ Help = "Unused"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "VALIDDIDS"
+ Value = "7"
+ Help = "Number of valis Device IDs"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+PATH
+ Name = "SwitchableGraphics_DIR"
+ Help = "SwitchableGraphics DXE source directory"
+End
+
+PATH
+ Name = "INCLUDE_DIR"
+ Path = "Include"
+End
+
+MODULE
+ Help = "Includes SwitchableGraphics.mak to Project"
+ File = "SwitchableGraphics.mak"
+End
+
+ELINK
+ Name = "/I$(SwitchableGraphics_DIR)"
+ Parent = "SwitchableGraphics_INCLUDES"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\SwitchableGraphics.sdb"
+ Parent = "SETUP_SDBS"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "$(SwitchableGraphics_DIR)\SwitchableGraphics.sd"
+ Parent = "SETUP_DEFINITIONS"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "SwitchableGraphics_INCLUDES"
+ InvokeOrder = ReplaceParent
+End
+
diff --git a/Board/EM/SwitchableGraphics/SwitchableGraphics.uni b/Board/EM/SwitchableGraphics/SwitchableGraphics.uni
new file mode 100644
index 0000000..6e14e8b
--- /dev/null
+++ b/Board/EM/SwitchableGraphics/SwitchableGraphics.uni
Binary files differ