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Diffstat (limited to 'ReferenceCode/Chipset/LynxPoint/AcpiTables')
13 files changed, 5641 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/Pch.asl b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/Pch.asl new file mode 100644 index 0000000..2b95557 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/Pch.asl @@ -0,0 +1,977 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + + // + // RPAx is root port addresses, which are updated when post to reflect + // the root port function number swapping. + // + Name (RPA0, 0x001C0000) + Name (RPA1, 0x001C0001) + Name (RPA2, 0x001C0002) + Name (RPA3, 0x001C0003) + Name (RPA4, 0x001C0004) + Name (RPA5, 0x001C0005) + Name (RPA6, 0x001C0006) + Name (RPA7, 0x001C0007) + + // + // PCHS stands for PCH series. This will be updated when post. + // 1: PchH + // 2: PchLp + // others: unknown + // + Name (PCHS, 0xFFFFFFFF) + + // + // Reserved MEM range for S3 Save/restore with 64K in size. + // This will be updated when post. + // + Name (SRMB, 0xFFFFFFFF) + + // + // Maximum Snoop Latency and Maximum No-Snoop Latency values for PCIE. + // This will be updated when post. + // + Name (PML1, 0xFFFFFFFF) + Name (PML2, 0xFFFFFFFF) + Name (PML3, 0xFFFFFFFF) + Name (PML4, 0xFFFFFFFF) + Name (PML5, 0xFFFFFFFF) + Name (PML6, 0xFFFFFFFF) + Name (PML7, 0xFFFFFFFF) + Name (PML8, 0xFFFFFFFF) + Name (PNL1, 0xFFFFFFFF) + Name (PNL2, 0xFFFFFFFF) + Name (PNL3, 0xFFFFFFFF) + Name (PNL4, 0xFFFFFFFF) + Name (PNL5, 0xFFFFFFFF) + Name (PNL6, 0xFFFFFFFF) + Name (PNL7, 0xFFFFFFFF) + Name (PNL8, 0xFFFFFFFF) + +Scope(\) +{ + // + // Define the IO Address 0810h-0813h as an ACPI Operating Region first, and + // then it will be dynamically updated during initialization of DTS code. + // The address presented here may not be the actual address used. + // This address range is used as a DTS I/O Trap SMI so that ASL and SMI + // can communicate when needed. + // + OperationRegion(IO_D,SystemIO,0x810,0x4) + Field(IO_D,ByteAcc,NoLock,Preserve) { + TRPD, 8 // 0x810 = DTS I/O Trap + } + // + // The IO address in this ACPI Operating Region will be updated during POST. + // This address range is used as a HotKey I/O Trap SMI so that ASL and SMI can + // communicate when needed. + // + OperationRegion(IO_H,SystemIO,0x1000,0x4) + Field(IO_H,ByteAcc,NoLock,Preserve) { + TRPH, 8 + } + // + // Define PCH PMBASE I/O as an ACPI operating region. The base address + // can be found in Device 31, Registers 40-43h. + // + OperationRegion(PMIO, SystemIo, \PMBS, 0x80) + Field(PMIO, ByteAcc, NoLock, Preserve) { + Offset(0x28), // GPE0 Enable + , 16, + , 3, // GPE for 0-2 GPIO's + GPE3, 1, + , 7, // GPE for 4-0xA GPIO's + GPEB, 1, + Offset(0x3c), // UPRWC - USB Per-Port registers write control + , 1, + UPRW, 1, // USB Per-Port registers write enable + Offset(0x42), // General Purpose Control + , 1, + GPEC, 1 + } + Field(PMIO, ByteAcc, NoLock, WriteAsZeros) { + Offset(0x20), // GPE0 Status + , 16, + , 3, // GPS for 0-2 GPIO's + GPS3, 1, + , 7, // GPS for 4-0xa GPIO's + GPSB, 1, + Offset(0x64), // TCO status register + , 9, + SCIS, 1, // TCO DMI SCI status + , 6 + } + + // + // Define PCH PMBASE I/O as an ACPI operating region. The base address + // can be found in Device 31, Registers 40-43h. + // + OperationRegion(PMLP, SystemIo, Add(\PMBS,0x80), 0x20) + Field(PMLP, ByteAcc, NoLock, Preserve) { + Offset(0x10), // GPE0 Enable + , 8, + GE08, 1, + , 8, + GE17, 1, + , 27, + GE45, 1, + , 5, + GE51, 1, + , 76, + } + Field(PMLP, ByteAcc, NoLock, WriteAsZeros) { + Offset(0x00), // GPE0 Status + , 8, + GS08, 1, + , 8, + GS17, 1, + , 27, + GS45, 1, + , 5, + GS51, 1, + , 76, + } + + // + // Define PCH GPIO I/O as an ACPI operating region. + // The base address can be found in Device 31, Registers 48-4Bh. + // + + OperationRegion(GPR, SystemIo, \GPBS, 0x400) + Field(GPR, ByteAcc, NoLock, Preserve) { + Offset(0x00), // GPIO, Use Select, Bank 0 + GU00, 8, + GU01, 8, + GU02, 8, + GU03, 8, + Offset(0x04), // GPIO, I/O Select, Bank 0 + GIO0, 8, + GIO1, 8, + GIO2, 8, + GIO3, 8, + Offset(0x0C), // GPIO, Level, Bank 0 + GL00, 8, + GL01, 8, + GL02, 8, + GP24, 1, + , 2, + GP27, 1, // SATA_PWR_EN#0 + GP28, 1, // SATA_PWR_EN#1 (SATA Ports 1 and 2) + , 3, + Offset(0x18), + GB00, 8, // GPIO, Blink, Bank 0 + GB01, 8, + GB02, 8, + GB03, 8, + Offset(0x2C), + GIV0, 8, // GPIO, Invert, Bank 0 + GIV1, 8, + GIV2, 8, + GIV3, 8, + Offset(0x30), // GPIO, Use Select, Bank 1 + GU04, 8, + GU05, 8, + GU06, 8, + GU07, 8, + Offset(0x34), // GPIO, I/O Select, Bank 1 + GIO4, 8, + GIO5, 8, + GIO6, 8, + GIO7, 8, + Offset(0x38), // GPIO, Level, Bank 1 + GL04, 8, + GL05, 8, + GL06, 8, + GL07, 8, + Offset(0x40), // GPIO, Use Select, Bank 2 + GU08, 8, + GU09, 8, + GU0A, 8, + GU0B, 8, + Offset(0x44), // GPIO, I/O Select, Bank 2 + GIO8, 8, + GIO9, 8, + GIOA, 8, + GIOB, 8, + Offset(0x48), // GPIO, Level, Bank 2 + GL08, 8, + GL09, 8, + GL0A, 8, + GL0B, 8 + } + + // + // Define PCH GPIO I/O as an ACPI operating region. + // The base address can be found in Device 31, Registers 48-4Bh. + // + OperationRegion(GPRL, SystemIo, \GPBS, 0x40) + Field(GPRL, ByteAcc, NoLock, Preserve) { + Offset(0x00), // GPI_OWN, 0 => ACPI driver owned + , 8, + GO08, 1, + GO09, 1, + , 3, + GO13, 1, + GO14, 1, + , 2, + GO17, 1, + , 27, + GO45, 1, + , 5, + GO51, 1, + , 76, + Offset(0x30), // GPI_ROUT, 0 => SCI + GR00, 32, + GR01, 32, + GR02, 32 + } + + // + // Define a Memory Region that will allow access to the Root Complex + // Register Block. Note that in the Intel Reference Solution, the RCBA + // will get fixed up dynamically during POST. + // + OperationRegion(RCRB,SystemMemory,\SRCB,0x4000) + Field(RCRB,DWordAcc,Lock,Preserve) { + Offset(0x0000), // Backbone Related Registers + Offset(0x1000), // Other Chipset Registers +#ifdef TRAD_FLAG + Offset(0x2330), // SBI AFE Address + AFEA, 32, + Offset(0x2334), // SBI AFE Data + AFED, 32, + Offset(0x2338), // SBI AFE Status + AFES, 16, + Offset(0x233A), // SBI AFE Routing Id + AFER, 16, +#endif // TRAD_FLAG + Offset(0x3000), // Legacy\Other Chipset Configuration Registers + Offset(0x331c), + , 24, + PMFS, 1, // PCIe Source Clock Request Status + Offset(0x3320), + CKEN, 32, // PCIe Source Clock Enable Register + Offset(0x3404), // High Performance Timer Configuration + HPAS, 2, // (1:0) High Performance Address Select + , 5, // (6:2) Reserved + HPAE, 1, // (7) High Performance Address Enable + Offset(0x3418), // Function Disable Register + , 1, // (0) Reserved + ADSD, 1, // (1) Audio DSP Disable + SATD, 1, // (2) Serial ATA Disable + SMBD, 1, // (3) SMBus Disable + HDAD, 1, // (4) High Definition Audio Disable + , 11, // (15:5) Skip for now + RP1D, 1, // (16) Root Port 1 Disable + RP2D, 1, // (17) Root Port 2 Disable + RP3D, 1, // (18) Root Port 3 Disable + RP4D, 1, // (19) Root Port 4 Disable + RP5D, 1, // (20) Root Port 5 Disable + RP6D, 1, // (21) Root Port 6 Disable + RP7D, 1, // (22) Root Port 7 Disable + RP8D, 1, // (23) Root Port 8 Disable + Offset(0x359c), // Usb Port Disable Override Register + UP0D, 1, // (0) Usb Port 0 disable + UP1D, 1, // (1) Usb Port 1 disable + UP2D, 1, // (2) Usb Port 2 disable + UP3D, 1, // (3) Usb Port 3 disable + UP4D, 1, // (4) Usb Port 4 disable + UP5D, 1, // (5) Usb Port 5 disable + UP6D, 1, // (6) Usb Port 6 disable + UP7D, 1, // (7) Usb Port 7 disable + UP8D, 1, // (8) Usb Port 8 disable + UP9D, 1, // (9) Usb Port 9 disable + UPAD, 1, // (10) Usb Port 10 disable + UPBD, 1, // (11) Usb Port 11 disable + UPCD, 1, // (12) Usb Port 12 disable + UPDD, 1, // (13) Usb Port 13 disable + , 1, // (14) Reserved + , 1 // (15) Reserved + } + // + // Support S0, S3, S4, and S5. The proper bits to be set when + // entering a given sleep state are found in the Power Management + // 1 Control ( PM1_CNT ) register, located at ACPIBASE + 04h, + // bits 10d - 12d. + // + + // + // Define the IO Address 1000h-1003h as an ACPI Operating Region first, and + // then it will be dynamically updated during initialization of PFAT code. + // The address presented here may not be the actual address used. + // This address range is used as a PFAT Tools Interface I/O Trap so that the + // update tool can trigger bios code to update the flash using the pfat flow. + // + OperationRegion (IO_P, SystemIO, 0x1000, 0x4) + Field (IO_P, ByteAcc, NoLock, Preserve) { + TRPF, 8 // 0x1000 = PFAT I/O Trap + } + +} //end Scope(\) + + Scope (\_SB) + { + + Method(RDGI,1,Serialized) //Read the value of Input GPIO Line + { + // Function to Read GPIO + // + // Arg0 : GPIn : GPIO Pin number to be read(Zero based) + // + If(LLessEqual(Arg0, 94)){ + // GPBS - GPIO Base Address - 0x800 + // Local0 = GPIOBASE + 100h + (GPIn * 0x08) + Store( Add(Add(GPBS,0x100) , Multiply(Arg0,0x08)),Local0) + OperationRegion(LGPI, SystemIo, Local0, 4) + Field(LGPI, AnyAcc, NoLock, Preserve) { + Offset(0x0), + ,30, + TEMP, 1 + } + Return(TEMP) + } + //AMI_OVERRIDE ---- Fixed for Ubuntu Firmware Test >> + Return(0) + //AMI_OVERRIDE ---- Fixed for Ubuntu Firmware Test << + } // End of Method(RDGI,1) + + Method(RDGP,1,Serialized) + { + // Function to Read GPIO + // + // Arg0 : GPIn : GPIO Pin number to be read(Zero based) + // + If(LLessEqual(Arg0, 94)){ + // GPBS - GPIO Base Address - 0x800 + // Local0 = GPIOBASE + 100h + (GPIn * 0x08) + Store( Add(Add(GPBS,0x100) , Multiply(Arg0,0x08)),Local0) + OperationRegion(LGPI, SystemIo, Local0, 4) + Field(LGPI, AnyAcc, NoLock, Preserve) { + Offset(0x0), + ,31, + TEMP, 1 + } + Return(TEMP) + } + //AMI_OVERRIDE ---- Fixed for Ubuntu Firmware Test >> + Return(0) + //AMI_OVERRIDE ---- Fixed for Ubuntu Firmware Test << + } // End of Method(RDGP,1) + + Method(WTGP,2,Serialized) + { + // Function to write GPIO + // Arg0 - GPIn : GPIO Pin number to write + // Arg1 - Value to be written + // + If(LLessEqual(Arg0, 94)){ + Store( Add(Add(GPBS,0x100) , Multiply(Arg0,0x08)),Local0) + OperationRegion(LGPI, SystemIo, Local0, 4) + Field(LGPI, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 31, + TEMP, 1 + } + Store(Arg1,TEMP) + } + } + Method(WTIN,2,Serialized) + { + // Function to write GPIO + // Arg0 - GPIn : GPIO Pin number to write + // Arg1 - Value to be written + // + If(LLessEqual(Arg0, 94)){ + Store( Add(Add(GPBS,0x100) , Multiply(Arg0,0x08)),Local0) + OperationRegion(LGPI, SystemIo, Local0, 4) + Field(LGPI, ByteAcc, NoLock, Preserve) { + Offset(0x0), + , 3, + TEMP, 1 + } + Store(Arg1,TEMP) + } + } + + Method(WPGP,2,Serialized) //GP Weak pull + { + // Function to write GPIO + // Arg0 - GPIn : GPIO Pin number to write + // Arg1 - 00 = none 01 = down 10 = up + // + If(LLessEqual(Arg0, 94)){ + Store( Add(Add(GPBS,0x104) , Multiply(Arg0,0x08)),Local0) + OperationRegion(LGPI, SystemIo, Local0, 4) + Field(LGPI, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 2 + } + Store(Arg1,TEMP) + } + } + + Method(GP2N,2,Serialized) //GPIO to Native + { + // Function to write GPIO + // Arg0 - GPIn : GPIO Pin number to write + // Arg1 - 0 = Native 1 = GPIO + // + If(LLessEqual(Arg0, 94)){ + Store( Add(Add(GPBS,0x100) , Multiply(Arg0,0x08)),Local0) + OperationRegion(LGPI, SystemIo, Local0, 4) + Field(LGPI, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 1 + } + Store(Arg1,TEMP) + } + } + + Method(GP2A,2,Serialized) //GP to APIC + { + // Function to write GPIO + // Arg0 - GPIn : GPIO Pin number to write + // Arg1 - 00 = mask 01 = route to IOxAPIC and also Pull UP/NONE the GPIO mode Sensing weak pull + // + If(LLessEqual(Arg0, 94)){ + Store( Add(Add(GPBS,0x104) , Multiply(Arg0,0x08)),Local0) + OperationRegion(LGP2, SystemIo, Local0, 4) + Field(LGP2, AnyAcc, NoLock, Preserve) { + Offset(0x0), + GPWP, 2, + GPIS, 1 + } + if(LEqual(Arg1,1)) + { + Store(0,GPIS) + Store(0,GPWP) + }Else{ + Store(2,GPWP) + Store(1,GPIS) + } + + Store(Add(GPBS, 0x10), Local0) + OperationRegion(LGPI, SystemIo, Local0, 2) + Field(LGPI, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 16 + } + + // GPI PIRQ to IOxAPIC enable bit map + // GPI[55:45] to IOxAPIC enable bit[15:5], Subtract 40 from GPI to get ACPI bit + // GPI[14:13] to IOxAPIC enable bit[4:3], Subtract 10 from GPI to get ACPI bit + // GPI[10:8] to IOxAPIC enable bit[2:0], Subtract 8 from GPI to get ACPI bit + If(LGreaterEqual(Arg0, 45)) + { + Subtract(Arg0, 40, Local1) // GPI[55:45] map to APIC[15:5] + }Else{ + If(LLessEqual(Arg0, 10)) + { + Subtract(Arg0, 8, Local1) // GPI[10:8] map to APIC[2:0] + }Else{ + Subtract(Arg0, 10, Local1) // GPI[14:13] map to APIC[4:3] + } + } + + Store(ShiftLeft(1, Local1), Local2) + If(Arg1){ //Enable GP to IOAPIC + Or(TEMP, Local2, TEMP) + } Else{ //mask + And(TEMP, Not(Local2), TEMP) + } + } + } + + Method(GP2B,2,Serialized) //GP to APIC + { + // Function to write GPIO + // Arg0 - GPIn : GPIO Pin number to write + // Arg1 - 00 = mask 01 = route to IOxAPIC + // + If(LLessEqual(Arg0, 94)){ + Store(Add(GPBS, 0x10), Local0) + OperationRegion(LGPI, SystemIo, Local0, 2) + Field(LGPI, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 16 + } + + // GPI PIRQ to IOxAPIC enable bit map + // GPI[55:45] to IOxAPIC enable bit[15:5], Subtract 40 from GPI to get ACPI bit + // GPI[14:13] to IOxAPIC enable bit[4:3], Subtract 10 from GPI to get ACPI bit + // GPI[10:8] to IOxAPIC enable bit[2:0], Subtract 8 from GPI to get ACPI bit + If(LGreaterEqual(Arg0, 45)) + { + Subtract(Arg0, 40, Local1) // GPI[55:45] map to APIC[15:5] + }Else{ + If(LLessEqual(Arg0, 10)) + { + Subtract(Arg0, 8, Local1) // GPI[10:8] map to APIC[2:0] + }Else{ + Subtract(Arg0, 10, Local1) // GPI[14:13] map to APIC[4:3] + } + } + + Store(ShiftLeft(1, Local1), Local2) + If(Arg1){ //Enable GP to IOAPIC + Or(TEMP, Local2, TEMP) + } Else{ //mask + And(TEMP, Not(Local2), TEMP) + } + } + } + + } // End of Scope SB + +scope (\_SB.PCI0) { + Name(LTRE, 0) + Name(OBFF, 0) + + Name(LMSL, 0) + Name(LNSL, 0) + // + // LAN Controller - Device 25, Function 0 + // + Device(GLAN) { // GbE Controller + Name(_ADR, 0x00190000) + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // can wakeup from S4 state + } // end "GbE Controller" + + // + // EHCI Controller #1 - Device 29, Function 0 + // + Device(EHC1) { + Name(_ADR, 0x001D0000) + include("PchEhci1.asl") + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // can wakeup from S4 state + } // end "EHCI Controller #1" + + // + // EHCI Controller #2 - Device 26, Function 0 + // + Device(EHC2) { + Name(_ADR, 0x001A0000) + include("PchEhci2.asl") + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // can wakeup from S4 state + } // end "EHCI Controller #2" + + // + // xHCI Controller - Device 20, Function 0 + // + Device(XHC) { + Name(_ADR, 0x00140000) + include("PchXhci.asl") + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // can wakeup from S4 state + } // end "xHCI Controller" + + // + // High Definition Audio Controller - Device 27, Function 0 + // + Device(HDEF) { + Name(_ADR, 0x001B0000) + include("PchAudio.asl") + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // can wakeup from S4 state + } // end "High Definition Audio Controller" + +#ifdef SERIAL_IO_FLAG + // + // Serial IO Controllers definitions + // + include ("PchSerialIo.asl") + include ("ReferenceCode\\Chipset\\LynxPoint\\SampleCode\\AcpiTables\\Dsdt\\SerialIoDevices.asl") +#endif // SERIAL_IO_FLAG + +#ifdef ADSP_FLAG + // + // Audio DSP Device definition - Device 19, Function 0 + // + Device(ADSP) { + Name(_ADR, 0) + include("PchAudioDsp.asl") + } +#endif // ADSP_FLAG + +#if 0 + // + // PCIE Root Port #1 + // + Device(RP01) { + Method (_ADR, 0) { Return (RPA0) } + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR1, LTRE) + Store (PML1, LMSL) + Store (PNL1, LNSL) + Store (OBF1, OBFF) + } + include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT,0) { + If(PICM) { Return(AR04) }// APIC mode + Return (PR04) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #1" +#endif + +#if 0 + // + // PCIE Root Port #2 + // + Device(RP02) { + Method (_ADR, 0) { Return (RPA1) } + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR2, LTRE) + Store (PML2, LMSL) + Store (PNL2, LNSL) + Store (OBF2, OBFF) + } + include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT,0) { + If(PICM) { Return(AR05) }// APIC mode + Return (PR05) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #2" +#endif + +#if 0 + // + // PCIE Root Port #3 + // + Device(RP03) { + Method (_ADR, 0) { Return (RPA2) } + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR3, LTRE) + Store (PML3, LMSL) + Store (PNL3, LNSL) + Store (OBF3, OBFF) + } + include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT,0) { + If(PICM) { Return(AR06) }// APIC mode + Return (PR06) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #3" +#endif + +#if 0 + // + // PCIE Root Port #4 + // + Device(RP04) { + Method (_ADR, 0) { Return (RPA3) } + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR4, LTRE) + Store (PML4, LMSL) + Store (PNL4, LNSL) + Store (OBF4, OBFF) + } + include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT,0) { + If(PICM) { Return(AR07) }// APIC mode + Return (PR07) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #4" +#endif + +#if 0 + // + // PCIE Root Port #5 + // + Device(RP05) { + Method (_ADR, 0) { Return (RPA4) } + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR5, LTRE) + Store (PML5, LMSL) + Store (PNL5, LNSL) + Store (OBF5, OBFF) + } + include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT,0) { + If(PICM) { Return(AR08) }// APIC mode + Return (PR08) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #5" +#endif + +#if 0 + // + // PCIE Root Port #6 + // + Device(RP06) { + Method (_ADR, 0) { Return (RPA5) } + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR6, LTRE) + Store (PML6, LMSL) + Store (PNL6, LNSL) + Store (OBF6, OBFF) + } + include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT,0) { + If (LEqual(And(CDID,0xF000), 0x8000)) { // LPT-H + If(PICM) { Return(AR09) }// APIC mode + Return (PR09) // PIC Mode + } Else { // ULT + If(PICM) { Return(AR08) }// APIC mode + Return (PR08) // PIC Mode + } + } // end _PRT + + } // end "PCIE Root Port #6" +#endif + +#if 0 + // + // PCIE Root Port #7 + // + Device(RP07) { + Method (_ADR, 0) { Return (RPA6) } + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR7, LTRE) + Store (PML7, LMSL) + Store (PNL7, LNSL) + Store (OBF7, OBFF) + } + include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT,0) { + If(PICM) { Return(AR0E) } // APIC mode + Return (PR0E) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #7" +#endif + +#if 0 + // + // PCIE Root Port #8 + // + Device(RP08) { + Method (_ADR, 0) { Return (RPA7) } + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR8, LTRE) + Store (PML8, LMSL) + Store (PNL8, LNSL) + Store (OBF8, OBFF) + } + include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT,0) { + If(PICM) { Return(AR0F) }// APIC mode + Return (PR0F) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #8" +#endif + + // + // Serial ATA Host Controller - Device 31, Function 2 + // + + // PCH SATA Controller + Device (SAT0) + { + //Bus 0x00, Device 0x1F, Function 0x02 + Name(_ADR, 0x001F0002) + Name(FDEV, Zero) + Name(FDRP, Zero) + + Method(_DEP){ + ADBG("SAT0 DEP Call") + + If(LGreaterEqual(OSYS,2013)) { // PEP SATA Constraint for WinBlue and newer version of WinOS + If(LAnd (LEqual(S0ID, 1), LNotEqual(And(PEPC, 0x03), 0))){ // PEPC Bit[1:0] - SATA (0:None, 1:SATA Ports[all], 2:SATA Controller) + // SATA PEP not set to No Constraint + ADBG("SAT0 DEP") + Return(Package() {\_SB.PEPD}) + } + } + + ADBG("SAT0 DEP NULL") + Return(Package() {}) // No dependency for other OS (non-WinBlue) + } + + Device(PRT0) + { + Name(_ADR,0x0000FFFF) // Port 0 + Method(_SDD,1, Serialized) + { + CreateByteField(Arg0, 157, BFDS) + ToInteger(BFDS, FDEV) + CreateByteField(Arg0, 154, BFRP) + ToInteger(BFRP, FDRP) + } + //Get Task File + Method(_GTF,0,Serialized) + { + //Set Feature Command to enable DevSlp + If (LAnd(LAnd(LEqual(DVS0, 1), LEqual(And(FDEV, 0x01), 0x01)), LEqual(And(FDRP, 0x80), 0x80))) { + Name(PIB1, Buffer(7) + {0x10, 0x09, 0x00, 0x00, 0x00, 0xB0, 0xEF }) + Return (PIB1) + } + Name(PIB2, Buffer(7) + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) + Return (PIB2) + } + } + Device(PRT1) + { + Name(_ADR,0x0001FFFF) // Port 1 + Name(FDEV, Zero) + Name(FDRP, Zero) + Method(_SDD,1, Serialized) + { + CreateByteField(Arg0, 157, BFDS) + ToInteger(BFDS, FDEV) + CreateByteField(Arg0, 154, BFRP) + ToInteger(BFRP, FDRP) + } + // Get Task File + Method(_GTF,0,Serialized) + { + //Set Feature Command to enable DevSlp + If (LAnd(LAnd(LEqual(DVS1, 1), LEqual(And(FDEV, 0x01), 0x01)), LEqual(And(FDRP, 0x80), 0x80))) { + Name(PIB1, Buffer(7) + {0x10, 0x09, 0x00, 0x00, 0x00, 0xB0, 0xEF }) + Return (PIB1) + } + Name(PIB2, Buffer(7) + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) + Return (PIB2) + } + } + Device(PRT2) + { + Name(_ADR,0x0002FFFF) // Port 1 + Name(FDEV, Zero) + Name(FDRP, Zero) + Method(_SDD,1, Serialized) + { + CreateByteField(Arg0, 157, BFDS) + ToInteger(BFDS, FDEV) + CreateByteField(Arg0, 154, BFRP) + ToInteger(BFRP, FDRP) + } + // Get Task File + Method(_GTF,0,Serialized) + { + //Set Feature Command to enable DevSlp + If (LAnd(LAnd(LEqual(DVS2, 1), LEqual(And(FDEV, 0x01), 0x01)), LEqual(And(FDRP, 0x80), 0x80))) { + Name(PIB1, Buffer(7) + {0x10, 0x09, 0x00, 0x00, 0x00, 0xB0, 0xEF }) + Return (PIB1) + } + Name(PIB2, Buffer(7) + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) + Return (PIB2) + } + } + Device(PRT3) + { + Name(_ADR,0x0003FFFF) // Port 3 + Name(FDEV, Zero) + Name(FDRP, Zero) + Method(_SDD,1, Serialized) + { + CreateByteField(Arg0, 157, BFDS) + ToInteger(BFDS, FDEV) + CreateByteField(Arg0, 154, BFRP) + ToInteger(BFRP, FDRP) + } + // Get Task File + Method(_GTF,0,Serialized) + { + //Set Feature Command to enable DevSlp + If (LAnd(LAnd(LEqual(DVS3, 1), LEqual(And(FDEV, 0x01), 0x01)), LEqual(And(FDRP, 0x80), 0x80))) { + Name(PIB1, Buffer(7) + {0x10, 0x09, 0x00, 0x00, 0x00, 0xB0, 0xEF }) + Return (PIB1) + } + Name(PIB2, Buffer(7) + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) + Return (PIB2) + } + } + } + + Device(SAT1) { + Name(_ADR,0x001F0005) + // + // SATA Methods pulled in via SSDT. + // + } + + // + // SMBus Controller - Device 31, Function 3 + // + Device(SBUS) { + Name(_ADR,0x001F0003) + Include("PchSmb.asl") + } +} diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAcpiTables.cif b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAcpiTables.cif new file mode 100644 index 0000000..e1bbbb9 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAcpiTables.cif @@ -0,0 +1,19 @@ +<component> + name = "PchAcpiTables" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\LynxPoint\AcpiTables\Dsdt" + RefName = "PchAcpiTables" +[files] +"PchAcpiTables.sdl" +"PchAcpiTables.inf" +"Pch.asl" +"PchAudio.asl" +"PchPcie.asl" +"PchSmb.asl" +"PchEhci1.asl" +"PchEhci2.asl" +"UsbSbd.asl" +"PchXhci.asl" +"PchAudioDsp.asl" +"PchSerialIo.asl" +<endComponent> diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAcpiTables.inf b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAcpiTables.inf new file mode 100644 index 0000000..0cce4b9 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAcpiTables.inf @@ -0,0 +1,53 @@ +## @file +# Component description file for the ACPI tables +# +#@copyright +# Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = PchAcpiTables +FILE_GUID = 31401EE7-1600-437c-A11C-B1035D8E6070 +COMPONENT_TYPE = PCH_ACPI_TABLES +FFS_EXT = .ffs + +[sources.common] + Pch.asl + PchAudio.asl + PchAudioDsp.asl + PchSerialIo.asl + PchPcie.asl + PchSmb.asl + PchEhci1.asl + PchEhci2.asl + UsbSbd.asl + PchXhci.asl + +[libraries.common] + +[includes.common] + . + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Efi + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + +[nmake.common] diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAcpiTables.sdl b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAcpiTables.sdl new file mode 100644 index 0000000..56ded8a --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAcpiTables.sdl @@ -0,0 +1,735 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchAcpiTables/PchAcpiTables.sdl 5 11/07/13 3:10a Littleyan $ +# +# $Revision: 5 $ +# +# $Date: 11/07/13 3:10a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchAcpiTables/PchAcpiTables.sdl $ +# +# 5 11/07/13 3:10a Littleyan +# [TAG] EIP142529 +# [Category] SPEC Update +# [Description] PCH RC update to 1.7.0 +# [Files] PchAcpiTables.sdl PchXhci.asl PchPciExpressHelpersLib.h +# PchRegsThermal.h PchPciExpressHelpersLibrary.c +# PchPm.c PchRootPorts.c PchInitPeim.c +# PchSmmSx.c PchPcieSmm.c PchInfo.h +# PchS3Peim.c SerialIoDevices.asl Sensor.asl +# +# 4 9/13/13 9:03a Barretlin +# [TAG] EIP132976 +# [Category] Improvement +# [Description] fix after plugging USB key on Rear USB3_1(TOP) +# port(HS03) , there's no remove and save item in bot right corner +# [Files] PchAcpiTables.sdl PchXhci.asl +# +# 3 5/24/13 2:48a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Set token for OEM to change PchEhxi1.asl and +# PchEhxi2.asl. +# [Files] PchAcpiTables.sdl, PchEhci1.asl, PchEhci2.asl +# +# 2 5/06/13 8:14a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Set token for OEM easy to modify. +# [Files] PchAcpiTables.sdl +# PchXhci.asl +# +# 1 2/08/12 8:39a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = PchAcpiTables_SUPPORT + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable PchAcpiTables support in Project" +End + +TOKEN + Name = "EHC1_PR01_UPC" + Value = "0xFF,0x00,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR01_PLD" + Value = "0x81, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00, 0x30, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR11_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR11_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE1, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR12_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR12_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE1, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR13_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR13_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE1, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR14_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR14_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE1, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR15_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR15_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB1, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR16_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR16_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB1, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR17_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR17_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB1, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR18_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC1_PR18_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB1, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR01_UPC" + Value = "0xFF,0x00,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR01_PLD" + Value = "0x81, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00, 0x30, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR11_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR11_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE1, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR12_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR12_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE1, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR13_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR13_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE1, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR14_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR14_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE1, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR15_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR15_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB1, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR16_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHC2_PR16_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB1, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS01_UPC" + Value = "0xFF,0x03,0x00,0x00" + Help = "HS01's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS01_PLD" + Value = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x0C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS01's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS02_UPC" + Value = "0xFF,0x03,0x00,0x00" + Help = "HS02's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS02_PLD" + Value = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x0C, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00" + Help = "HS02's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS03_INTERNAL" + Value = "1" + TokenType = Boolean + TargetH = Yes + Help = "1: HS03 is internal port./0: HS03 is external port." +End + +TOKEN + Name = "HS03_UPC" + Value = "0xFF,0x03,0x00,0x00" + Help = "HS03's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS03_PLD" + Value = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00" + Help = "HS03's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS04_UPC" + Value = "0xFF,0x03,0x00,0x00" + Help = "HS04's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS04_PLD" + Value = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00" + Help = "HS04's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS05_UPC" + Value = "0xFF,0x00,0x00,0x00" + Help = "HS05's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS05_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x0C, 0x80, 0x02, 0x00, 0x00, 0x00, 0x00" + Help = "HS05's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS06_UPC" + Value = "0xFF,0x00,0x00,0x00" + Help = "HS06's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS06_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00" + Help = "HS06's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS07_UPC" + Value = "0xFF,0x00,0x00,0x00" + Help = "HS07's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS07_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00" + Help = "HS07's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS08_UPC" + Value = "0xFF,0x00,0x00,0x00" + Help = "HS08's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS08_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00" + Help = "HS08's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS09_UPC" + Value = "0xFF,0x03,0x00,0x00" + Help = "HS09's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS09_PLD" + Value = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00" + Help = "HS09's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS10_UPC" + Value = "0xFF,0x03,0x00,0x00" + Help = "HS10's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS10_PLD" + Value = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00" + Help = "HS10's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS11_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS11's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS11_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS11's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS12_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS12's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS12_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS12's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS13_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS13's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS13_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS13's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS14_UPC" + Value = "0xFF,0xFF,0x00,0x00" + Help = "HS14's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS14_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS14's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS15_UPC" + Value = "0x00,0x00,0x00,0x00" + Help = "HS15's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "HS15_PLD" + Value = "0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "HS15's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP1_UPC" + Value = "0xFF,0x03,0x00,0x00" + Help = "SSP1's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP1_PLD" + Value = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x0C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00" + Help = "SSP1's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP1_PR3" + Value = "0x01" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "SSP2_UPC" + Value = "0xFF,0x03,0x00,0x00" + Help = "SSP2's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP2_PLD" + Value = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x0C, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00" + Help = "SSP2's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP2_PR3" + Value = "0x02" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "SSP3_UPC" + Value = "0xFF,0x03,0x00,0x00" + Help = "SSP3's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP3_PLD" + Value = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00" + Help = "SSP3's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP3_PR3" + Value = "0x04" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "SSP4_UPC" + Value = "0xFF,0x03,0x00,0x00" + Help = "SSP4's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP4_PLD" + Value = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00" + Help = "SSP4's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP4_PR3" + Value = "0x08" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "SSP5_UPC" + Value = "0xFF,0x03,0x00,0x00" + Help = "SSP5's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP5_PLD" + Value = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00" + Help = "SSP5's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP5_PR3" + Value = "0x10" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "SSP6_UPC" + Value = "0xFF,0x03,0x00,0x00" + Help = "SSP6's Usb Port Capabilities" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP6_PLD" + Value = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00" + Help = "SSP6's Physical Location Description" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SSP6_PR3" + Value = "0x20" + TokenType = Integer + TargetH = Yes +End + +PATH + Name = "PchAcpiTables_DIR" +End + +ELINK + Name = "$(PchAcpiTables_DIR)\Pch.asl" + Parent = "INTEL_GENERIC_ASL" + Priority = 1 + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAudio.asl b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAudio.asl new file mode 100644 index 0000000..df64da3 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAudio.asl @@ -0,0 +1,44 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + // + // High Definition Audio - Device 27, Function 0 + // + OperationRegion(HDAR, PCI_Config, 0x4C,0x10) + Field(HDAR,WordAcc,NoLock,Preserve) { + Offset(0), // 0x4C, Dock Control Register + DCKA,1, // Dock Attach + ,7, + Offset(1), // 04Dh, Dock Status Register + DCKM,1, // Dock Mated + ,6, + DCKS,1, // Docking Supported + Offset(8), // 0x54, Power Management Control and Status Register + , 8, + PMEE,1, + , 6, + PMES,1 // PME Status + } diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAudioDsp.asl b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAudioDsp.asl new file mode 100644 index 0000000..159179b --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchAudioDsp.asl @@ -0,0 +1,133 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + + Name (_HID, "INT33C8") + Name (_CID, "INT33C8") + Name (_DDN, "Intel(R) Smart Sound Technology Host Controller - INT33C8" ) + Name (_UID, 1) + + Method(_DEP){ + ADBG("ADSP DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("ADSP DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("ADSP DEP NULL") + Return(Package() {}) + } + } + + // Default parameters values for Realtek codec + Name (MCLK, Zero) + Name (SCLK, 0x9) + Name (SSPM, Zero) + + // Bluetooth support + Name (ABTH, Zero) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00100000, BAR0) // MMIO 1 - Audio DSP MMIO + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {3} // Audio DSP IRQ + }) + + Name (EOD, 1) + Method (_CRS, 0x0, NotSerialized) + { + Switch (ToInteger(CODS)) + { + Case (0) { + // Realtek param values + Store (\_SB.PCI0.I2C0.ACD0.MCLK, \_SB.PCI0.ADSP.MCLK) + Store (\_SB.PCI0.I2C0.ACD0.SCLK, \_SB.PCI0.ADSP.SCLK) + Store (\_SB.PCI0.I2C0.ACD0.SSPM, \_SB.PCI0.ADSP.SSPM) + } + Case (1) { + // Cirrus param values + Store (\_SB.PCI0.I2C0.ACD1.MCLK, \_SB.PCI0.ADSP.MCLK) + Store (\_SB.PCI0.I2C0.ACD1.SCLK, \_SB.PCI0.ADSP.SCLK) + Store (\_SB.PCI0.I2C0.ACD1.SSPM, \_SB.PCI0.ADSP.SSPM) + } + Case (2) { + // IDT param values + Store (\_SB.PCI0.I2C0.ACD2.MCLK, \_SB.PCI0.ADSP.MCLK) + Store (\_SB.PCI0.I2C0.ACD2.SCLK, \_SB.PCI0.ADSP.SCLK) + Store (\_SB.PCI0.I2C0.ACD2.SSPM, \_SB.PCI0.ADSP.SSPM) + } + Default { + // Realtek params as default + Store (\_SB.PCI0.I2C0.ACD0.MCLK, \_SB.PCI0.ADSP.MCLK) + Store (\_SB.PCI0.I2C0.ACD0.SCLK, \_SB.PCI0.ADSP.SCLK) + Store (\_SB.PCI0.I2C0.ACD0.SSPM, \_SB.PCI0.ADSP.SSPM) + } + } + Return (RBUF) + } + + Method (_SRS, 0x1, Serialized) + { + Store (1, EOD) + } + + Method (_STA, 0x0, NotSerialized) + { + If(LGreaterEqual(OSYS,2012)) + { + If(LEqual(S0ID, 1)) + { + CreateDWordField (^RBUF,^BAR0._BAS,BVAL) + If (LEqual(BVAL, 0)) + { + Return (0x0) + } + If (And (EOD, 0x1, EOD)) + { + Return (0xf) // Enabled 1111 + } + Else + { + Return (0xd) // Disabled 1101 + } + } + } + Return (0x0) + } + + Method (_DIS, 0x0, NotSerialized) + { + Store (0, EOD) + } + + Device (I2S0) + { // I2S Port 0 + Name (_ADR, 0) + } + Device (I2S1) + { // I2S Port 1 + Name (_ADR, 1) + }
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchEhci1.asl b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchEhci1.asl new file mode 100644 index 0000000..327b5c2 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchEhci1.asl @@ -0,0 +1,238 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + + OperationRegion(PWKE,PCI_Config,0x54,0x12) + + Field(PWKE,DWordAcc,NoLock,Preserve) + { + , 8, + PMEE, 1, // PWR_CNTL_STS.PME_En + , 6, + PMES, 1, // PWR_CNTL_STS.PME_Sts + Offset (0x0E), + , 1, + PWUC, 8 // Port Wake Up Capability Mask + } + + Method(_PSW,1) + { + If(Arg0) + { + Store(Ones,PWUC) + } + Else + { + Store(0,PWUC) + } + } + + // The CRB leaves the USB ports on in S3/S4 to allow + // the ability to Wake from USB. Therefore, define + // the below control methods to state D2 entry during + // the given S-State. + + Method(_S3D,0) + { + Return(2) + } + + Method(_S4D,0) + { + Return(2) + } + + Device(HUBN) + { + Name(_ADR, Zero) + + Device(PR01) + { + Name(_ADR, One) + + // + // There will have "Generic USB Hub" existed at Port 1 of each EHCI controller + // in Windows "Device Manager" while RMH is enabled, so need to add _UPC + // and _PLD to report OS that it's not user visible to pass WHQL: Single Computer + // Display Object test in Win7 + // + Method(_UPC,0,Serialized) { + Name(UPCA, Package() { ASL_EHC1_PR01_UPC }) + Return(UPCA) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC1_PR01_PLD} + }) + + Return (PLDP) + } + + Device(PR11) + { + Name(_ADR, One) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC1_PR11_UPC }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC1_PR11_PLD} + }) + Return (PLDP) + } + } + + Device(PR12) + { + Name(_ADR, 0x02) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC1_PR12_UPC }) + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC1_PR12_PLD} + }) + Return (PLDP) + } + } + + Device(PR13) + { + Name(_ADR, 0x03) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC1_PR13_UPC }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC1_PR13_PLD} + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LEqual(And(CDID,0xF000), 0x9000)) { // on LPT-LP platforms this port is internal + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(PR14) + { + Name(_ADR, 0x04) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC1_PR14_UPC }) + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC1_PR14_PLD} + }) + Return (PLDP) + } + Alias(SBV1,SDGV) // copy USB Sideband Deferring GPE Vector (HOST_ALERT#1) to DSM method + Include("UsbSBD.ASL") + } + + Device(PR15) + { + Name(_ADR, 0x05) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC1_PR15_UPC }) + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC1_PR15_PLD} + }) + Return (PLDP) + } + Alias(SBV2,SDGV) // copy USB Sideband Deferring GPE Vector (HOST_ALERT#2) to DSM method + Include("UsbSBD.ASL") + } + + Device(PR16) + { + Name(_ADR, 0x06) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC1_PR16_UPC }) + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC1_PR16_PLD} + }) + Return (PLDP) + } + Alias(SBV1,SDGV) // copy USB Sideband Deferring GPE Vector (HOST_ALERT#1) to DSM method + Include("UsbSBD.ASL") + } + + Device(PR17) + { + Name(_ADR, 0x07) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC1_PR17_UPC }) + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC1_PR17_PLD} + }) + Return (PLDP) + } + Alias(SBV2,SDGV) // copy USB Sideband Deferring GPE Vector (HOST_ALERT#2) to DSM method + Include("UsbSBD.ASL") + } + + Device(PR18) + { + Name(_ADR, 0x08) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC1_PR18_UPC }) + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC1_PR18_PLD} + }) + Return (PLDP) + } + } + } // End of PR01 + } // End of HUBN diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchEhci2.asl b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchEhci2.asl new file mode 100644 index 0000000..0449f59 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchEhci2.asl @@ -0,0 +1,199 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + + OperationRegion(PWKE,PCI_Config,0x54,0x12) + + Field(PWKE,DWordAcc,NoLock,Preserve) + { + , 8, + PMEE, 1, // PWR_CNTL_STS.PME_En + , 6, + PMES, 1, // PWR_CNTL_STS.PME_Sts + Offset (0x0E), + , 1, + PWUC, 6 // Port Wake Up Capability Mask + } + + Method(_PSW,1) + { + If(Arg0) + { + Store(Ones,PWUC) + } + Else + { + Store(0,PWUC) + } + } + + // The CRB leaves the USB ports on in S3/S4 to allow + // the ability to Wake from USB. Therefore, define + // the below control methods to state D2 entry during + // the given S-State. + + Method(_S3D,0) + { + Return(2) + } + + Method(_S4D,0) + { + Return(2) + } + + Device(HUBN) + { + Name(_ADR, Zero) + + Device(PR01) + { + Name(_ADR, One) + + // + // There will have "Generic USB Hub" existed at Port 1 of each EHCI controller + // in Windows "Device Manager" while RMH is enabled, so need to add _UPC + // and _PLD to report OS that it's not user visible to pass WHQL: Single Computer + // Display Object test in Win7 + // + Method(_UPC,0,Serialized) { + Name(UPCA, Package() { ASL_EHC2_PR01_UPC }) + Return(UPCA) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC2_PR01_PLD} + }) + Return (PLDP) + } + + Device(PR11) + { + Name(_ADR, One) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC2_PR11_UPC }) + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC2_PR11_PLD} + }) + Return (PLDP) + } + } + + Device(PR12) + { + Name(_ADR, 0x02) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC2_PR12_UPC }) + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC2_PR12_PLD} + }) + Return (PLDP) + } + Alias(SBV1,SDGV) // copy USB Sideband Deferring GPE Vector (HOST_ALERT#1) to DSM method + Include("UsbSBD.ASL") + } + + Device(PR13) + { + Name(_ADR, 0x03) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC2_PR13_UPC }) + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC2_PR13_PLD} + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LEqual(And(CDID,0xF000), 0x9000)) { // on LPT-LP platforms this port is internal + And(VIS,0,VIS) + } + Return (PLDP) + } + Alias(SBV2,SDGV) // copy USB Sideband Deferring GPE Vector (HOST_ALERT#2) to DSM method + Include("UsbSBD.ASL") + } + + Device(PR14) + { + Name(_ADR, 0x04) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC2_PR14_UPC }) + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC2_PR14_PLD} + }) + Return (PLDP) + } + } + + Device(PR15) + { + Name(_ADR, 0x05) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC2_PR15_UPC }) + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC2_PR15_PLD} + }) + Return (PLDP) + } + } + + Device(PR16) + { + Name(_ADR, 0x06) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_EHC2_PR16_UPC }) + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer (0x10) { + ASL_EHC2_PR16_PLD} + }) + Return (PLDP) + } + } + + } // End of PR01 + } // End of HUBN diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchPcie.asl b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchPcie.asl new file mode 100644 index 0000000..5a64ec9 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchPcie.asl @@ -0,0 +1,288 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + + + OperationRegion(PXCS,PCI_Config,0x00,0x380) + Field(PXCS,AnyAcc, NoLock, Preserve) + { + Offset(0), + VDID, 32, + Offset(0x19), // BNUM - Bus Number Register + SCBN, 8, // Secondary Bus Number + Offset(0x50), // LCTL - Link Control Register + L0SE, 1, // 0, L0s Entry Enabled + , 3, + LDIS, 1, + , 3, + Offset(0x52), // LSTS - Link Status Register + , 13, + LASX, 1, // 0, Link Active Status +// AMI_OVERRIDE, [EIP84720]> + Offset(0x54), // SLCAP - Slot Capabilities Register + , 6, + HPCE, 1, // 6, Hot Plug Capable +// AMI_OVERRIDE, [EIP84720]< + Offset(0x5A), // SLSTS[7:0] - Slot Status Register + ABPX, 1, // 0, Attention Button Pressed + , 2, + PDCX, 1, // 3, Presence Detect Changed + , 2, + PDSX, 1, // 6, Presence Detect State + , 1, + Offset(0x60), // RSTS - Root Status Register + , 16, + PSPX, 1, // 16, PME Status +// AMI_OVERRIDE, [EIP121262]> + PMEP, 1, // 17, PME Pending +// AMI_OVERRIDE, [EIP121262]< + Offset(0xA4), + D3HT, 2, // Power State + Offset(0xD8), // MPC - Miscellaneous Port Configuration Register + , 30, + HPEX, 1, // 30, Hot Plug SCI Enable + PMEX, 1, // 31, Power Management SCI Enable + Offset(0xE2), // RPPGEN - Root Port Power Gating Enable + , 2, + L23E, 1, // 2, L23_Rdy Entry Request (L23ER) + L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT) + Offset(0x324), + , 3, + LEDM, 1 // PCIEDBG.DMIL1EDM + } + Field(PXCS,AnyAcc, NoLock, WriteAsZeros) + { + Offset(0xDC), // SMSCS - SMI/SCI Status Register + , 30, + HPSX, 1, // 30, Hot Plug SCI Status + PMSX, 1 // 31, Power Management SCI Status + } + + Method(_STA, 0x0, NotSerialized) + { + If(LEqual(VDID, 0xFFFFFFFF)){ + Return(0x00) + } Else { + Return(0x0F) + } + } + + Name(LTRV, Package(){0,0,0,0}) + Name(OPTS, 0) // PCH SETUP options for LTR and OBFF +// AMI_OVERRIDE, [EIP121262]> + Name(RPAV, 0) +// AMI_OVERRIDE, [EIP121262]< + // + // _DSM Device Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index (0 = Return Supported Functions) + // Arg3: Package Parameters + Method(_DSM, 4, Serialized) { + // + // Switch based on which unique function identifier was passed in + // + Switch(ToInteger(Arg0)) { + // + // _DSM Definitions for Latency Tolerance Reporting + // + // Arguments: + // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D + // Arg1: Revision ID: 2 + // Arg2: Function Index: 1, 4 or 6 + // Arg3: Empty Package + // + // Return: + // A Package of four integers corresponding with the LTR encoding defined + // in the PCI Express Base Specification, as follows: + // Integer 0: Maximum Snoop Latency Scale + // Integer 1: Maximum Snoop Latency Value + // Integer 2: Maximum No-Snoop Latency Scale + // Integer 3: Maximum No-Snoop Latency Value + // These values correspond directly to the LTR Extended Capability Structure + // fields described in the PCI Express Base Specification. + // + Case(ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) { + // + // Switch by function index + // + Switch(ToInteger(Arg2)) { + // + // Function Index:0 + // Standard query - A bitmask of functions supported + // + Case (0) + { + if (LEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + Store(1, OPTS) // function 0 + if (LTRE){ + Or(OPTS,0x40,OPTS) // function 6 + } + if (OBFF){ + Or(OPTS,0x10,OPTS) // function 4 + } + Return (OPTS) // bitmask of supported functions: 6, 4, 0. + } else { + Return (0) + } + } + // + // Function Index: 4 + // + Case(4) { + if (LEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + if (OBFF){ + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,8,0,0,0,0}) // OBFF capable, offset 4[08h] + } else { + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}) + } + } + } + // + // Function Index: 6 + // LTR Extended Capability Structure + // + Case(6) { + if (LEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + if (LTRE){ + if (LOr(LEqual(LMSL, 0xFFFFFFFF),LEqual(LNSL, 0xFFFFFFFF))) + { + if (LEqual (PCHS, 1)) { + //PCH-H + Store (0x0846, LMSL) + Store (0x0846, LNSL) + } elseif (LEqual (PCHS, 2)) { + //PCH-LP + Store (0x1003, LMSL) + Store (0x1003, LNSL) + } + } + Store(And(ShiftRight(LMSL,10),7), Index(LTRV, 0)) + Store(And(LMSL,0x3FF), Index(LTRV, 1)) + Store(And(ShiftRight(LNSL,10),7), Index(LTRV, 2)) + Store(And(LNSL,0x3FF), Index(LTRV, 3)) + + Return (LTRV) + } else { + Return (0) + } + } + } + } // End of switch(Arg2) + } // End of case(ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) + } // End of switch(Arg0) + return (Buffer() {0x00}) + } // End of _DSM + + Device(PXSX) + { + Name(_ADR, 0x00000000) + + // NOTE: Any PCIE Hot-Plug dependency for this port is + // specific to the CRB. Please modify the code based on + // your platform requirements. + + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state +// AMI_OVERRIDE, [EIP84720]> + Method(_RMV, 0, NotSerialized){ +#if defined ASL_Thunderbolt_SUPPORT && ASL_Thunderbolt_SUPPORT == 1 && ASL_TBT_RC_VERSION > 17 + If(LEqual(\TBUS, SCBN)) + { +#if defined ASL_DEFAULT_TBT_RMV_RETURN_VALUE && ASL_DEFAULT_TBT_RMV_RETURN_VALUE == 1 + Return(TBMV) +#else + Return(0) +#endif + } + Else + { + Return(HPCE) //0:device cannot be removed 1:device can be removed + } +#else + Return(HPCE) //0:device cannot be removed 1:device can be removed +#endif + } +// AMI_OVERRIDE, [EIP84720]< + + } + +// AMI_OVERRIDE, [EIP121262]> + Method(_REG,2) + { + If(LAnd(LEqual(Arg0,2),LEqual(Arg1,1))) + { + Store(One, RPAV) + } + } +// AMI_OVERRIDE, [EIP121262]< + + // + // PCI_EXP_STS Handler for PCIE Root Port + // + Method(HPME,0,Serialized) + { +// AMI_OVERRIDE, [EIP105657]> + If(LOr(PSPX, PMEP)){ + Store(PMEX, Local1) + Store(0, PMEX) + Sleep(50) + Store(1, PSPX) + Sleep(50) + If(PSPX){ + Store(1, PSPX) + Sleep(50) + } + Store(Local1, PMEX) + } +// AMI_OVERRIDE, [EIP105657]< + + If(PMSX) { + // + // Clear the PME SCI status bit with timout + // + Store(200,Local0) + While(Local0) { + // + // Clear PME SCI Status + // + Store(1, PMSX) + // + // If PME SCI Status is still set, keep clearing it. + // Otherwise, break the while loop. + // + If(PMSX) { + Decrement(Local0) + } else { + Store(0,Local0) + } + } + // + // Notify PCIE Endpoint Devices + // + Notify(PXSX, 0x02) + } + } diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchSerialIo.asl b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchSerialIo.asl new file mode 100644 index 0000000..1142148 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchSerialIo.asl @@ -0,0 +1,1029 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the SandyBridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + + // + // System Bus + // + Scope (\_SB.PCI0) + { + + External(BID) + External(\_SB.PCI0.I2C0.PS0X, MethodObj) + External(\_SB.PCI0.I2C0.PS3X, MethodObj) + External(\_SB.PCI0.I2C1.PS0X, MethodObj) + External(\_SB.PCI0.SDHC.PS0X, MethodObj) + + Device(SIRC) + { + // + // Serial IO devices occupy 2 address ranges each: BAR0 and BAR1. + // Each device claims its BAR0 addresses in its own _CRS method + // BAR1 addresses are not defined inside devices; instead, they are gathered in SIRC device + // SIRC also contains about half of BAR0 for SDIO - upper half except 0xC bytes which are clamed by WiFi device + // + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,4) + + Method(_STA) + { + If(LLess(OSYS,2012)) { Return(0x0) } // check for Win7 or older + If(LEqual(And(CDID,0xF000), 0x8000)) { Return(0x0) } // check for LPT-H chipset + Return (0xF) + } + + // + // Base address of the below memory ranges will be updated with actual addresses during BIOS execution. + // + Name(BUF1,ResourceTemplate() { Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BU01) }) // Serial IO SDMA BAR1 + Name(BUF2,ResourceTemplate() { Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BU02) }) // Serial IO I2C0 BAR1 + Name(BUF3,ResourceTemplate() { Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BU03) }) // Serial IO I2C1 BAR1 + Name(BUF4,ResourceTemplate() { Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BU04) }) // Serial IO SPI0 BAR1 + Name(BUF5,ResourceTemplate() { Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BU05) }) // Serial IO SPI1 BAR1 + Name(BUF6,ResourceTemplate() { Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BU06) }) // Serial IO UA00 BAR1 + Name(BUF7,ResourceTemplate() { Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BU07) }) // Serial IO UA01 BAR1 + Name(BUF8,ResourceTemplate() { Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BU08) }) // Serial IO SDIO BAR1 + Name(BUFL,ResourceTemplate() { Memory32Fixed (ReadWrite, 0x00000000, 0x00000008, SDLO) }) // Serial IO SDIO BAR0 lower part + Name(BUFH,ResourceTemplate() { Memory32Fixed (ReadWrite, 0x00000000, 0x00000FEC, SDHI) }) // Serial IO SDIO BAR0 upper part + + Method (_CRS, 0x0, NotSerialized) + { + Store(ResourceTemplate() { }, Local0) // placeholder for concatenated buffers + CreateDWordField(BUF1, ^BU01._BAS, BR01) + CreateDWordField(BUF2, ^BU02._BAS, BR02) + CreateDWordField(BUF3, ^BU03._BAS, BR03) + CreateDWordField(BUF4, ^BU04._BAS, BR04) + CreateDWordField(BUF5, ^BU05._BAS, BR05) + CreateDWordField(BUF6, ^BU06._BAS, BR06) + CreateDWordField(BUF7, ^BU07._BAS, BR07) + CreateDWordField(BUF8, ^BU08._BAS, BR08) + // + // concatenate all buffers with non-zero address into Local0 + // + If(LNotEqual(BR01, 0)) { ConcatenateResTemplate(Local0, BUF1, Local0) } + If(LNotEqual(BR02, 0)) { ConcatenateResTemplate(Local0, BUF2, Local0) } + If(LNotEqual(BR03, 0)) { ConcatenateResTemplate(Local0, BUF3, Local0) } + If(LNotEqual(BR04, 0)) { ConcatenateResTemplate(Local0, BUF4, Local0) } + If(LNotEqual(BR05, 0)) { ConcatenateResTemplate(Local0, BUF5, Local0) } + If(LNotEqual(BR06, 0)) { ConcatenateResTemplate(Local0, BUF6, Local0) } + If(LNotEqual(BR07, 0)) { ConcatenateResTemplate(Local0, BUF7, Local0) } + + If(LNotEqual(BR08, 0)) { + ConcatenateResTemplate(Local0, ^BUF8, Local0) + // + // Calculate regions occupied by SDIO's BAR0 + // + OperationRegion(SDCH, SystemMemory, BR08, 0x40) // SDHC PCI Config Header + Field(SDCH, DWordAcc, NoLock, Preserve) { + Offset(0x10), + BAR0, 32 + } + + CreateDWordField(^BUFL, ^SDLO._BAS, LBAS) + CreateDWordField(^BUFH, ^SDHI._BAS, HBAS) + Add(BAR0, 0x1000, LBAS) + Add(BAR0, 0x1014, HBAS) + + ConcatenateResTemplate(Local0, BUFL, Local0) + ConcatenateResTemplate(Local0, BUFH, Local0) + } + + Return (Local0) + } //end _CRS + + Method(CNTR,1,Serialized) + { + Switch (ToInteger(Arg0)) + { + Case (1) { CreateDWordField(^BUF1,^BU01._BAS, BAR1); Return(BAR1) } + Case (2) { CreateDWordField(^BUF2,^BU02._BAS, BAR2); Return(BAR2) } + Case (3) { CreateDWordField(^BUF3,^BU03._BAS, BAR3); Return(BAR3) } + Case (4) { CreateDWordField(^BUF4,^BU04._BAS, BAR4); Return(BAR4) } + Case (5) { CreateDWordField(^BUF5,^BU05._BAS, BAR5); Return(BAR5) } + Case (6) { CreateDWordField(^BUF6,^BU06._BAS, BAR6); Return(BAR6) } + Case (7) { CreateDWordField(^BUF7,^BU07._BAS, BAR7); Return(BAR7) } + Case (8) { CreateDWordField(^BUF8,^BU08._BAS, BAR8); Return(BAR8) } + Default { Return (0xFFFFFFFF) } + } + } //end CNTR + + } // end of SIRC + + //---------------------------- + // Serial IO GPIO Controller + //---------------------------- + Device (GPI0) + { + Name (_HID, "INT33C7") + Name (_CID, "INT33C7") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + // + // BIOS specific change. + // Provide Min & Max IO range addresses + // BIOS to update AddressMinimum & AddressMaximum fields + // dynamically after PCI enumeration. + // + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x03FF, 0x0000, 0x0400,,, BAR0) + }) + + + Method (_CRS, 0x0, NotSerialized) + { + + Return (RBUF) + } + + Method (_HRV) + { + // + // Report LPC Revision Id + // + Return (CRID) + } + + CreateDWordField(RBUF,BAR0._MIN,BVAL) + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(BVAL, 0)) { Return(0x0) } // has BAR for this device been programmed by the OS? + If(LLess(OSYS,2012)) { Return(0x0) } // Win 8 or above? + If(LEqual(S0ID, 1)) { Return(0xF) } // CS enabled in SETUP? + Return(0x0) + } + } // Device (GPI0) + + //--------------------------- + // Serial IO DMA Controller + //--------------------------- + Device (SDMA) + { + Name (_HID, "INTL9C60") + Name (_UID, 1) + Name (_ADR, 0x00150000) + + Name (RBUF, ResourceTemplate () + { + // + // Resource settings will be overwritten after PCI enumeration + // + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {20} + }) + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + + Method (_HRV) + { + // + // Report LPC Revision Id + // + Return (CRID) + } + + Method (PTD3, 0x0, NotSerialized) { + // + // put DMA hardware in D3 + // + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(1), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(1),0x84 ,Local0) + OperationRegion(DMB1, SystemMemory, Local0, 4) + Field(DMB1, DWordAcc, NoLock, Preserve) { TEMP, 32 } + Or(TEMP, 0x3, TEMP) + } + } + + CreateDWordField(RBUF,BAR0._BAS,BVAL) + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(BVAL, 0)) { Return(0x0) } // has BAR for this device been programmed by the OS? + If(LLess(OSYS,2012)) { Return(0x0) } // OS older than Win 8? hide the device + If(LAnd(LEqual(DOSD, 2), LEqual(OSYS,2012))) { PTD3(); Return(0x0) } // "auto" mode & Win8? hide the device + If(LEqual(S0ID, 1)) { Return(0xF) } // CS enabled in SETUP? + Return(0x0) + } + + } // Device (SDMA) + + + //---------------------------- + // Serial IO I2C0 Controller + //---------------------------- + Device (I2C0) + { + Name (_HID, "INT33C2") + Name (_CID, "INT33C2") + Name (_UID, 1) + Name (_ADR, 0x00150001) + + Method(_DEP){ + ADBG("I2C0 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("I2C0 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("I2C0 DEP NULL") + Return(Package() {}) + } + } + + Method (SSCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 432, 507, 9 }) + Store(SSH0, Index(PKG,0)) + Store(SSL0, Index(PKG,1)) + Store(SSD0, Index(PKG,2)) + Return (PKG) + } + Method (FMCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 72, 160, 9 }) + Store(FMH0, Index(PKG,0)) + Store(FML0, Index(PKG,1)) + Store(FMD0, Index(PKG,2)) + Return (PKG) + } + Method (FPCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 26, 50, 5 }) + Store(FPH0, Index(PKG,0)) + Store(FPL0, Index(PKG,1)) + Store(FPD0, Index(PKG,2)) + Return (PKG) + } + Method (M0D3, 0x0, Notserialized) + { + Name (PKG, Package(1) { 200 }) + Store(M0C0, Index(PKG,0)) + Return (PKG) + } + Method (M1D3, 0x0, Notserialized) + { + Name (PKG, Package(1) { 2000 }) + Store(M1C0, Index(PKG,0)) + Return (PKG) + } + Method (M0D0, 0x0, Notserialized) + { + Name (PKG, Package(1) { 0 }) + Store(M2C0, Index(PKG,0)) + Return (PKG) + } + + Name (RBUF, ResourceTemplate () + { + // + // Resource settings will be overwritten after PCI enumeration + // + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {21} + }) + + Method (_CRS, 0x0, NotSerialized) + { + Name (DBUF, ResourceTemplate () + { + // + // Provide Serial IO DMA channels used by the I2C0 controller + // + FixedDMA(0x18, 4, Width32Bit, DMA1) //Tx + FixedDMA(0x19, 5, Width32Bit, DMA2) //Rx + }) + If(LNotEqual(\_SB_.PCI0.SDMA._STA, 0x0)) { + Return (ConcatenateResTemplate(RBUF, DBUF)) + } Else { + Return (RBUF) + } + } + + Method (_HRV) + { + // + // Report LPC Revision Id + // + Return (CRID) + } + + CreateDWordField(RBUF,BAR0._BAS,BVAL) + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(BVAL, 0)) { Return(0x0) } // has BAR for this device been programmed by the OS? + If(LLess(OSYS,2012)) { Return(0x0) } // Win 8 or above? + If(LEqual(S0ID, 1)) { Return(0xF) } // CS enabled in SETUP? + Return(0x0) + } + + // D0 Method for I2C0 + Method(_PS0,0,Serialized) + { + ADBG("I2C0 Ctrlr D0") + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(2), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(2),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + And(TEMP, 0xFFFFFFFC, TEMP) + Store(TEMP, Local0) + } + If(CondRefOf(\_SB.PCI0.I2C0.PS0X)) + { + \_SB.PCI0.I2C0.PS0X() + } + } + + // D3 Method for I2C0 + Method(_PS3,0,Serialized) + { + ADBG("I2C0 Ctrlr D3") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(2), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(2),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + Or(TEMP, 0x3, TEMP) + Store(TEMP, Local0) + } + If(CondRefOf(\_SB.PCI0.I2C0.PS3X)) + { + \_SB.PCI0.I2C0.PS3X() + } + + } + + } // Device (I2C0) + + //---------------------------- + // Serial IO I2C1 Controller + //---------------------------- + Device (I2C1) + { + Name (_HID, "INT33C3") + Name (_CID, "INT33C3") + Name (_UID, 2) + Name (_ADR, 0x00150002) + + Method(_DEP){ + ADBG("I2C1 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("I2C1 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("I2C1 DEP NULL") + Return(Package() {}) + } + } + + Method (SSCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 432, 507, 9 }) + Store(SSH1, Index(PKG,0)) + Store(SSL1, Index(PKG,1)) + Store(SSD1, Index(PKG,2)) + Return (PKG) + } + Method (FMCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 72, 160, 9 }) + Store(FMH1, Index(PKG,0)) + Store(FML1, Index(PKG,1)) + Store(FMD1, Index(PKG,2)) + Return (PKG) + } + Method (FPCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 26, 50, 5 }) + Store(FPH1, Index(PKG,0)) + Store(FPL1, Index(PKG,1)) + Store(FPD1, Index(PKG,2)) + Return (PKG) + } + Method (M0D3, 0x0, Notserialized) + { + Name (PKG, Package(1) { 200 }) + Store(M0C1, Index(PKG,0)) + Return (PKG) + } + Method (M1D3, 0x0, Notserialized) + { + Name (PKG, Package(1) { 2000 }) + Store(M1C1, Index(PKG,0)) + Return (PKG) + } + Method (M0D0, 0x0, Notserialized) + { + Name (PKG, Package(1) { 0 }) + Store(M2C1, Index(PKG,0)) + Return (PKG) + } + + Name (RBUF, ResourceTemplate () + { + // + // Resource settings will be overwritten after PCI enumeration + // + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {21} + }) + + Method (_CRS, 0x0, NotSerialized) + { + Name (DBUF, ResourceTemplate () + { + FixedDMA(0x1A, 6, Width32Bit, DMA1) //Tx + FixedDMA(0x1B, 7, Width32Bit, DMA2) //Rx + }) + + If(LNotEqual(\_SB_.PCI0.SDMA._STA, 0x0)) { + Return (ConcatenateResTemplate(RBUF, DBUF)) + } Else { + Return (RBUF) + } + } + + Method (_HRV) + { + // + // Report LPC Revision Id + // + Return (CRID) + } + + CreateDWordField(RBUF,BAR0._BAS,BVAL) + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(BVAL, 0)) { Return(0x0) } // has BAR for this device been programmed by the OS? + If(LLess(OSYS,2012)) { Return(0x0) } // Win 8 or above? + If(LEqual(S0ID, 1)) { Return(0xF) } // CS enabled in SETUP? + Return(0x0) + } + + // D0 Method for I2C1 + Method(_PS0,0,Serialized) + { + ADBG("I2C1 Ctrlr D0") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(3), 0)) { + If(CondRefOf(\_SB.PCI0.I2C1.PS0X)) + { + \_SB.PCI0.I2C1.PS0X() + } + Add(\_SB.PCI0.SIRC.CNTR(3),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + And(TEMP, 0xFFFFFFFC, TEMP) + Store(TEMP, Local0) + } + } + + // D3 Method for I2C1 + Method(_PS3,0,Serialized) + { + ADBG("I2C1 Ctrlr D3") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(3), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(3),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + Or(TEMP, 0x3, TEMP) + Store(TEMP, Local0) + } + } + } // Device (I2C1) + + //---------------------------- + // Serial IO SPI0 Controller + //---------------------------- + Device (SPI0) + { + Name (_HID, "INT33C0") + Name (_CID, "INT33C0") + Name (_UID, 1) + Name (_ADR, 0x00150003) + + Method (M0D3, 0x0, Notserialized) + { + Name (PKG, Package(1) { 200 }) + Store(M0C2, Index(PKG,0)) + Return (PKG) + } + Method (M1D3, 0x0, Notserialized) + { + Name (PKG, Package(1) { 2000 }) + Store(M1C2, Index(PKG,0)) + Return (PKG) + } + + Name (RBUF, ResourceTemplate () + { + // + // Resource settings will be overwritten after PCI enumeration + // + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {21} + }) + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + + Method (_HRV) + { + // + // Report LPC Revision Id + // + Return (CRID) + } + + CreateDWordField(RBUF,BAR0._BAS,BVAL) + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(BVAL, 0)) { Return(0x0) } // has BAR for this device been programmed by the OS? + If(LLess(OSYS,2012)) { Return(0x0) } // Win 8 or above? + If(LEqual(S0ID, 1)) { Return(0xF) } // CS enabled in SETUP? + Return(0x0) + + } + + // D0 Method for SPI0 + Method(_PS0,0,Serialized) + { + ADBG("SPI0 Ctrlr D0") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(4), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(4),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + And(TEMP, 0xFFFFFFFC, TEMP) + Store(TEMP, Local0) + } + } + + // D3 Method for SPI0 + Method(_PS3,0,Serialized) + { + ADBG("SPI0 Ctrlr D3") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(4), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(4),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + Or(TEMP, 0x3, TEMP) + Store(TEMP, Local0) + } + } + } // Device (SPI0) + + //---------------------------- + // Serial IO SPI1 Controller + //---------------------------- + Device (SPI1) + { + Name (_HID, "INT33C1") + Name (_CID, "INT33C1") + Name (_UID, 2) + Name (_ADR, 0x00150004) + + + Method (M0D3, 0x0, Notserialized) + { + Name (PKG, Package(1) { 200 }) + Store(M0C3, Index(PKG,0)) + Return (PKG) + } + Method (M1D3, 0x0, Notserialized) + { + Name (PKG, Package(1) { 2000 }) + Store(M1C3, Index(PKG,0)) + Return (PKG) + } + + Name (RBUF, ResourceTemplate () + { + // + // Resource settings will be overwritten after PCI enumeration + // + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {21} + }) + + Method (_CRS, 0x0, NotSerialized) + { + Name (DBUF, ResourceTemplate () + { + FixedDMA(0x10, 0, Width32Bit, DMA1) //Tx + FixedDMA(0x11, 1, Width32Bit, DMA2) //Rx + }) + + If(LNotEqual(\_SB_.PCI0.SDMA._STA, 0x0)) { + Return (ConcatenateResTemplate(RBUF, DBUF)) + } Else { + Return (RBUF) + } + } + + Method (_HRV) + { + // + // Report LPC Revision Id + // + Return (CRID) + } + + CreateDWordField(RBUF,BAR0._BAS,BVAL) + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(BVAL, 0)) { Return(0x0) } // has BAR for this device been programmed by the OS? + If(LLess(OSYS,2012)) { Return(0x0) } // Win 8 or above? + If(LEqual(S0ID, 1)) { Return(0xF) } // CS enabled in SETUP? + Return(0x0) + } + + // D0 Method for SPI1 + Method(_PS0,0,Serialized) + { + ADBG("SPI1 Ctrlr D0") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(5), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(5),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + And(TEMP, 0xFFFFFFFC, TEMP) + Store(TEMP, Local0) + } + } + + // D3 Method for SPI1 + Method(_PS3,0,Serialized) + { + ADBG("SPI1 Ctrlr D3") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(5), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(5),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + Or(TEMP, 0x3, TEMP) + Store(TEMP, Local0) + } + } + } // Device (SPI1) + + //----------------------------- + // Serial IO UART0 Controller + //----------------------------- + Device (UA00) + { + Name (_HID, "INT33C4") + Name (_CID, "INT33C4") + Name (_UID, 1) + Name (_ADR, 0x00150005) + + Method(_DEP){ + ADBG("UA00 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("UA00 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("UA00 DEP NULL") + Return(Package() {}) + } + } + + Method (M0D3, 0x0, Notserialized) + { + Name (PKG, Package(1) { 200 }) + Store(M0C4, Index(PKG,0)) + Return (PKG) + } + Method (M1D3, 0x0, Notserialized) + { + Name (PKG, Package(1) { 200 }) + Store(M1C4, Index(PKG,0)) + Return (PKG) + } + + Name (RBUF, ResourceTemplate () + { + // + // Resource settings will be overwritten after PCI enumeration + // + Memory32Fixed (ReadWrite, 0x00000000, 0x0001000, BAR0) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {21} + }) + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + + Method (_HRV) + { + // + // Report LPC Revision Id + // + Return (CRID) + } + + CreateDWordField(RBUF,BAR0._BAS,BVAL) + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(BVAL, 0)) { Return(0x0) } // has BAR for this device been programmed by the OS? + If(LLess(OSYS,2012)) { Return(0x0) } // Win 8 or above? + If(LEqual(S0ID, 1)) { Return(0xF) } // CS enabled in SETUP? + Return(0x0) + } + + // D0 Method for UAR0 + Method(_PS0,0,Serialized) + { + ADBG("UAR0 Ctrlr D0") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(6), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(6),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + And(TEMP, 0xFFFFFFFC, TEMP) + Store(TEMP, Local0) + } + } + + // D3 Method for UAR0 + Method(_PS3,0,Serialized) + { + ADBG("UAR0 Ctrlr D3") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(6), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(6),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + Or(TEMP, 0x3, TEMP) + Store(TEMP, Local0) + } + } + + + } // Device (UART0) + + //----------------------------- + // Serial IO UART1 Controller + //----------------------------- + Device (UA01) + { + Name (_HID, "INT33C5") + Name (_CID, "INT33C5") + Name (_UID, 2) + Name (_ADR, 0x00150006) + + Method(_DEP){ + ADBG("UA01 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("UA01 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("UA01 DEP NULL") + Return(Package() {}) + } + } + + Method (M0D3, 0x0, Notserialized) + { + Name (PKG, Package(1) { 200 }) + Store(M0C5, Index(PKG,0)) + Return (PKG) + } + Method (M1D3, 0x0, Notserialized) + { + Name (PKG, Package(1) { 200 }) + Store(M1C5, Index(PKG,0)) + Return (PKG) + } + + Name (RBUF, ResourceTemplate () + { + // + // Resource settings will be overwritten after PCI enumeration + // + Memory32Fixed (ReadWrite, 0x00000000, 0x0001000, BAR0) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {21} + }) + + Method (_CRS, 0x0, NotSerialized) + { + Name (DBUF, ResourceTemplate () + { + FixedDMA(0x16, 2, Width32Bit, DMA1) //Tx + FixedDMA(0x17, 3, Width32Bit, DMA2) //Rx + }) + + If(LNotEqual(\_SB_.PCI0.SDMA._STA, 0x0)) { + Return (ConcatenateResTemplate(RBUF, DBUF)) + } Else { + Return (RBUF) + } + } + + Method (_HRV) + { + // + // Report LPC Revision Id + // + Return (CRID) + } + + CreateDWordField(RBUF,BAR0._BAS,BVAL) + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(BVAL, 0)) { Return(0x0) } // has BAR for this device been programmed by the OS? + If(LLess(OSYS,2012)) { Return(0x0) } // Win 8 or above? + If(LEqual(S0ID, 1)) { Return(0xF) } // CS enabled in SETUP? + Return(0x0) + } + + // D0 Method for UAR1 + Method(_PS0,0,Serialized) + { + ADBG("UAR1 Ctrlr D0") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(7), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(7),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + And(TEMP, 0xFFFFFFFC, TEMP) + Store(TEMP, Local0) + } + } + + // D3 Method for UAR1 + Method(_PS3,0,Serialized) + { + ADBG("UAR1 Ctrlr D3") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(7), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(7),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + Or(TEMP, 0x3, TEMP) + Store(TEMP, Local0) + } + } + } // Device (UART1) + + //-------------------------------- + // Serial IO SDIO Host Controller + //-------------------------------- + Device (SDHC) + { + Name (_HID, "INT33C6") + Name (_CID, "PNP0D40") + Name (_UID, 1) + Name (_ADR, 0x00170000) + + Method(_DEP){ + ADBG("SDHC DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("SDHC DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("SDHC DEP NULL") + Return(Package() {}) + } + } + + Name (RBUF, ResourceTemplate () + { + // + // Resource settings will be overwritten after PCI enumeration + // + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BARA) // BAR0 Range + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {22} + }) + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + + CreateDWordField(RBUF,BARA._BAS,BVAL) + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(BVAL, 0)) { Return(0x0) } // has BAR for this device been programmed by the OS? + If(LLess(OSYS,2012)) { Return(0x0) } // Win 8 or above? + If(LEqual(S0ID, 1)) { Return(0xF) } // CS enabled in SETUP? + Return(0x0) + } + + // D0 Method for SDHC + Method(_PS0,0,Serialized) + { + ADBG("SDHC Ctrlr D0") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(8), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(8),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + And(TEMP, 0xFFFFFFFC, TEMP) + Store(TEMP, Local0) + } + + If(CondRefOf(\_SB.PCI0.SDHC.PS0X)) + { + \_SB.PCI0.SDHC.PS0X() + } + } + + // D3 Method for SDHC + Method(_PS3,0,Serialized) + { + ADBG("SDHC Ctrlr D3") + + If(LNotEqual(\_SB.PCI0.SIRC.CNTR(8), 0)) { + Add(\_SB.PCI0.SIRC.CNTR(8),0x84 ,Local0) + OperationRegion(ICB1, SystemMemory, Local0, 4) + Field(ICB1, DWordAcc, NoLock, Preserve) { + Offset(0x0), + TEMP, 32 + } + Or(TEMP, 0x3, TEMP) + Store(TEMP, Local0) + } + } + + } // Device (SDHC) + + } // Scope (\_SB.PCI0) diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchSmb.asl b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchSmb.asl new file mode 100644 index 0000000..6356e3c --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchSmb.asl @@ -0,0 +1,605 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2011 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + + +// Define various SMBus PCI Configuration Space Registers. + +OperationRegion(SMBP,PCI_Config,0x40,0xC0) +Field(SMBP,DWordAcc,NoLock,Preserve) +{ + , 2, + I2CE, 1 +} + +OperationRegion(SMPB,PCI_Config,0x20,4) +Field(SMPB,DWordAcc,NoLock,Preserve) +{ + , 5, + SBAR, 11 +} + +// Define various SMBus IO Mapped Registers. + +OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) +Field(SMBI,ByteAcc,NoLock,Preserve) +{ + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data +} + +// SMBus Send Byte - This function will write a single byte of +// data to a specific Slave Device per SMBus Send Byte Protocol. +// Arg0 = Address +// Arg1 = Data +// Return: Success = 1 +// Failure = 0 + +Method(SSXB,2,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform + // communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Send Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Data in HCOM. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 001 = Byte Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x48,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(1) // Return Success. + } + + Return(0) +} + +// SMBus Receive Byte - This function will write a single byte +// of data to a specific Slave Device per SMBus Receive Byte +// Protocol. +// Arg0 = Address +// Return: Success = Byte-Size Value +// Failure = Word-Size Value = FFFFh. + +Method(SRXB,1,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform + // communication. + + If(STRT()) + { + Return(0xFFFF) + } + + // Step 2: Initiate a Receive Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 001 = Byte Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x44,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(DAT0) // Return Success. + } + + Return(0xFFFF) // Return Failure. +} + +// SMBus Write Byte - This function will write a single byte +// of data to a specific Slave Device per SMBus Write Byte +// Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = Data +// Return: Success = 1 +// Failure = 0 + +Method(SWRB,3,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Write Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + Store(Arg2,DAT0) // Data in DAT0. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 010 = Byte Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x48,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(1) // Return Success. + } + + Return(0) // Return Failure. +} + +// SMBus Read Byte - This function will read a single byte of data +// from a specific slave device per SMBus Read Byte Protocol. +// Arg0 = Address +// Arg1 = Command +// Return: Success = Byte-Size Value +// Failure = Word-Size Value + +Method(SRDB,2,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0xFFFF) + } + + // Step 2: Initiate a Read Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 010 = Byte Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x48,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(DAT0) // Return Success. + } + + Return(0xFFFF) // Return Failure. +} + +// SMBus Write Word - This function will write a single word +// of data to a specific Slave Device per SMBus Write Word +// Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = Data (16 bits in size) +// Return: Success = 1 +// Failure = 0 + +Method(SWRW,3,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Write Word. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + And(Arg2,0xFF,DAT1) // Low byte Data in DAT1. + And(ShiftRight(Arg2,8),0xFF,DAT0) // High byte Data in DAT0. + + // Set the SMBus Host control register to 0x4C. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 011 = Word Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x4C,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP()) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others. + Return(1) // Return Success. + } + + Return(0) // Return Failure. +} + +// SMBus Read Word - This function will read a single byte of data +// from a specific slave device per SMBus Read Word Protocol. +// Arg0 = Address +// Arg1 = Command +// Return: Success = Word-Size Value +// Failure = Dword-Size Value + +Method(SRDW,2,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0xFFFF) + } + + // Step 2: Initiate a Read Word. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + + // Set the SMBus Host control register to 0x4C. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 011 = Word Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x4C,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP()) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others. + Return(Or(ShiftLeft(DAT0,8),DAT1)) // Return Success. + } + + Return(0xFFFFFFFF) // Return Failure. +} + +// SMBus Block Write - This function will write an entire block of data +// to a specific slave device per SMBus Block Write Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = Buffer of Data to Write +// Arg3 = 1 = I2C Block Write, 0 = SMBus Block Write +// Return: Success = 1 +// Failure = 0 + +Method(SBLW,4,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Block Write. + + Store(Arg3,I2CE) // Select the proper protocol. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + Store(Sizeof(Arg2),DAT0) // Count in DAT0. + Store(0,Local1) // Init Pointer to Buffer. + Store(DerefOf(Index(Arg2,0)),HBDR) // First Byte in HBD Register. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 101 = Block Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x54,HCON) + + // Step 3: Send the entire Block of Data. + + While(LGreater(Sizeof(Arg2),Local1)) + { + // Wait up to 200ms for Host Status to get set. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(LAnd(LNot(And(HSTS,0x80)),Local0)) + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + } + + If(LNot(Local0)) // Timeout? + { + KILL() // Yes. Kill Communication. + Return(0) // Return failure. + } + + Store(0x80,HSTS) // Clear Host Status. + Increment(Local1) // Point to Next Byte. + + // Place next byte in HBDR if last byte has not been sent. + + If(LGreater(Sizeof(Arg2),Local1)) + { + Store(DerefOf(Index(Arg2,Local1)),HBDR) + } + } + + // Step 4: Exit the Method correctly. + + If(COMP()) + { + Or(HSTS,0xFF,HSTS) // Clear all status bits. + Return(1) // Return Success. + } + + Return(0) // Return Failure. +} + +// SMBus Block Read - This function will read a block of data from +// a specific slave device per SMBus Block Read Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = 1 = I2C Block Write, 0 = SMBus Block Write +// Return: Success = Data Buffer (First Byte = length) +// Failure = 0 + +Method(SBLR,3,Serialized) +{ + Name(TBUF, Buffer(256) {}) + + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Block Read. + + Store(Arg2,I2CE) // Select the proper protocol. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 101 = Block Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x54,HCON) + + // Step 3: Wait up to 200ms to get the Data Count. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(LAnd(LNot(And(HSTS,0x80)),Local0)) + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + } + + If(LNot(Local0)) // Timeout? + { + KILL() // Yes. Kill Communication. + Return(0) // Return failure. + } + + Store(DAT0,Index(TBUF,0)) // Get the Data Count. + Store(0x80,HSTS) // Clear Host Status. + Store(1,Local1) // Local1 = Buffer Pointer. + + // Step 4: Get the Block Data and store it. + + While(LLess(Local1,DerefOf(Index(TBUF,0)))) + { + // Wait up to 200ms for Host Status to get set. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(LAnd(LNot(And(HSTS,0x80)),Local0)) + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + } + + If(LNot(Local0)) // Timeout? + { + KILL() // Yes. Kill Communication. + Return(0) // Return failure. + } + + Store(HBDR,Index(TBUF,Local1)) // Place into Buffer. + Store(0x80,HSTS) // Clear Host Status. + Increment(Local1) + } + + // Step 5: Exit the Method correctly. + + If(COMP()) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others. + Return(TBUF) // Return Success. + } + + Return(0) // Return Failure. +} + + +// SMBus Start Check +// Return: Success = 0 +// Failure = 1 + +Method(STRT,0,Serialized) +{ + // Wait up to 200ms to confirm the SMBus Semaphore has been + // released (In Use Status = 0). Note that the Sleep time may take + // longer as the This function will yield the Processor such that it + // may perform different tasks during the delay. + + Store(200,Local0) // 200 * 1ms = 200ms. + + While(Local0) + { + If(And(HSTS,0x40)) // In Use Set? + { + Decrement(Local0) // Yes. Decrement Count. + Sleep(1) // Delay = 1ms. + If(LEqual(Local0,0)) // Count = 0? + { + Return(1) // Return failure. + } + } + Else + { + Store(0,Local0) // In Use Clear. Continue. + } + } + + // In Use Status = 0 during last read, which will make subsequent + // reads return In Use Status = 1 until software clears it. All + // software using ICHx SMBus should check this bit before initiating + // any SMBus communication. + + // Wait up to 200ms to confirm the Host Interface is + // not processing a command. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(Local0) + { + If(And(HSTS,0x01)) // Host Busy Set? + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + If(LEqual(Local0,0)) // Count = 0? + { + KILL() // Yes. Kill Communication. + } + } + Else + { + Return(0) + } + } + + Return(1) // Timeout. Return failure. +} + +// SMBus Completion Check +// Return: Success = 1 +// Failure = 0 + +Method(COMP,0,Serialized) +{ + // Wait for up to 200ms for the Completion Command + // Status to get set. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(Local0) + { + If(And(HSTS,0x02)) // Completion Status Set? + { + Return(1) // Yes. We are done. + } + Else + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay 50us. + If(LEqual(Local0,0)) // Count = 0? + { + KILL() // Yes. Kill Communication. + } + } + } + + Return(0) // Timeout. Return Failure. +} + +// SMBus Kill Command + +Method(KILL,0,Serialized) +{ + Or(HCON,0x02,HCON) // Yes. Send Kill command. + Or(HSTS,0xFF,HSTS) // Clear all status. +} diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchXhci.asl b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchXhci.asl new file mode 100644 index 0000000..634e088 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/PchXhci.asl @@ -0,0 +1,1229 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2010 - 2014 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + + Method(_DEP){ + If(LEqual(S0ID, 1)){ + Return(Package() {\_SB.PEPD}) + }Else{ + Return(Package() {}) + } + } + + OperationRegion(XPRT,PCI_Config,0x00,0x100) + Field(XPRT,AnyAcc,NoLock,Preserve) + { + DVID, 16, + Offset(0x40), + , 11, + SWAI, 1, // 0x40 BIT[11] + , 20, + Offset(0x44), + , 12, + SAIP, 2, // 0x44 BIT[13:12] + , 18, + Offset(0x74), + D0D3, 2, // 0x74 BIT[1:0] + , 6, + PMEE, 1, // PME Enable + , 6, + PMES, 1, // PME Status + Offset(0xB0), // SSCFG Reg for LPTLP + , 13, + MB13, 1, // 0xB0 BIT[13] + MB14, 1, // 0xB0 BIT[14] + , 17, + Offset(0xD0), + PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register. + PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register. + PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register. + PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register + } + + OperationRegion(XHCP, SystemMemory, Add(PEBS, 0xA0000), 0x100) + Field(XHCP,AnyAcc,Lock,Preserve) + { + Offset(0x4), + PDBM, 16, + Offset(0x10), + MEMB, 64 + } + + // + // for each HS port, this method returns its corresponding selection bit in USB2PR register + // + Method(PR2S,1,Serialized) { + + If(LEqual(And(CDID,0xF000), 0x8000)) { // LPT-H + Switch(Arg0) { + Case( 1) {return (0x0001)} + Case( 2) {return (0x0002)} + Case( 3) {return (0x0004)} + Case( 4) {return (0x0008)} + Case( 5) {return (0x0100)} + Case( 6) {return (0x0200)} + Case( 7) {return (0x0400)} + Case( 8) {return (0x0800)} + Case( 9) {return (0x0010)} + Case(10) {return (0x0020)} + Case(11) {return (0x1000)} + Case(12) {return (0x2000)} + Case(13) {return (0x0040)} + Case(14) {return (0x0080)} + Case(15) {return (0x4000)} + } + } else { // LPT-LP + Switch(Arg0) { + Case( 1) {return (0x0001)} + Case( 2) {return (0x0002)} + Case( 3) {return (0x0004)} + Case( 4) {return (0x0008)} + Case( 5) {return (0x0010)} + Case( 6) {return (0x0020)} + Case( 7) {return (0x0040)} + Case( 8) {return (0x0080)} + Case( 9) {return (0x0100)} + } + } + } + + Name(XRST, Zero) + // + // Workaround for XHCI + // + // At D3 exit (AKA PS_ON) + // For LPT-LP + // Clear PCI CFG offset 0xB0[14:13] + // Clear MMIO Offset 0x816C[14] + // Clear MMIO Offset 0x816C[2] + // For LPT-H, LPT-LP + // Set MMIO Offset 8154[31] + // For LPT-LP + // Wait until all SS ports are out of polling + // For each SS port which is disconnected (i.e. PORTS.PLS=5h) and CSC=0 + // Issue Warm Port Reset + // Wait 101ms + // Write '1' to all Port Change Status bits if reset + // Set MMIO Offset 0x80E0[15] + // For LPT-H, LPT-LP + // Clear XHCI CFG REG 0x40[11] + // Clear XHCI CFG REG 0x44[13:12] + // + // Prior to D3 entry (AKA PS_OFF) + // For LPT-LP + // Set PCI CFG offset 0xB0[14:13] + // Set MMIO Offset 0x816C[14] + // Set MMIO Offset 0x816C[2] + // For LPT-H, LPT-LP + // Clear MMIO Offset 8154[31] + // For LPT-LP + // Clear MMIO Offset 0x80E0[15] + // For LPT-H, LPT-LP + // Set XHCI CFG REG 0x40[11] + // Set XHCI CFG REG 0x44[13:12] = '01' + // + External(\_SB.PCI0.XHC.PS0X, MethodObj) + External(\_SB.PCI0.XHC.PS3X, MethodObj) + // + // D0 Method for xHCI Host Controller + // + Method(_PS0,0,Serialized) + { + // Uses: + // Local0 - Temporary + // Local1 - Original command register + // Local2 - Original MBAR + // Local4 - Port reset mask + // + If(LEqual(^DVID,0xFFFF)) + { + Return() + } + + // + // MBAR Programming + // + Store(^MEMB,Local2) // Save MBAR + Store(^PDBM,Local1) // Save CMD + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME + + // + // Switch to D0 + // + Store(^D0D3,Local3) + Store(0,^D0D3) + + Store(\SRMB,^MEMB) // Set MBAR + Or(Local1,0x0002,^PDBM) // Set MSE + + OperationRegion(MCA1,SystemMemory,\SRMB,0x9000) + Field(MCA1,DWordAcc,Lock,Preserve) + { + Offset(0x510), + PSC1, 32, + Offset(0x520), + PSC2, 32, + Offset(0x530), + PSC3, 32, + Offset(0x540), + PSC4, 32, + Offset(0x80E0), // AUX Reset Control 1 + , 15, + AX15, 1, + Offset(0x8154), // AUX Domain PM control register 2 + , 31, + CLK2, 1, // [31] + Offset(0x816C), // AUXCLKCTL + , 2, + CLK0, 1, // [2] + , 11, + CLK1, 1, // [14] - USB3 Port Aux/Core clock gating enable + } + + If(LEqual(PCHS, 2)) // LPT-LP + { + // + // Clear PCI CFG offset 0xB0[14:13] + // + Store(0,^MB13) + Store(0,^MB14) + // + // Clear MMIO Offset 0x816C[14] + // Clear MMIO Offset 0x816C[2] + // + Store(0,CLK0) + Store(0,CLK1) + } + + // + // Set MMIO Offset 8154[31] for both LPT-LP and LPT-H + // + Store(1,CLK2) + + If(LEqual(PCHS, 2)) // LPT-LP + { + // + // Wait until all ports are out of polling (PP=1, PLS=7) + // + while(LOr(LOr(LEqual(And(PSC1,0x3F8),0x2E0), + LEqual(And(PSC2,0x3F8),0x2E0)), + LOr(LEqual(And(PSC3,0x3F8),0x2E0), + LEqual(And(PSC4,0x3F8),0x2E0)))) + { + Stall(10) + } + + // + // Bitmask of SS ports for which warm reset was performed + // + Store(0, Local4) + + // + // For each SS port which is disconnected (i.e. PORTS.PLS=5h) and CSC=0 + // Issue Warm Port Reset + // + And(PSC1,Not(0x02),Local0) // Mask PED + If(LEqual(And(Local0,0x203F9),0x2A0)) // If SS PSC1 PP=1, PLS=5, CSC=0 + { + Or(Local0,0x80000000,PSC1) // Set WPR and clear change flags + Or(Local4,0x1,Local4) + } + And(PSC2,Not(0x02),Local0) // Mask PED + If(LEqual(And(Local0,0x203F9),0x2A0)) // If SS PSC2 PP=1, PLS=5, CSC=0 + { + Or(Local0,0x80000000,PSC2) // Set WPR and clear change flags + Or(Local4,0x2,Local4) + } + And(PSC3,Not(0x02),Local0) // Mask PED + If(LEqual(And(Local0,0x203F9),0x2A0)) // If SS PSC3 PP=1, PLS=5, CSC=0 + { + Or(Local0,0x80000000,PSC3) // Set WPR and clear change flags + Or(Local4,0x4,Local4) + } + And(PSC4,Not(0x02),Local0) // Mask PED + If(LEqual(And(Local0,0x203F9),0x2A0)) // If SS PSC4 PP=1, PLS=5, CSC=0 + { + Or(Local0,0x80000000,PSC4) // Set WPR and clear change flags + Or(Local4,0x8,Local4) + } + // + // Wait 101ms + // Write '1' to all Port Change Status bits if reset + // + If (Local4) + { + Sleep(101) + + If (And(Local4,0x1)) + { + And(PSC1,Not(0x02),Local0) // Mask PED + Or(Local0, 0x00FE0000,PSC1) // Clear SS PSC1 Bit 23:17 + } + If (And(Local4,0x2)) + { + And(PSC2,Not(0x02),Local0) // Mask PED + Or(Local0,0x00FE0000,PSC2) // Clear SS PSC2 Bit 23:17 + } + If (And(Local4,0x4)) + { + And(PSC3,Not(0x02),Local0) // Mask PED + Or(Local0,0x00FE0000,PSC3) // Clear SS PSC3 Bit 23:17 + } + If (And(Local4,0x8)) + { + And(PSC4,Not(0x02),Local0) // Mask PED + Or(Local0,0x00FE0000,PSC4) // Clear SS PSC4 Bit 23:17 + } + } + + // + // Set MMIO Offset 0x80E0[15] + // + Store(1,AX15) //0x80E0 - BIT15, AUX Reset Control 1 + } + + // + // Clear PCI CFG offset 0x40[11] for both LPT-LP and LPT-H + // + Store(0,^SWAI) + // + // Clear PCI CFG offset 0x44[13:12] for both LPT-LP and LPT-H + // + Store(0,^SAIP) + + // + // Call platform XHC PS0 method if present + // + If(CondRefOf(\_SB.PCI0.XHC.PS0X)) + { + \_SB.PCI0.XHC.PS0X() + } + + // + // Leave device in D0 to avoid spurious PME event upon D3 entry + // + + // + // Restoring MBAR + // + And(^PDBM,Not(0x02),^PDBM) // Clear MSE + Store(Local2,^MEMB) // Restore MBAR + Store(Local1,^PDBM) // Restore CMD + } + + // + // D3 Method for xHCI Host Controller + // + Method(_PS3,0,Serialized) + { + // Uses: + // Local0 - Temporary + // Local1 - Original command register + // Local2 - Original MBAR + // Local3 - D0D3 temporary + // + If(LEqual(^DVID,0xFFFF)) + { + Return() + } + Store(1, ^PMES) //Clear PME status + Store(1, ^PMEE) //Enable PME + + + // + // MBAR Programming + // + Store(^MEMB,Local2) // Save MBAR + Store(^PDBM,Local1) // Save CMD + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME + Store(\SRMB,^MEMB) // Set MBAR + Or(^PDBM,0x02,^PDBM) // Set MSE + + OperationRegion(MCA1,SystemMemory,\SRMB,0x9000) + Field(MCA1,DWordAcc,Lock,Preserve) + { + Offset(0x80E0), // AUX Reset Control 1 + , 15, + AX15, 1, + Offset(0x8154), // AUX Domain PM control register 2 + , 31, + CLK2, 1, // BIT31 + Offset(0x816C), // 40.2.3.6.6040.2.3.6.59 AUXCLKCTL + , 2, + CLK0, 1, // BIT2 + , 11, + CLK1, 1, // BIT14 - USB3 Port Aux/Core clock gating enable + , 17, + } + + // + // If device is in D3, set to back to D0 + // + Store(^D0D3,Local3) + if(LEqual(Local3,3)) + { + Store(0,^D0D3) + } + + If(LEqual(PCHS, 2)) // LPT-LP + { + // + // Set PCI CFG offset 0xB0[14:13] + // + Store(1,^MB13) + Store(1,^MB14) + // + // Set MMIO Offset 0x816C[14] + // Set MMIO Offset 0x816C[2] + // + Store(1,CLK0) + Store(1,CLK1) + } + + // + // Clear MMIO Offset 8154[31] for both LPT-LP and LPT-H + // + Store(0,CLK2) + + If(LEqual(PCHS, 2)) // LPT-LP + { + // + // Clear MMIO Offset 0x80E0[15] + // + Store(0,AX15) //0x80E0 - BIT15 + } + + // + // Set PCI CFG offset 0x40[11] = '1' for both LPT-LP and LPT-H + // + Store(1,^SWAI) + // + // Set PCI CFG offset 0x44[13:12] = '01' for both LPT-LP and LPT-H + // + Store(1,^SAIP) + + // + // Call platform XHC PS3 method if existed. + // in the PS3X, MBAR is ready, CMD is ready, and Device is in D0. + // + If(CondRefOf(\_SB.PCI0.XHC.PS3X)) + { + \_SB.PCI0.XHC.PS3X() + } + + // + // Restoring device back to D3 + // + if(LEqual(Local3,3)) + { + Store(3,^D0D3) + } + // + // Restoring MBAR + // + And(^PDBM,Not(0x02),^PDBM) // Clear MSE + Store(Local2,^MEMB) // Restore MBAR + Store(Local1,^PDBM) // Restore CMD + } + + // + // + // Check for XHCI switch UUID + // + // Arguments: + // Arg0 (Buffer) : UUID + // + // Returns: + // 1: It's valid UUID + // 0: Invalid UUID + // + Method(CUID,1,Serialized) { + If(LEqual(Arg0,ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) { + Return(1) + } + Return(0) + } + + // + // _OSC for xHCI + // This method enables XHCI controller if available. + // + // Arguments: + // Arg0 (Integer): Revision ID - should be set to 1 + // Arg1 (Integer): Count + // Arg2 (Buffer) : Capabilities Buffer + // DWORD#1 (Status/Error): + // Bit 0 - Query Support Flag + // Bit 1 - Always clear(0) + // Bit 2 - Always clear(0) + // Bit 3 - Always clear(0) + // All others - reserved (return 0) + // + // DWORD#3 (Controlled): + // Bit 0 - If set OS request routing back to EHCI + // All others - reserved (return 0) + // Returns: + // Capabilities Buffer: + // DWORD#1 (Status): + // Bit 0 - Reserved (not used) + // Bit 1 - _OSC failure. Platform Firmware was unable to process the request or query. + // Capabilities bits may have been masked. + // Bit 2 - Unrecognized UUID. This bit is set to indicate that the platform firmware does not + // recognize the UUID passed in _OSC Arg0. + // Capabilities bits are preserved. + // Bit 3 - Unrecognized Revision. This bit is set to indicate that the platform firmware does not + // recognize the Revision ID passed in via Arg1. + // Capabilities bits beyond those comprehended by the firmware will be masked. + // Bit 4 - Capabilities Masked. This bit is set to indicate + // that capabilities bits set by driver software + // have been cleared by platform firmware. + // All others - reserved (return 0) + // + Method(POSC,3,Serialized) { + // + // Create DWord field from the Capabilities Buffer + // + CreateDWordField(Arg2,0,CDW1) + CreateDWordField(Arg2,8,CDW3) + + // + // Set failure if xHCI is disabled by BIOS + // + If (LEqual(XHCI, 0)) { + Or(CDW1,0x2,CDW1) + } + + // + // Query flag clear + // + If(LNot(And(CDW1,0x1))) { + If (And(CDW3,0x1)) { + // + // Perform switch back to EHCI + // + ESEL() + } + Else { + If (LEqual(And(CDID,0xF000), 0x8000)) { // if LPT-H chipset + If (LGreater(Arg0, 0x1)) { + // + // Perform switch to xHCI + // + XSEL() + } Else { + // + // Set failure if revision is not supported + // + Or(CDW1,0xA,CDW1) + } + } Else { // if LPT-LP chipset + If (LGreater(Arg0, 0x2)) { + // + // Perform switch to xHCI + // + XSEL() + } Else { + // + // Set failure if revision is not supported + // + Or(CDW1,0xA,CDW1) + } + } + } + } + + Return(Arg2) + } + + Method(XSEL, 0, Serialized) + { + // + // xHCI in auto or smart auto mode + // + If (LOr(LEqual(XHCI,2), LEqual(XHCI,3))) { + // + // Set B0:D31:F0 ACh[16] to indicate begin of Driver phase of USB port routing + // + Store(1, XUSB) + Store(1, XRST) // Backup XUSB, cause it might lost in iRST G3 or DeepSx + // + // Enable selected SS ports, route corresponding HS ports to xHCI + // + Store(0, Local0) + And(PR3, 0xFFFFFFC0, Local0) + Or(Local0, PR3M, PR3) + Store(0, Local0) + And(PR2, 0xFFFF8000, Local0) + Or(Local0, PR2M, PR2) + } + } + + Method(ESEL, 0, Serialized) + { + // + // xHCI in auto or smart auto mode + // + If (LOr(LEqual(XHCI,2), LEqual(XHCI,3))) { + // + // Disable all SS ports, route all HS ports to EHCI + // + And(PR3, 0xFFFFFFC0, PR3) + And(PR2, 0xFFFF8000, PR2) + + // + // Mark as not routed. + // + Store(0, XUSB) + Store(0, XRST) + } + } + + Method(XWAK, 0, Serialized) + { + // + // Ports were routed to xHCI before sleep + // + If (LOr(LEqual(XUSB,1), LEqual(XRST,1))) { + // + // Restore back to xHCI + // + XSEL() + } + } + + Method(_S3D, 0, NotSerialized) + { + Return(0x02) + } + + Method(_S4D, 0, NotSerialized) + { + Return(0x02) + } + + Device(RHUB) + { + Name(_ADR, Zero) + + // + // High Speed Ports + // + Device(HS01) + { + Name(_ADR, 0x01) + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS01_UPC }) //AMI_OVERRITE, Set token for OEM easy to modify. + + If(LNot(And(PR2S(1), PR2))) { + Store(0x00,Index(UPCP,0)) + } + + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS01_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(1), PR2))) { + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(HS02) + { + Name(_ADR, 0x02) + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS02_UPC }) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(2), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS02_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(2), PR2))) { + And(VIS,0,VIS) + } + + Return (PLDP) + } + } + + Device(HS03) + { + Name(_ADR, 0x03) + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS03_UPC }) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(3), PR2))) { + Store(0x00,Index(UPCP,0x00)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) { ASL_HS03_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(3), PR2))) { + And(VIS,0,VIS) + } +#if defined ASL_HS03_INTERNAL && ASL_HS03_INTERNAL == 1 //AMI_OVERRITE + If(LEqual(And(CDID,0xF000), 0x9000)) { // on LPT-LP platforms this port is internal + And(VIS,0,VIS) + } +#endif //AMI_OVERRITE + Return (PLDP) + } + } + + Device(HS04) + { + Name(_ADR, 0x04) + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS04_UPC }) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(4), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS04_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(4), PR2))) { + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(HS05) + { + Name(_ADR, 0x05) + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS05_UPC }) // Change Type from "USB 3 Standard-A connector" to "Type 'A' connector". //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(5), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS05_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(5), PR2))) { + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(HS06) + { + Name(_ADR, 0x06) + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS06_UPC }) // Change Type from "USB 3 Standard-A connector" to "Type 'A' connector". //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(6), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS06_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(6), PR2))) { + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(HS07) + { + Name(_ADR, 0x07) + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS07_UPC }) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(7), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS07_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(7), PR2))) { + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(HS08) + { + Name(_ADR, 0x08) + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS08_UPC }) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(8), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS08_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(8), PR2))) { + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(HS09) + { + Name(_ADR, 0x09) + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS09_UPC }) // HS09 is routed to a USB3 A Connector //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(9), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS09_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(9), PR2))) { + And(VIS,0,VIS) + } + If(LEqual(And(CDID,0xF000), 0x9000)) { + And(VIS,0,VIS) // invisible because on LPT-LP HS09 is KVM's USBR port + } + Return (PLDP) + } + } + + Device(HS10) + { + Method(_ADR, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0xA) + } Else { + Return (0xFA) // on LPT-LP, 0xA is assigned to SSP so move this port's address away + } + } + Method(_STA, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0xF) + } Else { + Return (0) // this port doesn't exist on LPT-LP + } + } + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS10_UPC }) // HS10 is routed to a USB3 A Connector //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(10), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS10_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(10), PR2))) { + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(HS11) + { + Method(_ADR, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0xB) + } Else { + Return (0xFB) // on LPT-LP, 0xB is assigned to SSP so move this port's address away + } + } + Method(_STA, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0xF) + } Else { + Return (0) //this port doesn't exist on LPT-LP + } + } + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS11_UPC }) // Proprietary connector (internal header) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(11), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS11_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(11), PR2))) { + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(HS12) + { + Method(_ADR, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0xC) + } Else { + Return (0xFC) // on LPT-LP, 0xC is assigned to SSP so move this port's address away + } + } + Method(_STA, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0xF) + } Else { + Return (0) //this port doesn't exist on LPT-LP + } + } + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS12_UPC }) // Proprietary connector (internal header) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(12), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS12_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(12), PR2))) { + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(HS13) + { + Method(_ADR, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0xD) + } Else { + Return (0xFD) // on LPT-LP, 0xD is assigned to SSP so move this port's address away + } + } + Method(_STA, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0xF) + } Else { + Return (0) //this port doesn't exist on LPT-LP + } + } + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS13_UPC }) // Proprietary connector (internal header) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(13), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS13_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(13), PR2))) { + And(VIS,0,VIS) + } + + Return (PLDP) + } + + } + + Device(HS14) + { + Name(_ADR, 0xE) + Method(_STA, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0xF) + } Else { + Return (0) //this port doesn't exist on LPT-LP + } + } + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS14_UPC }) // Proprietary connector (internal header) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(14), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS14_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(14), PR2))) { + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(HS15) + { + Name(_ADR, 0xF) + Method(_STA, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0xF) + } Else { + Return (0) //this port doesn't exist on LPT-LP + } + } + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_HS15_UPC }) // Not connectable, USBR not enabled in H87 //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR2S(15), PR2))) { + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_HS15_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR2S(15), PR2))) { + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + // + // Super Speed Ports - must match _UPC declarations of the coresponding Full Speed Ports. + // + Device(SSP1) + { + Method(_ADR, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0x10) + } Else { + Return (0xA) + } + } + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_SSP1_UPC }) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR3, ASL_SSP1_PR3))) { //AMI_OVERRITE, Set token for OEM easy to modify. + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_SSP1_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR3, ASL_SSP1_PR3))) { //AMI_OVERRITE, Set token for OEM easy to modify. + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(SSP2) + { + Method(_ADR, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0x11) + } Else { + Return (0xB) + } + } + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_SSP2_UPC }) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR3, ASL_SSP2_PR3))) { //AMI_OVERRITE, Set token for OEM easy to modify. + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_SSP2_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR3, ASL_SSP2_PR3))) { //AMI_OVERRITE, Set token for OEM easy to modify. + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(SSP3) + { + Method(_ADR, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0x12) + } Else { + Return (0xC) + } + } + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_SSP3_UPC }) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR3, ASL_SSP3_PR3))) { //AMI_OVERRITE, Set token for OEM easy to modify. + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_SSP3_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR3, ASL_SSP3_PR3))) { //AMI_OVERRITE, Set token for OEM easy to modify. + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(SSP4) + { + Method(_ADR, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0x13) + } Else { + Return (0xD) + } + } + Name(_STA, 0xF) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_SSP4_UPC }) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR3, ASL_SSP4_PR3))) { //AMI_OVERRITE, Set token for OEM easy to modify. + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_SSP4_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR3, ASL_SSP4_PR3))) { //AMI_OVERRITE, Set token for OEM easy to modify. + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(SSP5) + { + Name(_ADR, 0x14) + Method(_STA, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0xF) + } Else { + Return (0) //this port doesn't exist on LPT-LP + } + } + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_SSP5_UPC }) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR3, ASL_SSP5_PR3))) { //AMI_OVERRITE, Set token for OEM easy to modify. + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_SSP5_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR3, ASL_SSP5_PR3))) { //AMI_OVERRITE, Set token for OEM easy to modify. + And(VIS,0,VIS) + } + Return (PLDP) + } + } + + Device(SSP6) + { + Name(_ADR, 0x15) + Method(_STA, 0, Serialized) { + If(LEqual(And(CDID,0xF000), 0x8000)) { // check for LPT-H chipset + Return (0xF) + } Else { + Return (0) //this port doesn't exist on LPT-LP + } + } + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { ASL_SSP6_UPC }) //AMI_OVERRITE, Set token for OEM easy to modify. + If(LNot(And(PR3, ASL_SSP6_PR3))) { //AMI_OVERRITE, Set token for OEM easy to modify. + Store(0x00,Index(UPCP,0)) + } + Return(UPCP) + } + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10){ ASL_SSP6_PLD } //AMI_OVERRITE, Set token for OEM easy to modify. + }) + CreateBitField(DeRefOf(Index(PLDP,0)),64,VIS) + If(LNot(And(PR3, ASL_SSP6_PR3))) { //AMI_OVERRITE, Set token for OEM easy to modify. + And(VIS,0,VIS) + } + Return (PLDP) + } + } + } + diff --git a/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/UsbSbd.asl b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/UsbSbd.asl new file mode 100644 index 0000000..12bcbbf --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/AcpiTables/Dsdt/UsbSbd.asl @@ -0,0 +1,92 @@ +/************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* MPG-MSAE *; +;* *; +;* Copyright (c) 1999-2011 Intel Corporation. *; +;* *; +;* This program has been developed by Intel Corporation. *; +;* Licensee has Intel's permission to incorporate this source code *; +;* into their product, royalty free. This source code may NOT be *; +;* redistributed to anyone without Intel's written permission. *; +;* *; +;* Intel specifically disclaims all warranties, express or *; +;* implied, and all liability, including consequential and other *; +;* indirect damages, for the use of this code, including liability *; +;* for infringement of any proprietary rights, and including the *; +;* warranties of merchantability and fitness for a particular *; +;* purpose. Intel does not assume any responsibility for any *; +;* errors which may appear in this code nor any responsibility to *; +;* update it. *; +;* *; +;* Version: See README.TXT *; +;* *; +;************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +// +// _DSM : Device Specific Method supporting USB Sideband Deferring function +// +// Arg0: UUID Unique function identifier +// Arg1: Integer Revision Level +// Arg2: Integer Function Index +// Arg3: Package Parameters +// +Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) +{ + + If (LEqual(Arg0, ToUUID ("A5FC708F-8775-4BA6-BD0C-BA90A1EC72F8"))) + { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) + { + // + // Standard query - A bitmask of functions supported + // Supports function 0-2 + // + Case (0) + { + if (LEqual(Arg1, 1)){ // test Arg1 for the revision + Return (Buffer () {0x07}) + } else { + Return (Buffer () {0}) + } + } + // + // USB Sideband Deferring Support + // 0: USB Sideband Deferring not supported on this device + // 1: USB Sideband Deferring supported + // + Case (1) + { + if (LEqual(SDGV,0xFF)){ // check for valid GPE vector + Return (0) + } else { + Return (1) + } + } + // + // GPE Vector + // Return the bit offset within the GPE block of the GPIO (HOST_ALERT) driven by this device + // + Case (2) + { + Return (SDGV) + } + } + } + + Return (0) +} |