diff options
Diffstat (limited to 'ReferenceCode/Chipset/LynxPoint/Ppi')
22 files changed, 1521 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/IntelPchPpiLib.cif b/ReferenceCode/Chipset/LynxPoint/Ppi/IntelPchPpiLib.cif new file mode 100644 index 0000000..3136c1b --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/IntelPchPpiLib.cif @@ -0,0 +1,28 @@ +<component> + name = "IntelPchPpiLib" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\LynxPoint\Ppi\" + RefName = "IntelPchPpiLib" +[files] +"IntelPchPpiLib.inf" +"IntelPchPpiLib.sdl" +"IntelPchPpiLib.mak" +"Spi\Spi.h" +"Spi\Spi.c" +"PchInit\PchInit.h" +"PchInit\PchInit.c" +"PchPeiInitDone\PchPeiInitDone.c" +"PchPeiInitDone\PchPeiInitDone.h" +"PchUsbPolicy\PchUsbPolicy.c" +"PchUsbPolicy\PchUsbPolicy.h" +"PchDmiTcVcMap\PchDmiTcVcMap.c" +"PchDmiTcVcMap\PchDmiTcVcMap.h" +"PchPlatformPolicy\PchPlatformPolicy.c" +"PchPlatformPolicy\PchPlatformPolicy.h" +"Wdt\Wdt.h" +"Wdt\Wdt.c" +"PchReset\PchReset.h" +"PchReset\PchReset.c" +"SmmControl\SmmControl.c" +"SmmControl\SmmControl.h" +<endComponent> diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/IntelPchPpiLib.inf b/ReferenceCode/Chipset/LynxPoint/Ppi/IntelPchPpiLib.inf new file mode 100644 index 0000000..166d089 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/IntelPchPpiLib.inf @@ -0,0 +1,68 @@ +## @file +# Component description file for the PCH Ppi library +# +#@copyright +# Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = $(PROJECT_PCH_FAMILY)PpiLib +COMPONENT_TYPE = LIBRARY + +[sources.common] + Spi/Spi.h + Spi/Spi.c + PchInit/PchInit.h + PchInit/PchInit.c + PchUsbPolicy/PchUsbPolicy.h + PchUsbPolicy/PchUsbPolicy.c + PchDmiTcVcMap/PchDmiTcVcMap.h + PchDmiTcVcMap/PchDmiTcVcMap.c + PchPlatformPolicy/PchPlatformPolicy.h + PchPlatformPolicy/PchPlatformPolicy.c + Wdt/Wdt.h + Wdt/Wdt.c + PchReset/PchReset.h + PchReset/PchReset.c + PchPeiInitDone/PchPeiInitDone.h + PchPeiInitDone/PchPeiInitDone.c + SmmControl/SmmControl.h + SmmControl/SmmControl.c + +[includes.common] + . + $(EDK_SOURCE)/Foundation/Library/Pei/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol/PchPlatformPolicy +# +# EDK II Glue Library utilizes some standard headers from EDK +# + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[nmake.common] +C_STD_INCLUDE= + diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/IntelPchPpiLib.mak b/ReferenceCode/Chipset/LynxPoint/Ppi/IntelPchPpiLib.mak new file mode 100644 index 0000000..bd1e833 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/IntelPchPpiLib.mak @@ -0,0 +1,63 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/IntelPchPpiLib/IntelPchPpiLib.mak 1 2/08/12 8:58a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:58a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/IntelPchPpiLib/IntelPchPpiLib.mak $ +# +# 1 2/08/12 8:58a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* + +# MAK file for the ModulePart:IntelPchPpiLib +all : IntelPchPpiLib + +$(IntelPchPpiLib_LIB) : IntelPchPpiLib + +IntelPchPpiLib : $(BUILD_DIR)\IntelPchPpiLib.mak IntelPchPpiLibBin + +$(BUILD_DIR)\IntelPchPpiLib.mak : $(IntelPchPpiLib_DIR)\$(@B).cif $(IntelPchPpiLib_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(IntelPchPpiLib_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +IntelPchPpiLib_INCLUDES =\ + $(EDK_INCLUDES)\ + $(INTEL_PCH_INCLUDES)\ + +IntelPchPpiLibBin : + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\IntelPchPpiLib.mak all\ + "MY_INCLUDES=$(IntelPchPpiLib_INCLUDES)" \ + TYPE=PEI_LIBRARY LIBRARIES= \ + LIBRARY_NAME=$(IntelPchPpiLib_LIB) +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/IntelPchPpiLib.sdl b/ReferenceCode/Chipset/LynxPoint/Ppi/IntelPchPpiLib.sdl new file mode 100644 index 0000000..776a8cb --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/IntelPchPpiLib.sdl @@ -0,0 +1,72 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/IntelPchPpiLib/IntelPchPpiLib.sdl 1 2/08/12 8:58a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:58a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/IntelPchPpiLib/IntelPchPpiLib.sdl $ +# +# 1 2/08/12 8:58a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "IntelPchPpiLib_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable IntelPchPpiLib support in Project" +End + +PATH + Name = "IntelPchPpiLib_DIR" + Help = "IntelPchPpiLib file source directory" +End + +MODULE + File = "IntelPchPpiLib.mak" + Help = "Includes IntelPchPpiLib.mak to Project" +End + +ELINK + Name = "IntelPchPpiLib_LIB" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "$(BUILD_DIR)\IntelPchPpiLib.lib" + Parent = "IntelPchPpiLib_LIB" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/PchDmiTcVcMap/PchDmiTcVcMap.c b/ReferenceCode/Chipset/LynxPoint/Ppi/PchDmiTcVcMap/PchDmiTcVcMap.c new file mode 100644 index 0000000..f11b338 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/PchDmiTcVcMap/PchDmiTcVcMap.c @@ -0,0 +1,43 @@ +/** @file + This file defines the DMI TC/VC mapping policy + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Statements that include other files +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#endif +// +// Include the PPI header file +// +#include "PchDmiTcVcMap.h" + +// +// PPI GUID definition +// +EFI_GUID gPchDmiTcVcMapPpiGuid = PCH_DMI_TC_VC_PPI_GUID; + +// +// PPI description +// +EFI_GUID_STRING(&gPchDmiTcVcMapPpiGuid, "PCH DMI TC VC Map PPI", "PCH DMI TC VC Mapping PPI");
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/PchDmiTcVcMap/PchDmiTcVcMap.h b/ReferenceCode/Chipset/LynxPoint/Ppi/PchDmiTcVcMap/PchDmiTcVcMap.h new file mode 100644 index 0000000..7a2e555 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/PchDmiTcVcMap/PchDmiTcVcMap.h @@ -0,0 +1,80 @@ +/** @file + This file defines the PCH DMI TC/VC mapping PPI + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_DMI_TC_VC_MAP_H_ +#define _PCH_DMI_TC_VC_MAP_H_ + +/// +/// Define the PCH DMI TC VC Mapping PPI GUID +/// +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define PCH_DMI_TC_VC_PPI_GUID \ + { \ + 0xed097352, 0x9041, 0x445a, 0x80, 0xb6, 0xb2, 0x9d, 0x50, 0x9e, 0x88, 0x45 \ + } +#else +#define PCH_DMI_TC_VC_PPI_GUID \ + { \ + 0xed097352, 0x9041, 0x445a, \ + { \ + 0x80, 0xb6, 0xb2, 0x9d, 0x50, 0x9e, 0x88, 0x45 \ + } \ + } +#endif +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchDmiTcVcMapPpiGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_DMI_TC_VC_PPI PCH_DMI_TC_VC_PPI; + +typedef enum { + DmiVcTypeVc0, + DmiVcTypeVc1, + DmiVcTypeVcp, + DmiVcTypeVcm, + DmiVcTypeMax +} PCH_DMI_VC_TYPE; + +typedef struct { + PCH_DMI_VC_TYPE Vc; ///< The Virtual Channel to which the TC is mapped +} PCH_DMI_TC_CONFIG; + +typedef struct { + BOOLEAN Enable; ///< 0: Disable; 1: Enable + UINT8 VcId; ///< Vc ID Encoding for the Virtual Channel +} PCH_DMI_VC_CONFIG; + +#define DmiTcTypeMax 8 + +/// +/// PCH_DMI_TC_VC_PPI Structure Definition +/// Note: The default DMI TC/VC mapping will be used if it's not initialized +/// +struct _PCH_DMI_TC_VC_PPI { + PCH_DMI_TC_CONFIG DmiTc[DmiTcTypeMax]; ///< Configures PCH DMI Traffic class mapping. + PCH_DMI_VC_CONFIG DmiVc[DmiVcTypeMax]; ///< Configures PCH DMI Virtual Channel setting. +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/PchInit/PchInit.c b/ReferenceCode/Chipset/LynxPoint/Ppi/PchInit/PchInit.c new file mode 100644 index 0000000..bb31fa3 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/PchInit/PchInit.c @@ -0,0 +1,43 @@ +/** @file + This file defines the PCH Init PPI + +@copyright + Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Statements that include other files +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#endif +// +// Include the PPI header file +// +#include "PchInit.h" + +// +// PPI GUID definition +// +EFI_GUID gPchInitPpiGuid = PCH_INIT_PPI_GUID; + +// +// PPI description +// +EFI_GUID_STRING(&gPchInitPpiGuid, "PCH Init PPI", "PCH Initialization PPI"); diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/PchInit/PchInit.h b/ReferenceCode/Chipset/LynxPoint/Ppi/PchInit/PchInit.h new file mode 100644 index 0000000..9021a28 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/PchInit/PchInit.h @@ -0,0 +1,153 @@ +/** @file + This file defines the PCH Init PPI + +@copyright + Copyright (c) 2006 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_INIT_H_ +#define _PCH_INIT_H_ + +/// +/// Define the PCH Init PPI GUID +/// +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define PCH_INIT_PPI_GUID \ + { \ + 0x908c7f8b, 0x5c48, 0x47fb, 0x83, 0x57, 0xf5, 0xfd, 0x4e, 0x23, 0x52, 0x76 \ + } +#else +#define PCH_INIT_PPI_GUID \ + { \ + 0x908c7f8b, 0x5c48, 0x47fb, \ + { \ + 0x83, 0x57, 0xf5, 0xfd, 0x4e, 0x23, 0x52, 0x76 \ + } \ + } +#endif +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchInitPpiGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_INIT_PPI PCH_INIT_PPI; + +// +// Data structure definitions +// +typedef enum _CPU_STRAP_OPERATION +{ + GetCpuStrapSetData, + SetCpuStrapSetData, + LockCpuStrapSetData +} CPU_STRAP_OPERATION; + +/** + The function performing USB init in PEI phase. This could be used by USB recovery + or debug features that need USB initialization during PEI phase. + Note: Before executing this function, please be sure that PCH_INIT_PPI.Initialize + has been done and PchUsbPolicyPpi has been installed. + + @param[in] PeiServices General purpose services available to every PEIM + + @retval EFI_SUCCESS The function completed successfully + @retval Others All other error conditions encountered result in an ASSERT. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_USB_INIT) ( + IN EFI_PEI_SERVICES **PeiServices + ); + +/** + The function performing TC/VC mapping program, and poll all PCH Virtual Channel + until negotiation completion + + @param[in] PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS The function completed successfully + @retval Others All other error conditions encountered result in an ASSERT. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_DMI_TCVC_PROGPOLL) ( + IN EFI_PEI_SERVICES **PeiServices + ); + +/** + The function set the Target Link Speed in PCH to DMI GEN 2. + + @param[in] PeiServices General purpose services available to every PEIM. + + @retval None +**/ +typedef +VOID +(EFIAPI *PCH_DMI_GEN2_PROG) ( + IN EFI_PEI_SERVICES **PeiServices + ); + +/** + The function is used while doing CPU Only Reset, where PCH may be required + to initialize strap data before soft reset. + + @param[in] PeiServices General purpose services available to every PEIM + @param[in] Operation Get/Set Cpu Strap Set Data + @param[in] CpuStrapSet Cpu Strap Set Data + + @retval EFI_SUCCESS The function completed successfully. + @exception EFI_UNSUPPORTED The function is not supported. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_CPU_STRAP_SET) ( + IN EFI_PEI_SERVICES **PeiServices, + IN CPU_STRAP_OPERATION Operation, + IN OUT UINT16 *CpuStrapSet + ); + +/// +/// PCH_INIT_PPI Structure Definition +/// +struct _PCH_INIT_PPI { + /// + /// The function performs USB init in PEI phase. This could be used by USB recovery + /// or debug function that USB initialization needs to be done in PEI phase. + /// Note: Before executing this function, please be sure that PCH_PLATFORM_POLICY_PPI + /// and PCH_USB_POLICY_PPI have been installed. + /// + PCH_USB_INIT UsbInit; + /// + /// The function performing TC/VC mapping program, and poll all PCH Virtual Channel + /// until negotiation completion. + /// + PCH_DMI_TCVC_PROGPOLL DmiTcVcProgPoll; + /// + /// The function changes the PCH target link speed to DMI Gen 2 + /// + PCH_DMI_GEN2_PROG DmiGen2Prog; + /// + /// The function provides a way to initialize PCH strap data before soft reset + /// while doing CPU Only Reset + /// + PCH_CPU_STRAP_SET CpuStrapSet; +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/PchPeiInitDone/PchPeiInitDone.c b/ReferenceCode/Chipset/LynxPoint/Ppi/PchPeiInitDone/PchPeiInitDone.c new file mode 100644 index 0000000..b754481 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/PchPeiInitDone/PchPeiInitDone.c @@ -0,0 +1,47 @@ +/** @file + To indicate PCH code finish PCH controller initialization + upon policy configuration + +@copyright + Copyright (c) 2011 -2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Include the ppi header file +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGluePeim.h" +#endif + +#include EFI_PPI_DEFINITION (PchPeiInitDone) + +// +// PPI GUID definition +// +EFI_GUID gPchPeiInitDonePpiGuid = PCH_PEI_INIT_DONE_PPI_GUID; + +// +// PPI description +// +EFI_GUID_STRING + ( + &gPchPeiInitDonePpiGuid, "Pch PEI Init Done Ppi", + "This is a dummy PPI to ensure PCH PEI Init Done PPI is updated before RC modules" + ); diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/PchPeiInitDone/PchPeiInitDone.h b/ReferenceCode/Chipset/LynxPoint/Ppi/PchPeiInitDone/PchPeiInitDone.h new file mode 100644 index 0000000..ee764cb --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/PchPeiInitDone/PchPeiInitDone.h @@ -0,0 +1,53 @@ +/** @file + PCH Init Done PPI + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +#ifndef _PCH_PEI_INIT_DONE_PPI_H_ +#define _PCH_PEI_INIT_DONE_PPI_H_ + +/// +/// GUID for the PCH PEI Init Done PPI +/// +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define PCH_PEI_INIT_DONE_PPI_GUID \ + { \ + 0x1edcbdf9, 0xffc6, 0x4bd4, 0x94, 0xf6, 0x19, 0x5d, 0x1d, 0xe1, 0x70, 0x56 \ + } +#else +#define PCH_PEI_INIT_DONE_PPI_GUID \ + { \ + 0x1edcbdf9, 0xffc6, 0x4bd4, \ + { \ + 0x94, 0xf6, 0x19, 0x5d, 0x1d, 0xe1, 0x70, 0x56 \ + } \ + } +#endif +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchPeiInitDonePpiGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_PEI_INIT_DONE_PPI PCH_PEI_INIT_DONE_PPI; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/PchPlatformPolicy/PchPlatformPolicy.c b/ReferenceCode/Chipset/LynxPoint/Ppi/PchPlatformPolicy/PchPlatformPolicy.c new file mode 100644 index 0000000..206a26a --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/PchPlatformPolicy/PchPlatformPolicy.c @@ -0,0 +1,43 @@ +/** @file + PCH policy PPI produced by a platform driver specifying various + expected PCH settings. This PPI is consumed by the PCH PEI modules. + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Statements that include other files +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGluePeim.h" +#endif + +#include "PchPlatformPolicy.h" + +// +// PPI GUID definition +// +EFI_GUID gPchPlatformPolicyPpiGuid = PCH_PLATFORM_POLICY_PPI_GUID; + +// +// PPI description +// +EFI_GUID_STRING(&gPchPlatformPolicyPpiGuid, "PchPlatformPolicy PPI", "Intel(R) DXE Phase PCH Platform Policy PPI");
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/PchPlatformPolicy/PchPlatformPolicy.h b/ReferenceCode/Chipset/LynxPoint/Ppi/PchPlatformPolicy/PchPlatformPolicy.h new file mode 100644 index 0000000..fbf4694 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/PchPlatformPolicy/PchPlatformPolicy.h @@ -0,0 +1,263 @@ +/** @file + PCH policy PPI produced by a platform driver specifying various + expected PCH settings. This PPI is consumed by the PCH PEI modules. + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef PCH_PLATFORM_POLICY_H_ +#define PCH_PLATFORM_POLICY_H_ +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "PchAccess.h" +#include "PchUsbConfig.h" +#endif +/// +/// PCH policy provided by platform for PEI phase +/// +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define PCH_PLATFORM_POLICY_PPI_GUID \ + { \ + 0x36f6ce3d, 0xb76e, 0x42c2, 0x9f, 0x96, 0x3e, 0x41, 0x84, 0xa3, 0x50, 0x66 \ + } +#else +#define PCH_PLATFORM_POLICY_PPI_GUID \ + { \ + 0x36f6ce3d, 0xb76e, 0x42c2, \ + { \ + 0x9f, 0x96, 0x3e, 0x41, 0x84, 0xa3, 0x50, 0x66 \ + } \ + } +#endif + +extern EFI_GUID gPchPlatformPolicyPpiGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI; + +/// +/// PPI revision number +/// Any backwards compatible changes to this PPI will result in an update in the revision number +/// Major changes will require publication of a new PPI +/// +/// Revision 1: Original version +/// +#define PCH_PLATFORM_POLICY_PPI_REVISION_1 1 +/// +/// Revision 2: Add UsbConfig +/// +#define PCH_PLATFORM_POLICY_PPI_REVISION_2 2 +/// +/// Revision 3: Add Port30Settings in PCH_USB_CONFIG +/// +#define PCH_PLATFORM_POLICY_PPI_REVISION_3 3 +/// +/// Revision 4: Add Sata RxEq Settings in PCH_SATA_TRACE_CONFIG +/// Deprecate PortLength and PortTopology in PCH_SATA_TRACE_CONFIG +/// +#define PCH_PLATFORM_POLICY_PPI_REVISION_4 4 +// +// Generic definitions for device enabling/disabling used by PCH code. +// +#define PCH_DEVICE_ENABLE 1 +#define PCH_DEVICE_DISABLE 0 + +// +// ---------------------------- Gbe Config ----------------------------- +// +typedef struct { + /// + /// Determines if enable GBE + /// When EnableGbe is changed (from disabled to enabled or from enabled to disabled), + /// it needs to set LAN Disable regsiter, which might be locked by FDSWL register. + /// So it's recommendated to issue a global reset when changing the status for PCH Internal LAN. + /// + UINT8 EnableGbe : 1; + UINT8 Rsvdbits : 7; +} PCH_GBE_CONFIG; + +// +// ---------------------------- Thermal Config ----------------------------- +// +typedef struct { + UINT8 PmsyncEnable : 1; + UINT8 C0TransmitEnable : 1; + UINT8 PinSelection : 1; ///< GpioC 0:GPIO37; 1:GPIO4, GpioD 0:GPIO5; 1:GPIO0 + UINT8 Rsvdbits : 5; +} TS_GPIO_PIN_SETTING; + +typedef enum { + TsGpioC = 0, + TsGpioD, + MaxTsGpioPin +} PCH_PMSYNC_GPIO_X_SELECTION; + +typedef struct { + UINT8 Enable : 1; + UINT8 Rsvdbits : 7; + TS_GPIO_PIN_SETTING TsGpioPinSetting[MaxTsGpioPin]; +} PCH_MEMORY_THROTTLING; + +typedef struct { + PCH_MEMORY_THROTTLING *MemoryThrottling; +} PCH_THERMAL_MANAGEMENT; + +// +// ---------------------------- HPET Config ----------------------------- +// +typedef struct { + BOOLEAN Enable; ///< Determines if enable HPET function + UINT32 Base; ///< The HPET base address +} PCH_HPET_CONFIG; + +// +// ---------------------------- Reserved Page Config ----------------------------- +// +typedef enum { + PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC. + PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe. +} PCH_RESERVED_PAGE_ROUTE; + +// +// ---------------------------- SATA Config ----------------------------- +// +typedef enum { + PchSataModeIde = 0, + PchSataModeAhci = 1, + PchSataModeRaid = 2, + PchSataModeLoopbackTest = 3, + PchSataModeMax +} PCH_SATA_MODE; + +typedef enum { + PchDirectConnect, + PchCableUp +} PCH_SATA_TOPOLOGY; + +/// +/// This policy configures SATA RX Equalization for each Gen Speed. +/// When enabled, BIOS will configure SATA RXEQ according to RxEq setting, else BIOS will use default setting. +/// For which RxEq value to use, please refer to PCH EDS for more details. +/// +typedef struct { + UINT8 RxEq; + UINT8 Enable; +}PCH_SATA_GENSPEED; + +/// +/// This policy provides the SATA RX Equalization policy for each Gen Speed per port. +/// GenSpeed[0] configures GEN1 RxEq, GenSpeed[1] configures GEN2 RxEq, and GenSpeed[2] configures GEN3 RxEq. +/// +typedef struct { + PCH_SATA_GENSPEED GenSpeed[3]; +} PCH_SATA_PORT_RXEQ; + +typedef struct { + UINT16 PortLength[2]; ///< @deprecate + UINT8 TestMode : 1; ///< 0: Disable; 1: Allow entrance to the PCH SATA test modes + UINT8 RsvdBits : 7; + PCH_SATA_TOPOLOGY PortTopology[2]; ///< @deprecate + PCH_SATA_PORT_RXEQ PortRxEq[6]; ///< Configure SATA RX Equalization according to platform design +} PCH_SATA_TRACE_CONFIG; + +typedef struct { + PCH_SATA_MODE SataMode; ///< Determines the system will be configured to which SATA mode + PCH_SATA_TRACE_CONFIG *SataTraceConfig; ///< Decide SATA trace related configurations. +} PCH_SATA_CONTROL; + +// +// ---------------------------- PCI Express Config ----------------------------- +// +typedef enum { + PchPcieAuto, + PchPcieGen1, + PchPcieGen2 +} PCH_PCIE_SPEED; + +typedef struct { + PCH_PCIE_SPEED PcieSpeed[LPTH_PCIE_MAX_ROOT_PORTS]; ///< Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2. +} PCH_PCIE_CONFIG; + +// +// ---------------------------- IO APIC Config ----------------------------- +// +typedef struct { + UINT8 IoApicId; ///< This member determines IOAPIC ID. + UINT8 ApicRangeSelect; ///< Define address bits 19:12 for the IOxAPIC range + UINT8 IoApicEntry24_39 :1; ///< 0: Disable; 1: Enable IOAPIC Entry 24-39 + UINT8 RsvdBits :7; +} PCH_IOAPIC_CONFIG; + +// +// ---------------------------- PCH Platform Data ----------------------------- +// +typedef struct { + UINT8 EcPresent : 1; ///< Reports if EC is present or not. + UINT8 SmmBwp : 1; ///< 0: Clear SMM_BWP bit; 1: Set SMM_BWP bit. + ///< The BIOS must set the SMM_BWP bit while PFAT (Platform Firmware Armoring Technology) + ///< support is enabled. + UINT8 Rsvdbits : 6; + UINT32 TempMemBaseAddr; ///< Temporary Memory Base Address for PCI devices to be + ///< used to initialize MMIO registers. Minimum size is + ///< 32KB bytes +} PCH_PLATFORM_DATA; + +// +// ------------ General PCH Platform Policy PPI definition ------------ +// +struct _PCH_PLATFORM_POLICY_PPI { + /// + /// This member specifies the revision of the PCH policy PPI. This field is used to + /// indicate backwards compatible changes to the protocol. Platform code that produces + /// this PPI must fill with the correct revision value for the PCH reference code + /// to correctly interpret the content of the PPI fields. + /// + UINT8 Revision; + UINT8 BusNumber; ///< Bus Number of the PCH device. + UINT32 Rcba; ///< Root Complex Base Address. + UINT16 PmBase; ///< Power management I/O base address. + UINT16 GpioBase; ///< General purpose I/O base address. + PCH_GBE_CONFIG *GbeConfig; ///< Enable/Disable Gbe function. + PCH_THERMAL_MANAGEMENT *ThermalMgmt; ///< Enable the thermal management and pass the GPIO usage. + PCH_HPET_CONFIG *HpetConfig; ///< Enable HPET function and the pass HPET base address. + PCH_RESERVED_PAGE_ROUTE Port80Route; ///< Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + /// + /// SATA configuration that decides which Mode the SATA controller should operate in + /// and describes SATA Port 0, 1 Trace length and decides whether PCH SATA TEST mode + /// is enabled. + /// + PCH_SATA_CONTROL *SataConfig; + /// + /// PCIE configuration describes each PCIE Port speed capability. + /// 0: Auto; 1: Gen1; 2:Gen2 + /// + PCH_PCIE_CONFIG *PcieConfig; + PCH_IOAPIC_CONFIG *IoApicConfig; ///< Determines IO APIC ID and IO APIC Range. + PCH_PLATFORM_DATA *PlatformData; ///< Decides platform data, like EcPresent. + /// + /// This member decides the USB config and is a common structure for Protocols also. + /// + PCH_USB_CONFIG *UsbConfig; +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/PchReset/PchReset.c b/ReferenceCode/Chipset/LynxPoint/Ppi/PchReset/PchReset.c new file mode 100644 index 0000000..2eba7db --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/PchReset/PchReset.c @@ -0,0 +1,42 @@ +/** @file + This file defines the PCH Reset PPI + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Include the ppi header file +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#endif +#include "PchReset.h" + +// +// PPI GUID definition +// +EFI_GUID gPchResetPpiGuid = PCH_RESET_PPI_GUID; +EFI_GUID gPchResetCallbackPpiGuid = PCH_RESET_CALLBACK_PPI_GUID; + +// +// PPI description +// +EFI_GUID_STRING(&gPchResetPpiGuid, "PCH RESET PPI", "Intel(R) PCH Reset PPI"); +EFI_GUID_STRING(&gPchResetCallbackPpiGuid, "PCH RESET CALLBACK PPI", "Intel(R) PCH Reset Callback PPI"); diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/PchReset/PchReset.h b/ReferenceCode/Chipset/LynxPoint/Ppi/PchReset/PchReset.h new file mode 100644 index 0000000..8f2c9bd --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/PchReset/PchReset.h @@ -0,0 +1,68 @@ +/** @file + PCH Reset PPI + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PEI_PCH_RESET_H_ +#define _PEI_PCH_RESET_H_ + +#include <Protocol/PchReset/PchReset.h> + +/// +/// GUID for the PCH Reset PPI +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define PCH_RESET_PPI_GUID \ + { \ + 0x433e0f9f, 0x5ae, 0x410a, 0xa0, 0xc3, 0xbf, 0x29, 0x8e, 0xcb, 0x25, 0xac \ + } + +#define PCH_RESET_CALLBACK_PPI_GUID \ + { \ + 0x17865dc0, 0xb8b, 0x4da8, 0x8b, 0x42, 0x7c, 0x46, 0xb8, 0x5c, 0xca, 0x4d \ + } +#else +#define PCH_RESET_PPI_GUID \ + { \ + 0x433e0f9f, 0x5ae, 0x410a, \ + { \ + 0xa0, 0xc3, 0xbf, 0x29, 0x8e, 0xcb, 0x25, 0xac \ + } \ + } +#define PCH_RESET_CALLBACK_PPI_GUID \ + { \ + 0x17865dc0, 0xb8b, 0x4da8, \ + { \ + 0x8b, 0x42, 0x7c, 0x46, 0xb8, 0x5c, 0xca, 0x4d \ + } \ + } +#endif +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchResetPpiGuid; +extern EFI_GUID gPchResetCallbackPpiGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef PCH_RESET_PROTOCOL PCH_RESET_PPI; + +typedef PCH_RESET_CALLBACK_PROTOCOL PCH_RESET_CALLBACK_PPI; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/PchUsbPolicy/PchUsbPolicy.c b/ReferenceCode/Chipset/LynxPoint/Ppi/PchUsbPolicy/PchUsbPolicy.c new file mode 100644 index 0000000..b798bff --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/PchUsbPolicy/PchUsbPolicy.c @@ -0,0 +1,45 @@ +/** @file + PCH Usb policy PPI produced by a platform driver specifying + various expected PCH Usb settings. This PPI is consumed by the + PCH PEI drivers. + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Statements that include other files +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#endif +// +// Include the PPI header file +// +#include "PchUsbPolicy.h" + +// +// PPI GUID definition +// +EFI_GUID gPchUsbPolicyPpiGuid = PCH_USB_POLICY_PPI_GUID; + +// +// PPI description +// +EFI_GUID_STRING(&gPchUsbPolicyPpiGuid, "PchUsbPolicy PPI", "Intel(R) PCH USB Policy PPI"); diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/PchUsbPolicy/PchUsbPolicy.h b/ReferenceCode/Chipset/LynxPoint/Ppi/PchUsbPolicy/PchUsbPolicy.h new file mode 100644 index 0000000..65e918f --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/PchUsbPolicy/PchUsbPolicy.h @@ -0,0 +1,126 @@ +/** @file + PCH Usb policy PPI produced by a platform driver specifying + various expected PCH Usb settings. This PPI is consumed by the + PCH PEI drivers. + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_USB_POLICY_H_ +#define _PCH_USB_POLICY_H_ + +/// +/// PCH Usb policy provided by platform for PEI phase +/// +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "PchAccess.h" +#include "PchPlatformPolicy.h" +#endif + +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define PCH_USB_POLICY_PPI_GUID \ + { \ + 0x887acae1, 0x6a8c, 0x4eee, 0x97, 0xd, 0x91, 0x12, 0xda, 0x63, 0xbc, 0xf1 \ + } +#else +#define PCH_USB_POLICY_PPI_GUID \ + { \ + 0x887acae1, 0x6a8c, 0x4eee, \ + { \ + 0x97, 0xd, 0x91, 0x12, 0xda, 0x63, 0xbc, 0xf1 \ + } \ + } +#endif + +extern EFI_GUID gPchUsbPolicyPpiGuid; + +typedef struct _PCH_USB_POLICY_PPI PCH_USB_POLICY_PPI; + +/// +/// PPI revision number +/// Any backwards compatible changes to this PPI will result in an update in the revision number +/// Major changes will require publication of a new PPI +/// +/// Revision 1: Original version +/// +#define PCH_USB_POLICY_PPI_REVISION_1 1 +/// +/// Revision 2: Add ManualMode, ManualModeUsb20PerPinRoute and ManualModeUsb30PerPinEnable +/// to PCH_USB30_CONTROLLER_SETTINGS +/// Deprecated XhciStreams of PCH_USB30_CONTROLLER_SETTINGS +/// +#define PCH_USB_POLICY_PPI_REVISION_2 2 +/// +/// Revision 3: Add UsbPrecondition in UsbConfig +/// +#define PCH_USB_POLICY_PPI_REVISION_3 3 +/// +/// Revision 4: Add XhciIdleL1 to PCH_USB30_CONTROLLER_SETTINGS +/// +#define PCH_USB_POLICY_PPI_REVISION_4 4 + +// +// Generic definitions for device enabling/disabling used by PCH code. +// +#define PCH_DEVICE_ENABLE 1 +#define PCH_DEVICE_DISABLE 0 + +#define EHCI_MODE 1 + +/// +/// PCH Usb policy PPI produced by a platform driver specifying various expected +/// PCH Usb settings that would be used by PCH_INIT_PPI.UsbInit () and USB PEI module. +/// This PPI needs to be installed before calling PCH_INIT_PPI.UsbInit (). +/// +struct _PCH_USB_POLICY_PPI { + /// + /// This member specifies the revision of the PEI PCH USB Policy PPI. + /// This field is used to indicate backwards compatible changes to the protocol. + /// Platform code that produces this PPI must fill with the correct revision value + /// for the PCH reference code to correctly interpret the content of the PPI fields. + /// + UINT8 Revision; + /// + /// This member describes USB controller's related configuration. + /// + PCH_USB_CONFIG *UsbConfig; + /// + /// This member decides which USB controller needs to be initialed and allocated + /// resource in Pei Phase. It will be referred by USB PEI module. + /// For RMH enabled, please set this field to EHCI_MODE. + /// + UINT8 Mode; + /// + /// This member describes EHCI memory base address. USB PEI module will refer to + /// this field to program memory base address of each EHCI controllers. + /// + UINTN EhciMemBaseAddr; + /// + /// This member describes EHCI memory length. USB PEI module will check this field + /// to determine if the memory resource is less than the required. Each EHCI controller + /// requires 0x400 memory space. + /// + UINT32 EhciMemLength; + /// + /// This member describes XHCI memory base address. USB PEI module will refer to + /// this field to program memory base address of the XHCI controller. + /// + UINTN XhciMemBaseAddr; +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/SmmControl/SmmControl.c b/ReferenceCode/Chipset/LynxPoint/Ppi/SmmControl/SmmControl.c new file mode 100644 index 0000000..91c73b0 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/SmmControl/SmmControl.c @@ -0,0 +1,26 @@ +/** @file + This code abstracts the PEI core to provide SmmControl services. + +@copyright + Copyright (c) 2002 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +#include "Tiano.h" +#include "Pei.h" +#include EFI_PPI_DEFINITION (SmmControl) + +EFI_GUID gPeiSmmControlPpiGuid = PEI_SMM_CONTROL_PPI_GUID; + +EFI_GUID_STRING(&gPeiSmmControlPpiGuid, "SmmControl", "SMM Control PPI"); diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/SmmControl/SmmControl.h b/ReferenceCode/Chipset/LynxPoint/Ppi/SmmControl/SmmControl.h new file mode 100644 index 0000000..659aa63 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/SmmControl/SmmControl.h @@ -0,0 +1,72 @@ +/** @file + This code abstracts the PEI core to provide SmmControl services. + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +#ifndef _PEI_SMM_CONTROL_PPI_H_ +#define _PEI_SMM_CONTROL_PPI_H_ + +/// +/// Define the SPI PPI GUID +/// +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define PEI_SMM_CONTROL_PPI_GUID \ + { \ + 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 \ + } +#else +#define PEI_SMM_CONTROL_PPI_GUID \ + { \ + 0x61c68702, 0x4d7e, 0x4f43, \ + { \ + 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 \ + } \ + } +#endif + +EFI_FORWARD_DECLARATION (PEI_SMM_CONTROL_PPI); + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_ACTIVATE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI * This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_DEACTIVATE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI * This, + IN BOOLEAN Periodic OPTIONAL + ); + +typedef struct _PEI_SMM_CONTROL_PPI { + PEI_SMM_ACTIVATE Trigger; + PEI_SMM_DEACTIVATE Clear; +} PEI_SMM_CONTROL_PPI; + +extern EFI_GUID gPeiSmmControlPpiGuid; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/Spi/Spi.c b/ReferenceCode/Chipset/LynxPoint/Ppi/Spi/Spi.c new file mode 100644 index 0000000..5e58bed --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/Spi/Spi.c @@ -0,0 +1,44 @@ +/** @file + This file defines the EFI SPI PPI which implements the + Intel(R) SPI Host Controller Compatibility Interface. + +@copyright + Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Statements that include other files +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#endif +// +// Include the PPI header file +// +#include "Spi.h" + +// +// PPI GUID definition +// +EFI_GUID gPeiSpiPpiGuid = PEI_SPI_PPI_GUID; + +// +// PPI description +// +EFI_GUID_STRING(&gPeiSpiPpiGuid, "SPI PPI", "Intel(R) Serial Peripheral Interface PPI"); diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/Spi/Spi.h b/ReferenceCode/Chipset/LynxPoint/Ppi/Spi/Spi.h new file mode 100644 index 0000000..85fef0a --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/Spi/Spi.h @@ -0,0 +1,57 @@ +/** @file + This file defines the EFI SPI PPI which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + +@copyright + Copyright (c) 2006 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PEI_SPI_H_ +#define _PEI_SPI_H_ + +#include <Protocol/Spi/Spi.h> + +/// +/// Define the SPI PPI GUID +/// +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define PEI_SPI_PPI_GUID \ + { \ + 0xfbf26154, 0x4e55, 0x4bdc, 0xaf, 0x7b, 0xd9, 0x18, 0xac, 0x44, 0x3f, 0x61 \ + } +#else +#define PEI_SPI_PPI_GUID \ + { \ + 0xfbf26154, 0x4e55, 0x4bdc, \ + { \ + 0xaf, 0x7b, 0xd9, 0x18, 0xac, 0x44, 0x3f, 0x61 \ + } \ + } +#endif +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPeiSpiPpiGuid; + +/// +/// Reuse the EFI_SPI_PROTOCOL definitions +/// This is possible becaues the PPI implementation does not rely on a PeiService pointer, +/// as it uses EDKII Glue Lib to do IO accesses +/// +typedef EFI_SPI_PROTOCOL PEI_SPI_PPI; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/Wdt/Wdt.c b/ReferenceCode/Chipset/LynxPoint/Ppi/Wdt/Wdt.c new file mode 100644 index 0000000..1e7827c --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/Wdt/Wdt.c @@ -0,0 +1,32 @@ +/** @file + Watchdog Timer PPI + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#endif +#include "Wdt.h" + +// +// PPI GUID definition +// +EFI_GUID gWdtPpiGuid = WDT_PPI_GUID; + +// +// PPI description +// +EFI_GUID_STRING(&gWdtPpiGuid, "WDT PPI", "Watchdog Timer PPI"); diff --git a/ReferenceCode/Chipset/LynxPoint/Ppi/Wdt/Wdt.h b/ReferenceCode/Chipset/LynxPoint/Ppi/Wdt/Wdt.h new file mode 100644 index 0000000..8246fad --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Ppi/Wdt/Wdt.h @@ -0,0 +1,53 @@ +/** @file + Watchdog Timer PPI + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PEI_WDT_H_ +#define _PEI_WDT_H_ + +#include <Protocol/Wdt/Wdt.h> +/// +/// GUID for the WDT PPI +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define WDT_PPI_GUID \ + { \ + 0xF38D1338, 0xAF7A, 0x4FB6, 0x91, 0xDB, 0x1A, 0x9C, 0x21, 0x83, 0x57, 0x0D \ + } + +#else + +#define WDT_PPI_GUID \ + { \ + 0xF38D1338, 0xAF7A, 0x4FB6, \ + { \ + 0x91, 0xDB, 0x1A, 0x9C, 0x21, 0x83, 0x57, 0x0D \ + } \ + } + +#endif +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gWdtPpiGuid; + +/// +/// Reuse WDT_PROTOCOL definition +/// +typedef WDT_PROTOCOL WDT_PPI; + +#endif |