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-rw-r--r--ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchEhci.c229
-rw-r--r--ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchEhci.h82
-rw-r--r--ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.c77
-rw-r--r--ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.cif15
-rw-r--r--ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.dxs45
-rw-r--r--ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.h47
-rw-r--r--ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.inf87
-rw-r--r--ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.mak111
-rw-r--r--ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.sdl66
9 files changed, 759 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchEhci.c b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchEhci.c
new file mode 100644
index 0000000..e65e39e
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchEhci.c
@@ -0,0 +1,229 @@
+/** @file
+ Pch Ehci PPI Init
+
+@copyright
+ Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved
+ This software and associated documentation (if any) is furnished
+ under a license and may only be used or copied in accordance
+ with the terms of the license. Except as permitted by such
+ license, no part of this software or documentation may be
+ reproduced, stored in a retrieval system, or transmitted in any
+ form or by any means without the express written consent of
+ Intel Corporation.
+
+ This file contains an 'Intel Peripheral Driver' and uniquely
+ identified as "Intel Reference Module" and is
+ licensed for Intel CPUs and chipsets under the terms of your
+ license agreement with Intel or your vendor. This file may
+ be modified by the user, subject to additional terms of the
+ license agreement
+**/
+#include "PchEhci.h"
+#include "PchPlatformLib.h"
+
+EFI_GUID mPeiEhciControllerPpiGuid = PEI_USB_CONTROLLER_PPI_GUID;
+
+///
+/// PPI interface function
+///
+STATIC
+EFI_STATUS
+EFIAPI
+GetEhciController (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_CONTROLLER_PPI *This,
+ IN UINT8 UsbControllerId,
+ OUT UINTN *ControllerType,
+ OUT UINTN *BaseAddress
+ );
+
+///
+/// Globals variable
+///
+STATIC PEI_USB_CONTROLLER_PPI mEhciControllerPpi = { GetEhciController };
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &mPeiEhciControllerPpiGuid,
+ NULL
+};
+
+///
+/// Helper function
+///
+STATIC
+EFI_STATUS
+EnableEhciController (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PCH_EHCI_DEVICE *PeiPchEhciDev,
+ IN UINT8 UsbControllerId
+ );
+
+/**
+ Initialize PCH EHCI PEIM
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] UsbPolicyPpi PCH Usb Policy PPI
+
+ @retval EFI_SUCCESS The PCH EHCI PEIM is initialized successfully
+ @retval EFI_INVALID_PARAMETER UsbControllerId is out of range
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+ @retval Others All other error conditions encountered result in an ASSERT.
+**/
+EFI_STATUS
+InitForEHCI (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PCH_USB_POLICY_PPI *UsbPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ PCH_EHCI_DEVICE *PeiPchEhciDev;
+ EFI_BOOT_MODE BootMode;
+
+ DEBUG ((EFI_D_INFO, "InitForEHCI() Start\n"));
+
+ Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
+
+ ///
+ /// We do not export this in S3 boot path, because it is only for recovery.
+ ///
+ if (BootMode == BOOT_ON_S3_RESUME) {
+ return EFI_SUCCESS;
+ }
+
+ PeiPchEhciDev = (PCH_EHCI_DEVICE *) AllocatePool (sizeof (PCH_EHCI_DEVICE));
+ if (PeiPchEhciDev == NULL) {
+ DEBUG ((EFI_D_ERROR, "Failed to allocate memory for PeiPchEhciDev! \n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ PeiPchEhciDev->EhciControllerPpi = mEhciControllerPpi;
+ PeiPchEhciDev->PpiList = mPpiList;
+ PeiPchEhciDev->PpiList.Ppi = &PeiPchEhciDev->EhciControllerPpi;
+
+ PeiPchEhciDev->TotalEhciControllers = PchEhciControllerMax;
+
+ ///
+ /// Assign resources and enable EHCI controllers
+ ///
+ if (UsbPolicyPpi->EhciMemLength < (EHCI_MEMORY_SPACE * PeiPchEhciDev->TotalEhciControllers)) {
+ DEBUG ((EFI_D_ERROR, "The EhciMemLength got from UsbPolicyPpi is less than the required (%0x) !\n", (EHCI_MEMORY_SPACE * PeiPchEhciDev->TotalEhciControllers)));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ for (Index = 0; Index < PeiPchEhciDev->TotalEhciControllers; Index++) {
+ PeiPchEhciDev->MemBase[Index] = UsbPolicyPpi->EhciMemBaseAddr + EHCI_MEMORY_SPACE * Index;
+ Status = EnableEhciController (PeiServices, PeiPchEhciDev, (UINT8) Index);
+ ASSERT_EFI_ERROR (Status);
+ }
+ ///
+ /// Install USB Controller PPI
+ ///
+ Status = PeiServicesInstallPpi (&PeiPchEhciDev->PpiList);
+
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((EFI_D_INFO, "InitForEHCI() End\n"));
+
+ return Status;
+
+}
+
+///
+/// PPI interface implementation
+///
+
+/**
+ Get EHCI controller information
+
+ @param[in] PeiServices General PEI services
+ @param[in] This Pointer to the PEI_EHCI_CONTROLLER_PPI
+ @param[in] UsbControllerId The USB controller number
+ @param[out] ControllerType Output: USB controller type
+ @param[out] BaseAddress Output: EHCI controller memory base address
+
+ @retval EFI_INVALID_PARAMETER UsbControllerId is out of range
+ @retval EFI_SUCCESS Function completes successfully
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetEhciController (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB_CONTROLLER_PPI *This,
+ IN UINT8 UsbControllerId,
+ OUT UINTN *ControllerType,
+ OUT UINTN *BaseAddress
+ )
+{
+ PCH_EHCI_DEVICE *PeiPchEhciDev;
+
+ PeiPchEhciDev = PCH_EHCI_DEVICE_FROM_THIS (This);
+
+ if (UsbControllerId >= PeiPchEhciDev->TotalEhciControllers) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *ControllerType = PEI_EHCI_CONTROLLER;
+
+ *BaseAddress = PeiPchEhciDev->MemBase[UsbControllerId];
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Enable the EHCI controller
+
+ @param[in] PeiServices The general PEI services
+ @param[in] PeiPchEhciDev The EHCI device
+ @param[in] UsbControllerId The USB Controller number
+
+ @retval EFI_INVALID_PARAMETER UsbControllerId is out of range
+ @retval EFI_SUCCESS The function completes successfully
+**/
+STATIC
+EFI_STATUS
+EnableEhciController (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PCH_EHCI_DEVICE *PeiPchEhciDev,
+ IN UINT8 UsbControllerId
+ )
+{
+ UINTN BaseAddress;
+ UINTN EhciAddress;
+ PCH_SERIES PchSeries;
+
+ PchSeries = GetPchSeries();
+ if (UsbControllerId >= PeiPchEhciDev->TotalEhciControllers) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ BaseAddress = PeiPchEhciDev->MemBase[UsbControllerId];
+
+ EhciAddress = EFI_UNSUPPORTED;
+ if (PchSeries == PchH) {
+ EhciAddress = PCH_H_PCIE_EHCI_ADDR (UsbControllerId);
+ } else if (PchSeries == PchLp) {
+ EhciAddress = PCH_LP_PCIE_EHCI_ADDR (UsbControllerId);
+ }
+
+ if (EhciAddress == EFI_UNSUPPORTED) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ///
+ /// Assign base address register
+ ///
+ MmioWrite32 ((EhciAddress + R_PCH_EHCI_MEM_BASE), BaseAddress);
+
+ ///
+ /// Enable PCH EHCI register
+ ///
+ MmioOr16 (
+ (EhciAddress + R_PCH_EHCI_COMMAND_REGISTER),
+ (UINT16) (B_PCH_EHCI_COMMAND_BME | B_PCH_EHCI_COMMAND_MSE)
+ );
+
+ return EFI_SUCCESS;
+}
diff --git a/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchEhci.h b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchEhci.h
new file mode 100644
index 0000000..3c97998
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchEhci.h
@@ -0,0 +1,82 @@
+/** @file
+ Header file for the PCH EHCI PPI
+
+@copyright
+ Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved
+ This software and associated documentation (if any) is furnished
+ under a license and may only be used or copied in accordance
+ with the terms of the license. Except as permitted by such
+ license, no part of this software or documentation may be
+ reproduced, stored in a retrieval system, or transmitted in any
+ form or by any means without the express written consent of
+ Intel Corporation.
+
+ This file contains an 'Intel Peripheral Driver' and uniquely
+ identified as "Intel Reference Module" and is
+ licensed for Intel CPUs and chipsets under the terms of your
+ license agreement with Intel or your vendor. This file may
+ be modified by the user, subject to additional terms of the
+ license agreement
+**/
+#ifndef _PEI_PCH_EHCI_H
+#define _PEI_PCH_EHCI_H
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGluePeim.h"
+
+//
+// Driver Produced PPI Prototypes
+//
+#include EFI_PPI_DEFINITION (UsbController)
+
+//
+// Driver Consumed PPI Prototypes
+//
+#include EFI_PPI_CONSUMER (PchUsbPolicy)
+#include "PchAccess.h"
+#include "PchUsb.h"
+#endif
+
+#define PCH_PCIE_EHCI1_BUS_DEV_FUNC MmPciAddress ( \
+ 0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_USB, \
+ PCI_FUNCTION_NUMBER_PCH_EHCI, \
+ 0 \
+ )
+
+#define PCH_PCIE_EHCI2_BUS_DEV_FUNC MmPciAddress ( \
+ 0, \
+ DEFAULT_PCI_BUS_NUMBER_PCH, \
+ PCI_DEVICE_NUMBER_PCH_USB_EXT, \
+ PCI_FUNCTION_NUMBER_PCH_EHCI2, \
+ 0 \
+ )
+
+#define PCH_H_PCIE_EHCI_ADDR(Controller) ( \
+ (Controller == PchEhci1) ? PCH_PCIE_EHCI1_BUS_DEV_FUNC : \
+ (Controller == PchEhci2) ? PCH_PCIE_EHCI2_BUS_DEV_FUNC : EFI_UNSUPPORTED \
+ )
+
+#define PCH_LP_PCIE_EHCI_ADDR(Controller) ( \
+ (Controller == PchEhci1) ? PCH_PCIE_EHCI1_BUS_DEV_FUNC : EFI_UNSUPPORTED \
+ )
+
+#define PEI_PCH_EHCI_SIGNATURE EFI_SIGNATURE_32 ('E', 'H', 'C', 'I')
+#define EHCI_MEMORY_SPACE 0x400
+
+typedef struct {
+ UINTN Signature;
+ PEI_USB_CONTROLLER_PPI EhciControllerPpi;
+ EFI_PEI_PPI_DESCRIPTOR PpiList;
+ UINTN TotalEhciControllers;
+ UINTN MemBase[PchEhciControllerMax];
+} PCH_EHCI_DEVICE;
+
+#define PCH_EHCI_DEVICE_FROM_THIS(a) PEI_CR (a, PCH_EHCI_DEVICE, EhciControllerPpi, PEI_PCH_EHCI_SIGNATURE)
+
+#endif
diff --git a/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.c b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.c
new file mode 100644
index 0000000..493f5e6
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.c
@@ -0,0 +1,77 @@
+/** @file
+ Pch Usb Pei Init
+
+@copyright
+ Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved
+ This software and associated documentation (if any) is furnished
+ under a license and may only be used or copied in accordance
+ with the terms of the license. Except as permitted by such
+ license, no part of this software or documentation may be
+ reproduced, stored in a retrieval system, or transmitted in any
+ form or by any means without the express written consent of
+ Intel Corporation.
+
+ This file contains an 'Intel Peripheral Driver' and uniquely
+ identified as "Intel Reference Module" and is
+ licensed for Intel CPUs and chipsets under the terms of your
+ license agreement with Intel or your vendor. This file may
+ be modified by the user, subject to additional terms of the
+ license agreement
+**/
+#include "PchUsb.h"
+
+/**
+ Initialize PCH USB PEIM
+
+ @param[in] FfsHeader Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The PCH USB PEIM is initialized successfully
+ @retval Others All other error conditions encountered result in an ASSERT.
+**/
+EFI_STATUS
+InitializePchUsb (
+ IN EFI_FFS_FILE_HEADER *FfsHeader,
+ IN EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ PCH_USB_POLICY_PPI *UsbPolicyPpi;
+
+ DEBUG ((EFI_D_INFO, "InitializePchUsb() Start\n"));
+
+ ///
+ /// Locate UsbPolicy PPI
+ ///
+ Status = (**PeiServices).LocatePpi (
+ PeiServices,
+ &gPchUsbPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &UsbPolicyPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (Status == EFI_SUCCESS) {
+ ///
+ /// Enable USB controller and install PeiUsbControllerPpi for USB recovery function
+ ///
+ switch (UsbPolicyPpi->Mode) {
+ case EHCI_MODE:
+ DEBUG ((EFI_D_ERROR, "Usb Recovery Mode : EHCI !\n"));
+ DEBUG ((EFI_D_ERROR, "EhciMemBaseAddr:%0x!\n", UsbPolicyPpi->EhciMemBaseAddr));
+ DEBUG ((EFI_D_ERROR, "EhciMemLength:%0x!\n", UsbPolicyPpi->EhciMemLength));
+ InitForEHCI (PeiServices, UsbPolicyPpi);
+ break;
+
+ default:
+ ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
+ break;
+ }
+ }
+
+ DEBUG ((EFI_D_INFO, "InitializePchUsb() End\n"));
+
+ return Status;
+
+} \ No newline at end of file
diff --git a/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.cif b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.cif
new file mode 100644
index 0000000..277bd21
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.cif
@@ -0,0 +1,15 @@
+<component>
+ name = "PchUsb"
+ category = ModulePart
+ LocalRoot = "ReferenceCode\Chipset\LynxPoint\Usb\Pei"
+ RefName = "PchUsb"
+[files]
+"PchUsb.sdl"
+"PchUsb.mak"
+"PchUsb.dxs"
+"PchEhci.c"
+"PchEhci.h"
+"PchUsb.c"
+"PchUsb.h"
+"PchUsb.inf"
+<endComponent>
diff --git a/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.dxs b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.dxs
new file mode 100644
index 0000000..34d58dd
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.dxs
@@ -0,0 +1,45 @@
+/** @file
+ Dependency expression file for PCH USB PEIM.
+
+@copyright
+ Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved
+ This software and associated documentation (if any) is furnished
+ under a license and may only be used or copied in accordance
+ with the terms of the license. Except as permitted by such
+ license, no part of this software or documentation may be
+ reproduced, stored in a retrieval system, or transmitted in any
+ form or by any means without the express written consent of
+ Intel Corporation.
+
+ This file contains a 'Sample Driver' and is licensed as such
+ under the terms of your license agreement with Intel or your
+ vendor. This file may be modified by the user, subject to
+ the additional terms of the license agreement
+
+**/
+
+
+//
+// Same for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "PeimDepex.h"
+
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+
+#include EFI_PPI_DEFINITION (LoadFile)
+#include EFI_PPI_DEFINITION (PchUsbPolicy)
+#include EFI_PPI_CONSUMER (BootMode)
+#endif
+
+DEPENDENCY_START
+ EFI_PEI_FV_FILE_LOADER_GUID AND
+ PEI_MASTER_BOOT_MODE_PEIM_PPI AND
+ PCH_USB_POLICY_PPI_GUID
+DEPENDENCY_END \ No newline at end of file
diff --git a/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.h b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.h
new file mode 100644
index 0000000..7f20b4a
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.h
@@ -0,0 +1,47 @@
+/** @file
+ Header file for the PCH USB PEIM
+
+@copyright
+ Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved
+ This software and associated documentation (if any) is furnished
+ under a license and may only be used or copied in accordance
+ with the terms of the license. Except as permitted by such
+ license, no part of this software or documentation may be
+ reproduced, stored in a retrieval system, or transmitted in any
+ form or by any means without the express written consent of
+ Intel Corporation.
+
+ This file contains an 'Intel Peripheral Driver' and uniquely
+ identified as "Intel Reference Module" and is
+ licensed for Intel CPUs and chipsets under the terms of your
+ license agreement with Intel or your vendor. This file may
+ be modified by the user, subject to additional terms of the
+ license agreement
+**/
+#ifndef _PCH_USB_H_
+#define _PCH_USB_H_
+
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGluePeim.h"
+#include "PchAccess.h"
+#include EFI_PPI_CONSUMER (PchUsbPolicy)
+#endif
+
+/**
+ Initialize PCH EHCI PEIM
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] UsbPolicyPpi PCH Usb Policy PPI
+
+ @retval EFI_SUCCESS The PCH EHCI PEIM is initialized successfully
+ @retval EFI_INVALID_PARAMETER UsbControllerId is out of range
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+ @retval Others All other error conditions encountered result in an ASSERT.
+**/
+EFI_STATUS
+InitForEHCI (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PCH_USB_POLICY_PPI *UsbPolicyPpi
+ );
+
+#endif
diff --git a/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.inf b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.inf
new file mode 100644
index 0000000..bb6fe1e
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.inf
@@ -0,0 +1,87 @@
+## @file
+# Component description file for PCH USB PEIM
+#
+#@copyright
+# Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved
+# This software and associated documentation (if any) is furnished
+# under a license and may only be used or copied in accordance
+# with the terms of the license. Except as permitted by such
+# license, no part of this software or documentation may be
+# reproduced, stored in a retrieval system, or transmitted in any
+# form or by any means without the express written consent of
+# Intel Corporation.
+#
+# This file contains a 'Sample Driver' and is licensed as such
+# under the terms of your license agreement with Intel or your
+# vendor. This file may be modified by the user, subject to
+# the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME = PchUsb
+FILE_GUID = 6B4FDBD2-47E1-4a09-BA8E-8E041F208B95
+COMPONENT_TYPE = PE32_PEIM
+
+[sources.common]
+ PchEhci.c
+ PchUsb.c
+#
+# Edk II Glue Driver Entry Point
+#
+ EdkIIGluePeimEntryPoint.c
+
+[includes.common]
+ $(EDK_SOURCE)/Foundation/Efi
+ .
+ $(EDK_SOURCE)/Foundation/Include
+ $(EDK_SOURCE)/Foundation/Efi/Include
+ $(EDK_SOURCE)/Foundation/Framework/Include
+ $(EDK_SOURCE)/Foundation/Library/Pei/Include
+ $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include
+ $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)
+ $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol/PchPlatformPolicy
+ $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Library/PchPlatformLib
+ $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library
+#
+# EDK II Glue Library utilizes some standard headers from EDK
+#
+ $(EFI_SOURCE)
+ $(EDK_SOURCE)/Foundation
+ $(EDK_SOURCE)/Foundation/Framework
+ $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+ $(EDK_SOURCE)/Foundation/Core/Dxe
+ $(EDK_SOURCE)/Foundation/Include/Pei
+ $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+ $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
+ $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/SampleCode
+
+[libraries.common]
+ $(PROJECT_PCH_FAMILY)PpiLib
+ EdkIIGlueBaseMemoryLib
+ EdkIIGlueBaseIoLibIntrinsic
+ EdkIIGluePeiDebugLibReportStatusCode
+ EdkIIGluePeiReportStatusCodeLib
+ EdkIIGluePeiServicesLib
+ EdkIIGluePeiMemoryAllocationLib
+ EdkPpiLib
+ PchPlatformLib
+ EdkIIGlueBasePciLibPciExpress
+
+[nmake.common]
+ IMAGE_ENTRY_POINT=_ModuleEntryPoint
+ DPX_SOURCE=PchUsb.dxs
+#
+# Module Entry Point
+#
+ C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=InitializePchUsb
+ C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+ -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+ -D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \
+ -D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \
+ -D __EDKII_GLUE_PEI_SERVICES_LIB__ \
+ -D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__
diff --git a/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.mak b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.mak
new file mode 100644
index 0000000..22c8316
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.mak
@@ -0,0 +1,111 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2011, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchUsb/PchUsb.mak 4 10/16/12 3:37a Scottyang $
+#
+# $Revision: 4 $
+#
+# $Date: 10/16/12 3:37a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchUsb/PchUsb.mak $
+#
+# 4 10/16/12 3:37a Scottyang
+# [TAG] EIP103924
+#
+# [Category] Improvement
+#
+# [Description] Update RC 0.7.1
+#
+# [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SB.sd,
+# SbSetupData.c, GetSetupDate.c
+#
+# 3 7/02/12 9:19a Victortu
+#
+# 2 2/24/12 2:30a Victortu
+# Updated to support 4.6.5.3_IntelEDK_1117_Patch7_00.
+#
+# 1 2/08/12 9:30a Yurenlai
+# Intel Lynx Point/SB eChipset initially releases.
+#
+#*************************************************************************
+
+#---------------------------------------------------------------------------
+# Create PchUsb Driver
+#---------------------------------------------------------------------------
+EDK : PchUsb
+PchUsb : $(BUILD_DIR)\PchUsb.mak PchUsbBin
+
+
+$(BUILD_DIR)\PchUsb.mak : $(PchUsb_DIR)\$(@B).cif $(PchUsb_DIR)\$(@B).mak $(BUILD_RULES)
+ $(CIF2MAK) $(PchUsb_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+PchUsb_INCLUDES=\
+ $(INTEL_PCH_INCLUDES)\
+ /I$(INTEL_PCH_DIR)\Library\PchPlatformLib\
+ $(EdkIIGlueLib_INCLUDES)\
+
+PchUsb_DEFINES = $(MY_DEFINES)\
+ /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=InitializePchUsb"\
+ /D__EDKII_GLUE_BASE_MEMORY_LIB__ \
+ /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+ /D__EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \
+ /D__EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \
+ /D__EDKII_GLUE_PEI_SERVICES_LIB__ \
+ /D__EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__\
+ /D __EDKII_GLUE_BASE_PCI_LIB_CF8__
+
+PchUsb_LIB_LINKS =\
+ $(EDKFRAMEWORKPPILIB)\
+ $(EdkIIGlueBaseMemoryLib_LIB) \
+ $(EdkIIGlueBaseLib_LIB)\
+ $(EdkIIGlueBaseLibIA32_LIB)\
+ $(EdkIIGlueBaseIoLibIntrinsic_LIB) \
+ $(EdkIIGluePeiDebugLibReportStatusCode_LIB) \
+ $(EdkIIGluePeiReportStatusCodeLib_LIB) \
+ $(EdkIIGluePeiServicesLib_LIB) \
+ $(EdkIIGluePeiMemoryAllocationLib_LIB) \
+ $(EdkIIGlueBasePciLibCf8_LIB) \
+ $(IntelPchPpiLib_LIB) \
+ $(PchPlatformPeiLib_LIB)\
+ $(EdkIIGlueBasePciLibPciExpress_LIB)
+
+PchUsbBin: $(PchUsb_LIB_LINKS)
+ $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+ /f $(BUILD_DIR)\PchUsb.mak all\
+ NAME=PchUsb\
+ MAKEFILE=$(BUILD_DIR)\PchUsb.mak \
+ GUID=6B4FDBD2-47E1-4a09-BA8E-8E041F208B95\
+ "MY_INCLUDES=$(PchUsb_INCLUDES)"\
+ "MY_DEFINES=$(PchUsb_DEFINES)"\
+ ENTRY_POINT=_ModuleEntryPoint \
+ TYPE=PEIM \
+ EDKIIModule=PEIM\
+ DEPEX1=$(PchUsb_DIR)\PchUsb.dxs DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX \
+ COMPRESS=1
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2011, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
diff --git a/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.sdl b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.sdl
new file mode 100644
index 0000000..ca8d385
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Usb/Pei/PchUsb.sdl
@@ -0,0 +1,66 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2011, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchUsb/PchUsb.sdl 1 2/08/12 9:30a Yurenlai $
+#
+# $Revision: 1 $
+#
+# $Date: 2/08/12 9:30a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchUsb/PchUsb.sdl $
+#
+# 1 2/08/12 9:30a Yurenlai
+# Intel Lynx Point/SB eChipset initially releases.
+#
+#*************************************************************************
+TOKEN
+ Name = "PchUsb_SUPPORT"
+ Value = "1"
+ Help = "Main switch to enable PchUsb support in Project"
+ TokenType = Boolean
+ TargetMAK = Yes
+ Master = Yes
+End
+
+PATH
+ Name = "PchUsb_DIR"
+End
+
+MODULE
+ Help = "Includes PchUsb.mak to Project"
+ File = "PchUsb.mak"
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\PchUsb.ffs"
+ Parent = "FV_BB"
+ InvokeOrder = AfterParent
+End
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2011, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
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