diff options
Diffstat (limited to 'ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McMain.h')
| -rw-r--r-- | ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McMain.h | 19761 |
1 files changed, 19761 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McMain.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McMain.h new file mode 100644 index 0000000..fa1db62 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/Include/MrcRegisters/McMain.h @@ -0,0 +1,19761 @@ +/** @file + This file was automatically generated. Modify at your own risk. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef __McMain_h__ +#define __McMain_h__ + +#pragma pack(push, 1) +#include "MrcTypes.h" + +typedef union { + struct { + U32 Global_Start_Test : 1; // Bits 0:0 + U32 Global_Stop_Test : 1; // Bits 1:1 + U32 Global_Clear_Errors : 1; // Bits 2:2 + U32 : 1; // Bits 3:3 + U32 Global_Stop_Test_On_Any_Error : 1; // Bits 4:4 + U32 : 27; // Bits 31:5 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Channel_Error_Status_0 : 1; // Bits 0:0 + U32 Channel_Error_Status_1 : 1; // Bits 1:1 + U32 : 14; // Bits 15:2 + U32 Channel_Test_Done_Status_0 : 1; // Bits 16:16 + U32 Channel_Test_Done_Status_1 : 1; // Bits 17:17 + U32 : 14; // Bits 31:18 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 10; // Bits 17:8 + U32 : 2; // Bits 19:18 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 8; // Bits 15:8 + U32 : 4; // Bits 19:16 + U32 Subsequence_Type : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 25:25 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 28:27 + U32 : 1; // Bits 29:29 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_STRUCT_HSW_A0; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_STRUCT; + +typedef union { + struct { + U32 Number_of_Cachelines : 7; // Bits 6:0 + U32 Number_of_Cachelines_Scale : 1; // Bits 7:7 + U32 Subsequence_Wait : 14; // Bits 21:8 + U32 Subsequence_Type : 4; // Bits 25:22 + U32 Save_Current_Base_Address_To_Start : 1; // Bits 26:26 + U32 Reset_Current_Base_Address_To_Start : 1; // Bits 27:27 + U32 Data_and_ECC_Address_Inversion : 2; // Bits 29:28 + U32 Invert_Data_and_ECC : 1; // Bits 30:30 + U32 Stop_Base_Subsequence_On_Wrap_Trigger : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_STRUCT; + +typedef union { + struct { + U32 Offset_Address_Update_Rate : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 Base_Subsequence_Repeat_Rate : 5; // Bits 12:8 + U32 : 2; // Bits 14:13 + U32 Column_Offset_Wrap_Trigger_Enable : 1; // Bits 15:15 + U32 Row_Offset_Wrap_Trigger_Enable : 1; // Bits 16:16 + U32 : 3; // Bits 19:17 + U32 Base_Subsequence_Type : 1; // Bits 20:20 + U32 CADB_Deselect_Enable : 1; // Bits 21:21 + U32 CADB_Select_Enable : 1; // Bits 22:22 + U32 CADB_Seeds_Save_Enable : 1; // Bits 23:23 + U32 Column_Increment_Order : 1; // Bits 24:24 + U32 : 1; // Bits 25:25 + U32 Column_Increment_Enable : 1; // Bits 26:26 + U32 Row_Increment_Order : 1; // Bits 27:27 + U32 : 1; // Bits 28:28 + U32 Row_Increment_Enable : 1; // Bits 29:29 + U32 Base_Invert_Data_and_ECC : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Stop_Base_Sequence_On_Wrap_Trigger : 1; // Bits 3:3 + U32 : 1; // Bits 4:4 + U32 Address_Update_Rate_Mode : 1; // Bits 5:5 + U32 : 1; // Bits 6:6 + U32 Enable_Dummy_Reads : 1; // Bits 7:7 + U32 : 2; // Bits 9:8 + U32 Enable_Constant_Write_Strobe : 1; // Bits 10:10 + U32 Global_Control : 1; // Bits 11:11 + U32 Initialization_Mode : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Loopcount : 5; // Bits 20:16 ** Does not exist in C0 ** + U32 : 3; // Bits 23:21 + U32 Subsequence_Start_Pointer : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Subsequence_End_Pointer : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + U32 Start_Test_Delay : 10; // Bits 41:32 + U32 : 22; // Bits 63:42 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Stop_Base_Sequence_On_Wrap_Trigger : 1; // Bits 3:3 + U32 : 1; // Bits 4:4 + U32 Address_Update_Rate_Mode : 1; // Bits 5:5 + U32 : 1; // Bits 6:6 + U32 Enable_Dummy_Reads : 1; // Bits 7:7 + U32 : 2; // Bits 9:8 + U32 Enable_Constant_Write_Strobe : 1; // Bits 10:10 + U32 Global_Control : 1; // Bits 11:11 + U32 Initialization_Mode : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Loopcount : 5; // Bits 20:16 ** Does not exist in C0 ** + U32 : 3; // Bits 23:21 + U32 Subsequence_Start_Pointer : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Subsequence_End_Pointer : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + U32 Start_Test_Delay : 10; // Bits 41:32 + U32 : 22; // Bits 63:42 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Local_Start_Test : 1; // Bits 0:0 + U32 Local_Stop_Test : 1; // Bits 1:1 + U32 Local_Clear_Errors : 1; // Bits 2:2 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Local_Start_Test : 1; // Bits 0:0 + U32 Local_Stop_Test : 1; // Bits 1:1 + U32 Local_Clear_Errors : 1; // Bits 2:2 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Current_Loopcount : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Current_Loopcount : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Current_Subsequence_Pointer : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Current_Subsequence_Pointer : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Current_Cacheline : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Current_Cacheline : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 3; // Bits 58:56 + U32 : 5; // Bits 63:59 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 3; // Bits 58:56 + U32 : 5; // Bits 63:59 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 3; // Bits 58:56 + U32 : 5; // Bits 63:59 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 3; // Bits 58:56 + U32 : 5; // Bits 63:59 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 3; // Bits 58:56 + U32 : 5; // Bits 63:59 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 3; // Bits 58:56 + U32 : 5; // Bits 63:59 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Base_Column_Address_Order : 2; // Bits 1:0 + U32 Base_Row_Address_Order : 2; // Bits 3:2 + U32 Base_Bank_Address_Order : 2; // Bits 5:4 + U32 Base_Rank_Address_Order : 2; // Bits 7:6 + U32 : 5; // Bits 12:8 + U32 Base_Address_Invert_Rate : 3; // Bits 15:13 + U32 : 4; // Bits 19:16 + U32 Column_Base_Address_Invert_Enable : 1; // Bits 20:20 + U32 Row_Base_Address_Invert_Enable : 1; // Bits 21:21 + U32 Bank_Base_Address_Invert_Enable : 1; // Bits 22:22 + U32 Rank_Base_Address_Invert_Enable : 1; // Bits 23:23 + U32 Column_Base_Wrap_Trigger_Enable : 1; // Bits 24:24 + U32 Row_Base_Wrap_Trigger_Enable : 1; // Bits 25:25 + U32 Bank_Base_Wrap_Trigger_Enable : 1; // Bits 26:26 + U32 Rank_Base_Wrap_Trigger_Enable : 1; // Bits 27:27 + U32 Column_Base_Wrap_Carry_Enable : 1; // Bits 28:28 + U32 Row_Base_Wrap_Carry_Enable : 1; // Bits 29:29 + U32 Bank_Base_Wrap_Carry_Enable : 1; // Bits 30:30 + U32 Rank_Base_Wrap_Carry_Enable : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Base_Column_Address_Order : 2; // Bits 1:0 + U32 Base_Row_Address_Order : 2; // Bits 3:2 + U32 Base_Bank_Address_Order : 2; // Bits 5:4 + U32 Base_Rank_Address_Order : 2; // Bits 7:6 + U32 : 5; // Bits 12:8 + U32 Base_Address_Invert_Rate : 3; // Bits 15:13 + U32 : 4; // Bits 19:16 + U32 Column_Base_Address_Invert_Enable : 1; // Bits 20:20 + U32 Row_Base_Address_Invert_Enable : 1; // Bits 21:21 + U32 Bank_Base_Address_Invert_Enable : 1; // Bits 22:22 + U32 Rank_Base_Address_Invert_Enable : 1; // Bits 23:23 + U32 Column_Base_Wrap_Trigger_Enable : 1; // Bits 24:24 + U32 Row_Base_Wrap_Trigger_Enable : 1; // Bits 25:25 + U32 Bank_Base_Wrap_Trigger_Enable : 1; // Bits 26:26 + U32 Rank_Base_Wrap_Trigger_Enable : 1; // Bits 27:27 + U32 Column_Base_Wrap_Carry_Enable : 1; // Bits 28:28 + U32 Row_Base_Wrap_Carry_Enable : 1; // Bits 29:29 + U32 Bank_Base_Wrap_Carry_Enable : 1; // Bits 30:30 + U32 Rank_Base_Wrap_Carry_Enable : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Base_Address_Increment : 8; // Bits 10:3 + U32 : 1; // Bits 11:11 + U32 Column_Base_Address_Update_Rate : 5; // Bits 16:12 + U32 : 2; // Bits 18:17 + U32 Column_Base_Address_Update_Scale : 1; // Bits 19:19 + U32 Row_Base_Address_Increment : 12; // Bits 31:20 + U32 Row_Base_Address_Update_Rate : 4; // Bits 35:32 + U32 : 1; // Bits 36:36 + U32 Row_Base_Address_Update_Scale : 1; // Bits 37:37 + U32 Bank_Base_Address_Increment : 3; // Bits 40:38 + U32 : 3; // Bits 43:41 + U32 Bank_Base_Address_Update_Rate : 5; // Bits 48:44 + U32 : 2; // Bits 50:49 + U32 Bank_Base_Address_Update_Scale : 1; // Bits 51:51 + U32 Rank_Base_Address_Increment : 3; // Bits 54:52 + U32 : 1; // Bits 55:55 + U32 Rank_Base_Address_Update_Rate : 5; // Bits 60:56 + U32 : 2; // Bits 62:61 + U32 Rank_Base_Address_Update_Scale : 1; // Bits 63:63 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Base_Address_Increment : 8; // Bits 10:3 + U32 : 1; // Bits 11:11 + U32 Column_Base_Address_Update_Rate : 5; // Bits 16:12 + U32 : 2; // Bits 18:17 + U32 Column_Base_Address_Update_Scale : 1; // Bits 19:19 + U32 Row_Base_Address_Increment : 12; // Bits 31:20 + U32 Row_Base_Address_Update_Rate : 4; // Bits 35:32 + U32 : 1; // Bits 36:36 + U32 Row_Base_Address_Update_Scale : 1; // Bits 37:37 + U32 Bank_Base_Address_Increment : 3; // Bits 40:38 + U32 : 3; // Bits 43:41 + U32 Bank_Base_Address_Update_Rate : 5; // Bits 48:44 + U32 : 2; // Bits 50:49 + U32 Bank_Base_Address_Update_Scale : 1; // Bits 51:51 + U32 Rank_Base_Address_Increment : 3; // Bits 54:52 + U32 : 1; // Bits 55:55 + U32 Rank_Base_Address_Update_Rate : 5; // Bits 60:56 + U32 : 2; // Bits 62:61 + U32 Rank_Base_Address_Update_Scale : 1; // Bits 63:63 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 24; // Bits 63:40 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 : 3; // Bits 2:0 + U32 Column_Address : 8; // Bits 10:3 + U32 : 13; // Bits 23:11 + U32 Row_Address : 16; // Bits 39:24 + U32 : 24; // Bits 63:40 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Logical_to_Physical_Rank0_Mapping : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 Logical_to_Physical_Rank1_Mapping : 2; // Bits 5:4 + U32 : 2; // Bits 7:6 + U32 Logical_to_Physical_Rank2_Mapping : 2; // Bits 9:8 + U32 : 2; // Bits 11:10 + U32 Logical_to_Physical_Rank3_Mapping : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Logical_to_Physical_Rank4_Mapping : 2; // Bits 17:16 + U32 : 2; // Bits 19:18 + U32 Logical_to_Physical_Rank5_Mapping : 2; // Bits 21:20 + U32 : 2; // Bits 23:22 + U32 Logical_to_Physical_Rank6_Mapping : 2; // Bits 25:24 + U32 : 2; // Bits 27:26 + U32 Logical_to_Physical_Rank7_Mapping : 2; // Bits 29:28 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Logical_to_Physical_Rank0_Mapping : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 Logical_to_Physical_Rank1_Mapping : 2; // Bits 5:4 + U32 : 2; // Bits 7:6 + U32 Logical_to_Physical_Rank2_Mapping : 2; // Bits 9:8 + U32 : 2; // Bits 11:10 + U32 Logical_to_Physical_Rank3_Mapping : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Logical_to_Physical_Rank4_Mapping : 2; // Bits 17:16 + U32 : 2; // Bits 19:18 + U32 Logical_to_Physical_Rank5_Mapping : 2; // Bits 21:20 + U32 : 2; // Bits 23:22 + U32 Logical_to_Physical_Rank6_Mapping : 2; // Bits 25:24 + U32 : 2; // Bits 27:26 + U32 Logical_to_Physical_Rank7_Mapping : 2; // Bits 29:28 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Logical_to_Physical_Row0_Swizzle : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 Logical_to_Physical_Row1_Swizzle : 4; // Bits 8:5 + U32 : 1; // Bits 9:9 + U32 Logical_to_Physical_Row2_Swizzle : 4; // Bits 13:10 + U32 : 1; // Bits 14:14 + U32 Logical_to_Physical_Row3_Swizzle : 4; // Bits 18:15 + U32 : 1; // Bits 19:19 + U32 Logical_to_Physical_Row4_Swizzle : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Logical_to_Physical_Row5_Swizzle : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Logical_to_Physical_Row0_Swizzle : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 Logical_to_Physical_Row1_Swizzle : 4; // Bits 8:5 + U32 : 1; // Bits 9:9 + U32 Logical_to_Physical_Row2_Swizzle : 4; // Bits 13:10 + U32 : 1; // Bits 14:14 + U32 Logical_to_Physical_Row3_Swizzle : 4; // Bits 18:15 + U32 : 1; // Bits 19:19 + U32 Logical_to_Physical_Row4_Swizzle : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Logical_to_Physical_Row5_Swizzle : 4; // Bits 28:25 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Logical_to_Physical_Row6_Swizzle : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 Logical_to_Physical_Row7_Swizzle : 4; // Bits 8:5 + U32 : 1; // Bits 9:9 + U32 Logical_to_Physical_Row8_Swizzle : 4; // Bits 13:10 + U32 : 1; // Bits 14:14 + U32 Logical_to_Physical_Row9_Swizzle : 4; // Bits 18:15 + U32 : 1; // Bits 19:19 + U32 Logical_to_Physical_Row10_Swizzle : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Logical_to_Physical_Row11_Swizzle : 4; // Bits 28:25 + U32 : 1; // Bits 29:29 + U32 Logical_to_Physical_Row12_Swizzle : 4; // Bits 33:30 + U32 : 1; // Bits 34:34 + U32 Logical_to_Physical_Row13_Swizzle : 4; // Bits 38:35 + U32 : 1; // Bits 39:39 + U32 Logical_to_Physical_Row14_Swizzle : 4; // Bits 43:40 + U32 : 1; // Bits 44:44 + U32 Logical_to_Physical_Row15_Swizzle : 4; // Bits 48:45 + U32 : 15; // Bits 63:49 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Logical_to_Physical_Row6_Swizzle : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 Logical_to_Physical_Row7_Swizzle : 4; // Bits 8:5 + U32 : 1; // Bits 9:9 + U32 Logical_to_Physical_Row8_Swizzle : 4; // Bits 13:10 + U32 : 1; // Bits 14:14 + U32 Logical_to_Physical_Row9_Swizzle : 4; // Bits 18:15 + U32 : 1; // Bits 19:19 + U32 Logical_to_Physical_Row10_Swizzle : 4; // Bits 23:20 + U32 : 1; // Bits 24:24 + U32 Logical_to_Physical_Row11_Swizzle : 4; // Bits 28:25 + U32 : 1; // Bits 29:29 + U32 Logical_to_Physical_Row12_Swizzle : 4; // Bits 33:30 + U32 : 1; // Bits 34:34 + U32 Logical_to_Physical_Row13_Swizzle : 4; // Bits 38:35 + U32 : 1; // Bits 39:39 + U32 Logical_to_Physical_Row14_Swizzle : 4; // Bits 43:40 + U32 : 1; // Bits 44:44 + U32 Logical_to_Physical_Row15_Swizzle : 4; // Bits 48:45 + U32 : 15; // Bits 63:49 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Dummy_Read_Row_Current_Address : 16; // Bits 15:0 + U32 : 8; // Bits 23:16 + U32 Dummy_Read_Bank_Current_Address : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Dummy_Read_Row_Current_Address : 16; // Bits 15:0 + U32 : 8; // Bits 23:16 + U32 Dummy_Read_Bank_Current_Address : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 Dummy_Read_Bank_Mask : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Dummy_Read_Bank_Mask : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 L_DummyRead_Select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_Counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 L_DummyRead_Select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_Counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 EN_CLK : 1; // Bits 0:0 + U32 L0_DATA_BYTE_SEL : 7; // Bits 7:1 + U32 L0_BYP_SEL : 1; // Bits 8:8 + U32 L1_DATA_BYTE_SEL : 7; // Bits 15:9 + U32 L1_BYP_SEL : 1; // Bits 16:16 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Trigger_In_Global_Start : 1; // Bits 0:0 + U32 Trigger_Out_Global_Start : 1; // Bits 1:1 + U32 : 5; // Bits 6:2 + U32 Trigger_Out_On_Error_0 : 1; // Bits 7:7 + U32 Trigger_Out_On_Error_1 : 1; // Bits 8:8 + U32 : 6; // Bits 14:9 + U32 Trigger_Out_On_Channel_Test_Done_Status_0: 1; // Bits 15:15 + U32 Trigger_Out_On_Channel_Test_Done_Status_1: 1; // Bits 16:16 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Loopcount_Limit : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_STRUCT; + +typedef union { + struct { + U32 Loopcount_Limit : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_STRUCT; + +typedef union { + struct { + U32 tRCD : 5; // Bits 4:0 + U32 tRP : 5; // Bits 9:5 + U32 tRAS : 6; // Bits 15:10 + U32 tRDPRE : 4; // Bits 19:16 + U32 tWRPRE : 6; // Bits 25:20 + U32 tRRD : 4; // Bits 29:26 + U32 tRPab_ext : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_TC_BANK_STRUCT; + +typedef union { + struct { + U32 tCKE : 4; // Bits 3:0 + U32 tFAW : 8; // Bits 11:4 + U32 tRDRD : 3; // Bits 14:12 + U32 tRDRD_dr : 4; // Bits 18:15 + U32 tRDRD_dd : 4; // Bits 22:19 + U32 tRDPDEN : 5; // Bits 27:23 + U32 : 1; // Bits 28:28 + U32 CMD_3st : 1; // Bits 29:29 + U32 CMD_stretch : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_TC_BANK_RANK_A_STRUCT; + +typedef union { + struct { + U32 tWRRD : 6; // Bits 5:0 + U32 tWRRD_dr : 4; // Bits 9:6 + U32 tWRRD_dd : 4; // Bits 13:10 + U32 tWRWR : 3; // Bits 16:14 + U32 tWRWR_dr : 4; // Bits 20:17 + U32 tWRWR_dd : 4; // Bits 24:21 + U32 tWRPDEN : 6; // Bits 30:25 + U32 Dec_WRD : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_TC_BANK_RANK_B_STRUCT; + +typedef union { + struct { + U32 tXPDLL : 6; // Bits 5:0 + U32 tXP : 4; // Bits 9:6 + U32 TAONPD : 4; // Bits 13:10 + U32 tRDWR : 5; // Bits 18:14 + U32 tRDWR_dr : 5; // Bits 23:19 + U32 tRDWR_dd : 5; // Bits 28:24 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_TC_BANK_RANK_C_STRUCT; + +typedef union { + struct { + U32 enable_cmd_rate_limit : 1; // Bits 0:0 + U32 cmd_rate_limit : 3; // Bits 3:1 + U32 reset_on_command : 4; // Bits 7:4 + U32 reset_delay : 4; // Bits 11:8 + U32 ck_to_cke_delay : 2; // Bits 13:12 + U32 spare : 17; // Bits 30:14 + U32 init_mrw_2n_cs : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_CMD_RATE_STRUCT; + +typedef union { + struct { + U32 tCL : 5; // Bits 4:0 + U32 tWCL : 5; // Bits 9:5 + U32 tCPDED : 2; // Bits 11:10 + U32 tPRPDEN : 2; // Bits 13:12 + U32 Odt_Read_Delay : 3; // Bits 16:14 + U32 Odt_Read_Duration : 2; // Bits 18:17 + U32 Odt_Write_Duration : 2; // Bits 20:19 + U32 : 11; // Bits 31:21 + } Bits; +#ifdef ULT_FLAG + struct { + U32 tCL : 5; // Bits 4:0 + U32 tWCL : 5; // Bits 9:5 + U32 tCPDED : 2; // Bits 11:10 + U32 tPRPDEN : 2; // Bits 13:12 + U32 Odt_Read_Delay : 3; // Bits 16:14 + U32 Odt_Read_Duration : 2; // Bits 18:17 + U32 Odt_Write_Duration : 3; // Bits 21:19 + U32 Odt_Write_Delay : 3; // Bits 24:22 + U32 Odt_Always_Rank0 : 1; // Bits 25:25 + U32 cmd_delay : 2; // Bits 27:26 + U32 : 4; // Bits 31:28 + } UltBits; +#endif //ULT_FLAG + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_TC_BANK_RANK_D_STRUCT; + +typedef union { + struct { + U32 dis_opp_cas : 1; // Bits 0:0 + U32 dis_opp_is_cas : 1; // Bits 1:1 + U32 dis_opp_ras : 1; // Bits 2:2 + U32 dis_opp_is_ras : 1; // Bits 3:3 + U32 dis_1c_byp : 1; // Bits 4:4 + U32 dis_2c_byp : 1; // Bits 5:5 + U32 dis_deprd_opt : 1; // Bits 6:6 + U32 dis_pt_it : 1; // Bits 7:7 + U32 dis_prcnt_ring : 1; // Bits 8:8 + U32 dis_prcnt_sa : 1; // Bits 9:9 + U32 dis_blkr_ph : 1; // Bits 10:10 + U32 dis_blkr_pe : 1; // Bits 11:11 + U32 dis_blkr_pm : 1; // Bits 12:12 + U32 dis_odt : 1; // Bits 13:13 + U32 OE_alw_off : 1; // Bits 14:14 + U32 : 1; // Bits 15:15 + U32 dis_aom : 1; // Bits 16:16 + U32 block_rpq : 1; // Bits 17:17 + U32 block_wpq : 1; // Bits 18:18 + U32 invert_align : 1; // Bits 19:19 + U32 dis_write_gap : 1; // Bits 20:20 + U32 dis_zq : 1; // Bits 21:21 + U32 dis_tt : 1; // Bits 22:22 + U32 dis_opp_ref : 1; // Bits 23:23 + U32 Long_ZQ : 1; // Bits 24:24 + U32 dis_srx_zq : 1; // Bits 25:25 + U32 Serialize_ZQ : 1; // Bits 26:26 + U32 ZQ_fast_exec : 1; // Bits 27:27 + U32 Dis_DriveNop : 1; // Bits 28:28 + U32 Pres_WDB_Ent : 1; // Bits 29:29 + U32 dis_clk_gate : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SCHED_CBIT_STRUCT; + +typedef union { + struct { + U32 Lat_R0D0 : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 Lat_R1D0 : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 Lat_R0D1 : 6; // Bits 21:16 + U32 : 2; // Bits 23:22 + U32 Lat_R1D1 : 6; // Bits 29:24 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SC_ROUNDT_LAT_STRUCT; + +typedef union { + struct { + U32 IOLAT_R0D0 : 4; // Bits 3:0 + U32 IOLAT_R1D0 : 4; // Bits 7:4 + U32 IOLAT_R0D1 : 4; // Bits 11:8 + U32 IOLAT_R1D1 : 4; // Bits 15:12 + U32 RT_IOCOMP : 6; // Bits 21:16 + U32 : 8; // Bits 29:22 + U32 three_channels : 1; // Bits 30:30 + U32 DIS_RT_CLK_GATE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SC_IO_LATENCY_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_STRUCT; + +typedef union { + struct { + U32 WDAR : 1; // Bits 0:0 + U32 safe_mask_sel : 3; // Bits 3:1 + U32 force_rcv_en : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 DDR_QUAL : 2; // Bits 9:8 + U32 Qual_length : 2; // Bits 11:10 + U32 WDB_Block_En : 1; // Bits 12:12 + U32 RT_DFT_READ_PTR : 4; // Bits 16:13 + U32 RT_DFT_READ_ENABLE : 1; // Bits 17:17 + U32 RT_DFT_READ_SEL_ADDR : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_DFT_MISC_STRUCT; + +typedef union { + struct { + U32 ECC : 8; // Bits 7:0 + U32 RRD_DFT_Mode : 2; // Bits 9:8 + U32 LFSR_Seed_Index : 5; // Bits 14:10 + U32 Inversion_Mode : 1; // Bits 15:15 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_READ_RETURN_DFT_STRUCT; + +typedef union { + struct { + U32 dis_imph_error : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 dis_async_odt : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SCHED_SECOND_CBIT_STRUCT; + +typedef union { + struct { + U32 Mux0_Control : 2; // Bits 1:0 + U32 : 1; // Bits 2:2 + U32 Mux1_Control : 2; // Bits 4:3 + U32 : 1; // Bits 5:5 + U32 Mux2_Control : 2; // Bits 7:6 + U32 : 6; // Bits 13:8 + U32 ECC_Replace_Byte_Control : 1; // Bits 14:14 + U32 ECC_Data_Source_Sel : 1; // Bits 15:15 + U32 Save_LFSR_Seed_Rate : 6; // Bits 21:16 + U32 : 2; // Bits 23:22 + U32 Reload_LFSR_Seed_Rate : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT; + +typedef union { + struct { + U32 WDB_Current_Read_Pointer : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_STRUCT; + +typedef union { + struct { + U32 L_data_select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_STRUCT; + +typedef union { + struct { + U32 ECC_Inv_or_DC_Enable : 8; // Bits 7:0 + U32 : 8; // Bits 15:8 + U32 Inv_or_DC_Shift_Rate : 4; // Bits 19:16 + U32 DC_Polarity_Control : 1; // Bits 20:20 + U32 : 9; // Bits 29:21 + U32 Inv_or_DC_Control : 1; // Bits 30:30 + U32 Inv_or_DC_Shift_Enable : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_STRUCT; + +typedef union { + struct { + U64 Data_Inv_or_DC_Enable : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_STRUCT; + +typedef union { + struct { + U32 Stop_on_Nth_Error : 6; // Bits 5:0 + U32 : 6; // Bits 11:6 + U32 Stop_On_Error_Control : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Selective_Error_Enable_Chunk : 8; // Bits 23:16 + U32 Selective_Error_Enable_Cacheline : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_CTL_STRUCT; + +typedef union { + struct { + U32 ECC_Error_Mask : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_STRUCT; + +typedef union { + struct { + U32 Stretch_mode : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 STF : 3; // Bits 6:4 + U32 : 25; // Bits 31:7 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_STM_CONFIG_STRUCT; + +typedef union { + struct { + U32 Priority_count_ring : 10; // Bits 9:0 + U32 : 6; // Bits 15:10 + U32 Priority_count_SA : 10; // Bits 25:16 + U32 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SC_PR_CNT_CONFIG_STRUCT; + +typedef union { + struct { + U32 PCIT : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SC_PCIT_STRUCT; + +typedef union { + struct { + U32 PDWN_idle_counter : 12; // Bits 11:0 + U32 PDWN_mode : 4; // Bits 15:12 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_PM_PDWN_CONFIG_STRUCT; + +typedef union { + struct { + U32 Count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_ECC_INJECT_COUNT_STRUCT; + +typedef union { + struct { + U32 ECC4ANA_fill : 8; // Bits 7:0 + U32 ECC4ANA_trigger : 2; // Bits 9:8 + U32 ECC4ANA_BS : 1; // Bits 10:10 + U32 ECC_Inject : 3; // Bits 13:11 + U32 ECC_correction_disable : 1; // Bits 14:14 + U32 ECC4ANA_Inject : 1; // Bits 15:15 + U32 DIS_MCA_LOG : 1; // Bits 16:16 + U32 DIS_PCH_EVENT : 1; // Bits 17:17 + U32 DIS_PCIE_POISON : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_ECC_DFT_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_VISA_CTL_MCSCHEDS_STRUCT; + +typedef union { + struct { + U32 Data : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_STRUCT; + +typedef union { + struct { + U32 CERRSTS : 1; // Bits 0:0 + U32 MERRSTS : 1; // Bits 1:1 + U32 : 14; // Bits 15:2 + U32 ERRSYND : 8; // Bits 23:16 + U32 ERRCHUNK : 3; // Bits 26:24 + U32 ERRRANK : 2; // Bits 28:27 + U32 ERRBANK : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_ECCERRLOG0_STRUCT; + +typedef union { + struct { + U32 ERRROW : 16; // Bits 15:0 + U32 ERRCOL : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_ECCERRLOG1_STRUCT; + +typedef union { + struct { + U32 D0R0 : 2; // Bits 1:0 + U32 D0R1 : 2; // Bits 3:2 + U32 D1R0 : 2; // Bits 5:4 + U32 D1R1 : 2; // Bits 7:6 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_SC_WR_ADD_DELAY_STRUCT; + +typedef union { + struct { + U32 Dis_Opp_rd : 1; // Bits 0:0 + U32 ACT_Enable : 1; // Bits 1:1 + U32 PRE_Enable : 1; // Bits 2:2 + U32 MAX_RPQ_Cas : 4; // Bits 6:3 + U32 : 25; // Bits 31:7 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_WMM_READ_CONFIG_STRUCT; + +typedef union { + struct { + U64 Data_Error_Mask : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_STRUCT; + +typedef union { + struct { + U64 Data_Error_Status : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_STRUCT; + +typedef union { + struct { + U32 ECC_Error_Status : 8; // Bits 7:0 + U32 Chunk_Error_Status : 8; // Bits 15:8 + U32 Rank_Error_Status : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + U32 Byte_Group_Error_Status : 9; // Bits 40:32 + U32 : 11; // Bits 51:41 + U32 WDB_Rd_Chunk_Num_Status : 3; // Bits 54:52 + U32 : 1; // Bits 55:55 + U32 Nth_Error : 6; // Bits 61:56 + U32 : 2; // Bits 63:62 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_STRUCT; + +typedef union { + struct { + U32 Counter_Overflow_Status : 9; // Bits 8:0 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_STRUCT; + +typedef union { + struct { + U32 Column_Address : 10; // Bits 9:0 + U32 : 14; // Bits 23:10 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 2; // Bits 57:56 + U32 : 6; // Bits 63:58 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCSCHEDS_CR_REUT_CH_ERROR_ADDR_STRUCT; + +typedef union { + struct { + U32 WDB_Current_Error_Pointer : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_STRUCT; + +typedef union { + struct { + U32 Enable_WDB_Error_Capture : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 WDB_Starting_Error_Pointer : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 WDB_Ending_Error_Pointer : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_STRUCT; + +typedef union { + struct { + U32 CKE_Override : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 CKE_En_Start_Test_Sync : 1; // Bits 8:8 + U32 : 7; // Bits 15:9 + U32 CKE_On : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_STRUCT; + +typedef union { + struct { + U32 ODT_Override : 4; // Bits 3:0 + U32 : 12; // Bits 15:4 + U32 ODT_On : 4; // Bits 19:16 + U32 : 11; // Bits 30:20 + U32 MPR_Train_DDR_On : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_STRUCT; + +typedef union { + struct { + U32 Enable_CADB_on_Deselect : 1; // Bits 0:0 + U32 Enable_CADB_Always_On : 1; // Bits 1:1 + U32 CMD_Deselect_Start : 4; // Bits 5:2 + U32 CMD_Deselect_Stop : 4; // Bits 9:6 + U32 Lane_Deselect_Enable : 4; // Bits 13:10 + U32 CAS_Select_Enable : 2; // Bits 15:14 + U32 ACT_Select_Enable : 2; // Bits 17:16 + U32 PRE_Select_Enable : 2; // Bits 19:18 + U32 Save_Current_Seed : 4; // Bits 23:20 + U32 Reload_Starting_Seed : 4; // Bits 27:24 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_STRUCT; + +typedef union { + struct { + U32 MRS_Gap : 3; // Bits 2:0 + U32 : 5; // Bits 7:3 + U32 CADB_MRS_Start_Pointer : 3; // Bits 10:8 + U32 : 5; // Bits 15:11 + U32 CADB_MRS_End_Pointer : 3; // Bits 18:16 + U32 : 5; // Bits 23:19 + U32 CADB_MRS_Current_Pointer : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_STRUCT; + +typedef union { + struct { + U32 Mux0_Control : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 Mux1_Control : 2; // Bits 5:4 + U32 : 2; // Bits 7:6 + U32 Mux2_Control : 2; // Bits 9:8 + U32 : 6; // Bits 15:10 + U32 Select_Mux0_Control : 2; // Bits 17:16 + U32 : 2; // Bits 19:18 + U32 Select_Mux1_Control : 2; // Bits 21:20 + U32 : 2; // Bits 23:22 + U32 Select_Mux2_Control : 2; // Bits 25:24 + U32 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_STRUCT; + +typedef union { + struct { + U32 L_data_select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_STRUCT; + +typedef union { + struct { + U32 CADB_Write_Pointer : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_STRUCT; + +typedef union { + struct { + U32 CADB_Data_Address : 16; // Bits 15:0 + U32 : 8; // Bits 23:16 + U32 CADB_Data_Bank : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + U32 CADB_Data_CS : 4; // Bits 35:32 + U32 : 4; // Bits 39:36 + U32 CADB_Data_Control : 3; // Bits 42:40 + U32 : 5; // Bits 47:43 + U32 CADB_Data_ODT : 4; // Bits 51:48 + U32 : 4; // Bits 55:52 + U32 CADB_Data_CKE : 4; // Bits 59:56 + U32 : 4; // Bits 63:60 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_STRUCT; + +typedef union { + struct { + U32 WDB_Increment_Rate : 5; // Bits 4:0 + U32 WDB_Increment_Scale : 1; // Bits 5:5 + U32 : 2; // Bits 7:6 + U32 WDB_Start_Pointer : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 WDB_End_Pointer : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT; + +typedef union { + struct { + U32 Refresh_Rank_Mask : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 RefZQ_En_Start_Test_Sync : 1; // Bits 8:8 + U32 : 22; // Bits 30:9 + U32 Panic_Refresh_Only : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_STRUCT; + +typedef union { + struct { + U32 ZQ_Rank_Mask : 4; // Bits 3:0 + U32 : 27; // Bits 30:4 + U32 Always_Do_ZQ : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_STRUCT; + +#ifdef ULT_FLAG +typedef union { + struct { + U32 Rank_0_x32 : 1; // Bits 0:0 + U32 Rank_1_x32 : 1; // Bits 1:1 + U32 Rank_2_x32 : 1; // Bits 2:2 + U32 Rank_3_x32 : 1; // Bits 3:3 + U32 LPDDR2 : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 MR4_PERIOD : 16; // Bits 23:8 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_LPDDR_MR_PARAMS_STRUCT; + +typedef union { + struct { + U32 Address : 8; // Bits 7:0 + U32 Data : 8; // Bits 15:8 + U32 Rank : 2; // Bits 17:16 + U32 Write : 1; // Bits 18:18 + U32 Init_MRW : 1; // Bits 19:19 + U32 : 11; // Bits 30:20 + U32 Busy : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_LPDDR_MR_COMMAND_STRUCT; + +typedef union { + struct { + U32 Device_0 : 8; // Bits 7:0 + U32 Device_1 : 8; // Bits 15:8 + U32 Device_2 : 8; // Bits 23:16 + U32 Device_3 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_LPDDR_MR_RESULT_STRUCT; + +typedef union { + struct { + U32 Rank_0 : 3; // Bits 2:0 + U32 : 5; // Bits 7:3 + U32 Rank_1 : 3; // Bits 10:8 + U32 : 5; // Bits 15:11 + U32 Rank_2 : 3; // Bits 18:16 + U32 : 5; // Bits 23:19 + U32 Rank_3 : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_STRUCT; + +typedef union { + struct { + U32 Bit_0 : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 Bit_1 : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 Bit_2 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 Bit_16 : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 Bit_17 : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 Bit_18 : 3; // Bits 22:20 + U32 : 1; // Bits 23:23 + U32 Byte_0 : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Byte_2 : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_DESWIZZLE_LOW_STRUCT; + +typedef union { + struct { + U32 Bit_32 : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 Bit_33 : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 Bit_34 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 Bit_48 : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 Bit_49 : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 Bit_50 : 3; // Bits 22:20 + U32 : 1; // Bits 23:23 + U32 Byte_4 : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Byte_6 : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_DESWIZZLE_HIGH_STRUCT; +#endif // ULT_FLAG + +typedef union { + struct { + U32 Ref_Interval : 11; // Bits 10:0 + U32 Ref_Stagger_En : 1; // Bits 11:11 + U32 Ref_Stagger_Mode : 1; // Bits 12:12 + U32 Disable_Stolen_Refresh : 1; // Bits 13:13 + U32 En_Ref_Type_Display : 1; // Bits 14:14 + U32 : 17; // Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_MC_REFRESH_STAGGER_STRUCT; + +typedef union { + struct { + U32 ZQCS_period : 8; // Bits 7:0 + U32 tZQCS : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; +#ifdef ULT_FLAG + struct { + U32 ZQCS_period : 10; // Bits 9:0 + U32 tZQCS : 10; // Bits 19:10 + U32 : 12; // Bits 31:20 + } UltBits; +#endif // ULT_FLAG + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_TC_ZQCAL_STRUCT; + +typedef union { + struct { + U32 OREF_RI : 8; // Bits 7:0 + U32 Refresh_HP_WM : 4; // Bits 11:8 + U32 Refresh_panic_wm : 4; // Bits 15:12 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_TC_RFP_STRUCT; + +typedef union { + struct { + U32 tREFI : 16; // Bits 15:0 + U32 tRFC : 9; // Bits 24:16 + U32 tREFIx9 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_TC_RFTP_STRUCT; + +typedef union { + struct { + U32 MR2_sh_low : 6; // Bits 5:0 + U32 SRT_avail : 2; // Bits 7:6 + U32 MR2_sh_high : 3; // Bits 10:8 + U32 : 3; // Bits 13:11 + U32 Addr_bit_swizzle : 2; // Bits 15:14 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_TC_MR2_SHADDOW_STRUCT; + +typedef union { + struct { + U32 Rank_occupancy : 4; // Bits 3:0 + U32 : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_MC_INIT_STATE_STRUCT; + +typedef union { + struct { + U32 tXSDLL : 12; // Bits 11:0 + U32 tXS_offset : 4; // Bits 15:12 + U32 tZQOPER : 10; // Bits 25:16 + U32 : 2; // Bits 27:26 + U32 tMOD : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_TC_SRFTP_STRUCT; + +typedef union { + struct { + U32 VISAByteSel : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_WDB_VISA_SEL_STRUCT; + +typedef union { + struct { + U32 FASTADDR : 12; // Bits 11:0 + U32 : 4; // Bits 15:12 + U32 ADDREN : 1; // Bits 16:16 + U32 SEQEN : 1; // Bits 17:17 + U32 POL0 : 1; // Bits 18:18 + U32 POL1 : 1; // Bits 19:19 + U32 CMDA : 4; // Bits 23:20 + U32 CMDB : 4; // Bits 27:24 + U32 CMDC : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_DCLK_LDAT_PDAT_STRUCT; + +typedef union { + struct { + U32 BANKSEL : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 ARRAYSEL : 5; // Bits 9:5 + U32 CMP : 1; // Bits 10:10 + U32 REP : 1; // Bits 11:11 + U32 DWORD : 4; // Bits 15:12 + U32 MODE : 2; // Bits 17:16 + U32 MPMAP : 6; // Bits 23:18 + U32 MPBOFFSET : 4; // Bits 27:24 + U32 STAGE_EN : 1; // Bits 28:28 + U32 SHADOW : 2; // Bits 30:29 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_DCLK_LDAT_SDAT_STRUCT; + +typedef union { + struct { + U32 DATOUT : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_DCLK_LDAT_DATAOUT_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_DCLK_LDAT_DATAIN_0_STRUCT; + +typedef union { + struct { + U32 FASTADDR : 12; // Bits 11:0 + U32 : 4; // Bits 15:12 + U32 ADDREN : 1; // Bits 16:16 + U32 SEQEN : 1; // Bits 17:17 + U32 POL0 : 1; // Bits 18:18 + U32 POL1 : 1; // Bits 19:19 + U32 CMDA : 4; // Bits 23:20 + U32 CMDB : 4; // Bits 27:24 + U32 CMDC : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QCLK_LDAT_PDAT_STRUCT; + +typedef union { + struct { + U32 BANKSEL : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 ARRAYSEL : 5; // Bits 9:5 + U32 CMP : 1; // Bits 10:10 + U32 REP : 1; // Bits 11:11 + U32 DWORD : 4; // Bits 15:12 + U32 MODE : 2; // Bits 17:16 + U32 MPMAP : 6; // Bits 23:18 + U32 MPBOFFSET : 4; // Bits 27:24 + U32 STAGE_EN : 1; // Bits 28:28 + U32 SHADOW : 2; // Bits 30:29 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QCLK_LDAT_SDAT_STRUCT; + +typedef union { + struct { + U32 DATOUT : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QCLK_LDAT_DATAOUT_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QCLK_LDAT_DATAIN_0_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QCLK_LDAT_DATAIN_1_STRUCT; + +typedef union { + struct { + U32 RPQ_disable : 28; // Bits 27:0 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_STRUCT; + +typedef union { + struct { + U32 WPQ_disable : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_STRUCT; + +typedef union { + struct { + U32 DIMM0_IDLE_ENERGY : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 DIMM1_IDLE_ENERGY : 6; // Bits 13:8 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_PM_DIMM_IDLE_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_PD_ENERGY : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 DIMM1_PD_ENERGY : 6; // Bits 13:8 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_PM_DIMM_PD_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_ACT_ENERGY : 8; // Bits 7:0 + U32 DIMM1_ACT_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_PM_DIMM_ACT_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_RD_ENERGY : 8; // Bits 7:0 + U32 DIMM1_RD_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_PM_DIMM_RD_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_WR_ENERGY : 8; // Bits 7:0 + U32 DIMM1_WR_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_PM_DIMM_WR_ENERGY_STRUCT; + +typedef union { + struct { + U32 CKE_MIN : 8; // Bits 7:0 + U32 CKE_MIN_DEFEATURE : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_PM_THRT_CKE_MIN_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MATCH0_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MATCH1_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MATCH2_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MATCH3_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MASK0_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MASK1_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MASK2_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_MASK3_STRUCT; + +typedef union { + struct { + U32 BankMatch0 : 3; // Bits 2:0 + U32 BankMatch1 : 3; // Bits 5:3 + U32 BankMatch2 : 3; // Bits 8:6 + U32 BankMatch3 : 3; // Bits 11:9 + U32 BankMask0 : 3; // Bits 14:12 + U32 BankMask1 : 3; // Bits 17:15 + U32 BankMask2 : 3; // Bits 20:18 + U32 BankMask3 : 3; // Bits 23:21 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_CMD_BANK_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_SEQ_LEVEL0_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_SEQ_LEVEL1_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_SEQ_LEVEL2_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_SEQ_LEVEL3_STRUCT; + +typedef union { + struct { + U32 TriggerBlockEnable : 1; // Bits 0:0 + U32 GlobalCounterThreshold : 16; // Bits 16:1 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_ODLAT_SEQ_GLOBAL_STRUCT; + +typedef union { + struct { + U32 WMM_Enter : 8; // Bits 7:0 + U32 WMM_Exit : 8; // Bits 15:8 + U32 WPQ_IS : 8; // Bits 23:16 + U32 Starve_count : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_SC_WDBWM_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCMNTS_CR_VISA_CTL_MCMNTS_STRUCT; + +typedef union { + struct { + U32 CH_A : 2; // Bits 1:0 + U32 CH_B : 2; // Bits 3:2 + U32 CH_C : 2; // Bits 5:4 + U32 STKD_MODE : 1; // Bits 6:6 + U32 STKD_MODE_CH_BITS : 3; // Bits 9:7 + U32 LPDDR : 1; // Bits 10:10 + U32 : 21; // Bits 31:11 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MAD_CHNL_MCMAIN_STRUCT; + +typedef union { + struct { + U32 DIMM_A_Size : 8; // Bits 7:0 + U32 DIMM_B_Size : 8; // Bits 15:8 + U32 DAS : 1; // Bits 16:16 + U32 DANOR : 1; // Bits 17:17 + U32 DBNOR : 1; // Bits 18:18 + U32 DAW : 1; // Bits 19:19 + U32 DBW : 1; // Bits 20:20 + U32 RI : 1; // Bits 21:21 + U32 Enh_Interleave : 1; // Bits 22:22 + U32 : 1; // Bits 23:23 + U32 ECC : 2; // Bits 25:24 + U32 HORI : 1; // Bits 26:26 + U32 HORIAddr : 3; // Bits 29:27 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MAD_DIMM_CH0_MCMAIN_STRUCT; + +typedef union { + struct { + U32 DIMM_A_Size : 8; // Bits 7:0 + U32 DIMM_B_Size : 8; // Bits 15:8 + U32 DAS : 1; // Bits 16:16 + U32 DANOR : 1; // Bits 17:17 + U32 DBNOR : 1; // Bits 18:18 + U32 DAW : 1; // Bits 19:19 + U32 DBW : 1; // Bits 20:20 + U32 RI : 1; // Bits 21:21 + U32 Enh_Interleave : 1; // Bits 22:22 + U32 : 1; // Bits 23:23 + U32 ECC : 2; // Bits 25:24 + U32 HORI : 1; // Bits 26:26 + U32 HORIAddr : 3; // Bits 29:27 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MAD_DIMM_CH1_MCMAIN_STRUCT; + +typedef union { + struct { + U32 DIMM_A_Size : 8; // Bits 7:0 + U32 DIMM_B_Size : 8; // Bits 15:8 + U32 DAS : 1; // Bits 16:16 + U32 DANOR : 1; // Bits 17:17 + U32 DBNOR : 1; // Bits 18:18 + U32 DAW : 1; // Bits 19:19 + U32 DBW : 1; // Bits 20:20 + U32 RI : 1; // Bits 21:21 + U32 Enh_Interleave : 1; // Bits 22:22 + U32 : 1; // Bits 23:23 + U32 ECC : 2; // Bits 25:24 + U32 HORI : 1; // Bits 26:26 + U32 HORIAddr : 3; // Bits 29:27 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MAD_DIMM_CH2_MCMAIN_STRUCT; + +typedef union { + struct { + U32 OneC : 8; // Bits 7:0 + U32 ThreeC : 8; // Bits 15:8 + U32 TwoBandC : 8; // Bits 23:16 + U32 BandC : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MAD_ZR_MCMAIN_STRUCT; + +typedef union { + struct { + U32 spare : 23; // Bits 22:0 + U32 ovrd_pcu_sr_exit : 1; // Bits 23:23 + U32 isoch_stall_pattern : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MCDECS_MISC_MCMAIN_STRUCT; + +typedef union { + struct { + U32 increase_rcomp : 1; // Bits 0:0 + U32 noa_on_ecc : 1; // Bits 1:1 + U32 noa_demux : 1; // Bits 2:2 + U32 noa_countctrl : 1; // Bits 3:3 + U32 : 4; // Bits 7:4 + U32 psmi_freeze_pwm_counters : 1; // Bits 8:8 + U32 : 6; // Bits 14:9 + U32 dis_lp_prefetch : 1; // Bits 15:15 + U32 : 13; // Bits 28:16 + U32 dis_reg_clk_gate : 1; // Bits 29:29 + U32 dis_msg_clk_gate : 1; // Bits 30:30 + U32 dis_clk_gate : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MCDECS_CBIT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 4; // Bits 3:0 + U32 : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_SC_IS_CREDIT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Mask : 14; // Bits 13:0 + U32 : 7; // Bits 20:14 + U32 LSB_mask_bit : 2; // Bits 22:21 + U32 Enable : 1; // Bits 23:23 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_CHANNEL_HASH_MCMAIN_STRUCT; + +typedef union { + struct { + U32 pu_mrc_done : 1; // Bits 0:0 + U32 ddr_reset : 1; // Bits 1:1 + U32 : 1; // Bits 2:2 + U32 refresh_enable : 1; // Bits 3:3 + U32 : 1; // Bits 4:4 + U32 mc_init_done_ack : 1; // Bits 5:5 + U32 : 1; // Bits 6:6 + U32 mrc_done : 1; // Bits 7:7 + U32 safe_sr : 1; // Bits 8:8 + U32 : 1; // Bits 9:9 + U32 HVM_Gate_DDR_Reset : 1; // Bits 10:10 + U32 : 11; // Bits 21:11 + U32 dclk_enable : 1; // Bits 22:22 + U32 reset_io : 1; // Bits 23:23 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MC_INIT_STATE_G_MCMAIN_STRUCT; + +typedef union { + struct { + U32 REVISION : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MRC_REVISION_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Idle_timer : 16; // Bits 15:0 + U32 SR_Enable : 1; // Bits 16:16 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_PM_SREF_CONFIG_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Ch_dir : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 MCI_clk_div : 10; // Bits 17:8 + U32 : 14; // Bits 31:18 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MCI_CONFIG_MCMAIN_STRUCT; + +typedef union { + struct { + U32 stall_until_drain : 1; // Bits 0:0 + U32 stall_input : 1; // Bits 1:1 + U32 : 2; // Bits 3:2 + U32 mc_drained : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 sr_state : 2; // Bits 9:8 + U32 : 22; // Bits 31:10 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_STALL_DRAIN_MCMAIN_STRUCT; + +typedef union { + struct { + U32 RPQ_count : 5; // Bits 4:0 + U32 : 3; // Bits 7:5 + U32 WPQ_count : 7; // Bits 14:8 + U32 : 17; // Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_STRUCT; + +typedef union { + struct { + U32 count : 16; // Bits 15:0 + U32 First_Rcomp_done : 1; // Bits 16:16 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_RCOMP_TIMER_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Address : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Mask : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_STRUCT; + +typedef union { + struct { + U32 Data : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_STRUCT; + +typedef union { + struct { + U32 lock_addr_map : 1; // Bits 0:0 + U32 lock_mc_config : 1; // Bits 1:1 + U32 lock_iosav_init : 1; // Bits 2:2 + U32 lock_pwr_mngment : 1; // Bits 3:3 + U32 : 3; // Bits 6:4 + U32 lock_mc_dft : 1; // Bits 7:7 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCDECS_CR_MC_LOCK_MCMAIN_STRUCT; + +typedef union { + struct { + U32 tRCD : 5; // Bits 4:0 + U32 tRP : 5; // Bits 9:5 + U32 tRAS : 6; // Bits 15:10 + U32 tRDPRE : 4; // Bits 19:16 + U32 tWRPRE : 6; // Bits 25:20 + U32 tRRD : 4; // Bits 29:26 + U32 tRPab_ext : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_BANK_STRUCT; + +typedef union { + struct { + U32 tCKE : 4; // Bits 3:0 + U32 tFAW : 8; // Bits 11:4 + U32 tRDRD : 3; // Bits 14:12 + U32 tRDRD_dr : 4; // Bits 18:15 + U32 tRDRD_dd : 4; // Bits 22:19 + U32 tRDPDEN : 5; // Bits 27:23 + U32 : 1; // Bits 28:28 + U32 CMD_3st : 1; // Bits 29:29 + U32 CMD_stretch : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT; + +typedef union { + struct { + U32 tWRRD : 6; // Bits 5:0 + U32 tWRRD_dr : 4; // Bits 9:6 + U32 tWRRD_dd : 4; // Bits 13:10 + U32 tWRWR : 3; // Bits 16:14 + U32 tWRWR_dr : 4; // Bits 20:17 + U32 tWRWR_dd : 4; // Bits 24:21 + U32 tWRPDEN : 6; // Bits 30:25 + U32 Dec_WRD : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_BANK_RANK_B_STRUCT; + +typedef union { + struct { + U32 tXPDLL : 6; // Bits 5:0 + U32 tXP : 4; // Bits 9:6 + U32 TAONPD : 4; // Bits 13:10 + U32 tRDWR : 5; // Bits 18:14 + U32 tRDWR_dr : 5; // Bits 23:19 + U32 tRDWR_dd : 5; // Bits 28:24 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_BANK_RANK_C_STRUCT; + +typedef union { + struct { + U32 enable_cmd_rate_limit : 1; // Bits 0:0 + U32 cmd_rate_limit : 3; // Bits 3:1 + U32 reset_on_command : 4; // Bits 7:4 + U32 reset_delay : 4; // Bits 11:8 + U32 ck_to_cke_delay : 2; // Bits 13:12 + U32 spare : 17; // Bits 30:14 + U32 init_mrw_2n_cs : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_CMD_RATE_STRUCT; + +typedef union { + struct { + U32 tCL : 5; // Bits 4:0 + U32 tWCL : 5; // Bits 9:5 + U32 tCPDED : 2; // Bits 11:10 + U32 tPRPDEN : 2; // Bits 13:12 + U32 Odt_Read_Delay : 3; // Bits 16:14 + U32 Odt_Read_Duration : 2; // Bits 18:17 + U32 Odt_Write_Duration : 2; // Bits 20:19 + U32 : 11; // Bits 31:21 + } Bits; +#ifdef ULT_FLAG + struct { + U32 tCL : 5; // Bits 4:0 + U32 tWCL : 5; // Bits 9:5 + U32 tCPDED : 2; // Bits 11:10 + U32 tPRPDEN : 2; // Bits 13:12 + U32 Odt_Read_Delay : 3; // Bits 16:14 + U32 Odt_Read_Duration : 2; // Bits 18:17 + U32 Odt_Write_Duration : 3; // Bits 21:19 + U32 Odt_Write_Delay : 3; // Bits 24:22 + U32 Odt_Always_Rank0 : 1; // Bits 25:25 + U32 cmd_delay : 2; // Bits 27:26 + U32 : 4; // Bits 31:28 + } UltBits; +#endif // ULT_FLAG + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_BANK_RANK_D_STRUCT; + +typedef union { + struct { + U32 dis_opp_cas : 1; // Bits 0:0 + U32 dis_opp_is_cas : 1; // Bits 1:1 + U32 dis_opp_ras : 1; // Bits 2:2 + U32 dis_opp_is_ras : 1; // Bits 3:3 + U32 dis_1c_byp : 1; // Bits 4:4 + U32 dis_2c_byp : 1; // Bits 5:5 + U32 dis_deprd_opt : 1; // Bits 6:6 + U32 dis_pt_it : 1; // Bits 7:7 + U32 dis_prcnt_ring : 1; // Bits 8:8 + U32 dis_prcnt_sa : 1; // Bits 9:9 + U32 dis_blkr_ph : 1; // Bits 10:10 + U32 dis_blkr_pe : 1; // Bits 11:11 + U32 dis_blkr_pm : 1; // Bits 12:12 + U32 dis_odt : 1; // Bits 13:13 + U32 OE_alw_off : 1; // Bits 14:14 + U32 : 1; // Bits 15:15 + U32 dis_aom : 1; // Bits 16:16 + U32 block_rpq : 1; // Bits 17:17 + U32 block_wpq : 1; // Bits 18:18 + U32 invert_align : 1; // Bits 19:19 + U32 dis_write_gap : 1; // Bits 20:20 + U32 dis_zq : 1; // Bits 21:21 + U32 dis_tt : 1; // Bits 22:22 + U32 dis_opp_ref : 1; // Bits 23:23 + U32 Long_ZQ : 1; // Bits 24:24 + U32 dis_srx_zq : 1; // Bits 25:25 + U32 Serialize_ZQ : 1; // Bits 26:26 + U32 ZQ_fast_exec : 1; // Bits 27:27 + U32 Dis_DriveNop : 1; // Bits 28:28 + U32 Pres_WDB_Ent : 1; // Bits 29:29 + U32 dis_clk_gate : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SCHED_CBIT_STRUCT; + +typedef union { + struct { + U32 Lat_R0D0 : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 Lat_R1D0 : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 Lat_R0D1 : 6; // Bits 21:16 + U32 : 2; // Bits 23:22 + U32 Lat_R1D1 : 6; // Bits 29:24 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SC_ROUNDT_LAT_STRUCT; + +typedef union { + struct { + U32 IOLAT_R0D0 : 4; // Bits 3:0 + U32 IOLAT_R1D0 : 4; // Bits 7:4 + U32 IOLAT_R0D1 : 4; // Bits 11:8 + U32 IOLAT_R1D1 : 4; // Bits 15:12 + U32 RT_IOCOMP : 6; // Bits 21:16 + U32 : 8; // Bits 29:22 + U32 three_channels : 1; // Bits 30:30 + U32 DIS_RT_CLK_GATE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SC_IO_LATENCY_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_STRUCT; + +typedef union { + struct { + U32 WDAR : 1; // Bits 0:0 + U32 safe_mask_sel : 3; // Bits 3:1 + U32 force_rcv_en : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 DDR_QUAL : 2; // Bits 9:8 + U32 Qual_length : 2; // Bits 11:10 + U32 WDB_Block_En : 1; // Bits 12:12 + U32 RT_DFT_READ_PTR : 4; // Bits 16:13 + U32 RT_DFT_READ_ENABLE : 1; // Bits 17:17 + U32 RT_DFT_READ_SEL_ADDR : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DFT_MISC_STRUCT; + +typedef union { + struct { + U32 ECC : 8; // Bits 7:0 + U32 RRD_DFT_Mode : 2; // Bits 9:8 + U32 LFSR_Seed_Index : 5; // Bits 14:10 + U32 Inversion_Mode : 1; // Bits 15:15 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_READ_RETURN_DFT_STRUCT; + +typedef union { + struct { + U32 dis_imph_error : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 dis_async_odt : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SCHED_SECOND_CBIT_STRUCT; + +typedef union { + struct { + U32 Mux0_Control : 2; // Bits 1:0 + U32 : 1; // Bits 2:2 + U32 Mux1_Control : 2; // Bits 4:3 + U32 : 1; // Bits 5:5 + U32 Mux2_Control : 2; // Bits 7:6 + U32 : 6; // Bits 13:8 + U32 ECC_Replace_Byte_Control : 1; // Bits 14:14 + U32 ECC_Data_Source_Sel : 1; // Bits 15:15 + U32 Save_LFSR_Seed_Rate : 6; // Bits 21:16 + U32 : 2; // Bits 23:22 + U32 Reload_LFSR_Seed_Rate : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT; + +typedef union { + struct { + U32 WDB_Current_Read_Pointer : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_STRUCT; + +typedef union { + struct { + U32 L_data_select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_STRUCT; + +typedef union { + struct { + U32 ECC_Inv_or_DC_Enable : 8; // Bits 7:0 + U32 : 8; // Bits 15:8 + U32 Inv_or_DC_Shift_Rate : 4; // Bits 19:16 + U32 DC_Polarity_Control : 1; // Bits 20:20 + U32 : 9; // Bits 29:21 + U32 Inv_or_DC_Control : 1; // Bits 30:30 + U32 Inv_or_DC_Shift_Enable : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_STRUCT; + +typedef union { + struct { + U64 Data_Inv_or_DC_Enable : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_STRUCT; + +typedef union { + struct { + U32 Stop_on_Nth_Error : 6; // Bits 5:0 + U32 : 6; // Bits 11:6 + U32 Stop_On_Error_Control : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Selective_Error_Enable_Chunk : 8; // Bits 23:16 + U32 Selective_Error_Enable_Cacheline : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_CTL_STRUCT; + +typedef union { + struct { + U32 ECC_Error_Mask : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_STRUCT; + +typedef union { + struct { + U32 Stretch_mode : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 STF : 3; // Bits 6:4 + U32 : 25; // Bits 31:7 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_STM_CONFIG_STRUCT; + +typedef union { + struct { + U32 Priority_count_ring : 10; // Bits 9:0 + U32 : 6; // Bits 15:10 + U32 Priority_count_SA : 10; // Bits 25:16 + U32 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_STRUCT; + +typedef union { + struct { + U32 PCIT : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SC_PCIT_STRUCT; + +typedef union { + struct { + U32 PDWN_idle_counter : 12; // Bits 11:0 + U32 PDWN_mode : 4; // Bits 15:12 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_PDWN_CONFIG_STRUCT; + +typedef union { + struct { + U32 Count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ECC_INJECT_COUNT_STRUCT; + +typedef union { + struct { + U32 ECC4ANA_fill : 8; // Bits 7:0 + U32 ECC4ANA_trigger : 2; // Bits 9:8 + U32 ECC4ANA_BS : 1; // Bits 10:10 + U32 ECC_Inject : 3; // Bits 13:11 + U32 ECC_correction_disable : 1; // Bits 14:14 + U32 ECC4ANA_Inject : 1; // Bits 15:15 + U32 DIS_MCA_LOG : 1; // Bits 16:16 + U32 DIS_PCH_EVENT : 1; // Bits 17:17 + U32 DIS_PCIE_POISON : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ECC_DFT_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_STRUCT; + +typedef union { + struct { + U32 Data : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_STRUCT; + +typedef union { + struct { + U32 CERRSTS : 1; // Bits 0:0 + U32 MERRSTS : 1; // Bits 1:1 + U32 : 14; // Bits 15:2 + U32 ERRSYND : 8; // Bits 23:16 + U32 ERRCHUNK : 3; // Bits 26:24 + U32 ERRRANK : 2; // Bits 28:27 + U32 ERRBANK : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ECCERRLOG0_STRUCT; + +typedef union { + struct { + U32 ERRROW : 16; // Bits 15:0 + U32 ERRCOL : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ECCERRLOG1_STRUCT; + +typedef union { + struct { + U32 D0R0 : 2; // Bits 1:0 + U32 D0R1 : 2; // Bits 3:2 + U32 D1R0 : 2; // Bits 5:4 + U32 D1R1 : 2; // Bits 7:6 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SC_WR_ADD_DELAY_STRUCT; + +typedef union { + struct { + U32 Dis_Opp_rd : 1; // Bits 0:0 + U32 ACT_Enable : 1; // Bits 1:1 + U32 PRE_Enable : 1; // Bits 2:2 + U32 MAX_RPQ_Cas : 4; // Bits 6:3 + U32 : 25; // Bits 31:7 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_WMM_READ_CONFIG_STRUCT; + +typedef union { + struct { + U64 Data_Error_Mask : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_STRUCT; + +typedef union { + struct { + U64 Data_Error_Status : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_STRUCT; + +typedef union { + struct { + U32 ECC_Error_Status : 8; // Bits 7:0 + U32 Chunk_Error_Status : 8; // Bits 15:8 + U32 Rank_Error_Status : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + U32 Byte_Group_Error_Status : 9; // Bits 40:32 + U32 : 11; // Bits 51:41 + U32 WDB_Rd_Chunk_Num_Status : 3; // Bits 54:52 + U32 : 1; // Bits 55:55 + U32 Nth_Error : 6; // Bits 61:56 + U32 : 2; // Bits 63:62 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_STRUCT; + +typedef union { + struct { + U32 Counter_Overflow_Status : 9; // Bits 8:0 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_STRUCT; + +typedef union { + struct { + U32 Column_Address : 10; // Bits 9:0 + U32 : 14; // Bits 23:10 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 2; // Bits 57:56 + U32 : 6; // Bits 63:58 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_STRUCT; + +typedef union { + struct { + U32 WDB_Current_Error_Pointer : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_STRUCT; + +typedef union { + struct { + U32 Enable_WDB_Error_Capture : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 WDB_Starting_Error_Pointer : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 WDB_Ending_Error_Pointer : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_STRUCT; + +typedef union { + struct { + U32 CKE_Override : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 CKE_En_Start_Test_Sync : 1; // Bits 8:8 + U32 : 7; // Bits 15:9 + U32 CKE_On : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_STRUCT; + +typedef union { + struct { + U32 ODT_Override : 4; // Bits 3:0 + U32 : 12; // Bits 15:4 + U32 ODT_On : 4; // Bits 19:16 + U32 : 11; // Bits 30:20 + U32 MPR_Train_DDR_On : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_STRUCT; + +typedef union { + struct { + U32 Enable_CADB_on_Deselect : 1; // Bits 0:0 + U32 Enable_CADB_Always_On : 1; // Bits 1:1 + U32 CMD_Deselect_Start : 4; // Bits 5:2 + U32 CMD_Deselect_Stop : 4; // Bits 9:6 + U32 Lane_Deselect_Enable : 4; // Bits 13:10 + U32 CAS_Select_Enable : 2; // Bits 15:14 + U32 ACT_Select_Enable : 2; // Bits 17:16 + U32 PRE_Select_Enable : 2; // Bits 19:18 + U32 Save_Current_Seed : 4; // Bits 23:20 + U32 Reload_Starting_Seed : 4; // Bits 27:24 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_STRUCT; + +typedef union { + struct { + U32 MRS_Gap : 3; // Bits 2:0 + U32 : 5; // Bits 7:3 + U32 CADB_MRS_Start_Pointer : 3; // Bits 10:8 + U32 : 5; // Bits 15:11 + U32 CADB_MRS_End_Pointer : 3; // Bits 18:16 + U32 : 5; // Bits 23:19 + U32 CADB_MRS_Current_Pointer : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_STRUCT; + +typedef union { + struct { + U32 Mux0_Control : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 Mux1_Control : 2; // Bits 5:4 + U32 : 2; // Bits 7:6 + U32 Mux2_Control : 2; // Bits 9:8 + U32 : 6; // Bits 15:10 + U32 Select_Mux0_Control : 2; // Bits 17:16 + U32 : 2; // Bits 19:18 + U32 Select_Mux1_Control : 2; // Bits 21:20 + U32 : 2; // Bits 23:22 + U32 Select_Mux2_Control : 2; // Bits 25:24 + U32 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_STRUCT; + +typedef union { + struct { + U32 L_data_select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_STRUCT; + +typedef union { + struct { + U32 CADB_Write_Pointer : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_STRUCT; + +typedef union { + struct { + U32 CADB_Data_Address : 16; // Bits 15:0 + U32 : 8; // Bits 23:16 + U32 CADB_Data_Bank : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + U32 CADB_Data_CS : 4; // Bits 35:32 + U32 : 4; // Bits 39:36 + U32 CADB_Data_Control : 3; // Bits 42:40 + U32 : 5; // Bits 47:43 + U32 CADB_Data_ODT : 4; // Bits 51:48 + U32 : 4; // Bits 55:52 + U32 CADB_Data_CKE : 4; // Bits 59:56 + U32 : 4; // Bits 63:60 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_STRUCT; + +typedef union { + struct { + U32 WDB_Increment_Rate : 5; // Bits 4:0 + U32 WDB_Increment_Scale : 1; // Bits 5:5 + U32 : 2; // Bits 7:6 + U32 WDB_Start_Pointer : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 WDB_End_Pointer : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT; + +typedef union { + struct { + U32 Refresh_Rank_Mask : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 RefZQ_En_Start_Test_Sync : 1; // Bits 8:8 + U32 : 22; // Bits 30:9 + U32 Panic_Refresh_Only : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_STRUCT; + +typedef union { + struct { + U32 ZQ_Rank_Mask : 4; // Bits 3:0 + U32 : 27; // Bits 30:4 + U32 Always_Do_ZQ : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_STRUCT; + +#ifdef ULT_FLAG +typedef union { + struct { + U32 Rank_0_x32 : 1; // Bits 0:0 + U32 Rank_1_x32 : 1; // Bits 1:1 + U32 Rank_2_x32 : 1; // Bits 2:2 + U32 Rank_3_x32 : 1; // Bits 3:3 + U32 LPDDR2 : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 MR4_PERIOD : 16; // Bits 23:8 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_LPDDR_MR_PARAMS_STRUCT; + +typedef union { + struct { + U32 Address : 8; // Bits 7:0 + U32 Data : 8; // Bits 15:8 + U32 Rank : 2; // Bits 17:16 + U32 Write : 1; // Bits 18:18 + U32 Init_MRW : 1; // Bits 19:19 + U32 : 11; // Bits 30:20 + U32 Busy : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_LPDDR_MR_COMMAND_STRUCT; + +typedef union { + struct { + U32 Device_0 : 8; // Bits 7:0 + U32 Device_1 : 8; // Bits 15:8 + U32 Device_2 : 8; // Bits 23:16 + U32 Device_3 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_LPDDR_MR_RESULT_STRUCT; + +typedef union { + struct { + U32 Rank_0 : 3; // Bits 2:0 + U32 : 5; // Bits 7:3 + U32 Rank_1 : 3; // Bits 10:8 + U32 : 5; // Bits 15:11 + U32 Rank_2 : 3; // Bits 18:16 + U32 : 5; // Bits 23:19 + U32 Rank_3 : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_STRUCT; + +typedef union { + struct { + U32 Bit_0 : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 Bit_1 : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 Bit_2 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 Bit_16 : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 Bit_17 : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 Bit_18 : 3; // Bits 22:20 + U32 : 1; // Bits 23:23 + U32 Byte_0 : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Byte_2 : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DESWIZZLE_LOW_STRUCT; + +typedef union { + struct { + U32 Bit_32 : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 Bit_33 : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 Bit_34 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 Bit_48 : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 Bit_49 : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 Bit_50 : 3; // Bits 22:20 + U32 : 1; // Bits 23:23 + U32 Byte_4 : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Byte_6 : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DESWIZZLE_HIGH_STRUCT; +#endif // ULT_FLAG + +typedef union { + struct { + U32 Ref_Interval : 11; // Bits 10:0 + U32 Ref_Stagger_En : 1; // Bits 11:11 + U32 Ref_Stagger_Mode : 1; // Bits 12:12 + U32 Disable_Stolen_Refresh : 1; // Bits 13:13 + U32 En_Ref_Type_Display : 1; // Bits 14:14 + U32 : 17; // Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_MC_REFRESH_STAGGER_STRUCT; + +typedef union { + struct { + U32 ZQCS_period : 8; // Bits 7:0 + U32 tZQCS : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; +#ifdef ULT_FLAG + struct { + U32 ZQCS_period : 10; // Bits 9:0 + U32 tZQCS : 10; // Bits 19:10 + U32 : 12; // Bits 31:20 + } UltBits; +#endif // ULT_FLAG + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_ZQCAL_STRUCT; + +typedef union { + struct { + U32 OREF_RI : 8; // Bits 7:0 + U32 Refresh_HP_WM : 4; // Bits 11:8 + U32 Refresh_panic_wm : 4; // Bits 15:12 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_RFP_STRUCT; + +typedef union { + struct { + U32 tREFI : 16; // Bits 15:0 + U32 tRFC : 9; // Bits 24:16 + U32 tREFIx9 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_RFTP_STRUCT; + +typedef union { + struct { + U32 MR2_sh_low : 6; // Bits 5:0 + U32 SRT_avail : 2; // Bits 7:6 + U32 MR2_sh_high : 3; // Bits 10:8 + U32 : 3; // Bits 13:11 + U32 Addr_bit_swizzle : 2; // Bits 15:14 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_MR2_SHADDOW_STRUCT; + +typedef union { + struct { + U32 Rank_occupancy : 4; // Bits 3:0 + U32 : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_MC_INIT_STATE_STRUCT; + +typedef union { + struct { + U32 tXSDLL : 12; // Bits 11:0 + U32 tXS_offset : 4; // Bits 15:12 + U32 tZQOPER : 10; // Bits 25:16 + U32 : 2; // Bits 27:26 + U32 tMOD : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_TC_SRFTP_STRUCT; + +typedef union { + struct { + U32 VISAByteSel : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_WDB_VISA_SEL_STRUCT; + +typedef union { + struct { + U32 FASTADDR : 12; // Bits 11:0 + U32 : 4; // Bits 15:12 + U32 ADDREN : 1; // Bits 16:16 + U32 SEQEN : 1; // Bits 17:17 + U32 POL0 : 1; // Bits 18:18 + U32 POL1 : 1; // Bits 19:19 + U32 CMDA : 4; // Bits 23:20 + U32 CMDB : 4; // Bits 27:24 + U32 CMDC : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DCLK_LDAT_PDAT_STRUCT; + +typedef union { + struct { + U32 BANKSEL : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 ARRAYSEL : 5; // Bits 9:5 + U32 CMP : 1; // Bits 10:10 + U32 REP : 1; // Bits 11:11 + U32 DWORD : 4; // Bits 15:12 + U32 MODE : 2; // Bits 17:16 + U32 MPMAP : 6; // Bits 23:18 + U32 MPBOFFSET : 4; // Bits 27:24 + U32 STAGE_EN : 1; // Bits 28:28 + U32 SHADOW : 2; // Bits 30:29 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STRUCT; + +typedef union { + struct { + U32 DATOUT : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_STRUCT; + +typedef union { + struct { + U32 FASTADDR : 12; // Bits 11:0 + U32 : 4; // Bits 15:12 + U32 ADDREN : 1; // Bits 16:16 + U32 SEQEN : 1; // Bits 17:17 + U32 POL0 : 1; // Bits 18:18 + U32 POL1 : 1; // Bits 19:19 + U32 CMDA : 4; // Bits 23:20 + U32 CMDB : 4; // Bits 27:24 + U32 CMDC : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QCLK_LDAT_PDAT_STRUCT; + +typedef union { + struct { + U32 BANKSEL : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 ARRAYSEL : 5; // Bits 9:5 + U32 CMP : 1; // Bits 10:10 + U32 REP : 1; // Bits 11:11 + U32 DWORD : 4; // Bits 15:12 + U32 MODE : 2; // Bits 17:16 + U32 MPMAP : 6; // Bits 23:18 + U32 MPBOFFSET : 4; // Bits 27:24 + U32 STAGE_EN : 1; // Bits 28:28 + U32 SHADOW : 2; // Bits 30:29 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STRUCT; + +typedef union { + struct { + U32 DATOUT : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_STRUCT; + +typedef union { + struct { + U32 RPQ_disable : 28; // Bits 27:0 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_STRUCT; + +typedef union { + struct { + U32 WPQ_disable : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_STRUCT; + +typedef union { + struct { + U32 DIMM0_IDLE_ENERGY : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 DIMM1_IDLE_ENERGY : 6; // Bits 13:8 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_PD_ENERGY : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 DIMM1_PD_ENERGY : 6; // Bits 13:8 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_ACT_ENERGY : 8; // Bits 7:0 + U32 DIMM1_ACT_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_RD_ENERGY : 8; // Bits 7:0 + U32 DIMM1_RD_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_WR_ENERGY : 8; // Bits 7:0 + U32 DIMM1_WR_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_STRUCT; + +typedef union { + struct { + U32 CKE_MIN : 8; // Bits 7:0 + U32 CKE_MIN_DEFEATURE : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_PM_THRT_CKE_MIN_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MASK0_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MASK1_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MASK2_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_MASK3_STRUCT; + +typedef union { + struct { + U32 BankMatch0 : 3; // Bits 2:0 + U32 BankMatch1 : 3; // Bits 5:3 + U32 BankMatch2 : 3; // Bits 8:6 + U32 BankMatch3 : 3; // Bits 11:9 + U32 BankMask0 : 3; // Bits 14:12 + U32 BankMask1 : 3; // Bits 17:15 + U32 BankMask2 : 3; // Bits 20:18 + U32 BankMask3 : 3; // Bits 23:21 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_CMD_BANK_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_STRUCT; + +typedef union { + struct { + U32 TriggerBlockEnable : 1; // Bits 0:0 + U32 GlobalCounterThreshold : 16; // Bits 16:1 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_STRUCT; + +typedef union { + struct { + U32 WMM_Enter : 8; // Bits 7:0 + U32 WMM_Exit : 8; // Bits 15:8 + U32 WPQ_IS : 8; // Bits 23:16 + U32 Starve_count : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_SC_WDBWM_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH0_CR_VISA_CTL_MCMNTS_STRUCT; + +typedef union { + struct { + U32 tRCD : 5; // Bits 4:0 + U32 tRP : 5; // Bits 9:5 + U32 tRAS : 6; // Bits 15:10 + U32 tRDPRE : 4; // Bits 19:16 + U32 tWRPRE : 6; // Bits 25:20 + U32 tRRD : 4; // Bits 29:26 + U32 tRPab_ext : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_BANK_STRUCT; + +typedef union { + struct { + U32 tCKE : 4; // Bits 3:0 + U32 tFAW : 8; // Bits 11:4 + U32 tRDRD : 3; // Bits 14:12 + U32 tRDRD_dr : 4; // Bits 18:15 + U32 tRDRD_dd : 4; // Bits 22:19 + U32 tRDPDEN : 5; // Bits 27:23 + U32 : 1; // Bits 28:28 + U32 CMD_3st : 1; // Bits 29:29 + U32 CMD_stretch : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_BANK_RANK_A_STRUCT; + +typedef union { + struct { + U32 tWRRD : 6; // Bits 5:0 + U32 tWRRD_dr : 4; // Bits 9:6 + U32 tWRRD_dd : 4; // Bits 13:10 + U32 tWRWR : 3; // Bits 16:14 + U32 tWRWR_dr : 4; // Bits 20:17 + U32 tWRWR_dd : 4; // Bits 24:21 + U32 tWRPDEN : 6; // Bits 30:25 + U32 Dec_WRD : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_BANK_RANK_B_STRUCT; + +typedef union { + struct { + U32 tXPDLL : 6; // Bits 5:0 + U32 tXP : 4; // Bits 9:6 + U32 TAONPD : 4; // Bits 13:10 + U32 tRDWR : 5; // Bits 18:14 + U32 tRDWR_dr : 5; // Bits 23:19 + U32 tRDWR_dd : 5; // Bits 28:24 + U32 : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_BANK_RANK_C_STRUCT; + +typedef union { + struct { + U32 enable_cmd_rate_limit : 1; // Bits 0:0 + U32 cmd_rate_limit : 3; // Bits 3:1 + U32 reset_on_command : 4; // Bits 7:4 + U32 reset_delay : 4; // Bits 11:8 + U32 ck_to_cke_delay : 2; // Bits 13:12 + U32 spare : 17; // Bits 30:14 + U32 init_mrw_2n_cs : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_CMD_RATE_STRUCT; + +typedef union { + struct { + U32 tCL : 5; // Bits 4:0 + U32 tWCL : 5; // Bits 9:5 + U32 tCPDED : 2; // Bits 11:10 + U32 tPRPDEN : 2; // Bits 13:12 + U32 Odt_Read_Delay : 3; // Bits 16:14 + U32 Odt_Read_Duration : 2; // Bits 18:17 + U32 Odt_Write_Duration : 2; // Bits 20:19 + U32 : 11; // Bits 31:21 + } Bits; +#ifdef ULT_FLAG + struct { + U32 tCL : 5; // Bits 4:0 + U32 tWCL : 5; // Bits 9:5 + U32 tCPDED : 2; // Bits 11:10 + U32 tPRPDEN : 2; // Bits 13:12 + U32 Odt_Read_Delay : 3; // Bits 16:14 + U32 Odt_Read_Duration : 2; // Bits 18:17 + U32 Odt_Write_Duration : 3; // Bits 21:19 + U32 Odt_Write_Delay : 3; // Bits 24:22 + U32 Odt_Always_Rank0 : 1; // Bits 25:25 + U32 cmd_delay : 2; // Bits 27:26 + U32 : 4; // Bits 31:28 + } UltBits; +#endif // ULT_FLAG + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_BANK_RANK_D_STRUCT; + +typedef union { + struct { + U32 dis_opp_cas : 1; // Bits 0:0 + U32 dis_opp_is_cas : 1; // Bits 1:1 + U32 dis_opp_ras : 1; // Bits 2:2 + U32 dis_opp_is_ras : 1; // Bits 3:3 + U32 dis_1c_byp : 1; // Bits 4:4 + U32 dis_2c_byp : 1; // Bits 5:5 + U32 dis_deprd_opt : 1; // Bits 6:6 + U32 dis_pt_it : 1; // Bits 7:7 + U32 dis_prcnt_ring : 1; // Bits 8:8 + U32 dis_prcnt_sa : 1; // Bits 9:9 + U32 dis_blkr_ph : 1; // Bits 10:10 + U32 dis_blkr_pe : 1; // Bits 11:11 + U32 dis_blkr_pm : 1; // Bits 12:12 + U32 dis_odt : 1; // Bits 13:13 + U32 OE_alw_off : 1; // Bits 14:14 + U32 : 1; // Bits 15:15 + U32 dis_aom : 1; // Bits 16:16 + U32 block_rpq : 1; // Bits 17:17 + U32 block_wpq : 1; // Bits 18:18 + U32 invert_align : 1; // Bits 19:19 + U32 dis_write_gap : 1; // Bits 20:20 + U32 dis_zq : 1; // Bits 21:21 + U32 dis_tt : 1; // Bits 22:22 + U32 dis_opp_ref : 1; // Bits 23:23 + U32 Long_ZQ : 1; // Bits 24:24 + U32 dis_srx_zq : 1; // Bits 25:25 + U32 Serialize_ZQ : 1; // Bits 26:26 + U32 ZQ_fast_exec : 1; // Bits 27:27 + U32 Dis_DriveNop : 1; // Bits 28:28 + U32 Pres_WDB_Ent : 1; // Bits 29:29 + U32 dis_clk_gate : 1; // Bits 30:30 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SCHED_CBIT_STRUCT; + +typedef union { + struct { + U32 Lat_R0D0 : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 Lat_R1D0 : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 Lat_R0D1 : 6; // Bits 21:16 + U32 : 2; // Bits 23:22 + U32 Lat_R1D1 : 6; // Bits 29:24 + U32 : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SC_ROUNDT_LAT_STRUCT; + +typedef union { + struct { + U32 IOLAT_R0D0 : 4; // Bits 3:0 + U32 IOLAT_R1D0 : 4; // Bits 7:4 + U32 IOLAT_R0D1 : 4; // Bits 11:8 + U32 IOLAT_R1D1 : 4; // Bits 15:12 + U32 RT_IOCOMP : 6; // Bits 21:16 + U32 : 8; // Bits 29:22 + U32 three_channels : 1; // Bits 30:30 + U32 DIS_RT_CLK_GATE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SC_IO_LATENCY_STRUCT; + +typedef union { + struct { + U32 DATA : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_STRUCT; + +typedef union { + struct { + U32 WDAR : 1; // Bits 0:0 + U32 safe_mask_sel : 3; // Bits 3:1 + U32 force_rcv_en : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 DDR_QUAL : 2; // Bits 9:8 + U32 Qual_length : 2; // Bits 11:10 + U32 WDB_Block_En : 1; // Bits 12:12 + U32 RT_DFT_READ_PTR : 4; // Bits 16:13 + U32 RT_DFT_READ_ENABLE : 1; // Bits 17:17 + U32 RT_DFT_READ_SEL_ADDR : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DFT_MISC_STRUCT; + +typedef union { + struct { + U32 ECC : 8; // Bits 7:0 + U32 RRD_DFT_Mode : 2; // Bits 9:8 + U32 LFSR_Seed_Index : 5; // Bits 14:10 + U32 Inversion_Mode : 1; // Bits 15:15 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_READ_RETURN_DFT_STRUCT; + +typedef union { + struct { + U32 dis_imph_error : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 dis_async_odt : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SCHED_SECOND_CBIT_STRUCT; + +typedef union { + struct { + U32 Mux0_Control : 2; // Bits 1:0 + U32 : 1; // Bits 2:2 + U32 Mux1_Control : 2; // Bits 4:3 + U32 : 1; // Bits 5:5 + U32 Mux2_Control : 2; // Bits 7:6 + U32 : 6; // Bits 13:8 + U32 ECC_Replace_Byte_Control : 1; // Bits 14:14 + U32 ECC_Data_Source_Sel : 1; // Bits 15:15 + U32 Save_LFSR_Seed_Rate : 6; // Bits 21:16 + U32 : 2; // Bits 23:22 + U32 Reload_LFSR_Seed_Rate : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_STRUCT; + +typedef union { + struct { + U32 WDB_Current_Read_Pointer : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 24; // Bits 23:0 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_STRUCT; + +typedef union { + struct { + U32 L_data_select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_STRUCT; + +typedef union { + struct { + U32 ECC_Inv_or_DC_Enable : 8; // Bits 7:0 + U32 : 8; // Bits 15:8 + U32 Inv_or_DC_Shift_Rate : 4; // Bits 19:16 + U32 DC_Polarity_Control : 1; // Bits 20:20 + U32 : 9; // Bits 29:21 + U32 Inv_or_DC_Control : 1; // Bits 30:30 + U32 Inv_or_DC_Shift_Enable : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_STRUCT; + +typedef union { + struct { + U64 Data_Inv_or_DC_Enable : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_STRUCT; + +typedef union { + struct { + U32 Stop_on_Nth_Error : 6; // Bits 5:0 + U32 : 6; // Bits 11:6 + U32 Stop_On_Error_Control : 2; // Bits 13:12 + U32 : 2; // Bits 15:14 + U32 Selective_Error_Enable_Chunk : 8; // Bits 23:16 + U32 Selective_Error_Enable_Cacheline : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_CTL_STRUCT; + +typedef union { + struct { + U32 ECC_Error_Mask : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_STRUCT; + +typedef union { + struct { + U32 Stretch_mode : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 STF : 3; // Bits 6:4 + U32 : 25; // Bits 31:7 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_STM_CONFIG_STRUCT; + +typedef union { + struct { + U32 Priority_count_ring : 10; // Bits 9:0 + U32 : 6; // Bits 15:10 + U32 Priority_count_SA : 10; // Bits 25:16 + U32 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_STRUCT; + +typedef union { + struct { + U32 PCIT : 8; // Bits 7:0 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SC_PCIT_STRUCT; + +typedef union { + struct { + U32 PDWN_idle_counter : 12; // Bits 11:0 + U32 PDWN_mode : 4; // Bits 15:12 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_PDWN_CONFIG_STRUCT; + +typedef union { + struct { + U32 Count : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ECC_INJECT_COUNT_STRUCT; + +typedef union { + struct { + U32 ECC4ANA_fill : 8; // Bits 7:0 + U32 ECC4ANA_trigger : 2; // Bits 9:8 + U32 ECC4ANA_BS : 1; // Bits 10:10 + U32 ECC_Inject : 3; // Bits 13:11 + U32 ECC_correction_disable : 1; // Bits 14:14 + U32 ECC4ANA_Inject : 1; // Bits 15:15 + U32 DIS_MCA_LOG : 1; // Bits 16:16 + U32 DIS_PCH_EVENT : 1; // Bits 17:17 + U32 DIS_PCIE_POISON : 1; // Bits 18:18 + U32 : 13; // Bits 31:19 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ECC_DFT_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_STRUCT; + +typedef union { + struct { + U32 Data : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_STRUCT; + +typedef union { + struct { + U32 CERRSTS : 1; // Bits 0:0 + U32 MERRSTS : 1; // Bits 1:1 + U32 : 14; // Bits 15:2 + U32 ERRSYND : 8; // Bits 23:16 + U32 ERRCHUNK : 3; // Bits 26:24 + U32 ERRRANK : 2; // Bits 28:27 + U32 ERRBANK : 3; // Bits 31:29 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ECCERRLOG0_STRUCT; + +typedef union { + struct { + U32 ERRROW : 16; // Bits 15:0 + U32 ERRCOL : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ECCERRLOG1_STRUCT; + +typedef union { + struct { + U32 D0R0 : 2; // Bits 1:0 + U32 D0R1 : 2; // Bits 3:2 + U32 D1R0 : 2; // Bits 5:4 + U32 D1R1 : 2; // Bits 7:6 + U32 : 24; // Bits 31:8 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SC_WR_ADD_DELAY_STRUCT; + +typedef union { + struct { + U32 Dis_Opp_rd : 1; // Bits 0:0 + U32 ACT_Enable : 1; // Bits 1:1 + U32 PRE_Enable : 1; // Bits 2:2 + U32 MAX_RPQ_Cas : 4; // Bits 6:3 + U32 : 25; // Bits 31:7 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_WMM_READ_CONFIG_STRUCT; + +typedef union { + struct { + U64 Data_Error_Mask : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_STRUCT; + +typedef union { + struct { + U64 Data_Error_Status : 64; // Bits 63:0 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_STRUCT; + +typedef union { + struct { + U32 ECC_Error_Status : 8; // Bits 7:0 + U32 Chunk_Error_Status : 8; // Bits 15:8 + U32 Rank_Error_Status : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + U32 Byte_Group_Error_Status : 9; // Bits 40:32 + U32 : 11; // Bits 51:41 + U32 WDB_Rd_Chunk_Num_Status : 3; // Bits 54:52 + U32 : 1; // Bits 55:55 + U32 Nth_Error : 6; // Bits 61:56 + U32 : 2; // Bits 63:62 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_STRUCT; + +typedef union { + struct { + U32 Counter_Pointer : 7; // Bits 6:0 + U32 Counter_Control : 2; // Bits 8:7 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_STRUCT; + +typedef union { + struct { + U32 Counter_Status : 23; // Bits 22:0 + U32 : 9; // Bits 31:23 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_STRUCT; + +typedef union { + struct { + U32 Counter_Overflow_Status : 9; // Bits 8:0 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_STRUCT; + +typedef union { + struct { + U32 Column_Address : 10; // Bits 9:0 + U32 : 14; // Bits 23:10 + U32 Row_Address : 16; // Bits 39:24 + U32 : 8; // Bits 47:40 + U32 Bank_Address : 3; // Bits 50:48 + U32 : 5; // Bits 55:51 + U32 Rank_Address : 2; // Bits 57:56 + U32 : 6; // Bits 63:58 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_STRUCT; + +typedef union { + struct { + U32 WDB_Current_Error_Pointer : 6; // Bits 5:0 + U32 : 26; // Bits 31:6 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_STRUCT; + +typedef union { + struct { + U32 Enable_WDB_Error_Capture : 1; // Bits 0:0 + U32 : 7; // Bits 7:1 + U32 WDB_Starting_Error_Pointer : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 WDB_Ending_Error_Pointer : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_STRUCT; + +typedef union { + struct { + U32 CKE_Override : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 CKE_En_Start_Test_Sync : 1; // Bits 8:8 + U32 : 7; // Bits 15:9 + U32 CKE_On : 4; // Bits 19:16 + U32 : 12; // Bits 31:20 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_STRUCT; + +typedef union { + struct { + U32 ODT_Override : 4; // Bits 3:0 + U32 : 12; // Bits 15:4 + U32 ODT_On : 4; // Bits 19:16 + U32 : 11; // Bits 30:20 + U32 MPR_Train_DDR_On : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_STRUCT; + +typedef union { + struct { + U32 Enable_CADB_on_Deselect : 1; // Bits 0:0 + U32 Enable_CADB_Always_On : 1; // Bits 1:1 + U32 CMD_Deselect_Start : 4; // Bits 5:2 + U32 CMD_Deselect_Stop : 4; // Bits 9:6 + U32 Lane_Deselect_Enable : 4; // Bits 13:10 + U32 CAS_Select_Enable : 2; // Bits 15:14 + U32 ACT_Select_Enable : 2; // Bits 17:16 + U32 PRE_Select_Enable : 2; // Bits 19:18 + U32 Save_Current_Seed : 4; // Bits 23:20 + U32 Reload_Starting_Seed : 4; // Bits 27:24 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_STRUCT; + +typedef union { + struct { + U32 MRS_Gap : 3; // Bits 2:0 + U32 : 5; // Bits 7:3 + U32 CADB_MRS_Start_Pointer : 3; // Bits 10:8 + U32 : 5; // Bits 15:11 + U32 CADB_MRS_End_Pointer : 3; // Bits 18:16 + U32 : 5; // Bits 23:19 + U32 CADB_MRS_Current_Pointer : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_STRUCT; + +typedef union { + struct { + U32 Mux0_Control : 2; // Bits 1:0 + U32 : 2; // Bits 3:2 + U32 Mux1_Control : 2; // Bits 5:4 + U32 : 2; // Bits 7:6 + U32 Mux2_Control : 2; // Bits 9:8 + U32 : 6; // Bits 15:10 + U32 Select_Mux0_Control : 2; // Bits 17:16 + U32 : 2; // Bits 19:18 + U32 Select_Mux1_Control : 2; // Bits 21:20 + U32 : 2; // Bits 23:22 + U32 Select_Mux2_Control : 2; // Bits 25:24 + U32 : 6; // Bits 31:26 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_STRUCT; + +typedef union { + struct { + U32 L_data_select : 1; // Bits 0:0 + U32 Enable_Sweep_Frequency : 1; // Bits 1:1 + U32 : 6; // Bits 7:2 + U32 L_counter : 8; // Bits 15:8 + U32 M_counter : 8; // Bits 23:16 + U32 N_counter : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_STRUCT; + +typedef union { + struct { + U32 CADB_Write_Pointer : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_STRUCT; + +typedef union { + struct { + U32 CADB_Data_Address : 16; // Bits 15:0 + U32 : 8; // Bits 23:16 + U32 CADB_Data_Bank : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + U32 CADB_Data_CS : 4; // Bits 35:32 + U32 : 4; // Bits 39:36 + U32 CADB_Data_Control : 3; // Bits 42:40 + U32 : 5; // Bits 47:43 + U32 CADB_Data_ODT : 4; // Bits 51:48 + U32 : 4; // Bits 55:52 + U32 CADB_Data_CKE : 4; // Bits 59:56 + U32 : 4; // Bits 63:60 + } Bits; + U64 Data; + U32 Data32[2]; + U16 Data16[4]; + U8 Data8[8]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_STRUCT; + +typedef union { + struct { + U32 Pattern_Buffer : 16; // Bits 15:0 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_STRUCT; + +typedef union { + struct { + U32 WDB_Increment_Rate : 5; // Bits 4:0 + U32 WDB_Increment_Scale : 1; // Bits 5:5 + U32 : 2; // Bits 7:6 + U32 WDB_Start_Pointer : 6; // Bits 13:8 + U32 : 2; // Bits 15:14 + U32 WDB_End_Pointer : 6; // Bits 21:16 + U32 : 10; // Bits 31:22 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_STRUCT; + +typedef union { + struct { + U32 Refresh_Rank_Mask : 4; // Bits 3:0 + U32 : 4; // Bits 7:4 + U32 RefZQ_En_Start_Test_Sync : 1; // Bits 8:8 + U32 : 22; // Bits 30:9 + U32 Panic_Refresh_Only : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_STRUCT; + +typedef union { + struct { + U32 ZQ_Rank_Mask : 4; // Bits 3:0 + U32 : 27; // Bits 30:4 + U32 Always_Do_ZQ : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_STRUCT; + +#ifdef ULT_FLAG +typedef union { + struct { + U32 Rank_0_x32 : 1; // Bits 0:0 + U32 Rank_1_x32 : 1; // Bits 1:1 + U32 Rank_2_x32 : 1; // Bits 2:2 + U32 Rank_3_x32 : 1; // Bits 3:3 + U32 LPDDR2 : 1; // Bits 4:4 + U32 : 3; // Bits 7:5 + U32 MR4_PERIOD : 16; // Bits 23:8 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_LPDDR_MR_PARAMS_STRUCT; + +typedef union { + struct { + U32 Address : 8; // Bits 7:0 + U32 Data : 8; // Bits 15:8 + U32 Rank : 2; // Bits 17:16 + U32 Write : 1; // Bits 18:18 + U32 Init_MRW : 1; // Bits 19:19 + U32 : 11; // Bits 30:20 + U32 Busy : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_LPDDR_MR_COMMAND_STRUCT; + +typedef union { + struct { + U32 Device_0 : 8; // Bits 7:0 + U32 Device_1 : 8; // Bits 15:8 + U32 Device_2 : 8; // Bits 23:16 + U32 Device_3 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_LPDDR_MR_RESULT_STRUCT; + +typedef union { + struct { + U32 Rank_0 : 3; // Bits 2:0 + U32 : 5; // Bits 7:3 + U32 Rank_1 : 3; // Bits 10:8 + U32 : 5; // Bits 15:11 + U32 Rank_2 : 3; // Bits 18:16 + U32 : 5; // Bits 23:19 + U32 Rank_3 : 3; // Bits 26:24 + U32 : 5; // Bits 31:27 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_STRUCT; + +typedef union { + struct { + U32 Bit_0 : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 Bit_1 : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 Bit_2 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 Bit_16 : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 Bit_17 : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 Bit_18 : 3; // Bits 22:20 + U32 : 1; // Bits 23:23 + U32 Byte_0 : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Byte_2 : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DESWIZZLE_LOW_STRUCT; + +typedef union { + struct { + U32 Bit_32 : 3; // Bits 2:0 + U32 : 1; // Bits 3:3 + U32 Bit_33 : 3; // Bits 6:4 + U32 : 1; // Bits 7:7 + U32 Bit_34 : 3; // Bits 10:8 + U32 : 1; // Bits 11:11 + U32 Bit_48 : 3; // Bits 14:12 + U32 : 1; // Bits 15:15 + U32 Bit_49 : 3; // Bits 18:16 + U32 : 1; // Bits 19:19 + U32 Bit_50 : 3; // Bits 22:20 + U32 : 1; // Bits 23:23 + U32 Byte_4 : 3; // Bits 26:24 + U32 : 1; // Bits 27:27 + U32 Byte_6 : 3; // Bits 30:28 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DESWIZZLE_HIGH_STRUCT; +#endif // ULT_FLAG + +typedef union { + struct { + U32 Ref_Interval : 11; // Bits 10:0 + U32 Ref_Stagger_En : 1; // Bits 11:11 + U32 Ref_Stagger_Mode : 1; // Bits 12:12 + U32 Disable_Stolen_Refresh : 1; // Bits 13:13 + U32 En_Ref_Type_Display : 1; // Bits 14:14 + U32 : 17; // Bits 31:15 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_MC_REFRESH_STAGGER_STRUCT; + +typedef union { + struct { + U32 ZQCS_period : 8; // Bits 7:0 + U32 tZQCS : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; +#ifdef ULT_FLAG + struct { + U32 ZQCS_period : 10; // Bits 9:0 + U32 tZQCS : 10; // Bits 19:10 + U32 : 12; // Bits 31:20 + } UltBits; +#endif //ULT_FLAG + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_ZQCAL_STRUCT; + +typedef union { + struct { + U32 OREF_RI : 8; // Bits 7:0 + U32 Refresh_HP_WM : 4; // Bits 11:8 + U32 Refresh_panic_wm : 4; // Bits 15:12 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_RFP_STRUCT; + +typedef union { + struct { + U32 tREFI : 16; // Bits 15:0 + U32 tRFC : 9; // Bits 24:16 + U32 tREFIx9 : 7; // Bits 31:25 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_RFTP_STRUCT; + +typedef union { + struct { + U32 MR2_sh_low : 6; // Bits 5:0 + U32 SRT_avail : 2; // Bits 7:6 + U32 MR2_sh_high : 3; // Bits 10:8 + U32 : 3; // Bits 13:11 + U32 Addr_bit_swizzle : 2; // Bits 15:14 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_MR2_SHADDOW_STRUCT; + +typedef union { + struct { + U32 Rank_occupancy : 4; // Bits 3:0 + U32 : 28; // Bits 31:4 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_MC_INIT_STATE_STRUCT; + +typedef union { + struct { + U32 tXSDLL : 12; // Bits 11:0 + U32 tXS_offset : 4; // Bits 15:12 + U32 tZQOPER : 10; // Bits 25:16 + U32 : 2; // Bits 27:26 + U32 tMOD : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_TC_SRFTP_STRUCT; + +typedef union { + struct { + U32 VISAByteSel : 3; // Bits 2:0 + U32 : 29; // Bits 31:3 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_WDB_VISA_SEL_STRUCT; + +typedef union { + struct { + U32 FASTADDR : 12; // Bits 11:0 + U32 : 4; // Bits 15:12 + U32 ADDREN : 1; // Bits 16:16 + U32 SEQEN : 1; // Bits 17:17 + U32 POL0 : 1; // Bits 18:18 + U32 POL1 : 1; // Bits 19:19 + U32 CMDA : 4; // Bits 23:20 + U32 CMDB : 4; // Bits 27:24 + U32 CMDC : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DCLK_LDAT_PDAT_STRUCT; + +typedef union { + struct { + U32 BANKSEL : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 ARRAYSEL : 5; // Bits 9:5 + U32 CMP : 1; // Bits 10:10 + U32 REP : 1; // Bits 11:11 + U32 DWORD : 4; // Bits 15:12 + U32 MODE : 2; // Bits 17:16 + U32 MPMAP : 6; // Bits 23:18 + U32 MPBOFFSET : 4; // Bits 27:24 + U32 STAGE_EN : 1; // Bits 28:28 + U32 SHADOW : 2; // Bits 30:29 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STRUCT; + +typedef union { + struct { + U32 DATOUT : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_STRUCT; + +typedef union { + struct { + U32 FASTADDR : 12; // Bits 11:0 + U32 : 4; // Bits 15:12 + U32 ADDREN : 1; // Bits 16:16 + U32 SEQEN : 1; // Bits 17:17 + U32 POL0 : 1; // Bits 18:18 + U32 POL1 : 1; // Bits 19:19 + U32 CMDA : 4; // Bits 23:20 + U32 CMDB : 4; // Bits 27:24 + U32 CMDC : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QCLK_LDAT_PDAT_STRUCT; + +typedef union { + struct { + U32 BANKSEL : 4; // Bits 3:0 + U32 : 1; // Bits 4:4 + U32 ARRAYSEL : 5; // Bits 9:5 + U32 CMP : 1; // Bits 10:10 + U32 REP : 1; // Bits 11:11 + U32 DWORD : 4; // Bits 15:12 + U32 MODE : 2; // Bits 17:16 + U32 MPMAP : 6; // Bits 23:18 + U32 MPBOFFSET : 4; // Bits 27:24 + U32 STAGE_EN : 1; // Bits 28:28 + U32 SHADOW : 2; // Bits 30:29 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STRUCT; + +typedef union { + struct { + U32 DATOUT : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_STRUCT; + +typedef union { + struct { + U32 DATIN : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_STRUCT; + +typedef union { + struct { + U32 RPQ_disable : 28; // Bits 27:0 + U32 : 4; // Bits 31:28 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_STRUCT; + +typedef union { + struct { + U32 WPQ_disable : 32; // Bits 31:0 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_STRUCT; + +typedef union { + struct { + U32 DIMM0_IDLE_ENERGY : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 DIMM1_IDLE_ENERGY : 6; // Bits 13:8 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_PD_ENERGY : 6; // Bits 5:0 + U32 : 2; // Bits 7:6 + U32 DIMM1_PD_ENERGY : 6; // Bits 13:8 + U32 : 18; // Bits 31:14 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_ACT_ENERGY : 8; // Bits 7:0 + U32 DIMM1_ACT_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_RD_ENERGY : 8; // Bits 7:0 + U32 DIMM1_RD_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_STRUCT; + +typedef union { + struct { + U32 DIMM0_WR_ENERGY : 8; // Bits 7:0 + U32 DIMM1_WR_ENERGY : 8; // Bits 15:8 + U32 : 16; // Bits 31:16 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_STRUCT; + +typedef union { + struct { + U32 CKE_MIN : 8; // Bits 7:0 + U32 CKE_MIN_DEFEATURE : 1; // Bits 8:8 + U32 : 23; // Bits 31:9 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_PM_THRT_CKE_MIN_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MASK0_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MASK1_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MASK2_STRUCT; + +typedef union { + struct { + U32 ODT : 4; // Bits 3:0 + U32 Web : 1; // Bits 4:4 + U32 CASb : 1; // Bits 5:5 + U32 RASb : 1; // Bits 6:6 + U32 CSb : 4; // Bits 10:7 + U32 CKE : 4; // Bits 14:11 + U32 MA : 16; // Bits 30:15 + U32 : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_MASK3_STRUCT; + +typedef union { + struct { + U32 BankMatch0 : 3; // Bits 2:0 + U32 BankMatch1 : 3; // Bits 5:3 + U32 BankMatch2 : 3; // Bits 8:6 + U32 BankMatch3 : 3; // Bits 11:9 + U32 BankMask0 : 3; // Bits 14:12 + U32 BankMask1 : 3; // Bits 17:15 + U32 BankMask2 : 3; // Bits 20:18 + U32 BankMask3 : 3; // Bits 23:21 + U32 : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_CMD_BANK_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_STRUCT; + +typedef union { + struct { + U32 InputMatch : 4; // Bits 3:0 + U32 InputInvert : 4; // Bits 7:4 + U32 CountMatches : 1; // Bits 8:8 + U32 CounterThreshold : 15; // Bits 23:9 + U32 CounterAction : 2; // Bits 25:24 + U32 CounterNextState : 2; // Bits 27:26 + U32 MatchAction : 2; // Bits 29:28 + U32 MatchNextState : 2; // Bits 31:30 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_STRUCT; + +typedef union { + struct { + U32 TriggerBlockEnable : 1; // Bits 0:0 + U32 GlobalCounterThreshold : 16; // Bits 16:1 + U32 : 15; // Bits 31:17 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_STRUCT; + +typedef union { + struct { + U32 WMM_Enter : 8; // Bits 7:0 + U32 WMM_Exit : 8; // Bits 15:8 + U32 WPQ_IS : 8; // Bits 23:16 + U32 Starve_count : 8; // Bits 31:24 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_SC_WDBWM_STRUCT; + +typedef union { + struct { + U32 Data : 18; // Bits 17:0 + U32 : 13; // Bits 30:18 + U32 VORANGE : 1; // Bits 31:31 + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} MCHBAR_CH1_CR_VISA_CTL_MCMNTS_STRUCT; + +#define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_REG (0x00004800) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_OFF ( 0) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_MSK (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Start_Test_DEF (0x00000000) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_OFF ( 1) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_MSK (0x00000002) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_DEF (0x00000000) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_OFF ( 2) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_MSK (0x00000004) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Clear_Errors_DEF (0x00000000) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_OFF ( 4) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_MSK (0x00000010) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_CTL_MCMAIN_Global_Stop_Test_On_Any_Error_DEF (0x00000000) + +#define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_REG (0x00004804) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_OFF ( 0) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_MSK (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_0_DEF (0x00000000) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_OFF ( 1) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_MSK (0x00000002) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Error_Status_1_DEF (0x00000000) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_OFF (16) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_MSK (0x00010000) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_0_DEF (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_OFF (17) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_WID ( 1) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_MSK (0x00020000) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_MAX (0x00000001) + #define MCDFXS_CR_REUT_GLOBAL_ERR_MCMAIN_Channel_Test_Done_Status_1_DEF (0x00000001) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_REG (0x00004808) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_REG (0x0000480C) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_REG (0x00004810) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_REG (0x00004814) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_REG (0x00004818) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_REG (0x0000481C) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_REG (0x00004820) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_REG (0x00004824) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_WID (10) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_MSK (0x0003FF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_REG (0x00004830) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_REG (0x00004834) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_1_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_REG (0x00004838) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_2_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_REG (0x0000483C) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_3_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_REG (0x00004840) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_4_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_REG (0x00004844) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_5_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_REG (0x00004848) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_6_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_REG (0x0000484C) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_WID ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_OFF (25) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_MSK (0x18000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_HSW_A0_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_WID ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_MSK (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_MAX (0x0000007F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_OFF ( 7) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Number_of_Cachelines_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_WID (14) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_MSK (0x003FFF00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_MAX (0x00003FFF) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Wait_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_WID ( 4) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_MSK (0x03C00000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Subsequence_Type_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Save_Current_Base_Address_To_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Reset_Current_Base_Address_To_Start_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_OFF (28) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_WID ( 2) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Data_and_ECC_Address_Inversion_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Invert_Data_and_ECC_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_OFF (31) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_CTL_MCMAIN_7_Stop_Base_Subsequence_On_Wrap_Trigger_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_REG (0x00004858) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_REG (0x0000485C) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_REG (0x00004860) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_REG (0x00004864) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_REG (0x00004868) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_REG (0x0000486C) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_REG (0x00004870) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_REG (0x00004874) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH0_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_REG (0x00004880) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_0_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_REG (0x00004884) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_1_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_REG (0x00004888) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_2_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_REG (0x0000488C) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_3_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_REG (0x00004890) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_4_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_REG (0x00004894) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_5_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_REG (0x00004898) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_6_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_REG (0x0000489C) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_OFF ( 0) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_MSK (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Offset_Address_Update_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_OFF ( 8) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_WID ( 5) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_MSK (0x00001F00) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Repeat_Rate_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_OFF (15) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Offset_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_OFF (16) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Offset_Wrap_Trigger_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_OFF (20) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Subsequence_Type_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Deselect_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Select_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_CADB_Seeds_Save_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_OFF (24) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Column_Increment_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_OFF (27) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Row_Increment_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_OFF (30) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_WID ( 1) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH1_SUBSEQ_OFFSET_CTL_MCMAIN_7_Base_Invert_Data_and_ECC_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_REG (0x000048A8) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_OFF ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_MSK (0x00000008) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Stop_Base_Sequence_On_Wrap_Trigger_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_OFF ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_MSK (0x00000020) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Address_Update_Rate_Mode_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_OFF ( 7) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Dummy_Reads_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_OFF (10) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_MSK (0x00000400) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Enable_Constant_Write_Strobe_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_OFF (11) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_MSK (0x00000800) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Global_Control_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_OFF (12) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_MSK (0x00003000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Initialization_Mode_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_OFF (16) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_WID ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_MSK (0x001F0000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Loopcount_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_MSK (0x07000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_Start_Pointer_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_OFF (28) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_MSK (0x70000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Subsequence_End_Pointer_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_OFF (32) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_WID (10) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_MSK (0x3FF00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_0_Start_Test_Delay_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_REG (0x000048B0) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_OFF ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_MSK (0x00000008) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Stop_Base_Sequence_On_Wrap_Trigger_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_OFF ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_MSK (0x00000020) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Address_Update_Rate_Mode_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_OFF ( 7) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Dummy_Reads_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_OFF (10) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_MSK (0x00000400) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Enable_Constant_Write_Strobe_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_OFF (11) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_MSK (0x00000800) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Global_Control_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_OFF (12) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_MSK (0x00003000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Initialization_Mode_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_OFF (16) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_WID ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_MSK (0x001F0000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Loopcount_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_MSK (0x07000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_Start_Pointer_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_OFF (28) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_MSK (0x70000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Subsequence_End_Pointer_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_OFF (32) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_WID (10) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_MSK (0x3FF00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_MAX (0x000003FF) + #define MCDFXS_CR_REUT_CH_SEQ_CFG_MCMAIN_1_Start_Test_Delay_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_REG (0x000048B8) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_MSK (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Start_Test_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_OFF ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_MSK (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Stop_Test_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_OFF ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_MSK (0x00000004) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_0_Local_Clear_Errors_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_REG (0x000048BC) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_MSK (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Start_Test_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_OFF ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_MSK (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Stop_Test_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_OFF ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_MSK (0x00000004) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_CTL_MCMAIN_1_Local_Clear_Errors_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_REG (0x000048C0) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_WID (32) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_MSK (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_MAX (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_0_Current_Loopcount_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_REG (0x000048C4) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_WID (32) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_MSK (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_MAX (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_STATUS_MCMAIN_1_Current_Loopcount_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_REG (0x000048C8) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_MSK (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_0_Current_Subsequence_Pointer_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_REG (0x000048CC) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_MSK (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_SUBSEQ_PNTR_MCMAIN_1_Current_Subsequence_Pointer_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_REG (0x000048D0) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_MSK (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_0_Current_Cacheline_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_REG (0x000048D4) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_MSK (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_CACHELINE_STATUS_MCMAIN_1_Current_Cacheline_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_REG (0x000048D8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Column_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Row_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_OFF (48) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_MSK (0x7000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Bank_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_MSK (0x700000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_0_Rank_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_REG (0x000048E0) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Column_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Row_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_OFF (48) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_MSK (0x7000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Bank_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_MSK (0x700000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_START_MCMAIN_1_Rank_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_REG (0x000048E8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_DEF_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Column_Address_DEF (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_MSK (0xFFFF000000ULL) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Row_Address_DEF (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_OFF (48) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_MSK (0x7000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Bank_Address_DEF (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_MSK (0x700000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_0_Rank_Address_DEF (0x00000007) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_REG (0x000048F0) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_DEF_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Column_Address_DEF (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Row_Address_DEF (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_OFF (48) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_MSK (0x7000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Bank_Address_DEF (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_MSK (0x700000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_WRAP_MCMAIN_1_Rank_Address_DEF (0x00000007) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_REG (0x000048F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Column_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Row_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_OFF (48) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_MSK (0x7000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Bank_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_MSK (0x700000000000000ULL) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_0_Rank_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_REG (0x00004900) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Column_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Row_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_OFF (48) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_MSK (0x7000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Bank_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_MSK (0x700000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_CURRENT_MCMAIN_1_Rank_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_REG (0x00004908) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_MSK (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Column_Address_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_OFF ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_MSK (0x0000000C) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Row_Address_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_OFF ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_MSK (0x00000030) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Bank_Address_Order_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_OFF ( 6) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_MSK (0x000000C0) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Rank_Address_Order_DEF (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_OFF (13) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_MSK (0x0000E000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Base_Address_Invert_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_OFF (25) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_OFF (27) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_OFF (28) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_MSK (0x10000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Column_Base_Wrap_Carry_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Row_Base_Wrap_Carry_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_OFF (30) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Bank_Base_Wrap_Carry_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_OFF (31) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_0_Rank_Base_Wrap_Carry_Enable_DEF (0x00000001) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_REG (0x0000490C) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_MSK (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Column_Address_Order_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_OFF ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_MSK (0x0000000C) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Row_Address_Order_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_OFF ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_MSK (0x00000030) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Bank_Address_Order_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_OFF ( 6) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_MSK (0x000000C0) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Rank_Address_Order_DEF (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_OFF (13) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_MSK (0x0000E000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Base_Address_Invert_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_MSK (0x00100000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_OFF (21) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_MSK (0x00200000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_OFF (22) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_MSK (0x00400000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_OFF (23) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_MSK (0x00800000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Address_Invert_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_MSK (0x01000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_OFF (25) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_MSK (0x02000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_OFF (26) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_MSK (0x04000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_OFF (27) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_MSK (0x08000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Trigger_Enable_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_OFF (28) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_MSK (0x10000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Column_Base_Wrap_Carry_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_OFF (29) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_MSK (0x20000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Row_Base_Wrap_Carry_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_OFF (30) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_MSK (0x40000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Bank_Base_Wrap_Carry_Enable_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_OFF (31) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_MSK (0x80000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_ORDER_CARRY_INVERT_CTL_MCMAIN_1_Rank_Base_Wrap_Carry_Enable_DEF (0x00000001) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_REG (0x00004910) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Increment_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_OFF (12) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_WID (5) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_MSK (0x0001F000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_OFF (19) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_MSK (0x00080000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Column_Base_Address_Update_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_WID (12) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_MSK (0xFFF00000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_MAX (0x00000FFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Increment_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_OFF (32) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_WID (4) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_MSK (0xF00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_OFF (37) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_MSK (0x2000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Row_Base_Address_Update_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_OFF (38) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_MSK (0x1C000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Increment_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_OFF (44) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_WID (5) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_MSK (0x1F00000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_OFF (51) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_MSK (0x8000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Bank_Base_Address_Update_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_OFF (52) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_MSK (0x70000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Increment_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_WID (5) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_MSK (0x1F00000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_OFF (63) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_MSK (0x8000000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_0_Rank_Base_Address_Update_Scale_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_REG (0x00004918) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Increment_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_OFF (12) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_WID (5) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_MSK (0x0001F000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_OFF (19) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_MSK (0x00080000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Column_Base_Address_Update_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_WID (12) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_MSK (0xFFF00000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_MAX (0x00000FFF) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Increment_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_OFF (32) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_WID (4) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_MSK (0xF00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_OFF (37) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_MSK (0x2000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Row_Base_Address_Update_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_OFF (38) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_MSK (0x1C000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Increment_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_OFF (44) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_WID (5) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_MSK (0x1F00000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_OFF (51) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_MSK (0x8000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Bank_Base_Address_Update_Scale_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_OFF (52) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_WID (3) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_MSK (0x70000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Increment_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_OFF (56) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_WID (5) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_MSK (0x1F00000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_MAX (0x0000001F) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Rate_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_OFF (63) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_WID (1) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_MSK (0x8000000000000000) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_BASE_ADDR_INC_CTL_MCMAIN_1_Rank_Base_Address_Update_Scale_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_REG (0x00004920) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Column_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_0_Row_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_REG (0x00004928) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_OFF (3) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_WID_A0 (7) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_MSK_A0 (0x000003F8) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_MAX_A0 (0x0000007F) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_WID (8) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_MSK (0x000007F8) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Column_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_MSK (0xFFFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_OFFSET_ADDR_CURRENT_MCMAIN_1_Row_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_REG (0x00004930) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_MSK (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank0_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_OFF ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_MSK (0x00000030) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank1_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_OFF ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_MSK (0x00000300) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank2_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_OFF (12) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_MSK (0x00003000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank3_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_OFF (16) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_MSK (0x00030000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank4_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_MSK (0x00300000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank5_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_MSK (0x03000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank6_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_OFF (28) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_0_Logical_to_Physical_Rank7_Mapping_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_REG (0x00004934) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_MSK (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank0_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_OFF ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_MSK (0x00000030) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank1_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_OFF ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_MSK (0x00000300) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank2_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_OFF (12) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_MSK (0x00003000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank3_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_OFF (16) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_MSK (0x00030000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank4_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_MSK (0x00300000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank5_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_MSK (0x03000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank6_Mapping_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_OFF (28) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_WID ( 2) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_MSK (0x30000000) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_MAX (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_RANK_LOGICAL_TO_PHYSICAL_MAPPING_MCMAIN_1_Logical_to_Physical_Rank7_Mapping_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_REG (0x00004938) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_MSK (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row0_Swizzle_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_OFF ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_MSK (0x000001E0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row1_Swizzle_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_OFF (10) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_MSK (0x00003C00) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row2_Swizzle_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_OFF (15) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_MSK (0x00078000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row3_Swizzle_DEF (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row4_Swizzle_DEF (0x00000004) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_OFF (25) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_MSK (0x1E000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_0_Logical_to_Physical_Row5_Swizzle_DEF (0x00000005) + +#define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_REG (0x0000493C) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_MSK (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row0_Swizzle_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_OFF ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_MSK (0x000001E0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row1_Swizzle_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_OFF (10) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_MSK (0x00003C00) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row2_Swizzle_DEF (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_OFF (15) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_MSK (0x00078000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row3_Swizzle_DEF (0x00000003) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row4_Swizzle_DEF (0x00000004) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_OFF (25) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_MSK (0x1E000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_LOWER_MCMAIN_1_Logical_to_Physical_Row5_Swizzle_DEF (0x00000005) + +#define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_REG (0x00004940) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_MSK (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row6_Swizzle_DEF (0x00000006) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_OFF ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_MSK (0x000001E0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row7_Swizzle_DEF (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_OFF (10) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_MSK (0x00003C00) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row8_Swizzle_DEF (0x00000008) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_OFF (15) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_MSK (0x00078000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row9_Swizzle_DEF (0x00000009) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row10_Swizzle_DEF (0x0000000A) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_OFF (25) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_MSK (0x1E000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row11_Swizzle_DEF (0x0000000B) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_OFF (30) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_MSK (0x3C0000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row12_Swizzle_DEF (0x0000000C) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_OFF (35) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_MSK (0x7800000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row13_Swizzle_DEF (0x0000000D) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_OFF (40) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_MSK (0xF0000000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row14_Swizzle_DEF (0x0000000E) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_OFF (45) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_MSK (0x1E00000000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_0_Logical_to_Physical_Row15_Swizzle_DEF (0x0000000F) + +#define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_REG (0x00004948) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_MSK (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row6_Swizzle_DEF (0x00000006) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_OFF ( 5) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_MSK (0x000001E0) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row7_Swizzle_DEF (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_OFF (10) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_MSK (0x00003C00) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row8_Swizzle_DEF (0x00000008) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_OFF (15) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_MSK (0x00078000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row9_Swizzle_DEF (0x00000009) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_OFF (20) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_MSK (0x00F00000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row10_Swizzle_DEF (0x0000000A) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_OFF (25) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_MSK (0x1E000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row11_Swizzle_DEF (0x0000000B) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_OFF (30) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_MSK (0x3C0000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row12_Swizzle_DEF (0x0000000C) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_OFF (35) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_MSK (0x7800000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row13_Swizzle_DEF (0x0000000D) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_OFF (40) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_MSK (0xF0000000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row14_Swizzle_DEF (0x0000000E) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_OFF (45) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_WID ( 4) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_MSK (0x1E00000000000) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_MAX (0x0000000F) + #define MCDFXS_CR_REUT_CH_SEQ_ROW_ADDR_SWIZZLE_UPPER_MCMAIN_1_Logical_to_Physical_Row15_Swizzle_DEF (0x0000000F) + +#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_REG (0x00004950) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_MSK (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Row_Current_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_MSK (0x07000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_0_Dummy_Read_Bank_Current_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_REG (0x00004954) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_WID (16) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_MSK (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_MAX (0x0000FFFF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Row_Current_Address_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_WID ( 3) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_MSK (0x07000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_MAX (0x00000007) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_ADDRESS_MCMAIN_1_Dummy_Read_Bank_Current_Address_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_REG (0x00004958) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_MSK (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_0_Dummy_Read_Bank_Mask_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_REG (0x0000495C) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_MSK (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_MASK_MCMAIN_1_Dummy_Read_Bank_Mask_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_REG (0x00004960) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_MSK (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_DummyRead_Select_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_OFF ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_OFF ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_L_counter_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_OFF (16) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_MSK (0x00FF0000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_M_counter_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_MSK (0xFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_0_N_Counter_DEF (0x00000001) + +#define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_REG (0x00004964) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_OFF ( 0) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_MSK (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_DummyRead_Select_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_OFF ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_WID ( 1) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_OFF ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_MSK (0x0000FF00) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_L_counter_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_OFF (16) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_MSK (0x00FF0000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_M_counter_DEF (0x00000001) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_OFF (24) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_WID ( 8) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_MSK (0xFF000000) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_MAX (0x000000FF) + #define MCDFXS_CR_REUT_CH_SEQ_DUMMYREAD_CTL_MCMAIN_1_N_Counter_DEF (0x00000001) + +#define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_REG (0x00004968) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_OFF ( 0) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_WID ( 1) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_MSK (0x00000001) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_MAX (0x00000001) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_EN_CLK_DEF (0x00000000) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_OFF ( 1) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_WID ( 7) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_MSK (0x000000FE) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_MAX (0x0000007F) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_DATA_BYTE_SEL_DEF (0x00000000) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_OFF ( 8) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_WID ( 1) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_MSK (0x00000100) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_MAX (0x00000001) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L0_BYP_SEL_DEF (0x00000000) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_OFF ( 9) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_WID ( 7) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_MSK (0x0000FE00) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_MAX (0x0000007F) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_DATA_BYTE_SEL_DEF (0x00000000) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_OFF (16) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_WID ( 1) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_MSK (0x00010000) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_MAX (0x00000001) + #define MCDFXS_CR_VISA_CTL_MCDFXS_MCMAIN_L1_BYP_SEL_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_REG (0x0000496C) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_OFF ( 0) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_MSK (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_In_Global_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_OFF ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_WID ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_MSK (0x00000002) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_Global_Start_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_OFF ( 7) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_WID ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_MSK (0x00000080) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_0_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_OFF ( 8) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_WID ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_MSK (0x00000100) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Error_1_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_OFF (15) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_WID ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_MSK (0x00008000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_0_DEF (0x00000000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_OFF (16) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_WID ( 1) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_MSK (0x00010000) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_MAX (0x00000001) + #define MCDFXS_CR_REUT_CH_ERR_TRIGGER_CTL_MCMAIN_Trigger_Out_On_Channel_Test_Done_Status_1_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_REG (0x00004980) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_OFF (0) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_WID (32) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_MSK (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_MAX (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_0_Loopcount_Limit_DEF (0x00000000) + +#define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_REG (0x00004984) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_OFF (0) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_WID (32) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_MSK (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_MAX (0xFFFFFFFF) + #define MCDFXS_CR_REUT_CH_SEQ_LOOPCOUNT_LIMIT_MCMAIN_1_Loopcount_Limit_DEF (0x00000000) + +#define MCSCHEDS_CR_TC_BANK_REG (0x00004C00) + #define MCSCHEDS_CR_TC_BANK_tRCD_OFF ( 0) + #define MCSCHEDS_CR_TC_BANK_tRCD_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_tRCD_MSK (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_tRCD_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_tRCD_DEF (0x00000006) + #define MCSCHEDS_CR_TC_BANK_tRP_OFF ( 5) + #define MCSCHEDS_CR_TC_BANK_tRP_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_tRP_MSK (0x000003E0) + #define MCSCHEDS_CR_TC_BANK_tRP_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_tRP_DEF (0x00000006) + #define MCSCHEDS_CR_TC_BANK_tRAS_OFF (10) + #define MCSCHEDS_CR_TC_BANK_tRAS_WID ( 6) + #define MCSCHEDS_CR_TC_BANK_tRAS_MSK (0x0000FC00) + #define MCSCHEDS_CR_TC_BANK_tRAS_MAX (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_tRAS_DEF (0x00000014) + #define MCSCHEDS_CR_TC_BANK_tRDPRE_OFF (16) + #define MCSCHEDS_CR_TC_BANK_tRDPRE_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_tRDPRE_MSK (0x000F0000) + #define MCSCHEDS_CR_TC_BANK_tRDPRE_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_tRDPRE_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_tWRPRE_OFF (20) + #define MCSCHEDS_CR_TC_BANK_tWRPRE_WID ( 6) + #define MCSCHEDS_CR_TC_BANK_tWRPRE_MSK (0x03F00000) + #define MCSCHEDS_CR_TC_BANK_tWRPRE_MAX (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_tWRPRE_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_tRRD_OFF (26) + #define MCSCHEDS_CR_TC_BANK_tRRD_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_tRRD_MSK (0x3C000000) + #define MCSCHEDS_CR_TC_BANK_tRRD_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_tRRD_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_tRPab_ext_OFF (30) + #define MCSCHEDS_CR_TC_BANK_tRPab_ext_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_tRPab_ext_MSK (0xC0000000) + #define MCSCHEDS_CR_TC_BANK_tRPab_ext_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_tRPab_ext_DEF (0x00000000) + +#define MCSCHEDS_CR_TC_BANK_RANK_A_REG (0x00004C04) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_OFF ( 0) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_MSK (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tCKE_DEF (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_OFF ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_WID ( 8) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_MSK (0x00000FF0) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_MAX (0x000000FF) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tFAW_DEF (0x00000010) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_OFF (12) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_WID ( 3) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_MSK (0x00007000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_MAX (0x00000007) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_OFF (15) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_MSK (0x00078000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dr_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_OFF (19) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_MSK (0x00780000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDRD_dd_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_OFF (23) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_MSK (0x0F800000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_A_tRDPDEN_DEF (0x00000004) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_OFF (29) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_WID ( 1) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_MSK (0x20000000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_MAX (0x00000001) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_3st_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_OFF (30) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_MSK (0xC0000000) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_A_CMD_stretch_DEF (0x00000002) + +#define MCSCHEDS_CR_TC_BANK_RANK_B_REG (0x00004C08) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_OFF ( 0) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_WID ( 6) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_MSK (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_MAX (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_OFF ( 6) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_MSK (0x000003C0) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dr_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_OFF (10) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_MSK (0x00003C00) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRRD_dd_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_OFF (14) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_WID ( 3) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_MSK (0x0001C000) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_MAX (0x00000007) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_OFF (17) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_MSK (0x001E0000) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dr_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_OFF (21) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_MSK (0x01E00000) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRWR_dd_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_OFF (25) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_WID ( 6) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_MSK (0x7E000000) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_MAX (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_RANK_B_tWRPDEN_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_OFF (31) + #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_WID ( 1) + #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_MSK (0x80000000) + #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_MAX (0x00000001) + #define MCSCHEDS_CR_TC_BANK_RANK_B_Dec_WRD_DEF (0x00000000) + +#define MCSCHEDS_CR_TC_BANK_RANK_C_REG (0x00004C0C) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_OFF ( 0) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_WID ( 6) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_MSK (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_MAX (0x0000003F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXPDLL_DEF (0x0000000A) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_OFF ( 6) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_MSK (0x000003C0) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tXP_DEF (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_OFF (10) + #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_WID ( 4) + #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_MSK (0x00003C00) + #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_MAX (0x0000000F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_TAONPD_DEF (0x00000009) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_OFF (14) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_MSK (0x0007C000) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_OFF (19) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_MSK (0x00F80000) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dr_DEF (0x00000005) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_OFF (24) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_MSK (0x1F000000) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_C_tRDWR_dd_DEF (0x00000005) + +#define MCSCHEDS_CR_CMD_RATE_REG (0x00004C10) + #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_OFF ( 0) + #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_WID ( 1) + #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_MSK (0x00000001) + #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_MAX (0x00000001) + #define MCSCHEDS_CR_CMD_RATE_enable_cmd_rate_limit_DEF (0x00000000) + #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_OFF ( 1) + #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_WID ( 3) + #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_MSK (0x0000000E) + #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_MAX (0x00000007) + #define MCSCHEDS_CR_CMD_RATE_cmd_rate_limit_DEF (0x00000004) + #define MCSCHEDS_CR_CMD_RATE_reset_on_command_OFF ( 4) + #define MCSCHEDS_CR_CMD_RATE_reset_on_command_WID ( 4) + #define MCSCHEDS_CR_CMD_RATE_reset_on_command_MSK (0x000000F0) + #define MCSCHEDS_CR_CMD_RATE_reset_on_command_MAX (0x0000000F) + #define MCSCHEDS_CR_CMD_RATE_reset_on_command_DEF (0x00000000) + #define MCSCHEDS_CR_CMD_RATE_reset_delay_OFF ( 8) + #define MCSCHEDS_CR_CMD_RATE_reset_delay_WID ( 4) + #define MCSCHEDS_CR_CMD_RATE_reset_delay_MSK (0x00000F00) + #define MCSCHEDS_CR_CMD_RATE_reset_delay_MAX (0x0000000F) + #define MCSCHEDS_CR_CMD_RATE_reset_delay_DEF (0x00000000) + #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_OFF (12) + #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_WID ( 2) + #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_MSK (0x00003000) + #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_MAX (0x00000003) + #define MCSCHEDS_CR_CMD_RATE_ck_to_cke_delay_DEF (0x00000001) + #define MCSCHEDS_CR_CMD_RATE_spare_OFF (14) + #define MCSCHEDS_CR_CMD_RATE_spare_WID (17) + #define MCSCHEDS_CR_CMD_RATE_spare_MSK (0x7FFFC000) + #define MCSCHEDS_CR_CMD_RATE_spare_MAX (0x0001FFFF) + #define MCSCHEDS_CR_CMD_RATE_spare_DEF (0x00000000) + #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_OFF (31) + #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_WID ( 1) + #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_MSK (0x80000000) + #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_MAX (0x00000001) + #define MCSCHEDS_CR_CMD_RATE_init_mrw_2n_cs_DEF (0x00000000) + +#define MCSCHEDS_CR_TC_BANK_RANK_D_REG (0x00004C14) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_OFF ( 0) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_MSK (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCL_DEF (0x00000006) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_OFF ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_WID ( 5) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_MSK (0x000003E0) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_MAX (0x0000001F) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tWCL_DEF (0x00000006) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_OFF (10) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_MSK (0x00000C00) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tCPDED_DEF (0x00000001) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_OFF (12) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_MSK (0x00003000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_D_tPRPDEN_DEF (0x00000001) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_OFF (14) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_WID ( 3) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_MSK (0x0001C000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_MAX (0x00000007) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Delay_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_OFF (17) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_MSK (0x00060000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Read_Duration_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_OFF (19) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_MSK (0x00180000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_OFF (19) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_WID ( 3) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MSK (0x00380000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MAX (0x00000007) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_OFF (22) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_WID ( 3) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MSK (0x01C00000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MAX (0x00000007) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_OFF (25) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_WID ( 1) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MSK (0x02000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MAX (0x00000001) + #define MCSCHEDS_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_DEF (0x00000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_OFF (26) + #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_WID ( 2) + #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_MSK (0x0C000000) + #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_MAX (0x00000003) + #define MCSCHEDS_CR_TC_BANK_RANK_D_cmd_delay_Ult_DEF (0x00000000) + +#define MCSCHEDS_CR_SCHED_CBIT_REG (0x00004C20) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_OFF ( 0) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_MSK (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_cas_DEF (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_OFF ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_MSK (0x00000002) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_cas_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_OFF ( 2) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_MSK (0x00000004) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ras_DEF (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_OFF ( 3) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_MSK (0x00000008) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_is_ras_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_OFF ( 4) + #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_MSK (0x00000010) + #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_1c_byp_DEF (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_OFF ( 5) + #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_MSK (0x00000020) + #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_2c_byp_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_OFF ( 6) + #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_MSK (0x00000040) + #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_deprd_opt_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_OFF ( 7) + #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_MSK (0x00000080) + #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_pt_it_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_OFF ( 8) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_MSK (0x00000100) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_ring_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_OFF ( 9) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_MSK (0x00000200) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_prcnt_sa_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_OFF (10) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_MSK (0x00000400) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_ph_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_OFF (11) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_MSK (0x00000800) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pe_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_OFF (12) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_MSK (0x00001000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_blkr_pm_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_OFF (13) + #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_MSK (0x00002000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_odt_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_OFF (14) + #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_MSK (0x00004000) + #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_OE_alw_off_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_OFF (16) + #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_MSK (0x00010000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_aom_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_OFF (17) + #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_MSK (0x00020000) + #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_block_rpq_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_OFF (18) + #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_MSK (0x00040000) + #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_block_wpq_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_invert_align_OFF (19) + #define MCSCHEDS_CR_SCHED_CBIT_invert_align_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_invert_align_MSK (0x00080000) + #define MCSCHEDS_CR_SCHED_CBIT_invert_align_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_invert_align_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_OFF (20) + #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_MSK (0x00100000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_write_gap_DEF (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_OFF (21) + #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_MSK (0x00200000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_zq_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_OFF (22) + #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_MSK (0x00400000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_tt_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_OFF (23) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_MSK (0x00800000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_opp_ref_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_OFF (24) + #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_MSK (0x01000000) + #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_Long_ZQ_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_OFF (25) + #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_MSK (0x02000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_srx_zq_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_OFF (26) + #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_MSK (0x04000000) + #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_Serialize_ZQ_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_OFF (27) + #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_MSK (0x08000000) + #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_ZQ_fast_exec_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_OFF (28) + #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_MSK (0x10000000) + #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_Dis_DriveNop_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_OFF (29) + #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_MSK (0x20000000) + #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_Pres_WDB_Ent_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_OFF (30) + #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_WID ( 1) + #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_MSK (0x40000000) + #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_CBIT_dis_clk_gate_DEF (0x00000000) + +#define MCSCHEDS_CR_SC_ROUNDT_LAT_REG (0x00004C24) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_OFF ( 0) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_WID ( 6) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_MSK (0x0000003F) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_MAX (0x0000003F) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D0_DEF (0x00000020) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_OFF ( 8) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_WID ( 6) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_MSK (0x00003F00) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_MAX (0x0000003F) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D0_DEF (0x00000020) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_OFF (16) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_WID ( 6) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_MSK (0x003F0000) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_MAX (0x0000003F) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R0D1_DEF (0x00000020) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_OFF (24) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_WID ( 6) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_MSK (0x3F000000) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_MAX (0x0000003F) + #define MCSCHEDS_CR_SC_ROUNDT_LAT_Lat_R1D1_DEF (0x00000020) + +#define MCSCHEDS_CR_SC_IO_LATENCY_REG (0x00004C28) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_OFF ( 0) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_WID ( 4) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_MSK (0x0000000F) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_MAX (0x0000000F) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D0_DEF (0x00000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_OFF ( 4) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_WID ( 4) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_MSK (0x000000F0) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_MAX (0x0000000F) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D0_DEF (0x00000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_OFF ( 8) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_WID ( 4) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_MSK (0x00000F00) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_MAX (0x0000000F) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R0D1_DEF (0x00000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_OFF (12) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_WID ( 4) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_MSK (0x0000F000) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_MAX (0x0000000F) + #define MCSCHEDS_CR_SC_IO_LATENCY_IOLAT_R1D1_DEF (0x00000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_OFF (16) + #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_WID ( 6) + #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_MSK (0x003F0000) + #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_MAX (0x0000003F) + #define MCSCHEDS_CR_SC_IO_LATENCY_RT_IOCOMP_DEF (0x0000000E) + #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_OFF (30) + #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_WID ( 1) + #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_MSK (0x40000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_MAX (0x00000001) + #define MCSCHEDS_CR_SC_IO_LATENCY_three_channels_DEF (0x00000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_OFF (31) + #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_WID ( 1) + #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MSK (0x80000000) + #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MAX (0x00000001) + #define MCSCHEDS_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_DEF (0x00000000) + +#define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_REG (0x00004C2C) + #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_OFF ( 0) + #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_WID (32) + #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_MSK (0xFFFFFFFF) + #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_MAX (0xFFFFFFFF) + #define MCSCHEDS_CR_ROUND_TRIP_DFT_DATA_DATA_DEF (0x00000000) + +#define MCSCHEDS_CR_DFT_MISC_REG (0x00004C30) + #define MCSCHEDS_CR_DFT_MISC_WDAR_OFF ( 0) + #define MCSCHEDS_CR_DFT_MISC_WDAR_WID ( 1) + #define MCSCHEDS_CR_DFT_MISC_WDAR_MSK (0x00000001) + #define MCSCHEDS_CR_DFT_MISC_WDAR_MAX (0x00000001) + #define MCSCHEDS_CR_DFT_MISC_WDAR_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_OFF ( 1) + #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_WID ( 3) + #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_MSK (0x0000000E) + #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_MAX (0x00000007) + #define MCSCHEDS_CR_DFT_MISC_safe_mask_sel_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_OFF ( 4) + #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_WID ( 1) + #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_MSK (0x00000010) + #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_MAX (0x00000001) + #define MCSCHEDS_CR_DFT_MISC_force_rcv_en_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_OFF ( 8) + #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_WID ( 2) + #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_MSK (0x00000300) + #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_MAX (0x00000003) + #define MCSCHEDS_CR_DFT_MISC_DDR_QUAL_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_Qual_length_OFF (10) + #define MCSCHEDS_CR_DFT_MISC_Qual_length_WID ( 2) + #define MCSCHEDS_CR_DFT_MISC_Qual_length_MSK (0x00000C00) + #define MCSCHEDS_CR_DFT_MISC_Qual_length_MAX (0x00000003) + #define MCSCHEDS_CR_DFT_MISC_Qual_length_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_OFF (12) + #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_WID ( 1) + #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_MSK (0x00001000) + #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_MAX (0x00000001) + #define MCSCHEDS_CR_DFT_MISC_WDB_Block_En_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_OFF (13) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_WID ( 4) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_MSK (0x0001E000) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_MAX (0x0000000F) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_PTR_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_OFF (17) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_WID ( 1) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_MSK (0x00020000) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_MAX (0x00000001) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_ENABLE_DEF (0x00000000) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_OFF (18) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_WID ( 1) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MSK (0x00040000) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MAX (0x00000001) + #define MCSCHEDS_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_DEF (0x00000000) + +#define MCSCHEDS_CR_READ_RETURN_DFT_REG (0x00004C34) + #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_OFF ( 0) + #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_WID ( 8) + #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_MSK (0x000000FF) + #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_MAX (0x000000FF) + #define MCSCHEDS_CR_READ_RETURN_DFT_ECC_DEF (0x00000000) + #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_OFF ( 8) + #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_WID ( 2) + #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_MSK (0x00000300) + #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_MAX (0x00000003) + #define MCSCHEDS_CR_READ_RETURN_DFT_RRD_DFT_Mode_DEF (0x00000000) + #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_OFF (10) + #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_WID ( 5) + #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_MSK (0x00007C00) + #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_MAX (0x0000001F) + #define MCSCHEDS_CR_READ_RETURN_DFT_LFSR_Seed_Index_DEF (0x00000000) + #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_OFF (15) + #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_WID ( 1) + #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_MSK (0x00008000) + #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_MAX (0x00000001) + #define MCSCHEDS_CR_READ_RETURN_DFT_Inversion_Mode_DEF (0x00000000) + +#define MCSCHEDS_CR_SCHED_SECOND_CBIT_REG (0x00004C38) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_OFF ( 0) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_WID ( 1) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_MSK (0x00000001) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_imph_error_DEF (0x00000000) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_OFF ( 8) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_WID ( 1) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_MSK (0x00000100) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_MAX (0x00000001) + #define MCSCHEDS_CR_SCHED_SECOND_CBIT_dis_async_odt_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG (0x00004C40) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MSK (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_OFF ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MSK (0x00000018) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_OFF ( 6) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MSK (0x000000C0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_OFF (14) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MSK (0x00004000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_OFF (15) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MSK (0x00008000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_OFF (16) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MSK (0x003F0000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_OFF (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MSK (0x07000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_REG (0x00004C44) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MSK (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG (0x00004C48) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_REG (0x00004C4C) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_REG (0x00004C50) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG (0x00004C54) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_REG (0x00004C58) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_REG (0x00004C5C) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_REG (0x00004C60) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_REG (0x00004C64) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_REG (0x00004C68) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_REG (0x00004C6C) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_REG (0x00004C70) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_REG (0x00004C74) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_WID (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_REG (0x00004C78) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MSK (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MSK (0x0000FF00) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_OFF (16) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MSK (0x00FF0000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_OFF (24) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MSK (0xFF000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_DEF (0x00000001) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_REG (0x00004C84) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MSK (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_OFF (16) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MSK (0x000F0000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_OFF (20) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MSK (0x00100000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_OFF (30) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MSK (0x40000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_OFF (31) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MSK (0x80000000) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_REG (0x00004C90) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_WID (64) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MSK (0xFFFFFFFFFFFFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MAX (0xFFFFFFFFFFFFFFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_CTL_REG (0x00004C98) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MSK (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_OFF (12) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MSK (0x00003000) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_OFF (16) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MSK (0x00FF0000) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_DEF (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_OFF (24) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MSK (0xFF000000) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_DEF (0x000000FF) + +#define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_REG (0x00004C9C) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MSK (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_DEF (0x00000000) + +#define MCSCHEDS_CR_STM_CONFIG_REG (0x00004CA4) + #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_OFF ( 0) + #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_WID ( 2) + #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_MSK (0x00000003) + #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_MAX (0x00000003) + #define MCSCHEDS_CR_STM_CONFIG_Stretch_mode_DEF (0x00000000) + #define MCSCHEDS_CR_STM_CONFIG_STF_OFF ( 4) + #define MCSCHEDS_CR_STM_CONFIG_STF_WID ( 3) + #define MCSCHEDS_CR_STM_CONFIG_STF_MSK (0x00000070) + #define MCSCHEDS_CR_STM_CONFIG_STF_MAX (0x00000007) + #define MCSCHEDS_CR_STM_CONFIG_STF_DEF (0x00000000) + +#define MCSCHEDS_CR_SC_PR_CNT_CONFIG_REG (0x00004CA8) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_OFF ( 0) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_WID (10) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MSK (0x000003FF) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MAX (0x000003FF) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_ring_DEF (0x00000040) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_OFF (16) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_WID (10) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MSK (0x03FF0000) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MAX (0x000003FF) + #define MCSCHEDS_CR_SC_PR_CNT_CONFIG_Priority_count_SA_DEF (0x00000100) + +#define MCSCHEDS_CR_SC_PCIT_REG (0x00004CAC) + #define MCSCHEDS_CR_SC_PCIT_PCIT_OFF ( 0) + #define MCSCHEDS_CR_SC_PCIT_PCIT_WID ( 8) + #define MCSCHEDS_CR_SC_PCIT_PCIT_MSK (0x000000FF) + #define MCSCHEDS_CR_SC_PCIT_PCIT_MAX (0x000000FF) + #define MCSCHEDS_CR_SC_PCIT_PCIT_DEF (0x00000040) + +#define MCSCHEDS_CR_PM_PDWN_CONFIG_REG (0x00004CB0) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_OFF ( 0) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_WID (12) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MSK (0x00000FFF) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MAX (0x00000FFF) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_idle_counter_DEF (0x00000000) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_OFF (12) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_WID ( 4) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_MSK (0x0000F000) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_MAX (0x0000000F) + #define MCSCHEDS_CR_PM_PDWN_CONFIG_PDWN_mode_DEF (0x00000000) + +#define MCSCHEDS_CR_ECC_INJECT_COUNT_REG (0x00004CB4) + #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_OFF ( 0) + #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_WID (32) + #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_MSK (0xFFFFFFFF) + #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_MAX (0xFFFFFFFF) + #define MCSCHEDS_CR_ECC_INJECT_COUNT_Count_DEF (0xFFFFFFFF) + +#define MCSCHEDS_CR_ECC_DFT_REG (0x00004CB8) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_OFF ( 0) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_WID ( 8) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_MSK (0x000000FF) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_MAX (0x000000FF) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_fill_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_OFF ( 8) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_WID ( 2) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_MSK (0x00000300) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_MAX (0x00000003) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_trigger_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_OFF (10) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_WID ( 1) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_MSK (0x00000400) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_MAX (0x00000001) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_BS_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_OFF (11) + #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_WID ( 3) + #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_MSK (0x00003800) + #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_MAX (0x00000007) + #define MCSCHEDS_CR_ECC_DFT_ECC_Inject_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_OFF (14) + #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_WID ( 1) + #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_MSK (0x00004000) + #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_MAX (0x00000001) + #define MCSCHEDS_CR_ECC_DFT_ECC_correction_disable_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_OFF (15) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_WID ( 1) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_MSK (0x00008000) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_MAX (0x00000001) + #define MCSCHEDS_CR_ECC_DFT_ECC4ANA_Inject_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_OFF (16) + #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_WID ( 1) + #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_MSK (0x00010000) + #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_MAX (0x00000001) + #define MCSCHEDS_CR_ECC_DFT_DIS_MCA_LOG_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_OFF (17) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_WID ( 1) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_MSK (0x00020000) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_MAX (0x00000001) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCH_EVENT_DEF (0x00000000) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_OFF (18) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_WID ( 1) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_MSK (0x00040000) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_MAX (0x00000001) + #define MCSCHEDS_CR_ECC_DFT_DIS_PCIE_POISON_DEF (0x00000000) + +#define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_REG (0x00004CC0) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_OFF ( 0) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_WID (18) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_MSK (0x0003FFFF) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_MAX (0x0003FFFF) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_Data_DEF (0x00000000) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_OFF (31) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_WID ( 1) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_MSK (0x80000000) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_MAX (0x00000001) + #define MCSCHEDS_CR_VISA_CTL_MCSCHEDS_VORANGE_DEF (0x00000000) + +#define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_REG (0x00004CC4) + #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_OFF ( 0) + #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_WID (32) + #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_MSK (0xFFFFFFFF) + #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_MAX (0xFFFFFFFF) + #define MCSCHEDS_CR_VISA_XBAR_MCSCHEDS_Data_DEF (0x76543210) + +#define MCSCHEDS_CR_ECCERRLOG0_REG (0x00004CC8) + #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_OFF ( 0) + #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_WID ( 1) + #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_MSK (0x00000001) + #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_MAX (0x00000001) + #define MCSCHEDS_CR_ECCERRLOG0_CERRSTS_DEF (0x00000000) + #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_OFF ( 1) + #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_WID ( 1) + #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_MSK (0x00000002) + #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_MAX (0x00000001) + #define MCSCHEDS_CR_ECCERRLOG0_MERRSTS_DEF (0x00000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_OFF (16) + #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_WID ( 8) + #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_MSK (0x00FF0000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_MAX (0x000000FF) + #define MCSCHEDS_CR_ECCERRLOG0_ERRSYND_DEF (0x00000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_OFF (24) + #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_WID ( 3) + #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_MSK (0x07000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_MAX (0x00000007) + #define MCSCHEDS_CR_ECCERRLOG0_ERRCHUNK_DEF (0x00000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_OFF (27) + #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_WID ( 2) + #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_MSK (0x18000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_MAX (0x00000003) + #define MCSCHEDS_CR_ECCERRLOG0_ERRRANK_DEF (0x00000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_OFF (29) + #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_WID ( 3) + #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_MSK (0xE0000000) + #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_MAX (0x00000007) + #define MCSCHEDS_CR_ECCERRLOG0_ERRBANK_DEF (0x00000000) + +#define MCSCHEDS_CR_ECCERRLOG1_REG (0x00004CCC) + #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_OFF ( 0) + #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_WID (16) + #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_MSK (0x0000FFFF) + #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_MAX (0x0000FFFF) + #define MCSCHEDS_CR_ECCERRLOG1_ERRROW_DEF (0x00000000) + #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_OFF (16) + #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_WID (16) + #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_MSK (0xFFFF0000) + #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_MAX (0x0000FFFF) + #define MCSCHEDS_CR_ECCERRLOG1_ERRCOL_DEF (0x00000000) + +#define MCSCHEDS_CR_SC_WR_ADD_DELAY_REG (0x00004CD0) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_OFF ( 0) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_WID ( 2) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_MSK (0x00000003) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_MAX (0x00000003) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R0_DEF (0x00000000) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_OFF ( 2) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_WID ( 2) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_MSK (0x0000000C) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_MAX (0x00000003) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D0R1_DEF (0x00000000) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_OFF ( 4) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_WID ( 2) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_MSK (0x00000030) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_MAX (0x00000003) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R0_DEF (0x00000000) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_OFF ( 6) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_WID ( 2) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_MSK (0x000000C0) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_MAX (0x00000003) + #define MCSCHEDS_CR_SC_WR_ADD_DELAY_D1R1_DEF (0x00000000) + +#define MCSCHEDS_CR_WMM_READ_CONFIG_REG (0x00004CD4) + #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_OFF ( 0) + #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_WID ( 1) + #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_MSK (0x00000001) + #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_MAX (0x00000001) + #define MCSCHEDS_CR_WMM_READ_CONFIG_Dis_Opp_rd_DEF (0x00000000) + #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_OFF ( 1) + #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_WID ( 1) + #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_MSK (0x00000002) + #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_MAX (0x00000001) + #define MCSCHEDS_CR_WMM_READ_CONFIG_ACT_Enable_DEF (0x00000001) + #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_OFF ( 2) + #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_WID ( 1) + #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_MSK (0x00000004) + #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_MAX (0x00000001) + #define MCSCHEDS_CR_WMM_READ_CONFIG_PRE_Enable_DEF (0x00000001) + #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_OFF ( 3) + #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_WID ( 4) + #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MSK (0x00000078) + #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MAX (0x0000000F) + #define MCSCHEDS_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_DEF (0x00000008) + +#define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_REG (0x00004CD8) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_WID (64) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MSK (0xFFFFFFFFFFFFFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MAX (0xFFFFFFFFFFFFFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_REG (0x00004CE0) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_WID (64) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MSK (0xFFFFFFFFFFFFFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MAX (0xFFFFFFFFFFFFFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG (0x00004CE8) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MSK (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MSK (0x0000FF00) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_OFF (16) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MSK (0x000F0000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_OFF (32) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_WID ( 9) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MSK (0x1FF00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MAX (0x000001FF) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_OFF (52) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MSK (0x70000000000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_OFF (56) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MSK (0x3F00000000000000) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_REG (0x00004CF0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_REG (0x00004CF4) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_REG (0x00004CF8) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_REG (0x00004CFC) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_REG (0x00004D00) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_REG (0x00004D04) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_REG (0x00004D08) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_REG (0x00004D0C) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_REG (0x00004D10) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_WID ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MSK (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MAX (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_DEF (0x0000007F) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_OFF ( 7) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MSK (0x00000180) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG (0x00004D14) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_REG (0x00004D18) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_REG (0x00004D1C) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_REG (0x00004D20) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_REG (0x00004D24) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_REG (0x00004D28) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_REG (0x00004D2C) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_REG (0x00004D30) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_REG (0x00004D34) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_WID (23) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MSK (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MAX (0x007FFFFF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_REG (0x00004D38) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_WID ( 9) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MSK (0x000001FF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MAX (0x000001FF) + #define MCSCHEDS_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_REG (0x00004D80) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_WID (10) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_MSK (0x000003FF) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_MAX (0x000003FF) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Column_Address_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_OFF (24) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_WID (16) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_MSK (0xFFFF000000) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Row_Address_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_OFF (48) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_MSK (0x7000000000000) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Bank_Address_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_OFF (56) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_MSK (0x300000000000000) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_ERROR_ADDR_Rank_Address_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_REG (0x00004D88) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MSK (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_REG (0x00004D8C) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MSK (0x00000001) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MSK (0x00003F00) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_OFF (16) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_WID ( 6) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MSK (0x003F0000) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MAX (0x0000003F) + #define MCSCHEDS_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_REG (0x00004D90) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MSK (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_DEF (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MSK (0x00000100) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_OFF (16) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MSK (0x000F0000) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_REG (0x00004D94) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MSK (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_DEF (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_OFF (16) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MSK (0x000F0000) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_OFF (31) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MSK (0x80000000) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_REG (0x00004D98) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MSK (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_OFF ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MSK (0x00000002) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_OFF ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MSK (0x0000003C) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_OFF ( 6) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MSK (0x000003C0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_OFF ( 10) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MSK (0x00003C00) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_OFF ( 14) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MSK (0x0000C000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_OFF ( 16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MSK (0x00030000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_OFF ( 18) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MSK (0x000C0000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_OFF ( 20) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MSK (0x00F00000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_OFF ( 24) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MSK (0x0F000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_REG (0x00004D9C) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MSK (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_DEF (0x00000002) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MSK (0x00000700) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_OFF (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MSK (0x00070000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_DEF (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_OFF (24) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MSK (0x07000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG (0x00004DA0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MSK (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_OFF ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MSK (0x00000030) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MSK (0x00000300) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_OFF ( 16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MSK (0x00030000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_OFF ( 20) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MSK (0x00300000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_OFF ( 24) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_WID ( 2) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MSK (0x03000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MAX (0x00000003) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_DEF (0x00000001) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG (0x00004DA4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG (0x00004DA8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG (0x00004DAC) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_REG (0x00004DB0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MSK (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_OFF ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MSK (0x0000FF00) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_OFF (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MSK (0x00FF0000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_DEF (0x00000001) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_OFF (24) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_WID ( 8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MSK (0xFF000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MAX (0x000000FF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_DEF (0x00000001) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG (0x00004DBC) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MSK (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_REG (0x00004DC0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_OFF (24) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MSK (0x07000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_OFF (32) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MSK (0xF00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_OFF (40) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_WID ( 3) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MSK (0x70000000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MAX (0x00000007) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_OFF (48) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MSK (0xF000000000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_DEF (0x00000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_OFF (56) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_WID ( 4) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MSK (0xF00000000000000) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MAX (0x0000000F) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_REG (0x00004DC8) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_REG (0x00004DCC) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_DEF (0x00000000) + +#define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_REG (0x00004DD0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_OFF ( 0) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_WID (16) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF) + #define MCSCHEDS_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_DEF (0x00000000) + +#define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_REG (0x00004E00) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_OFF ( 0) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_WID ( 5) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MSK (0x0000001F) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MAX (0x0000001F) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_DEF (0x00000000) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_OFF ( 5) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_WID ( 1) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MSK (0x00000020) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MAX (0x00000001) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_DEF (0x00000000) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_OFF ( 8) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_WID ( 6) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MSK (0x00003F00) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MAX (0x0000003F) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_DEF (0x00000000) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_OFF (16) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_WID ( 6) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MSK (0x003F0000) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MAX (0x0000003F) + #define MCMNTS_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_DEF (0x0000003F) + +#define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_REG (0x00004E04) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_OFF ( 0) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_WID ( 4) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MSK (0x0000000F) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MAX (0x0000000F) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_DEF (0x00000000) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_OFF ( 8) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_WID ( 1) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MSK (0x00000100) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MAX (0x00000001) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_DEF (0x00000000) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_OFF (31) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_WID ( 1) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MSK (0x80000000) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MAX (0x00000001) + #define MCMNTS_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_DEF (0x00000000) + +#define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_REG (0x00004E08) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_OFF ( 0) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_WID ( 4) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MSK (0x0000000F) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MAX (0x0000000F) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_DEF (0x00000000) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_OFF (31) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_WID ( 1) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MSK (0x80000000) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MAX (0x00000001) + #define MCMNTS_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_DEF (0x00000000) + +#define MCMNTS_CR_LPDDR_MR_PARAMS_REG (0x00004E10) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_OFF ( 0) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_MSK (0x00000001) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_0_x32_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_OFF ( 1) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_MSK (0x00000002) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_1_x32_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_OFF ( 2) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_MSK (0x00000004) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_2_x32_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_OFF ( 3) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_MSK (0x00000008) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_PARAMS_Rank_3_x32_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_OFF ( 4) + #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_MSK (0x00000010) + #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_PARAMS_LPDDR2_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_OFF ( 8) + #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_WID (16) + #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MSK (0x00FFFF00) + #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MAX (0x0000FFFF) + #define MCMNTS_CR_LPDDR_MR_PARAMS_MR4_PERIOD_DEF (0x00000000) + +#define MCMNTS_CR_LPDDR_MR_COMMAND_REG (0x00004E14) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_OFF ( 0) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_WID ( 8) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_MSK (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_MAX (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Address_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_OFF ( 8) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_WID ( 8) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_MSK (0x0000FF00) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_MAX (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Data_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_OFF (16) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_WID ( 2) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_MSK (0x00030000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_MAX (0x00000003) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Rank_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_OFF (18) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_MSK (0x00040000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Write_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_OFF (19) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_MSK (0x00080000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Init_MRW_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_OFF (31) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_WID ( 1) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_MSK (0x80000000) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_MAX (0x00000001) + #define MCMNTS_CR_LPDDR_MR_COMMAND_Busy_DEF (0x00000000) + +#define MCMNTS_CR_LPDDR_MR_RESULT_REG (0x00004E18) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_OFF ( 0) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_WID ( 8) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_MSK (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_MAX (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_0_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_OFF ( 8) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_WID ( 8) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_MSK (0x0000FF00) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_MAX (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_1_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_OFF (16) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_WID ( 8) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_MSK (0x00FF0000) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_MAX (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_2_DEF (0x00000000) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_OFF (24) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_WID ( 8) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_MSK (0xFF000000) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_MAX (0x000000FF) + #define MCMNTS_CR_LPDDR_MR_RESULT_Device_3_DEF (0x00000000) + +#define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_REG (0x00004E1C) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_OFF ( 0) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_WID ( 3) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MSK (0x00000007) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MAX (0x00000007) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_DEF (0x00000003) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_OFF ( 8) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_WID ( 3) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MSK (0x00000700) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MAX (0x00000007) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_DEF (0x00000003) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_OFF (16) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_WID ( 3) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MSK (0x00070000) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MAX (0x00000007) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_DEF (0x00000003) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_OFF (24) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_WID ( 3) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MSK (0x07000000) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MAX (0x00000007) + #define MCMNTS_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_DEF (0x00000003) + +#define MCMNTS_CR_DESWIZZLE_LOW_REG (0x00004E20) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_OFF ( 0) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_MSK (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_0_DEF (0x00000000) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_OFF ( 4) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_MSK (0x00000070) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_1_DEF (0x00000001) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_OFF ( 8) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_MSK (0x00000700) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_2_DEF (0x00000002) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_OFF (12) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_MSK (0x00007000) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_16_DEF (0x00000000) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_OFF (16) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_MSK (0x00070000) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_17_DEF (0x00000001) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_OFF (20) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_MSK (0x00700000) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Bit_18_DEF (0x00000002) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_OFF (24) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_MSK (0x07000000) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_0_DEF (0x00000000) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_OFF (28) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_MSK (0x70000000) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_LOW_Byte_2_DEF (0x00000002) + +#define MCMNTS_CR_DESWIZZLE_HIGH_REG (0x00004E24) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_OFF ( 0) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_MSK (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_32_DEF (0x00000000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_OFF ( 4) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_MSK (0x00000070) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_33_DEF (0x00000001) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_OFF ( 8) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_MSK (0x00000700) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_34_DEF (0x00000002) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_OFF (12) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_MSK (0x00007000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_48_DEF (0x00000000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_OFF (16) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_MSK (0x00070000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_49_DEF (0x00000001) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_OFF (20) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_MSK (0x00700000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Bit_50_DEF (0x00000002) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_OFF (24) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_MSK (0x07000000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_4_DEF (0x00000004) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_OFF (28) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_WID ( 3) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_MSK (0x70000000) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_MAX (0x00000007) + #define MCMNTS_CR_DESWIZZLE_HIGH_Byte_6_DEF (0x00000006) + +#define MCMNTS_CR_MC_REFRESH_STAGGER_REG (0x00004E8C) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_OFF ( 0) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_WID (11) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_MSK (0x000007FF) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_MAX (0x000007FF) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Interval_DEF (0x00000000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_OFF (11) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_WID ( 1) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MSK (0x00000800) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MAX (0x00000001) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_DEF (0x00000000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_OFF (12) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_WID ( 1) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MSK (0x00001000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MAX (0x00000001) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_DEF (0x00000000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_OFF (13) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_WID ( 1) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MSK (0x00002000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MAX (0x00000001) + #define MCMNTS_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_DEF (0x00000000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_OFF (14) + #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_WID ( 1) + #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MSK (0x00004000) + #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MAX (0x00000001) + #define MCMNTS_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_DEF (0x00000000) + +#define MCMNTS_CR_TC_ZQCAL_REG (0x00004E90) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_OFF ( 0) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_WID ( 8) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_MSK (0x000000FF) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_MAX (0x000000FF) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_DEF (0x00000080) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_OFF ( 8) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_WID ( 8) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_MSK (0x0000FF00) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_MAX (0x000000FF) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_DEF (0x00000040) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_OFF ( 0) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_WID (10) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_MSK (0x000003FF) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_MAX (0x000003FF) + #define MCMNTS_CR_TC_ZQCAL_ZQCS_period_Ult_DEF (0x00000080) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_OFF (10) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_WID (10) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_MSK (0x000FFC00) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_MAX (0x000003FF) + #define MCMNTS_CR_TC_ZQCAL_tZQCS_Ult_DEF (0x00000040) + +#define MCMNTS_CR_TC_RFP_REG (0x00004E94) + #define MCMNTS_CR_TC_RFP_OREF_RI_OFF ( 0) + #define MCMNTS_CR_TC_RFP_OREF_RI_WID ( 8) + #define MCMNTS_CR_TC_RFP_OREF_RI_MSK (0x000000FF) + #define MCMNTS_CR_TC_RFP_OREF_RI_MAX (0x000000FF) + #define MCMNTS_CR_TC_RFP_OREF_RI_DEF (0x0000000F) + #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_OFF ( 8) + #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_WID ( 4) + #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_MSK (0x00000F00) + #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_MAX (0x0000000F) + #define MCMNTS_CR_TC_RFP_Refresh_HP_WM_DEF (0x00000008) + #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_OFF (12) + #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_WID ( 4) + #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_MSK (0x0000F000) + #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_MAX (0x0000000F) + #define MCMNTS_CR_TC_RFP_Refresh_panic_wm_DEF (0x00000009) + +#define MCMNTS_CR_TC_RFTP_REG (0x00004E98) + #define MCMNTS_CR_TC_RFTP_tREFI_OFF ( 0) + #define MCMNTS_CR_TC_RFTP_tREFI_WID (16) + #define MCMNTS_CR_TC_RFTP_tREFI_MSK (0x0000FFFF) + #define MCMNTS_CR_TC_RFTP_tREFI_MAX (0x0000FFFF) + #define MCMNTS_CR_TC_RFTP_tREFI_DEF (0x00001004) + #define MCMNTS_CR_TC_RFTP_tRFC_OFF (16) + #define MCMNTS_CR_TC_RFTP_tRFC_WID ( 9) + #define MCMNTS_CR_TC_RFTP_tRFC_MSK (0x01FF0000) + #define MCMNTS_CR_TC_RFTP_tRFC_MAX (0x000001FF) + #define MCMNTS_CR_TC_RFTP_tRFC_DEF (0x000000B4) + #define MCMNTS_CR_TC_RFTP_tREFIx9_OFF (25) + #define MCMNTS_CR_TC_RFTP_tREFIx9_WID ( 7) + #define MCMNTS_CR_TC_RFTP_tREFIx9_MSK (0xFE000000) + #define MCMNTS_CR_TC_RFTP_tREFIx9_MAX (0x0000007F) + #define MCMNTS_CR_TC_RFTP_tREFIx9_DEF (0x00000023) + +#define MCMNTS_CR_TC_MR2_SHADDOW_REG (0x00004E9C) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_OFF ( 0) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_WID ( 6) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_MSK (0x0000003F) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_MAX (0x0000003F) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_low_DEF (0x00000000) + #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_OFF ( 6) + #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_WID ( 2) + #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_MSK (0x000000C0) + #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_MAX (0x00000003) + #define MCMNTS_CR_TC_MR2_SHADDOW_SRT_avail_DEF (0x00000000) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_OFF ( 8) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_WID ( 3) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_MSK (0x00000700) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_MAX (0x00000007) + #define MCMNTS_CR_TC_MR2_SHADDOW_MR2_sh_high_DEF (0x00000000) + #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_OFF (14) + #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_WID ( 2) + #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MSK (0x0000C000) + #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MAX (0x00000003) + #define MCMNTS_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_DEF (0x00000000) + +#define MCMNTS_CR_MC_INIT_STATE_REG (0x00004EA0) + #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_OFF ( 0) + #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_WID ( 4) + #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_MSK (0x0000000F) + #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_MAX (0x0000000F) + #define MCMNTS_CR_MC_INIT_STATE_Rank_occupancy_DEF (0x0000000F) + +#define MCMNTS_CR_TC_SRFTP_REG (0x00004EA4) + #define MCMNTS_CR_TC_SRFTP_tXSDLL_OFF ( 0) + #define MCMNTS_CR_TC_SRFTP_tXSDLL_WID (12) + #define MCMNTS_CR_TC_SRFTP_tXSDLL_MSK (0x00000FFF) + #define MCMNTS_CR_TC_SRFTP_tXSDLL_MAX (0x00000FFF) + #define MCMNTS_CR_TC_SRFTP_tXSDLL_DEF (0x00000200) + #define MCMNTS_CR_TC_SRFTP_tXS_offset_OFF (12) + #define MCMNTS_CR_TC_SRFTP_tXS_offset_WID ( 4) + #define MCMNTS_CR_TC_SRFTP_tXS_offset_MSK (0x0000F000) + #define MCMNTS_CR_TC_SRFTP_tXS_offset_MAX (0x0000000F) + #define MCMNTS_CR_TC_SRFTP_tXS_offset_DEF (0x0000000B) + #define MCMNTS_CR_TC_SRFTP_tZQOPER_OFF (16) + #define MCMNTS_CR_TC_SRFTP_tZQOPER_WID (10) + #define MCMNTS_CR_TC_SRFTP_tZQOPER_MSK (0x03FF0000) + #define MCMNTS_CR_TC_SRFTP_tZQOPER_MAX (0x000003FF) + #define MCMNTS_CR_TC_SRFTP_tZQOPER_DEF (0x00000100) + #define MCMNTS_CR_TC_SRFTP_tMOD_OFF (28) + #define MCMNTS_CR_TC_SRFTP_tMOD_WID ( 4) + #define MCMNTS_CR_TC_SRFTP_tMOD_MSK (0xF0000000) + #define MCMNTS_CR_TC_SRFTP_tMOD_MAX (0x0000000F) + #define MCMNTS_CR_TC_SRFTP_tMOD_DEF (0x00000000) + +#define MCMNTS_CR_WDB_VISA_SEL_REG (0x00004EA8) + #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_OFF ( 0) + #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_WID ( 3) + #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_MSK (0x00000007) + #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_MAX (0x00000007) + #define MCMNTS_CR_WDB_VISA_SEL_VISAByteSel_DEF (0x00000000) + +#define MCMNTS_CR_DCLK_LDAT_PDAT_REG (0x00004EC0) + #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_OFF ( 0) + #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_WID (12) + #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_MSK (0x00000FFF) + #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_MAX (0x00000FFF) + #define MCMNTS_CR_DCLK_LDAT_PDAT_FASTADDR_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_OFF (16) + #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_MSK (0x00010000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_PDAT_ADDREN_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_OFF (17) + #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_MSK (0x00020000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_PDAT_SEQEN_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_OFF (18) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_MSK (0x00040000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL0_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_OFF (19) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_MSK (0x00080000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_PDAT_POL1_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_OFF (20) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_WID ( 4) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_MSK (0x00F00000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_MAX (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDA_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_OFF (24) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_WID ( 4) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_MSK (0x0F000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_MAX (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDB_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_OFF (28) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_WID ( 4) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_MSK (0xF0000000) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_MAX (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_PDAT_CMDC_DEF (0x00000000) + +#define MCMNTS_CR_DCLK_LDAT_SDAT_REG (0x00004EC4) + #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_OFF ( 0) + #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_WID ( 4) + #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_MSK (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_MAX (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_SDAT_BANKSEL_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_OFF ( 5) + #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_WID ( 5) + #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_MSK (0x000003E0) + #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_MAX (0x0000001F) + #define MCMNTS_CR_DCLK_LDAT_SDAT_ARRAYSEL_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_OFF (10) + #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_MSK (0x00000400) + #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_SDAT_CMP_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_OFF (11) + #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_MSK (0x00000800) + #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_SDAT_REP_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_OFF (12) + #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_WID ( 4) + #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_MSK (0x0000F000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_MAX (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_SDAT_DWORD_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_OFF (16) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_WID ( 2) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_MSK (0x00030000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_MAX (0x00000003) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MODE_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_OFF (18) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_WID ( 6) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_MSK (0x00FC0000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_MAX (0x0000003F) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPMAP_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_OFF (24) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_WID ( 4) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_MSK (0x0F000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_MAX (0x0000000F) + #define MCMNTS_CR_DCLK_LDAT_SDAT_MPBOFFSET_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_OFF (28) + #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_WID ( 1) + #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_MSK (0x10000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_MAX (0x00000001) + #define MCMNTS_CR_DCLK_LDAT_SDAT_STAGE_EN_DEF (0x00000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_OFF (29) + #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_WID ( 2) + #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_MSK (0x60000000) + #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_MAX (0x00000003) + #define MCMNTS_CR_DCLK_LDAT_SDAT_SHADOW_DEF (0x00000000) + +#define MCMNTS_CR_DCLK_LDAT_DATAOUT_REG (0x00004EC8) + #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_OFF ( 0) + #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_WID (32) + #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_MSK (0xFFFFFFFF) + #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_MAX (0xFFFFFFFF) + #define MCMNTS_CR_DCLK_LDAT_DATAOUT_DATOUT_DEF (0x00000000) + +#define MCMNTS_CR_DCLK_LDAT_DATAIN_0_REG (0x00004ECC) + #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_OFF ( 0) + #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_WID (32) + #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_MSK (0xFFFFFFFF) + #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_MAX (0xFFFFFFFF) + #define MCMNTS_CR_DCLK_LDAT_DATAIN_0_DATIN_DEF (0x00000000) + +#define MCMNTS_CR_QCLK_LDAT_PDAT_REG (0x00004ED0) + #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_OFF ( 0) + #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_WID (12) + #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_MSK (0x00000FFF) + #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_MAX (0x00000FFF) + #define MCMNTS_CR_QCLK_LDAT_PDAT_FASTADDR_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_OFF (16) + #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_MSK (0x00010000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_PDAT_ADDREN_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_OFF (17) + #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_MSK (0x00020000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_PDAT_SEQEN_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_OFF (18) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_MSK (0x00040000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL0_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_OFF (19) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_MSK (0x00080000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_PDAT_POL1_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_OFF (20) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_WID ( 4) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_MSK (0x00F00000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_MAX (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDA_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_OFF (24) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_WID ( 4) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_MSK (0x0F000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_MAX (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDB_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_OFF (28) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_WID ( 4) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_MSK (0xF0000000) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_MAX (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_PDAT_CMDC_DEF (0x00000000) + +#define MCMNTS_CR_QCLK_LDAT_SDAT_REG (0x00004ED4) + #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_OFF ( 0) + #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_WID ( 4) + #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_MSK (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_MAX (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_SDAT_BANKSEL_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_OFF ( 5) + #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_WID ( 5) + #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_MSK (0x000003E0) + #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_MAX (0x0000001F) + #define MCMNTS_CR_QCLK_LDAT_SDAT_ARRAYSEL_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_OFF (10) + #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_MSK (0x00000400) + #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_SDAT_CMP_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_OFF (11) + #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_MSK (0x00000800) + #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_SDAT_REP_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_OFF (12) + #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_WID ( 4) + #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_MSK (0x0000F000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_MAX (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_SDAT_DWORD_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_OFF (16) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_WID ( 2) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_MSK (0x00030000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_MAX (0x00000003) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MODE_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_OFF (18) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_WID ( 6) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_MSK (0x00FC0000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_MAX (0x0000003F) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPMAP_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_OFF (24) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_WID ( 4) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_MSK (0x0F000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_MAX (0x0000000F) + #define MCMNTS_CR_QCLK_LDAT_SDAT_MPBOFFSET_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_OFF (28) + #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_WID ( 1) + #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_MSK (0x10000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_MAX (0x00000001) + #define MCMNTS_CR_QCLK_LDAT_SDAT_STAGE_EN_DEF (0x00000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_OFF (29) + #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_WID ( 2) + #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_MSK (0x60000000) + #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_MAX (0x00000003) + #define MCMNTS_CR_QCLK_LDAT_SDAT_SHADOW_DEF (0x00000000) + +#define MCMNTS_CR_QCLK_LDAT_DATAOUT_REG (0x00004ED8) + #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_OFF ( 0) + #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_WID (32) + #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_MSK (0xFFFFFFFF) + #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_MAX (0xFFFFFFFF) + #define MCMNTS_CR_QCLK_LDAT_DATAOUT_DATOUT_DEF (0x00000000) + +#define MCMNTS_CR_QCLK_LDAT_DATAIN_0_REG (0x00004EDC) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_OFF ( 0) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_WID (32) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_MSK (0xFFFFFFFF) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_MAX (0xFFFFFFFF) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_0_DATIN_DEF (0x00000000) + +#define MCMNTS_CR_QCLK_LDAT_DATAIN_1_REG (0x00004EE0) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_OFF ( 0) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_WID (32) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_MSK (0xFFFFFFFF) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_MAX (0xFFFFFFFF) + #define MCMNTS_CR_QCLK_LDAT_DATAIN_1_DATIN_DEF (0x00000000) + +#define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_REG (0x00004EE4) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_OFF ( 0) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_WID (28) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MSK (0x0FFFFFFF) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MAX (0x0FFFFFFF) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_DEF (0x00000000) + +#define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_REG (0x00004EE8) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_OFF ( 0) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_WID (32) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MSK (0xFFFFFFFF) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MAX (0xFFFFFFFF) + #define MCMNTS_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_DEF (0x00000000) + +#define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_REG (0x00004EEC) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_OFF ( 0) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_WID ( 6) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MSK (0x0000003F) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MAX (0x0000003F) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_DEF (0x00000000) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_OFF ( 8) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_WID ( 6) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MSK (0x00003F00) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MAX (0x0000003F) + #define MCMNTS_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_DEF (0x00000000) + +#define MCMNTS_CR_PM_DIMM_PD_ENERGY_REG (0x00004EF0) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_OFF ( 0) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_WID ( 6) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MSK (0x0000003F) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MAX (0x0000003F) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_DEF (0x00000000) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_OFF ( 8) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_WID ( 6) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MSK (0x00003F00) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MAX (0x0000003F) + #define MCMNTS_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_DEF (0x00000000) + +#define MCMNTS_CR_PM_DIMM_ACT_ENERGY_REG (0x00004EF4) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_OFF ( 0) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_WID ( 8) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MSK (0x000000FF) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MAX (0x000000FF) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_DEF (0x00000000) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_OFF ( 8) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_WID ( 8) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MSK (0x0000FF00) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MAX (0x000000FF) + #define MCMNTS_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_DEF (0x00000000) + +#define MCMNTS_CR_PM_DIMM_RD_ENERGY_REG (0x00004EF8) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_OFF ( 0) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_WID ( 8) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MSK (0x000000FF) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MAX (0x000000FF) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_DEF (0x00000000) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_OFF ( 8) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_WID ( 8) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MSK (0x0000FF00) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MAX (0x000000FF) + #define MCMNTS_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_DEF (0x00000000) + +#define MCMNTS_CR_PM_DIMM_WR_ENERGY_REG (0x00004EFC) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_OFF ( 0) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_WID ( 8) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MSK (0x000000FF) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MAX (0x000000FF) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_DEF (0x00000000) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_OFF ( 8) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_WID ( 8) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MSK (0x0000FF00) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MAX (0x000000FF) + #define MCMNTS_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_DEF (0x00000000) + +#define MCMNTS_CR_PM_THRT_CKE_MIN_REG (0x00004F28) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_OFF ( 0) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_WID ( 8) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_MSK (0x000000FF) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_MAX (0x000000FF) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEF (0x00000000) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_OFF ( 8) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_WID ( 1) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MSK (0x00000100) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MAX (0x00000001) + #define MCMNTS_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MATCH0_REG (0x00004F40) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MATCH0_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MATCH1_REG (0x00004F44) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MATCH1_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MATCH2_REG (0x00004F48) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MATCH2_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MATCH3_REG (0x00004F4C) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MATCH3_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MASK0_REG (0x00004F50) + #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK0_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK0_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK0_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK0_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MASK0_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MASK1_REG (0x00004F54) + #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK1_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK1_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK1_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK1_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MASK1_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MASK2_REG (0x00004F58) + #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK2_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK2_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK2_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK2_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MASK2_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_MASK3_REG (0x00004F5C) + #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK3_ODT_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_OFF ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_MSK (0x00000010) + #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK3_Web_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_OFF ( 5) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_MSK (0x00000020) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_WID ( 1) + #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_MSK (0x00000040) + #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_CMD_MASK3_RASb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_OFF ( 7) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_MSK (0x00000780) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CSb_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_OFF (11) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_WID ( 4) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_MSK (0x00007800) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_CMD_MASK3_CKE_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_WID (16) + #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_MSK (0x7FFF8000) + #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_CMD_MASK3_MA_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_CMD_BANK_REG (0x00004F60) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_OFF ( 0) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_MSK (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch0_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_OFF ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_MSK (0x00000038) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch1_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_OFF ( 6) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_MSK (0x000001C0) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch2_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_OFF ( 9) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_MSK (0x00000E00) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMatch3_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_OFF (12) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_MSK (0x00007000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask0_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_OFF (15) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_MSK (0x00038000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask1_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_OFF (18) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_MSK (0x001C0000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask2_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_OFF (21) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_WID ( 3) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_MSK (0x00E00000) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_MAX (0x00000007) + #define MCMNTS_CR_ODLAT_CMD_BANK_BankMask3_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_SEQ_LEVEL0_REG (0x00004F64) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_OFF ( 0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputMatch_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_OFF ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_MSK (0x000000F0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_InputInvert_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_OFF ( 8) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_WID ( 1) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_MSK (0x00000100) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CountMatches_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_OFF ( 9) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_WID (15) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MSK (0x00FFFE00) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MAX (0x00007FFF) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_OFF (24) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_MSK (0x03000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_OFF (26) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MSK (0x0C000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_CounterNextState_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_OFF (28) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_MSK (0x30000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_OFF (30) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MSK (0xC0000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL0_MatchNextState_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_SEQ_LEVEL1_REG (0x00004F68) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_OFF ( 0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputMatch_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_OFF ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_MSK (0x000000F0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_InputInvert_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_OFF ( 8) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_WID ( 1) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_MSK (0x00000100) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CountMatches_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_OFF ( 9) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_WID (15) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MSK (0x00FFFE00) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MAX (0x00007FFF) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_OFF (24) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_MSK (0x03000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_OFF (26) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MSK (0x0C000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_CounterNextState_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_OFF (28) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_MSK (0x30000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_OFF (30) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MSK (0xC0000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL1_MatchNextState_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_SEQ_LEVEL2_REG (0x00004F6C) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_OFF ( 0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputMatch_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_OFF ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_MSK (0x000000F0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_InputInvert_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_OFF ( 8) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_WID ( 1) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_MSK (0x00000100) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CountMatches_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_OFF ( 9) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_WID (15) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MSK (0x00FFFE00) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MAX (0x00007FFF) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_OFF (24) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_MSK (0x03000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_OFF (26) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MSK (0x0C000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_CounterNextState_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_OFF (28) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_MSK (0x30000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_OFF (30) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MSK (0xC0000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL2_MatchNextState_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_SEQ_LEVEL3_REG (0x00004F70) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_OFF ( 0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_MSK (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputMatch_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_OFF ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_WID ( 4) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_MSK (0x000000F0) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_MAX (0x0000000F) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_InputInvert_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_OFF ( 8) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_WID ( 1) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_MSK (0x00000100) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CountMatches_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_OFF ( 9) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_WID (15) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MSK (0x00FFFE00) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MAX (0x00007FFF) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_OFF (24) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_MSK (0x03000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_OFF (26) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MSK (0x0C000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_CounterNextState_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_OFF (28) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_MSK (0x30000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchAction_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_OFF (30) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_WID ( 2) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MSK (0xC0000000) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MAX (0x00000003) + #define MCMNTS_CR_ODLAT_SEQ_LEVEL3_MatchNextState_DEF (0x00000000) + +#define MCMNTS_CR_ODLAT_SEQ_GLOBAL_REG (0x00004F74) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_OFF ( 0) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_WID ( 1) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MSK (0x00000001) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MAX (0x00000001) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_DEF (0x00000000) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_OFF ( 1) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_WID (16) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MSK (0x0001FFFE) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MAX (0x0000FFFF) + #define MCMNTS_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_DEF (0x00000000) + +#define MCMNTS_CR_SC_WDBWM_REG (0x00004F8C) + #define MCMNTS_CR_SC_WDBWM_WMM_Enter_OFF ( 0) + #define MCMNTS_CR_SC_WDBWM_WMM_Enter_WID ( 8) + #define MCMNTS_CR_SC_WDBWM_WMM_Enter_MSK (0x000000FF) + #define MCMNTS_CR_SC_WDBWM_WMM_Enter_MAX (0x000000FF) + #define MCMNTS_CR_SC_WDBWM_WMM_Enter_DEF (0x00000038) + #define MCMNTS_CR_SC_WDBWM_WMM_Exit_OFF ( 8) + #define MCMNTS_CR_SC_WDBWM_WMM_Exit_WID ( 8) + #define MCMNTS_CR_SC_WDBWM_WMM_Exit_MSK (0x0000FF00) + #define MCMNTS_CR_SC_WDBWM_WMM_Exit_MAX (0x000000FF) + #define MCMNTS_CR_SC_WDBWM_WMM_Exit_DEF (0x00000030) + #define MCMNTS_CR_SC_WDBWM_WPQ_IS_OFF (16) + #define MCMNTS_CR_SC_WDBWM_WPQ_IS_WID ( 8) + #define MCMNTS_CR_SC_WDBWM_WPQ_IS_MSK (0x00FF0000) + #define MCMNTS_CR_SC_WDBWM_WPQ_IS_MAX (0x000000FF) + #define MCMNTS_CR_SC_WDBWM_WPQ_IS_DEF (0x0000003C) + #define MCMNTS_CR_SC_WDBWM_Starve_count_OFF (24) + #define MCMNTS_CR_SC_WDBWM_Starve_count_WID ( 8) + #define MCMNTS_CR_SC_WDBWM_Starve_count_MSK (0xFF000000) + #define MCMNTS_CR_SC_WDBWM_Starve_count_MAX (0x000000FF) + #define MCMNTS_CR_SC_WDBWM_Starve_count_DEF (0x000000FF) + +#define MCMNTS_CR_VISA_CTL_MCMNTS_REG (0x00004F90) + #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_OFF ( 0) + #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_WID (18) + #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_MSK (0x0003FFFF) + #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_MAX (0x0003FFFF) + #define MCMNTS_CR_VISA_CTL_MCMNTS_Data_DEF (0x00000000) + #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_OFF (31) + #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_WID ( 1) + #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_MSK (0x80000000) + #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_MAX (0x00000001) + #define MCMNTS_CR_VISA_CTL_MCMNTS_VORANGE_DEF (0x00000000) + +#define MCDECS_CR_MAD_CHNL_MCMAIN_REG (0x00005000) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_OFF ( 0) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_WID ( 2) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_MSK (0x00000003) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_MAX (0x00000003) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_A_DEF (0x00000000) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_OFF ( 2) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_WID ( 2) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_MSK (0x0000000C) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_MAX (0x00000003) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_B_DEF (0x00000001) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_OFF ( 4) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_WID ( 2) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_MSK (0x00000030) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_MAX (0x00000003) + #define MCDECS_CR_MAD_CHNL_MCMAIN_CH_C_DEF (0x00000002) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_OFF ( 6) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_WID ( 1) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_MSK (0x00000040) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_MAX (0x00000001) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_DEF (0x00000000) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_OFF ( 7) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_WID ( 3) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_MSK (0x00000380) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_MAX (0x00000007) + #define MCDECS_CR_MAD_CHNL_MCMAIN_STKD_MODE_CH_BITS_DEF (0x00000000) + #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_OFF (10) + #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_WID ( 1) + #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_MSK (0x00000400) + #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_MAX (0x00000001) + #define MCDECS_CR_MAD_CHNL_MCMAIN_LPDDR_DEF (0x00000000) + +#define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG (0x00005004) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_OFF ( 0) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_WID ( 8) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_MSK (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_MAX (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_OFF ( 8) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_WID ( 8) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_MSK (0x0000FF00) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_MAX (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_OFF (16) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_MSK (0x00010000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAS_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_OFF (17) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_MSK (0x00020000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_OFF (18) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_MSK (0x00040000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_OFF (19) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_MSK (0x00080000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DAW_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_OFF (20) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_MSK (0x00100000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBW_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_OFF (21) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_MSK (0x00200000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_RI_DEF (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_OFF (22) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_MSK (0x00400000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_Enh_Interleave_DEF (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_OFF (24) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_WID ( 2) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_MSK (0x03000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_MAX (0x00000003) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_ECC_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_OFF (26) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_MSK (0x04000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORI_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_OFF (27) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_WID ( 3) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_MSK (0x38000000) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_MAX (0x00000007) + #define MCDECS_CR_MAD_DIMM_CH0_MCMAIN_HORIAddr_DEF (0x00000000) + +#define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_REG (0x00005008) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_OFF ( 0) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_WID ( 8) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_MSK (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_MAX (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_A_Size_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_OFF ( 8) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_WID ( 8) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_MSK (0x0000FF00) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_MAX (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DIMM_B_Size_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_OFF (16) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_MSK (0x00010000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAS_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_OFF (17) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_MSK (0x00020000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DANOR_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_OFF (18) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_MSK (0x00040000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBNOR_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_OFF (19) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_MSK (0x00080000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DAW_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_OFF (20) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_MSK (0x00100000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_DBW_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_OFF (21) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_MSK (0x00200000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_RI_DEF (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_OFF (22) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_MSK (0x00400000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_Enh_Interleave_DEF (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_OFF (24) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_WID ( 2) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_MSK (0x03000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_MAX (0x00000003) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_ECC_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_OFF (26) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_MSK (0x04000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORI_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_OFF (27) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_WID ( 3) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_MSK (0x38000000) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_MAX (0x00000007) + #define MCDECS_CR_MAD_DIMM_CH1_MCMAIN_HORIAddr_DEF (0x00000000) + +#define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_REG (0x0000500C) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_OFF ( 0) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_WID ( 8) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_MSK (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_MAX (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_A_Size_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_OFF ( 8) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_WID ( 8) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_MSK (0x0000FF00) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_MAX (0x000000FF) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DIMM_B_Size_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_OFF (16) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_MSK (0x00010000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAS_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_OFF (17) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_MSK (0x00020000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DANOR_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_OFF (18) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_MSK (0x00040000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBNOR_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_OFF (19) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_MSK (0x00080000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DAW_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_OFF (20) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_MSK (0x00100000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_DBW_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_OFF (21) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_MSK (0x00200000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_RI_DEF (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_OFF (22) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_MSK (0x00400000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_Enh_Interleave_DEF (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_OFF (24) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_WID ( 2) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_MSK (0x03000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_MAX (0x00000003) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_ECC_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_OFF (26) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_WID ( 1) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_MSK (0x04000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_MAX (0x00000001) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORI_DEF (0x00000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_OFF (27) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_WID ( 3) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_MSK (0x38000000) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_MAX (0x00000007) + #define MCDECS_CR_MAD_DIMM_CH2_MCMAIN_HORIAddr_DEF (0x00000000) + +#define MCDECS_CR_MAD_ZR_MCMAIN_REG (0x00005014) + #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_OFF ( 0) + #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_WID ( 8) + #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_MSK (0x000000FF) + #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_MAX (0x000000FF) + #define MCDECS_CR_MAD_ZR_MCMAIN_OneC_DEF (0x00000000) + #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_OFF ( 8) + #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_WID ( 8) + #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_MSK (0x0000FF00) + #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_MAX (0x000000FF) + #define MCDECS_CR_MAD_ZR_MCMAIN_ThreeC_DEF (0x00000000) + #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_OFF (16) + #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_WID ( 8) + #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_MSK (0x00FF0000) + #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_MAX (0x000000FF) + #define MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_DEF (0x00000000) + #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_OFF (24) + #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_WID ( 8) + #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_MSK (0xFF000000) + #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_MAX (0x000000FF) + #define MCDECS_CR_MAD_ZR_MCMAIN_BandC_DEF (0x00000000) + +#define MCDECS_CR_MCDECS_MISC_MCMAIN_REG (0x00005018) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_OFF ( 0) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_WID (23) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_MSK (0x007FFFFF) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_MAX (0x007FFFFF) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_spare_DEF (0x00000000) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_OFF (23) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_WID ( 1) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_MSK (0x00800000) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_MAX (0x00000001) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_ovrd_pcu_sr_exit_DEF (0x00000000) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_OFF (24) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_WID ( 8) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_MSK (0xFF000000) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_MAX (0x000000FF) + #define MCDECS_CR_MCDECS_MISC_MCMAIN_isoch_stall_pattern_DEF (0x00000000) + +#define MCDECS_CR_MCDECS_CBIT_MCMAIN_REG (0x0000501C) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_OFF ( 0) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_MSK (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_increase_rcomp_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_OFF ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_MSK (0x00000002) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_on_ecc_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_OFF ( 2) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_MSK (0x00000004) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_demux_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_OFF ( 3) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_MSK (0x00000008) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_noa_countctrl_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_OFF ( 8) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_MSK (0x00000100) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_psmi_freeze_pwm_counters_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_OFF (15) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_MSK (0x00008000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_lp_prefetch_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_OFF (29) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_MSK (0x20000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_reg_clk_gate_DEF (0x00000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_OFF (30) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_MSK (0x40000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_msg_clk_gate_DEF (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_OFF (31) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_WID ( 1) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_MSK (0x80000000) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_MAX (0x00000001) + #define MCDECS_CR_MCDECS_CBIT_MCMAIN_dis_clk_gate_DEF (0x00000000) + +#define MCDECS_CR_SC_IS_CREDIT_MCMAIN_REG (0x00005020) + #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_WID ( 4) + #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_MSK (0x0000000F) + #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_MAX (0x0000000F) + #define MCDECS_CR_SC_IS_CREDIT_MCMAIN_count_DEF (0x00000008) + +#define MCDECS_CR_CHANNEL_HASH_MCMAIN_REG (0x00005024) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_OFF ( 0) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_WID (14) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_MSK (0x00003FFF) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_MAX (0x00003FFF) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_DEF (0x00000000) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_OFF (21) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_WID ( 2) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_MSK (0x00600000) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_MAX (0x00000003) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_DEF (0x00000000) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_OFF (23) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_WID ( 1) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_MSK (0x00800000) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_MAX (0x00000001) + #define MCDECS_CR_CHANNEL_HASH_MCMAIN_Enable_DEF (0x00000000) + +#define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_REG (0x00005030) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_OFF ( 0) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_MSK (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_pu_mrc_done_DEF (0x00000000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_OFF ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_MSK (0x00000002) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_ddr_reset_DEF (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_OFF ( 3) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_MSK (0x00000008) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_refresh_enable_DEF (0x00000000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_OFF ( 5) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_MSK (0x00000020) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mc_init_done_ack_DEF (0x00000000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_OFF ( 7) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_MSK (0x00000080) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_mrc_done_DEF (0x00000000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_OFF ( 8) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_MSK (0x00000100) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_safe_sr_DEF (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_OFF (10) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_MSK (0x00000400) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_HVM_Gate_DDR_Reset_DEF (0x00000000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_OFF (22) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_MSK (0x00400000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_dclk_enable_DEF (0x00000000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_OFF (23) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_WID ( 1) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_MSK (0x00800000) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_MAX (0x00000001) + #define MCDECS_CR_MC_INIT_STATE_G_MCMAIN_reset_io_DEF (0x00000000) + +#define MCDECS_CR_MRC_REVISION_MCMAIN_REG (0x00005034) + #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_OFF ( 0) + #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_WID (32) + #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_MSK (0xFFFFFFFF) + #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_MAX (0xFFFFFFFF) + #define MCDECS_CR_MRC_REVISION_MCMAIN_REVISION_DEF (0x00000000) + +#define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_REG (0x00005040) + #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_WID (32) + #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_MSK (0xFFFFFFFF) + #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_MAX (0xFFFFFFFF) + #define MCDECS_CR_PWM_GT_REQCOUNT_MCMAIN_count_DEF (0x00000000) + +#define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_REG (0x00005044) + #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_WID (32) + #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_MSK (0xFFFFFFFF) + #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_MAX (0xFFFFFFFF) + #define MCDECS_CR_PWM_IA_REQCOUNT_MCMAIN_count_DEF (0x00000000) + +#define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_REG (0x00005048) + #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_WID (32) + #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_MSK (0xFFFFFFFF) + #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_MAX (0xFFFFFFFF) + #define MCDECS_CR_PWM_IO_REQCOUNT_MCMAIN_count_DEF (0x00000000) + +#define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_REG (0x00005050) + #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_WID (32) + #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_MSK (0xFFFFFFFF) + #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_MAX (0xFFFFFFFF) + #define MCDECS_CR_PWM_RDDATA_COUNT_MCMAIN_count_DEF (0x00000000) + +#define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_REG (0x00005054) + #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_WID (32) + #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_MSK (0xFFFFFFFF) + #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_MAX (0xFFFFFFFF) + #define MCDECS_CR_PWM_WRDATA_COUNT_MCMAIN_count_DEF (0x00000000) + +#define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_REG (0x00005058) + #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_WID (32) + #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_MSK (0xFFFFFFFF) + #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_MAX (0xFFFFFFFF) + #define MCDECS_CR_PWM_COMMAND_COUNT_MCMAIN_count_DEF (0x00000000) + +#define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_REG (0x00005060) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_OFF ( 0) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_WID (16) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_MSK (0x0000FFFF) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_MAX (0x0000FFFF) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_Idle_timer_DEF (0x00000200) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_OFF (16) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_WID ( 1) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_MSK (0x00010000) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_MAX (0x00000001) + #define MCDECS_CR_PM_SREF_CONFIG_MCMAIN_SR_Enable_DEF (0x00000001) + +#define MCDECS_CR_MCI_CONFIG_MCMAIN_REG (0x00005070) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_OFF ( 0) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_WID ( 4) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_MSK (0x0000000F) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_MAX (0x0000000F) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_Ch_dir_DEF (0x00000000) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_OFF ( 8) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_WID (10) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_MSK (0x0003FF00) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_MAX (0x000003FF) + #define MCDECS_CR_MCI_CONFIG_MCMAIN_MCI_clk_div_DEF (0x00000000) + +#define MCDECS_CR_STALL_DRAIN_MCMAIN_REG (0x00005074) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_OFF ( 0) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_WID ( 1) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_MSK (0x00000001) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_MAX (0x00000001) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_until_drain_DEF (0x00000000) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_OFF ( 1) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_WID ( 1) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_MSK (0x00000002) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_MAX (0x00000001) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_stall_input_DEF (0x00000000) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_OFF ( 4) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_WID ( 1) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_MSK (0x00000010) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_MAX (0x00000001) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_mc_drained_DEF (0x00000000) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_OFF ( 8) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_WID ( 2) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_MSK (0x00000300) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_MAX (0x00000003) + #define MCDECS_CR_STALL_DRAIN_MCMAIN_sr_state_DEF (0x00000000) + +#define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_REG (0x00005080) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_OFF ( 0) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_WID ( 5) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_MSK (0x0000001F) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_MAX (0x0000001F) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_RPQ_count_DEF (0x0000001C) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_OFF ( 8) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_WID ( 7) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_MSK (0x00007F00) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_MAX (0x0000007F) + #define MCDECS_CR_QUEUE_CREDIT_C_MCMAIN_WPQ_count_DEF (0x00000040) + +#define MCDECS_CR_RCOMP_TIMER_MCMAIN_REG (0x00005084) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_OFF ( 0) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_WID (16) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_MSK (0x0000FFFF) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_MAX (0x0000FFFF) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_count_DEF (0x00000CFF) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_OFF (16) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_WID ( 1) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_MSK (0x00010000) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_MAX (0x00000001) + #define MCDECS_CR_RCOMP_TIMER_MCMAIN_First_Rcomp_done_DEF (0x00000000) + +#define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_REG (0x00005090) + #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_OFF ( 0) + #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_WID (32) + #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_MSK (0xFFFFFFFF) + #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_MAX (0xFFFFFFFF) + #define MCDECS_CR_ECC_INJ_ADDR_COMPARE_MCMAIN_Address_DEF (0x00000000) + +#define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_REG (0x00005094) + #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_OFF ( 0) + #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_WID (32) + #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_MSK (0xFFFFFFFF) + #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_MAX (0xFFFFFFFF) + #define MCDECS_CR_ECC_INJ_ADDR_MASK_MCMAIN_Mask_DEF (0xFFFFFFFF) + +#define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_REG (0x000050A0) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_OFF ( 0) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_WID (18) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_MSK (0x0003FFFF) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_MAX (0x0003FFFF) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_Data_DEF (0x00000000) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_OFF (31) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_WID ( 1) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_MSK (0x80000000) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_MAX (0x00000001) + #define MCDECS_CR_VISA_CTL_MCDECS_MCMAIN_VORANGE_DEF (0x00000000) + +#define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_REG (0x000050A4) + #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_OFF ( 0) + #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_WID (32) + #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_MSK (0xFFFFFFFF) + #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_MAX (0xFFFFFFFF) + #define MCDECS_CR_VISA_XBAR_MCDECS_MCMAIN_Data_DEF (0x76543210) + +#define MCDECS_CR_MC_LOCK_MCMAIN_REG (0x000050FC) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_OFF ( 0) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_WID ( 1) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_MSK (0x00000001) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_MAX (0x00000001) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_addr_map_DEF (0x00000000) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_OFF ( 1) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_WID ( 1) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_MSK (0x00000002) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_MAX (0x00000001) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_config_DEF (0x00000000) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_OFF ( 2) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_WID ( 1) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_MSK (0x00000004) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_MAX (0x00000001) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_iosav_init_DEF (0x00000000) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_OFF ( 3) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_WID ( 1) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_MSK (0x00000008) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_MAX (0x00000001) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_pwr_mngment_DEF (0x00000000) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_OFF ( 7) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_WID ( 1) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_MSK (0x00000080) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_MAX (0x00000001) + #define MCDECS_CR_MC_LOCK_MCMAIN_lock_mc_dft_DEF (0x00000000) + +#define MCHBAR_CH0_CR_TC_BANK_REG (0x00004000) + #define MCHBAR_CH0_CR_TC_BANK_tRCD_OFF ( 0) + #define MCHBAR_CH0_CR_TC_BANK_tRCD_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_tRCD_MSK (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_tRCD_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_tRCD_DEF (0x00000006) + #define MCHBAR_CH0_CR_TC_BANK_tRP_OFF ( 5) + #define MCHBAR_CH0_CR_TC_BANK_tRP_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_tRP_MSK (0x000003E0) + #define MCHBAR_CH0_CR_TC_BANK_tRP_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_tRP_DEF (0x00000006) + #define MCHBAR_CH0_CR_TC_BANK_tRAS_OFF (10) + #define MCHBAR_CH0_CR_TC_BANK_tRAS_WID ( 6) + #define MCHBAR_CH0_CR_TC_BANK_tRAS_MSK (0x0000FC00) + #define MCHBAR_CH0_CR_TC_BANK_tRAS_MAX (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_tRAS_DEF (0x00000014) + #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_OFF (16) + #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_MSK (0x000F0000) + #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_tRDPRE_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_OFF (20) + #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_WID ( 6) + #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_MSK (0x03F00000) + #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_MAX (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_tWRPRE_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_tRRD_OFF (26) + #define MCHBAR_CH0_CR_TC_BANK_tRRD_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_tRRD_MSK (0x3C000000) + #define MCHBAR_CH0_CR_TC_BANK_tRRD_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_tRRD_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_OFF (30) + #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_MSK (0xC0000000) + #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_tRPab_ext_DEF (0x00000000) + +#define MCHBAR_CH0_CR_TC_BANK_RANK_A_REG (0x00004004) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_OFF ( 0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_MSK (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tCKE_DEF (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_OFF ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_WID ( 8) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_MSK (0x00000FF0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_MAX (0x000000FF) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tFAW_DEF (0x00000010) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_OFF (12) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_WID ( 3) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_MSK (0x00007000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_MAX (0x00000007) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_OFF (15) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_MSK (0x00078000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dr_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_OFF (19) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_MSK (0x00780000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDRD_dd_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_OFF (23) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_MSK (0x0F800000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_tRDPDEN_DEF (0x00000004) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_OFF (29) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_WID ( 1) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_MSK (0x20000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_MAX (0x00000001) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_3st_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_OFF (30) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_MSK (0xC0000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_A_CMD_stretch_DEF (0x00000002) + +#define MCHBAR_CH0_CR_TC_BANK_RANK_B_REG (0x00004008) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_OFF ( 0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_WID ( 6) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_MSK (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_MAX (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_OFF ( 6) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_MSK (0x000003C0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_OFF (10) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_MSK (0x00003C00) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_OFF (14) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_WID ( 3) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_MSK (0x0001C000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_MAX (0x00000007) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_OFF (17) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_MSK (0x001E0000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_OFF (21) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_MSK (0x01E00000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_OFF (25) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_WID ( 6) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_MSK (0x7E000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_MAX (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_OFF (31) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_WID ( 1) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_MSK (0x80000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_MAX (0x00000001) + #define MCHBAR_CH0_CR_TC_BANK_RANK_B_Dec_WRD_DEF (0x00000000) + +#define MCHBAR_CH0_CR_TC_BANK_RANK_C_REG (0x0000400C) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_OFF ( 0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_WID ( 6) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_MSK (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_MAX (0x0000003F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_DEF (0x0000000A) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_OFF ( 6) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_MSK (0x000003C0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_DEF (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_OFF (10) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_WID ( 4) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_MSK (0x00003C00) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_DEF (0x00000009) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_OFF (14) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_MSK (0x0007C000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_OFF (19) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_MSK (0x00F80000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_DEF (0x00000005) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_OFF (24) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_MSK (0x1F000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_DEF (0x00000005) + +#define MCHBAR_CH0_CR_CMD_RATE_REG (0x00004010) + #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_OFF ( 0) + #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_WID ( 1) + #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_MSK (0x00000001) + #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_MAX (0x00000001) + #define MCHBAR_CH0_CR_CMD_RATE_enable_cmd_rate_limit_DEF (0x00000000) + #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_OFF ( 1) + #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_WID ( 3) + #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_MSK (0x0000000E) + #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_MAX (0x00000007) + #define MCHBAR_CH0_CR_CMD_RATE_cmd_rate_limit_DEF (0x00000004) + #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_OFF ( 4) + #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_WID ( 4) + #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_MSK (0x000000F0) + #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_MAX (0x0000000F) + #define MCHBAR_CH0_CR_CMD_RATE_reset_on_command_DEF (0x00000000) + #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_OFF ( 8) + #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_WID ( 4) + #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_MSK (0x00000F00) + #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_MAX (0x0000000F) + #define MCHBAR_CH0_CR_CMD_RATE_reset_delay_DEF (0x00000000) + #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_OFF (12) + #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_WID ( 2) + #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_MSK (0x00003000) + #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_MAX (0x00000003) + #define MCHBAR_CH0_CR_CMD_RATE_ck_to_cke_delay_DEF (0x00000001) + #define MCHBAR_CH0_CR_CMD_RATE_spare_OFF (14) + #define MCHBAR_CH0_CR_CMD_RATE_spare_WID (17) + #define MCHBAR_CH0_CR_CMD_RATE_spare_MSK (0x7FFFC000) + #define MCHBAR_CH0_CR_CMD_RATE_spare_MAX (0x0001FFFF) + #define MCHBAR_CH0_CR_CMD_RATE_spare_DEF (0x00000000) + #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_OFF (31) + #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_WID ( 1) + #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_MSK (0x80000000) + #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_MAX (0x00000001) + #define MCHBAR_CH0_CR_CMD_RATE_init_mrw_2n_cs_DEF (0x00000000) + +#define MCHBAR_CH0_CR_TC_BANK_RANK_D_REG (0x00004014) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_OFF ( 0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_MSK (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_DEF (0x00000006) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_OFF ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_WID ( 5) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_MSK (0x000003E0) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_MAX (0x0000001F) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_DEF (0x00000006) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_OFF (10) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_MSK (0x00000C00) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_DEF (0x00000001) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_OFF (12) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_MSK (0x00003000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_DEF (0x00000001) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_OFF (14) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_WID ( 3) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_MSK (0x0001C000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_MAX (0x00000007) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_OFF (17) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_MSK (0x00060000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Duration_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_OFF (19) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_MSK (0x00180000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_OFF (19) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_WID ( 3) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MSK (0x00380000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MAX (0x00000007) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_OFF (22) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_WID ( 3) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MSK (0x01C00000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MAX (0x00000007) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_OFF (25) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_WID ( 1) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MSK (0x02000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MAX (0x00000001) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_OFF (26) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_WID ( 2) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_MSK (0x0C000000) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_BANK_RANK_D_cmd_delay_Ult_DEF (0x00000000) + +#define MCHBAR_CH0_CR_SCHED_CBIT_REG (0x00004020) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_OFF ( 0) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_MSK (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_cas_DEF (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_OFF ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_MSK (0x00000002) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_cas_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_OFF ( 2) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_MSK (0x00000004) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ras_DEF (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_OFF ( 3) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_MSK (0x00000008) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_is_ras_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_OFF ( 4) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_MSK (0x00000010) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_1c_byp_DEF (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_OFF ( 5) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_MSK (0x00000020) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_2c_byp_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_OFF ( 6) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_MSK (0x00000040) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_deprd_opt_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_OFF ( 7) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_MSK (0x00000080) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_pt_it_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_OFF ( 8) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_MSK (0x00000100) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_ring_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_OFF ( 9) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_MSK (0x00000200) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_prcnt_sa_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_OFF (10) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_MSK (0x00000400) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_ph_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_OFF (11) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_MSK (0x00000800) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pe_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_OFF (12) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_MSK (0x00001000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_blkr_pm_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_OFF (13) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_MSK (0x00002000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_odt_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_OFF (14) + #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_MSK (0x00004000) + #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_OE_alw_off_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_OFF (16) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_MSK (0x00010000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_aom_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_OFF (17) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_MSK (0x00020000) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_rpq_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_OFF (18) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_MSK (0x00040000) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_block_wpq_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_OFF (19) + #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_MSK (0x00080000) + #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_invert_align_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_OFF (20) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_MSK (0x00100000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_write_gap_DEF (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_OFF (21) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_MSK (0x00200000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_zq_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_OFF (22) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_MSK (0x00400000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_tt_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_OFF (23) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_MSK (0x00800000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_opp_ref_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_OFF (24) + #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_MSK (0x01000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_Long_ZQ_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_OFF (25) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_MSK (0x02000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_srx_zq_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_OFF (26) + #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_MSK (0x04000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_Serialize_ZQ_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_OFF (27) + #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_MSK (0x08000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_ZQ_fast_exec_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_OFF (28) + #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_MSK (0x10000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_Dis_DriveNop_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_OFF (29) + #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_MSK (0x20000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_Pres_WDB_Ent_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_OFF (30) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_MSK (0x40000000) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_CBIT_dis_clk_gate_DEF (0x00000000) + +#define MCHBAR_CH0_CR_SC_ROUNDT_LAT_REG (0x00004024) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_OFF ( 0) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_WID ( 6) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_MSK (0x0000003F) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_MAX (0x0000003F) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D0_DEF (0x00000020) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_OFF ( 8) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_WID ( 6) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_MSK (0x00003F00) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_MAX (0x0000003F) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D0_DEF (0x00000020) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_OFF (16) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_WID ( 6) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_MSK (0x003F0000) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_MAX (0x0000003F) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R0D1_DEF (0x00000020) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_OFF (24) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_WID ( 6) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_MSK (0x3F000000) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_MAX (0x0000003F) + #define MCHBAR_CH0_CR_SC_ROUNDT_LAT_Lat_R1D1_DEF (0x00000020) + +#define MCHBAR_CH0_CR_SC_IO_LATENCY_REG (0x00004028) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_OFF ( 0) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_WID ( 4) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_MSK (0x0000000F) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_MAX (0x0000000F) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D0_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_OFF ( 4) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_WID ( 4) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_MSK (0x000000F0) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_MAX (0x0000000F) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D0_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_OFF ( 8) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_WID ( 4) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_MSK (0x00000F00) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_MAX (0x0000000F) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R0D1_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_OFF (12) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_WID ( 4) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_MSK (0x0000F000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_MAX (0x0000000F) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_IOLAT_R1D1_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_OFF (16) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_WID ( 6) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_MSK (0x003F0000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_MAX (0x0000003F) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_RT_IOCOMP_DEF (0x0000000E) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_OFF (30) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_WID ( 1) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_MSK (0x40000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_MAX (0x00000001) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_three_channels_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_OFF (31) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_WID ( 1) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MSK (0x80000000) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MAX (0x00000001) + #define MCHBAR_CH0_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_REG (0x0000402C) + #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_OFF ( 0) + #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_WID (32) + #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_ROUND_TRIP_DFT_DATA_DATA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_DFT_MISC_REG (0x00004030) + #define MCHBAR_CH0_CR_DFT_MISC_WDAR_OFF ( 0) + #define MCHBAR_CH0_CR_DFT_MISC_WDAR_WID ( 1) + #define MCHBAR_CH0_CR_DFT_MISC_WDAR_MSK (0x00000001) + #define MCHBAR_CH0_CR_DFT_MISC_WDAR_MAX (0x00000001) + #define MCHBAR_CH0_CR_DFT_MISC_WDAR_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_OFF ( 1) + #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_WID ( 3) + #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_MSK (0x0000000E) + #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_MAX (0x00000007) + #define MCHBAR_CH0_CR_DFT_MISC_safe_mask_sel_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_OFF ( 4) + #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_WID ( 1) + #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_MSK (0x00000010) + #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_MAX (0x00000001) + #define MCHBAR_CH0_CR_DFT_MISC_force_rcv_en_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_OFF ( 8) + #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_WID ( 2) + #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_MSK (0x00000300) + #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_MAX (0x00000003) + #define MCHBAR_CH0_CR_DFT_MISC_DDR_QUAL_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_OFF (10) + #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_WID ( 2) + #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_MSK (0x00000C00) + #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_MAX (0x00000003) + #define MCHBAR_CH0_CR_DFT_MISC_Qual_length_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_OFF (12) + #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_WID ( 1) + #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_MSK (0x00001000) + #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_MAX (0x00000001) + #define MCHBAR_CH0_CR_DFT_MISC_WDB_Block_En_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_OFF (13) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_WID ( 4) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_MSK (0x0001E000) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_PTR_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_OFF (17) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_WID ( 1) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_MSK (0x00020000) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_MAX (0x00000001) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_ENABLE_DEF (0x00000000) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_OFF (18) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_WID ( 1) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MSK (0x00040000) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MAX (0x00000001) + #define MCHBAR_CH0_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_DEF (0x00000000) + +#define MCHBAR_CH0_CR_READ_RETURN_DFT_REG (0x00004034) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_OFF ( 0) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_WID ( 8) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_MSK (0x000000FF) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_MAX (0x000000FF) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_ECC_DEF (0x00000000) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_OFF ( 8) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_WID ( 2) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_MSK (0x00000300) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_MAX (0x00000003) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_RRD_DFT_Mode_DEF (0x00000000) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_OFF (10) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_WID ( 5) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_MSK (0x00007C00) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_MAX (0x0000001F) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_LFSR_Seed_Index_DEF (0x00000000) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_OFF (15) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_WID ( 1) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_MSK (0x00008000) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_MAX (0x00000001) + #define MCHBAR_CH0_CR_READ_RETURN_DFT_Inversion_Mode_DEF (0x00000000) + +#define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_REG (0x00004038) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_OFF ( 0) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_MSK (0x00000001) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_imph_error_DEF (0x00000000) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_OFF ( 8) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_WID ( 1) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_MSK (0x00000100) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_MAX (0x00000001) + #define MCHBAR_CH0_CR_SCHED_SECOND_CBIT_dis_async_odt_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG (0x00004040) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MSK (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_OFF ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MSK (0x00000018) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_OFF ( 6) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MSK (0x000000C0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_OFF (14) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MSK (0x00004000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_OFF (15) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MSK (0x00008000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MSK (0x003F0000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MSK (0x07000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_REG (0x00004044) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MSK (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG (0x00004048) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_REG (0x0000404C) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_REG (0x00004050) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG (0x00004054) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_REG (0x00004058) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_REG (0x0000405C) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_REG (0x00004060) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_REG (0x00004064) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_REG (0x00004068) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_REG (0x0000406C) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_REG (0x00004070) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_REG (0x00004074) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_REG (0x00004078) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MSK (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MSK (0x00FF0000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MSK (0xFF000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_DEF (0x00000001) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_REG (0x00004084) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MSK (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MSK (0x000F0000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_OFF (20) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MSK (0x00100000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_OFF (30) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MSK (0x40000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_OFF (31) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MSK (0x80000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_REG (0x00004090) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_WID (64) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MSK (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MAX (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_REG (0x00004098) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MSK (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_OFF (12) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MSK (0x00003000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MSK (0x00FF0000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_DEF (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MSK (0xFF000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_DEF (0x000000FF) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_REG (0x0000409C) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MSK (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_DEF (0x00000000) + +#define MCHBAR_CH0_CR_STM_CONFIG_REG (0x000040A4) + #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_OFF ( 0) + #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_WID ( 2) + #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_MSK (0x00000003) + #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_MAX (0x00000003) + #define MCHBAR_CH0_CR_STM_CONFIG_Stretch_mode_DEF (0x00000000) + #define MCHBAR_CH0_CR_STM_CONFIG_STF_OFF ( 4) + #define MCHBAR_CH0_CR_STM_CONFIG_STF_WID ( 3) + #define MCHBAR_CH0_CR_STM_CONFIG_STF_MSK (0x00000070) + #define MCHBAR_CH0_CR_STM_CONFIG_STF_MAX (0x00000007) + #define MCHBAR_CH0_CR_STM_CONFIG_STF_DEF (0x00000000) + +#define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_REG (0x000040A8) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_OFF ( 0) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_WID (10) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MSK (0x000003FF) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MAX (0x000003FF) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_ring_DEF (0x00000040) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_OFF (16) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_WID (10) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MSK (0x03FF0000) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MAX (0x000003FF) + #define MCHBAR_CH0_CR_SC_PR_CNT_CONFIG_Priority_count_SA_DEF (0x00000100) + +#define MCHBAR_CH0_CR_SC_PCIT_REG (0x000040AC) + #define MCHBAR_CH0_CR_SC_PCIT_PCIT_OFF ( 0) + #define MCHBAR_CH0_CR_SC_PCIT_PCIT_WID ( 8) + #define MCHBAR_CH0_CR_SC_PCIT_PCIT_MSK (0x000000FF) + #define MCHBAR_CH0_CR_SC_PCIT_PCIT_MAX (0x000000FF) + #define MCHBAR_CH0_CR_SC_PCIT_PCIT_DEF (0x00000040) + +#define MCHBAR_CH0_CR_PM_PDWN_CONFIG_REG (0x000040B0) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_OFF ( 0) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_WID (12) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MSK (0x00000FFF) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MAX (0x00000FFF) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_idle_counter_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_OFF (12) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_WID ( 4) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_MSK (0x0000F000) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_MAX (0x0000000F) + #define MCHBAR_CH0_CR_PM_PDWN_CONFIG_PDWN_mode_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ECC_INJECT_COUNT_REG (0x000040B4) + #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_OFF ( 0) + #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_WID (32) + #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_ECC_INJECT_COUNT_Count_DEF (0xFFFFFFFF) + +#define MCHBAR_CH0_CR_ECC_DFT_REG (0x000040B8) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_OFF ( 0) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_WID ( 8) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_MSK (0x000000FF) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_MAX (0x000000FF) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_fill_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_OFF ( 8) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_WID ( 2) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_MSK (0x00000300) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_MAX (0x00000003) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_trigger_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_OFF (10) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_WID ( 1) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_MSK (0x00000400) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_BS_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_OFF (11) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_WID ( 3) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_MSK (0x00003800) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_MAX (0x00000007) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_Inject_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_OFF (14) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_WID ( 1) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_MSK (0x00004000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECC_DFT_ECC_correction_disable_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_OFF (15) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_WID ( 1) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_MSK (0x00008000) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECC_DFT_ECC4ANA_Inject_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_OFF (16) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_WID ( 1) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_MSK (0x00010000) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_MCA_LOG_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_OFF (17) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_WID ( 1) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_MSK (0x00020000) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCH_EVENT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_OFF (18) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_WID ( 1) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_MSK (0x00040000) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECC_DFT_DIS_PCIE_POISON_DEF (0x00000000) + +#define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_REG (0x000040C0) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_OFF ( 0) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_WID (18) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_MSK (0x0003FFFF) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_MAX (0x0003FFFF) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_Data_DEF (0x00000000) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_OFF (31) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_WID ( 1) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_MSK (0x80000000) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_MAX (0x00000001) + #define MCHBAR_CH0_CR_VISA_CTL_MCSCHEDS_VORANGE_DEF (0x00000000) + +#define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_REG (0x000040C4) + #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_OFF ( 0) + #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_WID (32) + #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_VISA_XBAR_MCSCHEDS_Data_DEF (0x76543210) + +#define MCHBAR_CH0_CR_ECCERRLOG0_REG (0x000040C8) + #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_OFF ( 0) + #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_WID ( 1) + #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_MSK (0x00000001) + #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECCERRLOG0_CERRSTS_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_OFF ( 1) + #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_WID ( 1) + #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_MSK (0x00000002) + #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_MAX (0x00000001) + #define MCHBAR_CH0_CR_ECCERRLOG0_MERRSTS_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_OFF (16) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_WID ( 8) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_MSK (0x00FF0000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_MAX (0x000000FF) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRSYND_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_OFF (24) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_WID ( 3) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_MSK (0x07000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_MAX (0x00000007) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRCHUNK_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_OFF (27) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_WID ( 2) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_MSK (0x18000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_MAX (0x00000003) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRRANK_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_OFF (29) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_WID ( 3) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_MSK (0xE0000000) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_MAX (0x00000007) + #define MCHBAR_CH0_CR_ECCERRLOG0_ERRBANK_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ECCERRLOG1_REG (0x000040CC) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_OFF ( 0) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_WID (16) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRROW_DEF (0x00000000) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_OFF (16) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_WID (16) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_MSK (0xFFFF0000) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ECCERRLOG1_ERRCOL_DEF (0x00000000) + +#define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_REG (0x000040D0) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_OFF ( 0) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_WID ( 2) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_MSK (0x00000003) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_MAX (0x00000003) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_OFF ( 2) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_WID ( 2) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_MSK (0x0000000C) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_MAX (0x00000003) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_OFF ( 4) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_WID ( 2) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_MSK (0x00000030) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_MAX (0x00000003) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_DEF (0x00000000) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_OFF ( 6) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_WID ( 2) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_MSK (0x000000C0) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_MAX (0x00000003) + #define MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_DEF (0x00000000) + +#define MCHBAR_CH0_CR_WMM_READ_CONFIG_REG (0x000040D4) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_OFF ( 0) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_WID ( 1) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_MSK (0x00000001) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_MAX (0x00000001) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_Dis_Opp_rd_DEF (0x00000000) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_OFF ( 1) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_WID ( 1) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_MSK (0x00000002) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_MAX (0x00000001) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_ACT_Enable_DEF (0x00000001) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_OFF ( 2) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_WID ( 1) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_MSK (0x00000004) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_MAX (0x00000001) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_PRE_Enable_DEF (0x00000001) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_OFF ( 3) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_WID ( 4) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MSK (0x00000078) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MAX (0x0000000F) + #define MCHBAR_CH0_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_DEF (0x00000008) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_REG (0x000040D8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_WID (64) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MSK (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MAX (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_REG (0x000040E0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_WID (64) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MSK (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MAX (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG (0x000040E8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MSK (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MSK (0x000F0000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_OFF (32) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_WID ( 9) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MSK (0x1FF00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MAX (0x000001FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_OFF (52) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MSK (0x70000000000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_OFF (56) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MSK (0x3F00000000000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_REG (0x000040F0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_REG (0x000040F4) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_REG (0x000040F8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_REG (0x000040FC) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_REG (0x00004100) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_REG (0x00004104) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_REG (0x00004108) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_REG (0x0000410C) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_REG (0x00004110) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_WID ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_OFF ( 7) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG (0x00004114) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_REG (0x00004118) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_REG (0x0000411C) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_REG (0x00004120) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_REG (0x00004124) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_REG (0x00004128) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_REG (0x0000412C) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_REG (0x00004130) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_REG (0x00004134) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_WID (23) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_REG (0x00004138) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_WID ( 9) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MSK (0x000001FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MAX (0x000001FF) + #define MCHBAR_CH0_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_REG (0x00004180) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_WID (10) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_MSK (0x000003FF) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_MAX (0x000003FF) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Column_Address_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_MSK (0xFFFF000000) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Row_Address_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_OFF (48) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_MSK (0x7000000000000) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Bank_Address_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_OFF (56) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_MSK (0x300000000000000) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_ERROR_ADDR_Rank_Address_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_REG (0x00004188) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MSK (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_REG (0x0000418C) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MSK (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MSK (0x00003F00) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MSK (0x003F0000) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_REG (0x00004190) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MSK (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_DEF (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MSK (0x00000100) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MSK (0x000F0000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_REG (0x00004194) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MSK (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_DEF (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MSK (0x000F0000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_OFF (31) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MSK (0x80000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_REG (0x00004198) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MSK (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_OFF ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MSK (0x00000002) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_OFF ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MSK (0x0000003C) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_OFF ( 6) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MSK (0x000003C0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_OFF ( 10) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MSK (0x00003C00) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_OFF ( 14) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MSK (0x0000C000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_OFF ( 16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MSK (0x00030000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_OFF ( 18) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MSK (0x000C0000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_OFF ( 20) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MSK (0x00F00000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_OFF ( 24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MSK (0x0F000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_REG (0x0000419C) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MSK (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_DEF (0x00000002) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MSK (0x00000700) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MSK (0x00070000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_DEF (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MSK (0x07000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG (0x000041A0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MSK (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_OFF ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MSK (0x00000030) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MSK (0x00000300) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_OFF ( 16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MSK (0x00030000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_OFF ( 20) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MSK (0x00300000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_OFF ( 24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_WID ( 2) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MSK (0x03000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MAX (0x00000003) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_DEF (0x00000001) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG (0x000041A4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG (0x000041A8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG (0x000041AC) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_REG (0x000041B0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MSK (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MSK (0x00FF0000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_DEF (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_WID ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MSK (0xFF000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_DEF (0x00000001) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG (0x000041BC) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MSK (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_REG (0x000041C8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_REG (0x000041CC) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_REG (0x000041D0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_REG (0x000041C0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_WID (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_OFF (24) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MSK (0x07000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_OFF (32) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MSK (0xF00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_OFF (40) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_WID ( 3) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MSK (0x70000000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MAX (0x00000007) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_OFF (48) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MSK (0xF000000000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_OFF (56) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MSK (0xF00000000000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_REG (0x00004200) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_WID ( 5) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MSK (0x0000001F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MAX (0x0000001F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_OFF ( 5) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MSK (0x00000020) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MSK (0x00003F00) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_OFF (16) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_WID ( 6) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MSK (0x003F0000) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MAX (0x0000003F) + #define MCHBAR_CH0_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_DEF (0x0000003F) + +#define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_REG (0x00004204) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MSK (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_OFF ( 8) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MSK (0x00000100) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_OFF (31) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MSK (0x80000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_DEF (0x00000000) + +#define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_REG (0x00004208) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_OFF ( 0) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_WID ( 4) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MSK (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MAX (0x0000000F) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_DEF (0x00000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_OFF (31) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_WID ( 1) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MSK (0x80000000) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MAX (0x00000001) + #define MCHBAR_CH0_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_DEF (0x00000000) + +#define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_REG (0x00004210) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_OFF ( 0) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_MSK (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_0_x32_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_OFF ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_MSK (0x00000002) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_1_x32_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_OFF ( 2) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_MSK (0x00000004) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_2_x32_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_OFF ( 3) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_MSK (0x00000008) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_Rank_3_x32_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_OFF ( 4) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_MSK (0x00000010) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_LPDDR2_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_OFF ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_WID (16) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MSK (0x00FFFF00) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_LPDDR_MR_PARAMS_MR4_PERIOD_DEF (0x00000000) + +#define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_REG (0x00004214) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_OFF ( 0) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_WID ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_MSK (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_MAX (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Address_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_OFF ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_WID ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_MAX (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Data_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_OFF (16) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_WID ( 2) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_MSK (0x00030000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_MAX (0x00000003) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Rank_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_OFF (18) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_MSK (0x00040000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Write_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_OFF (19) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_MSK (0x00080000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Init_MRW_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_OFF (31) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_WID ( 1) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_MSK (0x80000000) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_MAX (0x00000001) + #define MCHBAR_CH0_CR_LPDDR_MR_COMMAND_Busy_DEF (0x00000000) + +#define MCHBAR_CH0_CR_LPDDR_MR_RESULT_REG (0x00004218) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_OFF ( 0) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_WID ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_MSK (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_MAX (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_0_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_OFF ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_WID ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_MAX (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_1_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_OFF (16) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_WID ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_MSK (0x00FF0000) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_MAX (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_2_DEF (0x00000000) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_OFF (24) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_WID ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_MSK (0xFF000000) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_MAX (0x000000FF) + #define MCHBAR_CH0_CR_LPDDR_MR_RESULT_Device_3_DEF (0x00000000) + +#define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_REG (0x0000421C) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_OFF ( 0) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_WID ( 3) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MSK (0x00000007) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MAX (0x00000007) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_DEF (0x00000003) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_OFF ( 8) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_WID ( 3) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MSK (0x00000700) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MAX (0x00000007) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_DEF (0x00000003) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_OFF (16) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_WID ( 3) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MSK (0x00070000) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MAX (0x00000007) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_DEF (0x00000003) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_OFF (24) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_WID ( 3) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MSK (0x07000000) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MAX (0x00000007) + #define MCHBAR_CH0_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_DEF (0x00000003) + +#define MCHBAR_CH0_CR_DESWIZZLE_LOW_REG (0x00004220) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_OFF ( 0) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_MSK (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_0_DEF (0x00000000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_OFF ( 4) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_MSK (0x00000070) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_1_DEF (0x00000001) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_OFF ( 8) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_MSK (0x00000700) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_2_DEF (0x00000002) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_OFF (12) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_MSK (0x00007000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_16_DEF (0x00000000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_OFF (16) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_MSK (0x00070000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_17_DEF (0x00000001) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_OFF (20) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_MSK (0x00700000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Bit_18_DEF (0x00000002) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_OFF (24) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_MSK (0x07000000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_0_DEF (0x00000000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_OFF (28) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_MSK (0x70000000) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_LOW_Byte_2_DEF (0x00000002) + +#define MCHBAR_CH0_CR_DESWIZZLE_HIGH_REG (0x00004224) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_OFF ( 0) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_MSK (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_32_DEF (0x00000000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_OFF ( 4) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_MSK (0x00000070) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_33_DEF (0x00000001) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_OFF ( 8) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_MSK (0x00000700) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_34_DEF (0x00000002) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_OFF (12) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_MSK (0x00007000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_48_DEF (0x00000000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_OFF (16) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_MSK (0x00070000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_49_DEF (0x00000001) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_OFF (20) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_MSK (0x00700000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Bit_50_DEF (0x00000002) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_OFF (24) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_MSK (0x07000000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_4_DEF (0x00000004) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_OFF (28) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_WID ( 3) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_MSK (0x70000000) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_MAX (0x00000007) + #define MCHBAR_CH0_CR_DESWIZZLE_HIGH_Byte_6_DEF (0x00000006) + +#define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_REG (0x0000428C) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_OFF ( 0) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_WID (11) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_MSK (0x000007FF) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_MAX (0x000007FF) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Interval_DEF (0x00000000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_OFF (11) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_WID ( 1) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MSK (0x00000800) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MAX (0x00000001) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_DEF (0x00000000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_OFF (12) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_WID ( 1) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MSK (0x00001000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MAX (0x00000001) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_DEF (0x00000000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_OFF (13) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_WID ( 1) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MSK (0x00002000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MAX (0x00000001) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_DEF (0x00000000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_OFF (14) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_WID ( 1) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MSK (0x00004000) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MAX (0x00000001) + #define MCHBAR_CH0_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_DEF (0x00000000) + +#define MCHBAR_CH0_CR_TC_ZQCAL_REG (0x00004290) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_OFF ( 0) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_WID ( 8) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_MSK (0x000000FF) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_MAX (0x000000FF) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_DEF (0x00000080) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_OFF ( 8) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_WID ( 8) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_MAX (0x000000FF) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_DEF (0x00000040) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_OFF ( 0) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_WID (10) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_MSK (0x000003FF) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_MAX (0x000003FF) + #define MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_DEF (0x00000080) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_OFF (10) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_WID (10) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_MSK (0x000FFC00) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_MAX (0x000003FF) + #define MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_DEF (0x00000040) + +#define MCHBAR_CH0_CR_TC_RFP_REG (0x00004294) + #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_OFF ( 0) + #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_WID ( 8) + #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_MSK (0x000000FF) + #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_MAX (0x000000FF) + #define MCHBAR_CH0_CR_TC_RFP_OREF_RI_DEF (0x0000000F) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_OFF ( 8) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_WID ( 4) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_MSK (0x00000F00) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_HP_WM_DEF (0x00000008) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_OFF (12) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_WID ( 4) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_MSK (0x0000F000) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_RFP_Refresh_panic_wm_DEF (0x00000009) + +#define MCHBAR_CH0_CR_TC_RFTP_REG (0x00004298) + #define MCHBAR_CH0_CR_TC_RFTP_tREFI_OFF ( 0) + #define MCHBAR_CH0_CR_TC_RFTP_tREFI_WID (16) + #define MCHBAR_CH0_CR_TC_RFTP_tREFI_MSK (0x0000FFFF) + #define MCHBAR_CH0_CR_TC_RFTP_tREFI_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_TC_RFTP_tREFI_DEF (0x00001004) + #define MCHBAR_CH0_CR_TC_RFTP_tRFC_OFF (16) + #define MCHBAR_CH0_CR_TC_RFTP_tRFC_WID ( 9) + #define MCHBAR_CH0_CR_TC_RFTP_tRFC_MSK (0x01FF0000) + #define MCHBAR_CH0_CR_TC_RFTP_tRFC_MAX (0x000001FF) + #define MCHBAR_CH0_CR_TC_RFTP_tRFC_DEF (0x000000B4) + #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_OFF (25) + #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_WID ( 7) + #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_MSK (0xFE000000) + #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_MAX (0x0000007F) + #define MCHBAR_CH0_CR_TC_RFTP_tREFIx9_DEF (0x00000023) + +#define MCHBAR_CH0_CR_TC_MR2_SHADDOW_REG (0x0000429C) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_OFF ( 0) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_WID ( 6) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_MSK (0x0000003F) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_MAX (0x0000003F) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_low_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_OFF ( 6) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_WID ( 2) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_MSK (0x000000C0) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_SRT_avail_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_OFF ( 8) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_WID ( 3) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_MSK (0x00000700) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_MAX (0x00000007) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_MR2_sh_high_DEF (0x00000000) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_OFF (14) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_WID ( 2) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MSK (0x0000C000) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MAX (0x00000003) + #define MCHBAR_CH0_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_DEF (0x00000000) + +#define MCHBAR_CH0_CR_MC_INIT_STATE_REG (0x000042A0) + #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_OFF ( 0) + #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_WID ( 4) + #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_MSK (0x0000000F) + #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_MAX (0x0000000F) + #define MCHBAR_CH0_CR_MC_INIT_STATE_Rank_occupancy_DEF (0x0000000F) + +#define MCHBAR_CH0_CR_TC_SRFTP_REG (0x000042A4) + #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_OFF ( 0) + #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_WID (12) + #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_MSK (0x00000FFF) + #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_MAX (0x00000FFF) + #define MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_DEF (0x00000200) + #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_OFF (12) + #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_WID ( 4) + #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_MSK (0x0000F000) + #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_DEF (0x0000000B) + #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_OFF (16) + #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_WID (10) + #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_MSK (0x03FF0000) + #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_MAX (0x000003FF) + #define MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_DEF (0x00000100) + #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_OFF (28) + #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_WID ( 4) + #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_MSK (0xF0000000) + #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_MAX (0x0000000F) + #define MCHBAR_CH0_CR_TC_SRFTP_tMOD_DEF (0x00000000) + +#define MCHBAR_CH0_CR_WDB_VISA_SEL_REG (0x000042A8) + #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_OFF ( 0) + #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_WID ( 3) + #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_MSK (0x00000007) + #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_MAX (0x00000007) + #define MCHBAR_CH0_CR_WDB_VISA_SEL_VISAByteSel_DEF (0x00000000) + +#define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_REG (0x000042C0) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_OFF ( 0) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_WID (12) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_MSK (0x00000FFF) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_MAX (0x00000FFF) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_FASTADDR_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_OFF (16) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_MSK (0x00010000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_ADDREN_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_OFF (17) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_MSK (0x00020000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_SEQEN_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_OFF (18) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_MSK (0x00040000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL0_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_OFF (19) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_MSK (0x00080000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_POL1_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_OFF (20) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_WID ( 4) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_MSK (0x00F00000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDA_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_OFF (24) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_WID ( 4) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_MSK (0x0F000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDB_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_OFF (28) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_WID ( 4) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_MSK (0xF0000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_PDAT_CMDC_DEF (0x00000000) + +#define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REG (0x000042C4) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_OFF ( 0) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_WID ( 4) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_MSK (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_BANKSEL_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_OFF ( 5) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_WID ( 5) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_MSK (0x000003E0) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_MAX (0x0000001F) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_ARRAYSEL_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_OFF (10) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_MSK (0x00000400) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_CMP_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_OFF (11) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_MSK (0x00000800) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_REP_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_OFF (12) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_WID ( 4) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_MSK (0x0000F000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_DWORD_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_OFF (16) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_WID ( 2) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_MSK (0x00030000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_MAX (0x00000003) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MODE_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_OFF (18) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_WID ( 6) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_MSK (0x00FC0000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_MAX (0x0000003F) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPMAP_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_OFF (24) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_WID ( 4) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_MSK (0x0F000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_MAX (0x0000000F) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_MPBOFFSET_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_OFF (28) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_WID ( 1) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_MSK (0x10000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_MAX (0x00000001) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_STAGE_EN_DEF (0x00000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_OFF (29) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_WID ( 2) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_MSK (0x60000000) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_MAX (0x00000003) + #define MCHBAR_CH0_CR_DCLK_LDAT_SDAT_SHADOW_DEF (0x00000000) + +#define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_REG (0x000042C8) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_OFF ( 0) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_WID (32) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAOUT_DATOUT_DEF (0x00000000) + +#define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_REG (0x000042CC) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_OFF ( 0) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_WID (32) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_DCLK_LDAT_DATAIN_0_DATIN_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_REG (0x000042D0) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_OFF ( 0) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_WID (12) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_MSK (0x00000FFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_MAX (0x00000FFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_FASTADDR_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_OFF (16) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_MSK (0x00010000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_ADDREN_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_OFF (17) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_MSK (0x00020000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_SEQEN_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_OFF (18) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_MSK (0x00040000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL0_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_OFF (19) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_MSK (0x00080000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_POL1_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_OFF (20) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_WID ( 4) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_MSK (0x00F00000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_MAX (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDA_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_OFF (24) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_WID ( 4) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_MSK (0x0F000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_MAX (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDB_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_OFF (28) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_WID ( 4) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_MSK (0xF0000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_MAX (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_PDAT_CMDC_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REG (0x000042D4) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_OFF ( 0) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_WID ( 4) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_MSK (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_MAX (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_BANKSEL_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_OFF ( 5) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_WID ( 5) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_MSK (0x000003E0) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_MAX (0x0000001F) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_ARRAYSEL_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_OFF (10) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_MSK (0x00000400) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_CMP_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_OFF (11) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_MSK (0x00000800) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_REP_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_OFF (12) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_WID ( 4) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_MSK (0x0000F000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_MAX (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_DWORD_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_OFF (16) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_WID ( 2) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_MSK (0x00030000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_MAX (0x00000003) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MODE_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_OFF (18) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_WID ( 6) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_MSK (0x00FC0000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_MAX (0x0000003F) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPMAP_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_OFF (24) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_WID ( 4) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_MSK (0x0F000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_MAX (0x0000000F) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_MPBOFFSET_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_OFF (28) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_WID ( 1) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_MSK (0x10000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_MAX (0x00000001) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_STAGE_EN_DEF (0x00000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_OFF (29) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_WID ( 2) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_MSK (0x60000000) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_MAX (0x00000003) + #define MCHBAR_CH0_CR_QCLK_LDAT_SDAT_SHADOW_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_REG (0x000042D8) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_OFF ( 0) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_WID (32) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAOUT_DATOUT_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_REG (0x000042DC) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_OFF ( 0) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_WID (32) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_0_DATIN_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_REG (0x000042E0) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_OFF ( 0) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_WID (32) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QCLK_LDAT_DATAIN_1_DATIN_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_REG (0x000042E4) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_OFF ( 0) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_WID (28) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MSK (0x0FFFFFFF) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MAX (0x0FFFFFFF) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_DEF (0x00000000) + +#define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_REG (0x000042E8) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_OFF ( 0) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_WID (32) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MSK (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MAX (0xFFFFFFFF) + #define MCHBAR_CH0_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_DEF (0x00000000) + +#define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_REG (0x000042EC) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_OFF ( 0) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_WID ( 6) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MSK (0x0000003F) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_OFF ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_WID ( 6) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MSK (0x00003F00) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_REG (0x000042F0) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_OFF ( 0) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_WID ( 6) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MSK (0x0000003F) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_OFF ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_WID ( 6) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MSK (0x00003F00) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_REG (0x000042F4) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_OFF ( 0) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_WID ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MSK (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_OFF ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_WID ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_REG (0x000042F8) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_OFF ( 0) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_WID ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MSK (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_OFF ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_WID ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_REG (0x000042FC) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_OFF ( 0) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_WID ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MSK (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_OFF ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_WID ( 8) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_REG (0x00004328) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_OFF ( 0) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_WID ( 8) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_MSK (0x000000FF) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_MAX (0x000000FF) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEF (0x00000000) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_OFF ( 8) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_WID ( 1) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MSK (0x00000100) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MAX (0x00000001) + #define MCHBAR_CH0_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_REG (0x00004340) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH0_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_REG (0x00004344) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH1_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_REG (0x00004348) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH2_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_REG (0x0000434C) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MATCH3_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_REG (0x00004350) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK0_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_REG (0x00004354) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK1_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_REG (0x00004358) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK2_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_REG (0x0000435C) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_ODT_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_MSK (0x00000010) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_Web_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_OFF ( 5) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_MSK (0x00000020) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_MSK (0x00000040) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_RASb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_OFF ( 7) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_MSK (0x00000780) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CSb_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_OFF (11) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_MSK (0x00007800) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_CKE_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_WID (16) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_MSK (0x7FFF8000) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_CMD_MASK3_MA_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_CMD_BANK_REG (0x00004360) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_MSK (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch0_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_OFF ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_MSK (0x00000038) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch1_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_OFF ( 6) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_MSK (0x000001C0) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch2_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_OFF ( 9) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_MSK (0x00000E00) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMatch3_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_OFF (12) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_MSK (0x00007000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask0_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_OFF (15) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_MSK (0x00038000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask1_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_OFF (18) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_MSK (0x001C0000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask2_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_OFF (21) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_WID ( 3) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_MSK (0x00E00000) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_MAX (0x00000007) + #define MCHBAR_CH0_CR_ODLAT_CMD_BANK_BankMask3_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_REG (0x00004364) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputMatch_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_InputInvert_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_OFF ( 8) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_MSK (0x00000100) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CountMatches_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_OFF ( 9) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_WID (15) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_OFF (24) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_MSK (0x03000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_OFF (26) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_OFF (28) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_MSK (0x30000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_OFF (30) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL0_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_REG (0x00004368) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputMatch_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_InputInvert_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_OFF ( 8) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_MSK (0x00000100) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CountMatches_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_OFF ( 9) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_WID (15) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_OFF (24) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_MSK (0x03000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_OFF (26) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_OFF (28) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_MSK (0x30000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_OFF (30) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL1_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_REG (0x0000436C) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputMatch_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_InputInvert_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_OFF ( 8) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_MSK (0x00000100) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CountMatches_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_OFF ( 9) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_WID (15) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_OFF (24) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_MSK (0x03000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_OFF (26) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_OFF (28) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_MSK (0x30000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_OFF (30) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL2_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_REG (0x00004370) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputMatch_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_OFF ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_WID ( 4) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_InputInvert_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_OFF ( 8) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_MSK (0x00000100) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CountMatches_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_OFF ( 9) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_WID (15) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_OFF (24) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_MSK (0x03000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_OFF (26) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_OFF (28) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_MSK (0x30000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchAction_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_OFF (30) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_WID ( 2) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH0_CR_ODLAT_SEQ_LEVEL3_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_REG (0x00004374) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_OFF ( 0) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_WID ( 1) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MSK (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MAX (0x00000001) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_DEF (0x00000000) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_OFF ( 1) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_WID (16) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MSK (0x0001FFFE) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MAX (0x0000FFFF) + #define MCHBAR_CH0_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_DEF (0x00000000) + +#define MCHBAR_CH0_CR_SC_WDBWM_REG (0x0000438C) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_OFF ( 0) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_WID ( 8) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_MSK (0x000000FF) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_MAX (0x000000FF) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Enter_DEF (0x00000038) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_OFF ( 8) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_WID ( 8) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_MSK (0x0000FF00) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_MAX (0x000000FF) + #define MCHBAR_CH0_CR_SC_WDBWM_WMM_Exit_DEF (0x00000030) + #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_OFF (16) + #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_WID ( 8) + #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_MSK (0x00FF0000) + #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_MAX (0x000000FF) + #define MCHBAR_CH0_CR_SC_WDBWM_WPQ_IS_DEF (0x0000003C) + #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_OFF (24) + #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_WID ( 8) + #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_MSK (0xFF000000) + #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_MAX (0x000000FF) + #define MCHBAR_CH0_CR_SC_WDBWM_Starve_count_DEF (0x000000FF) + +#define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_REG (0x00004390) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_OFF ( 0) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_WID (18) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_MSK (0x0003FFFF) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_MAX (0x0003FFFF) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_Data_DEF (0x00000000) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_OFF (31) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_WID ( 1) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_MSK (0x80000000) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_MAX (0x00000001) + #define MCHBAR_CH0_CR_VISA_CTL_MCMNTS_VORANGE_DEF (0x00000000) + +#define MCHBAR_CH1_CR_TC_BANK_REG (0x00004400) + #define MCHBAR_CH1_CR_TC_BANK_tRCD_OFF ( 0) + #define MCHBAR_CH1_CR_TC_BANK_tRCD_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_tRCD_MSK (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_tRCD_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_tRCD_DEF (0x00000006) + #define MCHBAR_CH1_CR_TC_BANK_tRP_OFF ( 5) + #define MCHBAR_CH1_CR_TC_BANK_tRP_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_tRP_MSK (0x000003E0) + #define MCHBAR_CH1_CR_TC_BANK_tRP_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_tRP_DEF (0x00000006) + #define MCHBAR_CH1_CR_TC_BANK_tRAS_OFF (10) + #define MCHBAR_CH1_CR_TC_BANK_tRAS_WID ( 6) + #define MCHBAR_CH1_CR_TC_BANK_tRAS_MSK (0x0000FC00) + #define MCHBAR_CH1_CR_TC_BANK_tRAS_MAX (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_tRAS_DEF (0x00000014) + #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_OFF (16) + #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_MSK (0x000F0000) + #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_tRDPRE_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_OFF (20) + #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_WID ( 6) + #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_MSK (0x03F00000) + #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_MAX (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_tWRPRE_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_tRRD_OFF (26) + #define MCHBAR_CH1_CR_TC_BANK_tRRD_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_tRRD_MSK (0x3C000000) + #define MCHBAR_CH1_CR_TC_BANK_tRRD_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_tRRD_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_OFF (30) + #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_MSK (0xC0000000) + #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_tRPab_ext_DEF (0x00000000) + +#define MCHBAR_CH1_CR_TC_BANK_RANK_A_REG (0x00004404) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_OFF ( 0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_MSK (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_DEF (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_OFF ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_WID ( 8) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_MSK (0x00000FF0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_MAX (0x000000FF) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_DEF (0x00000010) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_OFF (12) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_WID ( 3) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_MSK (0x00007000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_MAX (0x00000007) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_OFF (15) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_MSK (0x00078000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_OFF (19) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_MSK (0x00780000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_OFF (23) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_MSK (0x0F800000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_DEF (0x00000004) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_OFF (29) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_WID ( 1) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_MSK (0x20000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_MAX (0x00000001) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_3st_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_OFF (30) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_MSK (0xC0000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_DEF (0x00000002) + +#define MCHBAR_CH1_CR_TC_BANK_RANK_B_REG (0x00004408) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_OFF ( 0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_WID ( 6) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_MSK (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_MAX (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_OFF ( 6) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_MSK (0x000003C0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dr_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_OFF (10) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_MSK (0x00003C00) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRRD_dd_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_OFF (14) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_WID ( 3) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_MSK (0x0001C000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_MAX (0x00000007) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_OFF (17) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_MSK (0x001E0000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dr_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_OFF (21) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_MSK (0x01E00000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRWR_dd_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_OFF (25) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_WID ( 6) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_MSK (0x7E000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_MAX (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_tWRPDEN_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_OFF (31) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_WID ( 1) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_MSK (0x80000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_MAX (0x00000001) + #define MCHBAR_CH1_CR_TC_BANK_RANK_B_Dec_WRD_DEF (0x00000000) + +#define MCHBAR_CH1_CR_TC_BANK_RANK_C_REG (0x0000440C) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_OFF ( 0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_WID ( 6) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_MSK (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_MAX (0x0000003F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXPDLL_DEF (0x0000000A) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_OFF ( 6) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_MSK (0x000003C0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tXP_DEF (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_OFF (10) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_WID ( 4) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_MSK (0x00003C00) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_TAONPD_DEF (0x00000009) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_OFF (14) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_MSK (0x0007C000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_OFF (19) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_MSK (0x00F80000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dr_DEF (0x00000005) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_OFF (24) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_MSK (0x1F000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_C_tRDWR_dd_DEF (0x00000005) + +#define MCHBAR_CH1_CR_CMD_RATE_REG (0x00004410) + #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_OFF ( 0) + #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_WID ( 1) + #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_MSK (0x00000001) + #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_MAX (0x00000001) + #define MCHBAR_CH1_CR_CMD_RATE_enable_cmd_rate_limit_DEF (0x00000000) + #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_OFF ( 1) + #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_WID ( 3) + #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_MSK (0x0000000E) + #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_MAX (0x00000007) + #define MCHBAR_CH1_CR_CMD_RATE_cmd_rate_limit_DEF (0x00000004) + #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_OFF ( 4) + #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_WID ( 4) + #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_MSK (0x000000F0) + #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_MAX (0x0000000F) + #define MCHBAR_CH1_CR_CMD_RATE_reset_on_command_DEF (0x00000000) + #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_OFF ( 8) + #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_WID ( 4) + #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_MSK (0x00000F00) + #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_MAX (0x0000000F) + #define MCHBAR_CH1_CR_CMD_RATE_reset_delay_DEF (0x00000000) + #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_OFF (12) + #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_WID ( 2) + #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_MSK (0x00003000) + #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_MAX (0x00000003) + #define MCHBAR_CH1_CR_CMD_RATE_ck_to_cke_delay_DEF (0x00000001) + #define MCHBAR_CH1_CR_CMD_RATE_spare_OFF (14) + #define MCHBAR_CH1_CR_CMD_RATE_spare_WID (17) + #define MCHBAR_CH1_CR_CMD_RATE_spare_MSK (0x7FFFC000) + #define MCHBAR_CH1_CR_CMD_RATE_spare_MAX (0x0001FFFF) + #define MCHBAR_CH1_CR_CMD_RATE_spare_DEF (0x00000000) + #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_OFF (31) + #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_WID ( 1) + #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_MSK (0x80000000) + #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_MAX (0x00000001) + #define MCHBAR_CH1_CR_CMD_RATE_init_mrw_2n_cs_DEF (0x00000000) + +#define MCHBAR_CH1_CR_TC_BANK_RANK_D_REG (0x00004414) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_OFF ( 0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_MSK (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCL_DEF (0x00000006) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_OFF ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_WID ( 5) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_MSK (0x000003E0) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_MAX (0x0000001F) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tWCL_DEF (0x00000006) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_OFF (10) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_MSK (0x00000C00) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tCPDED_DEF (0x00000001) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_OFF (12) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_MSK (0x00003000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_tPRPDEN_DEF (0x00000001) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_OFF (14) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_WID ( 3) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_MSK (0x0001C000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_MAX (0x00000007) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Delay_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_OFF (17) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_MSK (0x00060000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Read_Duration_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_OFF (19) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_MSK (0x00180000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_OFF (19) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_WID ( 3) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MSK (0x00380000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MAX (0x00000007) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_OFF (22) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_WID ( 3) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MSK (0x01C00000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MAX (0x00000007) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_OFF (25) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_WID ( 1) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MSK (0x02000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_MAX (0x00000001) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_Odt_Always_Rank0_Ult_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_OFF (26) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_WID ( 2) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_MSK (0x0C000000) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_BANK_RANK_D_cmd_delay_Ult_DEF (0x00000000) + +#define MCHBAR_CH1_CR_SCHED_CBIT_REG (0x00004420) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_OFF ( 0) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_MSK (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_cas_DEF (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_OFF ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_MSK (0x00000002) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_cas_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_OFF ( 2) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_MSK (0x00000004) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ras_DEF (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_OFF ( 3) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_MSK (0x00000008) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_is_ras_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_OFF ( 4) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_MSK (0x00000010) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_1c_byp_DEF (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_OFF ( 5) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_MSK (0x00000020) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_2c_byp_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_OFF ( 6) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_MSK (0x00000040) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_deprd_opt_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_OFF ( 7) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_MSK (0x00000080) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_pt_it_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_OFF ( 8) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_MSK (0x00000100) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_ring_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_OFF ( 9) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_MSK (0x00000200) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_prcnt_sa_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_OFF (10) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_MSK (0x00000400) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_ph_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_OFF (11) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_MSK (0x00000800) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pe_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_OFF (12) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_MSK (0x00001000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_blkr_pm_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_OFF (13) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_MSK (0x00002000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_odt_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_OFF (14) + #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_MSK (0x00004000) + #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_OE_alw_off_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_OFF (16) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_MSK (0x00010000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_aom_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_OFF (17) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_MSK (0x00020000) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_rpq_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_OFF (18) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_MSK (0x00040000) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_block_wpq_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_OFF (19) + #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_MSK (0x00080000) + #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_invert_align_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_OFF (20) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_MSK (0x00100000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_write_gap_DEF (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_OFF (21) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_MSK (0x00200000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_zq_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_OFF (22) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_MSK (0x00400000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_tt_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_OFF (23) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_MSK (0x00800000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_opp_ref_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_OFF (24) + #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_MSK (0x01000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_Long_ZQ_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_OFF (25) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_MSK (0x02000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_srx_zq_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_OFF (26) + #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_MSK (0x04000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_Serialize_ZQ_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_OFF (27) + #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_MSK (0x08000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_ZQ_fast_exec_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_OFF (28) + #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_MSK (0x10000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_Dis_DriveNop_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_OFF (29) + #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_MSK (0x20000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_Pres_WDB_Ent_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_OFF (30) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_MSK (0x40000000) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_CBIT_dis_clk_gate_DEF (0x00000000) + +#define MCHBAR_CH1_CR_SC_ROUNDT_LAT_REG (0x00004424) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_OFF ( 0) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_WID ( 6) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_MSK (0x0000003F) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_MAX (0x0000003F) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D0_DEF (0x00000020) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_OFF ( 8) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_WID ( 6) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_MSK (0x00003F00) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_MAX (0x0000003F) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D0_DEF (0x00000020) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_OFF (16) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_WID ( 6) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_MSK (0x003F0000) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_MAX (0x0000003F) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R0D1_DEF (0x00000020) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_OFF (24) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_WID ( 6) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_MSK (0x3F000000) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_MAX (0x0000003F) + #define MCHBAR_CH1_CR_SC_ROUNDT_LAT_Lat_R1D1_DEF (0x00000020) + +#define MCHBAR_CH1_CR_SC_IO_LATENCY_REG (0x00004428) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_OFF ( 0) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_WID ( 4) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_MSK (0x0000000F) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_MAX (0x0000000F) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D0_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_OFF ( 4) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_WID ( 4) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_MSK (0x000000F0) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_MAX (0x0000000F) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D0_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_OFF ( 8) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_WID ( 4) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_MSK (0x00000F00) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_MAX (0x0000000F) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R0D1_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_OFF (12) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_WID ( 4) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_MSK (0x0000F000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_MAX (0x0000000F) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_IOLAT_R1D1_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_OFF (16) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_WID ( 6) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_MSK (0x003F0000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_MAX (0x0000003F) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_RT_IOCOMP_DEF (0x0000000E) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_OFF (30) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_WID ( 1) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_MSK (0x40000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_MAX (0x00000001) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_three_channels_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_OFF (31) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_WID ( 1) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MSK (0x80000000) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_MAX (0x00000001) + #define MCHBAR_CH1_CR_SC_IO_LATENCY_DIS_RT_CLK_GATE_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_REG (0x0000442C) + #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_OFF ( 0) + #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_WID (32) + #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_ROUND_TRIP_DFT_DATA_DATA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_DFT_MISC_REG (0x00004430) + #define MCHBAR_CH1_CR_DFT_MISC_WDAR_OFF ( 0) + #define MCHBAR_CH1_CR_DFT_MISC_WDAR_WID ( 1) + #define MCHBAR_CH1_CR_DFT_MISC_WDAR_MSK (0x00000001) + #define MCHBAR_CH1_CR_DFT_MISC_WDAR_MAX (0x00000001) + #define MCHBAR_CH1_CR_DFT_MISC_WDAR_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_OFF ( 1) + #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_WID ( 3) + #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_MSK (0x0000000E) + #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_MAX (0x00000007) + #define MCHBAR_CH1_CR_DFT_MISC_safe_mask_sel_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_OFF ( 4) + #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_WID ( 1) + #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_MSK (0x00000010) + #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_MAX (0x00000001) + #define MCHBAR_CH1_CR_DFT_MISC_force_rcv_en_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_OFF ( 8) + #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_WID ( 2) + #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_MSK (0x00000300) + #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_MAX (0x00000003) + #define MCHBAR_CH1_CR_DFT_MISC_DDR_QUAL_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_OFF (10) + #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_WID ( 2) + #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_MSK (0x00000C00) + #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_MAX (0x00000003) + #define MCHBAR_CH1_CR_DFT_MISC_Qual_length_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_OFF (12) + #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_WID ( 1) + #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_MSK (0x00001000) + #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_MAX (0x00000001) + #define MCHBAR_CH1_CR_DFT_MISC_WDB_Block_En_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_OFF (13) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_WID ( 4) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_MSK (0x0001E000) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_PTR_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_OFF (17) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_WID ( 1) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_MSK (0x00020000) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_MAX (0x00000001) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_ENABLE_DEF (0x00000000) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_OFF (18) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_WID ( 1) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MSK (0x00040000) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_MAX (0x00000001) + #define MCHBAR_CH1_CR_DFT_MISC_RT_DFT_READ_SEL_ADDR_DEF (0x00000000) + +#define MCHBAR_CH1_CR_READ_RETURN_DFT_REG (0x00004434) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_OFF ( 0) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_WID ( 8) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_MSK (0x000000FF) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_MAX (0x000000FF) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_ECC_DEF (0x00000000) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_OFF ( 8) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_WID ( 2) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_MSK (0x00000300) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_MAX (0x00000003) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_RRD_DFT_Mode_DEF (0x00000000) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_OFF (10) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_WID ( 5) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_MSK (0x00007C00) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_MAX (0x0000001F) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_LFSR_Seed_Index_DEF (0x00000000) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_OFF (15) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_WID ( 1) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_MSK (0x00008000) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_MAX (0x00000001) + #define MCHBAR_CH1_CR_READ_RETURN_DFT_Inversion_Mode_DEF (0x00000000) + +#define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_REG (0x00004438) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_OFF ( 0) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_MSK (0x00000001) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_imph_error_DEF (0x00000000) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_OFF ( 8) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_WID ( 1) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_MSK (0x00000100) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_MAX (0x00000001) + #define MCHBAR_CH1_CR_SCHED_SECOND_CBIT_dis_async_odt_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_REG (0x00004440) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MSK (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux0_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_OFF ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MSK (0x00000018) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux1_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_OFF ( 6) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MSK (0x000000C0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Mux2_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_OFF (14) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MSK (0x00004000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Replace_Byte_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_OFF (15) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MSK (0x00008000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_ECC_Data_Source_Sel_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MSK (0x003F0000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Save_LFSR_Seed_Rate_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MSK (0x07000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_CFG_Reload_LFSR_Seed_Rate_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_REG (0x00004444) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MSK (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_RD_STATUS_WDB_Current_Read_Pointer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_REG (0x00004448) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_0_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_REG (0x0000444C) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_1_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_REG (0x00004450) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_WR_2_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_REG (0x00004454) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_0_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_REG (0x00004458) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_1_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_REG (0x0000445C) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_RD_2_Pattern_Buffer_MAX (0x00FFFFFF) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_REG (0x00004460) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_REG (0x00004464) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_REG (0x00004468) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_WR_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_REG (0x0000446C) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_REG (0x00004470) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_REG (0x00004474) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_WID (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MSK (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_MAX (0x00FFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_PB_STATUS_RD_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_REG (0x00004478) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MSK (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_data_select_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_L_counter_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MSK (0x00FF0000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_M_counter_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MSK (0xFF000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_MUX_LMN_N_counter_DEF (0x00000001) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_REG (0x00004484) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MSK (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_ECC_Inv_or_DC_Enable_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MSK (0x000F0000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Rate_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_OFF (20) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MSK (0x00100000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_DC_Polarity_Control_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_OFF (30) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MSK (0x40000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Control_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_OFF (31) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MSK (0x80000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_INV_Inv_or_DC_Shift_Enable_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_REG (0x00004490) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_WID (64) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MSK (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_MAX (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_DATA_INV_Data_Inv_or_DC_Enable_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_REG (0x00004498) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MSK (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_on_Nth_Error_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_OFF (12) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MSK (0x00003000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Stop_On_Error_Control_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MSK (0x00FF0000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Chunk_DEF (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MSK (0xFF000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_CTL_Selective_Error_Enable_Cacheline_DEF (0x000000FF) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_REG (0x0000449C) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MSK (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_MASK_ECC_Error_Mask_DEF (0x00000000) + +#define MCHBAR_CH1_CR_STM_CONFIG_REG (0x000044A4) + #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_OFF ( 0) + #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_WID ( 2) + #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_MSK (0x00000003) + #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_MAX (0x00000003) + #define MCHBAR_CH1_CR_STM_CONFIG_Stretch_mode_DEF (0x00000000) + #define MCHBAR_CH1_CR_STM_CONFIG_STF_OFF ( 4) + #define MCHBAR_CH1_CR_STM_CONFIG_STF_WID ( 3) + #define MCHBAR_CH1_CR_STM_CONFIG_STF_MSK (0x00000070) + #define MCHBAR_CH1_CR_STM_CONFIG_STF_MAX (0x00000007) + #define MCHBAR_CH1_CR_STM_CONFIG_STF_DEF (0x00000000) + +#define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_REG (0x000044A8) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_OFF ( 0) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_WID (10) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MSK (0x000003FF) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_MAX (0x000003FF) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_ring_DEF (0x00000040) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_OFF (16) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_WID (10) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MSK (0x03FF0000) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_MAX (0x000003FF) + #define MCHBAR_CH1_CR_SC_PR_CNT_CONFIG_Priority_count_SA_DEF (0x00000100) + +#define MCHBAR_CH1_CR_SC_PCIT_REG (0x000044AC) + #define MCHBAR_CH1_CR_SC_PCIT_PCIT_OFF ( 0) + #define MCHBAR_CH1_CR_SC_PCIT_PCIT_WID ( 8) + #define MCHBAR_CH1_CR_SC_PCIT_PCIT_MSK (0x000000FF) + #define MCHBAR_CH1_CR_SC_PCIT_PCIT_MAX (0x000000FF) + #define MCHBAR_CH1_CR_SC_PCIT_PCIT_DEF (0x00000040) + +#define MCHBAR_CH1_CR_PM_PDWN_CONFIG_REG (0x000044B0) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_OFF ( 0) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_WID (12) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MSK (0x00000FFF) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_MAX (0x00000FFF) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_idle_counter_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_OFF (12) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_WID ( 4) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_MSK (0x0000F000) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_MAX (0x0000000F) + #define MCHBAR_CH1_CR_PM_PDWN_CONFIG_PDWN_mode_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ECC_INJECT_COUNT_REG (0x000044B4) + #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_OFF ( 0) + #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_WID (32) + #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_ECC_INJECT_COUNT_Count_DEF (0xFFFFFFFF) + +#define MCHBAR_CH1_CR_ECC_DFT_REG (0x000044B8) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_OFF ( 0) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_WID ( 8) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_MSK (0x000000FF) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_MAX (0x000000FF) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_fill_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_OFF ( 8) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_WID ( 2) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_MSK (0x00000300) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_MAX (0x00000003) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_trigger_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_OFF (10) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_WID ( 1) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_MSK (0x00000400) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_BS_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_OFF (11) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_WID ( 3) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_MSK (0x00003800) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_MAX (0x00000007) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_Inject_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_OFF (14) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_WID ( 1) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_MSK (0x00004000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECC_DFT_ECC_correction_disable_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_OFF (15) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_WID ( 1) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_MSK (0x00008000) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECC_DFT_ECC4ANA_Inject_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_OFF (16) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_WID ( 1) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_MSK (0x00010000) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_MCA_LOG_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_OFF (17) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_WID ( 1) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_MSK (0x00020000) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCH_EVENT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_OFF (18) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_WID ( 1) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_MSK (0x00040000) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECC_DFT_DIS_PCIE_POISON_DEF (0x00000000) + +#define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_REG (0x000044C0) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_OFF ( 0) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_WID (18) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_MSK (0x0003FFFF) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_MAX (0x0003FFFF) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_Data_DEF (0x00000000) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_OFF (31) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_WID ( 1) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_MSK (0x80000000) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_MAX (0x00000001) + #define MCHBAR_CH1_CR_VISA_CTL_MCSCHEDS_VORANGE_DEF (0x00000000) + +#define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_REG (0x000044C4) + #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_OFF ( 0) + #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_WID (32) + #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_VISA_XBAR_MCSCHEDS_Data_DEF (0x76543210) + +#define MCHBAR_CH1_CR_ECCERRLOG0_REG (0x000044C8) + #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_OFF ( 0) + #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_WID ( 1) + #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_MSK (0x00000001) + #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECCERRLOG0_CERRSTS_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_OFF ( 1) + #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_WID ( 1) + #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_MSK (0x00000002) + #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_MAX (0x00000001) + #define MCHBAR_CH1_CR_ECCERRLOG0_MERRSTS_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_OFF (16) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_WID ( 8) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_MSK (0x00FF0000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_MAX (0x000000FF) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRSYND_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_OFF (24) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_WID ( 3) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_MSK (0x07000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_MAX (0x00000007) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRCHUNK_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_OFF (27) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_WID ( 2) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_MSK (0x18000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_MAX (0x00000003) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRRANK_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_OFF (29) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_WID ( 3) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_MSK (0xE0000000) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_MAX (0x00000007) + #define MCHBAR_CH1_CR_ECCERRLOG0_ERRBANK_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ECCERRLOG1_REG (0x000044CC) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_OFF ( 0) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_WID (16) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRROW_DEF (0x00000000) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_OFF (16) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_WID (16) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_MSK (0xFFFF0000) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ECCERRLOG1_ERRCOL_DEF (0x00000000) + +#define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_REG (0x000044D0) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_OFF ( 0) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_WID ( 2) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_MSK (0x00000003) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_MAX (0x00000003) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R0_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_OFF ( 2) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_WID ( 2) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_MSK (0x0000000C) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_MAX (0x00000003) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D0R1_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_OFF ( 4) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_WID ( 2) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_MSK (0x00000030) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_MAX (0x00000003) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R0_DEF (0x00000000) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_OFF ( 6) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_WID ( 2) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_MSK (0x000000C0) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_MAX (0x00000003) + #define MCHBAR_CH1_CR_SC_WR_ADD_DELAY_D1R1_DEF (0x00000000) + +#define MCHBAR_CH1_CR_WMM_READ_CONFIG_REG (0x000044D4) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_OFF ( 0) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_WID ( 1) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_MSK (0x00000001) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_MAX (0x00000001) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_Dis_Opp_rd_DEF (0x00000000) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_OFF ( 1) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_WID ( 1) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_MSK (0x00000002) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_MAX (0x00000001) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_ACT_Enable_DEF (0x00000001) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_OFF ( 2) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_WID ( 1) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_MSK (0x00000004) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_MAX (0x00000001) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_PRE_Enable_DEF (0x00000001) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_OFF ( 3) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_WID ( 4) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MSK (0x00000078) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_MAX (0x0000000F) + #define MCHBAR_CH1_CR_WMM_READ_CONFIG_MAX_RPQ_Cas_DEF (0x00000008) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_REG (0x000044D8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_WID (64) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MSK (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_MAX (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_MASK_Data_Error_Mask_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_REG (0x000044E0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_WID (64) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MSK (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_MAX (0xFFFFFFFFFFFFFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_DATA_STATUS_Data_Error_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_REG (0x000044E8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MSK (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_ECC_Error_Status_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Chunk_Error_Status_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MSK (0x000F0000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Rank_Error_Status_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_OFF (32) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_WID ( 9) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MSK (0x1FF00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_MAX (0x000001FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Byte_Group_Error_Status_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_OFF (52) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MSK (0x70000000000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_WDB_Rd_Chunk_Num_Status_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_OFF (56) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MSK (0x3F00000000000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS_Nth_Error_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_REG (0x000044F0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_0_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_REG (0x000044F4) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_1_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_REG (0x000044F8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_2_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_REG (0x000044FC) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_3_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_REG (0x00004500) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_4_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_REG (0x00004504) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_5_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_REG (0x00004508) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_6_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_REG (0x0000450C) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_7_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_REG (0x00004510) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_WID ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MSK (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_MAX (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Pointer_DEF (0x0000007F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_OFF ( 7) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MSK (0x00000180) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_CTL_8_Counter_Control_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_REG (0x00004514) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_0_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_REG (0x00004518) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_1_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_REG (0x0000451C) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_2_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_REG (0x00004520) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_3_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_REG (0x00004524) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_4_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_REG (0x00004528) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_5_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_REG (0x0000452C) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_6_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_REG (0x00004530) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_7_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_REG (0x00004534) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_WID (23) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MSK (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_MAX (0x007FFFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_STATUS_8_Counter_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_REG (0x00004538) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_WID ( 9) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MSK (0x000001FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_MAX (0x000001FF) + #define MCHBAR_CH1_CR_REUT_CH_ERR_COUNTER_OVERFLOW_STATUS_Counter_Overflow_Status_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_REG (0x00004580) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_WID (10) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_MSK (0x000003FF) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_MAX (0x000003FF) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Column_Address_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_MSK (0xFFFF000000) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Row_Address_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_OFF (48) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_MSK (0x7000000000000) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Bank_Address_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_OFF (56) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_MSK (0x300000000000000) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_ERROR_ADDR_Rank_Address_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_REG (0x00004588) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MSK (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_STATUS_WDB_Current_Error_Pointer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_REG (0x0000458C) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MSK (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_Enable_WDB_Error_Capture_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MSK (0x00003F00) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Starting_Error_Pointer_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MSK (0x003F0000) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_ERR_WDB_CAPTURE_CTL_WDB_Ending_Error_Pointer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_REG (0x00004590) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MSK (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_Override_DEF (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MSK (0x00000100) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_En_Start_Test_Sync_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MSK (0x000F0000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_CKE_CTRL_CKE_On_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_REG (0x00004594) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MSK (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_Override_DEF (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MSK (0x000F0000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_ODT_On_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_OFF (31) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MSK (0x80000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ODT_CTRL_MPR_Train_DDR_On_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_REG (0x00004598) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MSK (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_on_Deselect_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_OFF ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MSK (0x00000002) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Enable_CADB_Always_On_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_OFF ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MSK (0x0000003C) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Start_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_OFF ( 6) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MSK (0x000003C0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CMD_Deselect_Stop_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_OFF ( 10) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MSK (0x00003C00) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Lane_Deselect_Enable_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_OFF ( 14) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MSK (0x0000C000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_CAS_Select_Enable_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_OFF ( 16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MSK (0x00030000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_ACT_Select_Enable_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_OFF ( 18) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MSK (0x000C0000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_PRE_Select_Enable_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_OFF ( 20) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MSK (0x00F00000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Save_Current_Seed_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_OFF ( 24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MSK (0x0F000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CTRL_Reload_Starting_Seed_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_REG (0x0000459C) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MSK (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_MRS_Gap_DEF (0x00000002) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MSK (0x00000700) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Start_Pointer_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MSK (0x00070000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_End_Pointer_DEF (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MSK (0x07000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MRS_CADB_MRS_Current_Pointer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_REG (0x000045A0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MSK (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux0_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_OFF ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MSK (0x00000030) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux1_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MSK (0x00000300) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Mux2_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_OFF ( 16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MSK (0x00030000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux0_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_OFF ( 20) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MSK (0x00300000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux1_Control_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_OFF ( 24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_WID ( 2) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MSK (0x03000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_MAX (0x00000003) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_CTRL_Select_Mux2_Control_DEF (0x00000001) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_REG (0x000045A4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_REG (0x000045A8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_REG (0x000045AC) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_MUX_PB_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_REG (0x000045B0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MSK (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_data_select_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_OFF ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MSK (0x00000002) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_Enable_Sweep_Frequency_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_L_counter_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MSK (0x00FF0000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_M_counter_DEF (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_WID ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MSK (0xFF000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_CL_MUX_LMN_N_counter_DEF (0x00000001) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_REG (0x000045BC) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MSK (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_WRITE_POINTER_CADB_Write_Pointer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_REG (0x000045C0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Address_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_OFF (24) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MSK (0x07000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Bank_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_OFF (32) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MSK (0xF00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CS_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_OFF (40) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_WID ( 3) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MSK (0x70000000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_MAX (0x00000007) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_Control_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_OFF (48) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MSK (0xF000000000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_OFF (56) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MSK (0xF00000000000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_PROG_CADB_Data_CKE_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_REG (0x000045C8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_0_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_REG (0x000045CC) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_1_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_REG (0x000045D0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_WID (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_REUT_CH_PAT_CADB_SEL_MUX_PB_2_Pattern_Buffer_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_REG (0x00004600) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_WID ( 5) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MSK (0x0000001F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_MAX (0x0000001F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Rate_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_OFF ( 5) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MSK (0x00000020) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Increment_Scale_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MSK (0x00003F00) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_Start_Pointer_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_OFF (16) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_WID ( 6) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MSK (0x003F0000) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_MAX (0x0000003F) + #define MCHBAR_CH1_CR_REUT_CH_PAT_WDB_CL_CTRL_WDB_End_Pointer_DEF (0x0000003F) + +#define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_REG (0x00004604) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MSK (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Refresh_Rank_Mask_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_OFF ( 8) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MSK (0x00000100) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_RefZQ_En_Start_Test_Sync_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_OFF (31) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MSK (0x80000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_MISC_REFRESH_CTRL_Panic_Refresh_Only_DEF (0x00000000) + +#define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_REG (0x00004608) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_OFF ( 0) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_WID ( 4) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MSK (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_MAX (0x0000000F) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_ZQ_Rank_Mask_DEF (0x00000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_OFF (31) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_WID ( 1) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MSK (0x80000000) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_MAX (0x00000001) + #define MCHBAR_CH1_CR_REUT_CH_MISC_ZQ_CTRL_Always_Do_ZQ_DEF (0x00000000) + +#define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_REG (0x00004610) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_OFF ( 0) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_MSK (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_0_x32_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_OFF ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_MSK (0x00000002) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_1_x32_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_OFF ( 2) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_MSK (0x00000004) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_2_x32_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_OFF ( 3) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_MSK (0x00000008) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_Rank_3_x32_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_OFF ( 4) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_MSK (0x00000010) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_LPDDR2_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_OFF ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_WID (16) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MSK (0x00FFFF00) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_LPDDR_MR_PARAMS_MR4_PERIOD_DEF (0x00000000) + +#define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_REG (0x00004614) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_OFF ( 0) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_WID ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_MSK (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_MAX (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Address_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_OFF ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_WID ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_MAX (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Data_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_OFF (16) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_WID ( 2) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_MSK (0x00030000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_MAX (0x00000003) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Rank_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_OFF (18) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_MSK (0x00040000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Write_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_OFF (19) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_MSK (0x00080000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Init_MRW_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_OFF (31) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_WID ( 1) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_MSK (0x80000000) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_MAX (0x00000001) + #define MCHBAR_CH1_CR_LPDDR_MR_COMMAND_Busy_DEF (0x00000000) + +#define MCHBAR_CH1_CR_LPDDR_MR_RESULT_REG (0x00004618) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_OFF ( 0) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_WID ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_MSK (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_MAX (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_0_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_OFF ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_WID ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_MAX (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_1_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_OFF (16) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_WID ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_MSK (0x00FF0000) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_MAX (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_2_DEF (0x00000000) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_OFF (24) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_WID ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_MSK (0xFF000000) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_MAX (0x000000FF) + #define MCHBAR_CH1_CR_LPDDR_MR_RESULT_Device_3_DEF (0x00000000) + +#define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_REG (0x0000461C) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_OFF ( 0) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_WID ( 3) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MSK (0x00000007) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_MAX (0x00000007) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_0_DEF (0x00000003) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_OFF ( 8) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_WID ( 3) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MSK (0x00000700) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_MAX (0x00000007) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_1_DEF (0x00000003) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_OFF (16) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_WID ( 3) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MSK (0x00070000) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_MAX (0x00000007) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_2_DEF (0x00000003) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_OFF (24) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_WID ( 3) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MSK (0x07000000) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_MAX (0x00000007) + #define MCHBAR_CH1_CR_LPDDR_MR4_RANK_TEMPERATURE_Rank_3_DEF (0x00000003) + +#define MCHBAR_CH1_CR_DESWIZZLE_LOW_REG (0x00004620) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_OFF ( 0) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_MSK (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_0_DEF (0x00000000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_OFF ( 4) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_MSK (0x00000070) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_1_DEF (0x00000001) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_OFF ( 8) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_MSK (0x00000700) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_2_DEF (0x00000002) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_OFF (12) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_MSK (0x00007000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_16_DEF (0x00000000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_OFF (16) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_MSK (0x00070000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_17_DEF (0x00000001) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_OFF (20) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_MSK (0x00700000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Bit_18_DEF (0x00000002) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_OFF (24) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_MSK (0x07000000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_0_DEF (0x00000000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_OFF (28) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_MSK (0x70000000) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_LOW_Byte_2_DEF (0x00000002) + +#define MCHBAR_CH1_CR_DESWIZZLE_HIGH_REG (0x00004624) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_OFF ( 0) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_MSK (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_32_DEF (0x00000000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_OFF ( 4) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_MSK (0x00000070) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_33_DEF (0x00000001) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_OFF ( 8) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_MSK (0x00000700) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_34_DEF (0x00000002) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_OFF (12) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_MSK (0x00007000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_48_DEF (0x00000000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_OFF (16) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_MSK (0x00070000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_49_DEF (0x00000001) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_OFF (20) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_MSK (0x00700000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Bit_50_DEF (0x00000002) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_OFF (24) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_MSK (0x07000000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_4_DEF (0x00000004) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_OFF (28) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_WID ( 3) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_MSK (0x70000000) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_MAX (0x00000007) + #define MCHBAR_CH1_CR_DESWIZZLE_HIGH_Byte_6_DEF (0x00000006) + +#define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_REG (0x0000468C) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_OFF ( 0) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_WID (11) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_MSK (0x000007FF) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_MAX (0x000007FF) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Interval_DEF (0x00000000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_OFF (11) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_WID ( 1) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MSK (0x00000800) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_MAX (0x00000001) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_En_DEF (0x00000000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_OFF (12) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_WID ( 1) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MSK (0x00001000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_MAX (0x00000001) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Ref_Stagger_Mode_DEF (0x00000000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_OFF (13) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_WID ( 1) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MSK (0x00002000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_MAX (0x00000001) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_Disable_Stolen_Refresh_DEF (0x00000000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_OFF (14) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_WID ( 1) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MSK (0x00004000) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_MAX (0x00000001) + #define MCHBAR_CH1_CR_MC_REFRESH_STAGGER_En_Ref_Type_Display_DEF (0x00000000) + +#define MCHBAR_CH1_CR_TC_ZQCAL_REG (0x00004690) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_OFF ( 0) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_WID ( 8) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_MSK (0x000000FF) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_MAX (0x000000FF) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_DEF (0x00000080) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_OFF ( 8) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_WID ( 8) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_MAX (0x000000FF) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_DEF (0x00000040) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_OFF ( 0) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_WID (10) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_MSK (0x000003FF) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_MAX (0x000003FF) + #define MCHBAR_CH1_CR_TC_ZQCAL_ZQCS_period_Ult_DEF (0x00000080) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_OFF (10) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_WID (10) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_MSK (0x000FFC00) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_MAX (0x000003FF) + #define MCHBAR_CH1_CR_TC_ZQCAL_tZQCS_Ult_DEF (0x00000040) + +#define MCHBAR_CH1_CR_TC_RFP_REG (0x00004694) + #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_OFF ( 0) + #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_WID ( 8) + #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_MSK (0x000000FF) + #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_MAX (0x000000FF) + #define MCHBAR_CH1_CR_TC_RFP_OREF_RI_DEF (0x0000000F) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_OFF ( 8) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_WID ( 4) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_MSK (0x00000F00) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_HP_WM_DEF (0x00000008) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_OFF (12) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_WID ( 4) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_MSK (0x0000F000) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_RFP_Refresh_panic_wm_DEF (0x00000009) + +#define MCHBAR_CH1_CR_TC_RFTP_REG (0x00004698) + #define MCHBAR_CH1_CR_TC_RFTP_tREFI_OFF ( 0) + #define MCHBAR_CH1_CR_TC_RFTP_tREFI_WID (16) + #define MCHBAR_CH1_CR_TC_RFTP_tREFI_MSK (0x0000FFFF) + #define MCHBAR_CH1_CR_TC_RFTP_tREFI_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_TC_RFTP_tREFI_DEF (0x00001004) + #define MCHBAR_CH1_CR_TC_RFTP_tRFC_OFF (16) + #define MCHBAR_CH1_CR_TC_RFTP_tRFC_WID ( 9) + #define MCHBAR_CH1_CR_TC_RFTP_tRFC_MSK (0x01FF0000) + #define MCHBAR_CH1_CR_TC_RFTP_tRFC_MAX (0x000001FF) + #define MCHBAR_CH1_CR_TC_RFTP_tRFC_DEF (0x000000B4) + #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_OFF (25) + #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_WID ( 7) + #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_MSK (0xFE000000) + #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_MAX (0x0000007F) + #define MCHBAR_CH1_CR_TC_RFTP_tREFIx9_DEF (0x00000023) + +#define MCHBAR_CH1_CR_TC_MR2_SHADDOW_REG (0x0000469C) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_OFF ( 0) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_WID ( 6) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_MSK (0x0000003F) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_MAX (0x0000003F) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_low_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_OFF ( 6) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_WID ( 2) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_MSK (0x000000C0) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_SRT_avail_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_OFF ( 8) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_WID ( 3) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_MSK (0x00000700) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_MAX (0x00000007) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_MR2_sh_high_DEF (0x00000000) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_OFF (14) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_WID ( 2) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MSK (0x0000C000) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_MAX (0x00000003) + #define MCHBAR_CH1_CR_TC_MR2_SHADDOW_Addr_bit_swizzle_DEF (0x00000000) + +#define MCHBAR_CH1_CR_MC_INIT_STATE_REG (0x000046A0) + #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_OFF ( 0) + #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_WID ( 4) + #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_MSK (0x0000000F) + #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_MAX (0x0000000F) + #define MCHBAR_CH1_CR_MC_INIT_STATE_Rank_occupancy_DEF (0x0000000F) + +#define MCHBAR_CH1_CR_TC_SRFTP_REG (0x000046A4) + #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_OFF ( 0) + #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_WID (12) + #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_MSK (0x00000FFF) + #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_MAX (0x00000FFF) + #define MCHBAR_CH1_CR_TC_SRFTP_tXSDLL_DEF (0x00000200) + #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_OFF (12) + #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_WID ( 4) + #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_MSK (0x0000F000) + #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_SRFTP_tXS_offset_DEF (0x0000000B) + #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_OFF (16) + #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_WID (10) + #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_MSK (0x03FF0000) + #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_MAX (0x000003FF) + #define MCHBAR_CH1_CR_TC_SRFTP_tZQOPER_DEF (0x00000100) + #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_OFF (28) + #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_WID ( 4) + #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_MSK (0xF0000000) + #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_MAX (0x0000000F) + #define MCHBAR_CH1_CR_TC_SRFTP_tMOD_DEF (0x00000000) + +#define MCHBAR_CH1_CR_WDB_VISA_SEL_REG (0x000046A8) + #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_OFF ( 0) + #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_WID ( 3) + #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_MSK (0x00000007) + #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_MAX (0x00000007) + #define MCHBAR_CH1_CR_WDB_VISA_SEL_VISAByteSel_DEF (0x00000000) + +#define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_REG (0x000046C0) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_OFF ( 0) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_WID (12) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_MSK (0x00000FFF) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_MAX (0x00000FFF) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_FASTADDR_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_OFF (16) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_MSK (0x00010000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_ADDREN_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_OFF (17) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_MSK (0x00020000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_SEQEN_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_OFF (18) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_MSK (0x00040000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL0_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_OFF (19) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_MSK (0x00080000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_POL1_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_OFF (20) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_WID ( 4) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_MSK (0x00F00000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDA_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_OFF (24) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_WID ( 4) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_MSK (0x0F000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDB_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_OFF (28) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_WID ( 4) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_MSK (0xF0000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_PDAT_CMDC_DEF (0x00000000) + +#define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REG (0x000046C4) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_OFF ( 0) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_WID ( 4) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_MSK (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_BANKSEL_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_OFF ( 5) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_WID ( 5) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_MSK (0x000003E0) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_MAX (0x0000001F) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_ARRAYSEL_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_OFF (10) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_MSK (0x00000400) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_CMP_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_OFF (11) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_MSK (0x00000800) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_REP_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_OFF (12) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_WID ( 4) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_MSK (0x0000F000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_DWORD_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_OFF (16) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_WID ( 2) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_MSK (0x00030000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_MAX (0x00000003) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MODE_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_OFF (18) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_WID ( 6) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_MSK (0x00FC0000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_MAX (0x0000003F) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPMAP_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_OFF (24) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_WID ( 4) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_MSK (0x0F000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_MAX (0x0000000F) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_MPBOFFSET_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_OFF (28) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_WID ( 1) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_MSK (0x10000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_MAX (0x00000001) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_STAGE_EN_DEF (0x00000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_OFF (29) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_WID ( 2) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_MSK (0x60000000) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_MAX (0x00000003) + #define MCHBAR_CH1_CR_DCLK_LDAT_SDAT_SHADOW_DEF (0x00000000) + +#define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_REG (0x000046C8) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_OFF ( 0) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_WID (32) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAOUT_DATOUT_DEF (0x00000000) + +#define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_REG (0x000046CC) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_OFF ( 0) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_WID (32) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_DCLK_LDAT_DATAIN_0_DATIN_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_REG (0x000046D0) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_OFF ( 0) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_WID (12) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_MSK (0x00000FFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_MAX (0x00000FFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_FASTADDR_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_OFF (16) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_MSK (0x00010000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_ADDREN_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_OFF (17) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_MSK (0x00020000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_SEQEN_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_OFF (18) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_MSK (0x00040000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL0_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_OFF (19) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_MSK (0x00080000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_POL1_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_OFF (20) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_WID ( 4) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_MSK (0x00F00000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_MAX (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDA_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_OFF (24) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_WID ( 4) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_MSK (0x0F000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_MAX (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDB_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_OFF (28) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_WID ( 4) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_MSK (0xF0000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_MAX (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_PDAT_CMDC_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REG (0x000046D4) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_OFF ( 0) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_WID ( 4) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_MSK (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_MAX (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_BANKSEL_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_OFF ( 5) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_WID ( 5) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_MSK (0x000003E0) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_MAX (0x0000001F) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_ARRAYSEL_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_OFF (10) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_MSK (0x00000400) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_CMP_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_OFF (11) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_MSK (0x00000800) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_REP_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_OFF (12) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_WID ( 4) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_MSK (0x0000F000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_MAX (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_DWORD_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_OFF (16) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_WID ( 2) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_MSK (0x00030000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_MAX (0x00000003) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MODE_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_OFF (18) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_WID ( 6) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_MSK (0x00FC0000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_MAX (0x0000003F) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPMAP_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_OFF (24) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_WID ( 4) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_MSK (0x0F000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_MAX (0x0000000F) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_MPBOFFSET_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_OFF (28) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_WID ( 1) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_MSK (0x10000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_MAX (0x00000001) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_STAGE_EN_DEF (0x00000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_OFF (29) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_WID ( 2) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_MSK (0x60000000) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_MAX (0x00000003) + #define MCHBAR_CH1_CR_QCLK_LDAT_SDAT_SHADOW_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_REG (0x000046D8) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_OFF ( 0) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_WID (32) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAOUT_DATOUT_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_REG (0x000046DC) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_OFF ( 0) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_WID (32) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_0_DATIN_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_REG (0x000046E0) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_OFF ( 0) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_WID (32) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QCLK_LDAT_DATAIN_1_DATIN_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_REG (0x000046E4) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_OFF ( 0) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_WID (28) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MSK (0x0FFFFFFF) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_MAX (0x0FFFFFFF) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_RPQ_RPQ_disable_DEF (0x00000000) + +#define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_REG (0x000046E8) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_OFF ( 0) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_WID (32) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MSK (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_MAX (0xFFFFFFFF) + #define MCHBAR_CH1_CR_QUEUE_ENTRY_DISABLE_WPQ_WPQ_disable_DEF (0x00000000) + +#define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_REG (0x000046EC) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_OFF ( 0) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_WID ( 6) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MSK (0x0000003F) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM0_IDLE_ENERGY_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_OFF ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_WID ( 6) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MSK (0x00003F00) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_DIMM1_IDLE_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_REG (0x000046F0) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_OFF ( 0) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_WID ( 6) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MSK (0x0000003F) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM0_PD_ENERGY_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_OFF ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_WID ( 6) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MSK (0x00003F00) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_MAX (0x0000003F) + #define MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_DIMM1_PD_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_REG (0x000046F4) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_OFF ( 0) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_WID ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MSK (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM0_ACT_ENERGY_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_OFF ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_WID ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_DIMM1_ACT_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_REG (0x000046F8) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_OFF ( 0) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_WID ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MSK (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM0_RD_ENERGY_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_OFF ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_WID ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_DIMM1_RD_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_REG (0x000046FC) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_OFF ( 0) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_WID ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MSK (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM0_WR_ENERGY_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_OFF ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_WID ( 8) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_DIMM1_WR_ENERGY_DEF (0x00000000) + +#define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_REG (0x00004728) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_OFF ( 0) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_WID ( 8) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_MSK (0x000000FF) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_MAX (0x000000FF) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEF (0x00000000) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_OFF ( 8) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_WID ( 1) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MSK (0x00000100) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_MAX (0x00000001) + #define MCHBAR_CH1_CR_PM_THRT_CKE_MIN_CKE_MIN_DEFEATURE_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_REG (0x00004740) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH0_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_REG (0x00004744) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH1_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_REG (0x00004748) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH2_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_REG (0x0000474C) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MATCH3_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_REG (0x00004750) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK0_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_REG (0x00004754) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK1_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_REG (0x00004758) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK2_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_REG (0x0000475C) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_ODT_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_MSK (0x00000010) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_Web_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_OFF ( 5) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_MSK (0x00000020) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_MSK (0x00000040) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_RASb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_OFF ( 7) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_MSK (0x00000780) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CSb_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_OFF (11) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_MSK (0x00007800) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_CKE_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_WID (16) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_MSK (0x7FFF8000) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_CMD_MASK3_MA_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_CMD_BANK_REG (0x00004760) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_MSK (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch0_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_OFF ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_MSK (0x00000038) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch1_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_OFF ( 6) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_MSK (0x000001C0) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch2_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_OFF ( 9) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_MSK (0x00000E00) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMatch3_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_OFF (12) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_MSK (0x00007000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask0_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_OFF (15) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_MSK (0x00038000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask1_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_OFF (18) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_MSK (0x001C0000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask2_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_OFF (21) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_WID ( 3) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_MSK (0x00E00000) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_MAX (0x00000007) + #define MCHBAR_CH1_CR_ODLAT_CMD_BANK_BankMask3_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_REG (0x00004764) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputMatch_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_InputInvert_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_OFF ( 8) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_MSK (0x00000100) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CountMatches_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_OFF ( 9) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_WID (15) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_OFF (24) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_MSK (0x03000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_OFF (26) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_OFF (28) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_MSK (0x30000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_OFF (30) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL0_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_REG (0x00004768) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputMatch_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_InputInvert_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_OFF ( 8) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_MSK (0x00000100) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CountMatches_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_OFF ( 9) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_WID (15) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_OFF (24) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_MSK (0x03000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_OFF (26) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_OFF (28) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_MSK (0x30000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_OFF (30) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL1_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_REG (0x0000476C) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputMatch_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_InputInvert_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_OFF ( 8) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_MSK (0x00000100) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CountMatches_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_OFF ( 9) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_WID (15) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_OFF (24) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_MSK (0x03000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_OFF (26) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_OFF (28) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_MSK (0x30000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_OFF (30) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL2_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_REG (0x00004770) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_MSK (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputMatch_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_OFF ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_WID ( 4) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_MSK (0x000000F0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_MAX (0x0000000F) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_InputInvert_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_OFF ( 8) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_MSK (0x00000100) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CountMatches_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_OFF ( 9) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_WID (15) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MSK (0x00FFFE00) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_MAX (0x00007FFF) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterThreshold_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_OFF (24) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_MSK (0x03000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_OFF (26) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MSK (0x0C000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_CounterNextState_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_OFF (28) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_MSK (0x30000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchAction_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_OFF (30) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_WID ( 2) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MSK (0xC0000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_MAX (0x00000003) + #define MCHBAR_CH1_CR_ODLAT_SEQ_LEVEL3_MatchNextState_DEF (0x00000000) + +#define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_REG (0x00004774) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_OFF ( 0) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_WID ( 1) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MSK (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_MAX (0x00000001) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_TriggerBlockEnable_DEF (0x00000000) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_OFF ( 1) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_WID (16) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MSK (0x0001FFFE) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_MAX (0x0000FFFF) + #define MCHBAR_CH1_CR_ODLAT_SEQ_GLOBAL_GlobalCounterThreshold_DEF (0x00000000) + +#define MCHBAR_CH1_CR_SC_WDBWM_REG (0x0000478C) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_OFF ( 0) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_WID ( 8) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_MSK (0x000000FF) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_MAX (0x000000FF) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Enter_DEF (0x00000038) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_OFF ( 8) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_WID ( 8) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_MSK (0x0000FF00) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_MAX (0x000000FF) + #define MCHBAR_CH1_CR_SC_WDBWM_WMM_Exit_DEF (0x00000030) + #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_OFF (16) + #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_WID ( 8) + #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_MSK (0x00FF0000) + #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_MAX (0x000000FF) + #define MCHBAR_CH1_CR_SC_WDBWM_WPQ_IS_DEF (0x0000003C) + #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_OFF (24) + #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_WID ( 8) + #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_MSK (0xFF000000) + #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_MAX (0x000000FF) + #define MCHBAR_CH1_CR_SC_WDBWM_Starve_count_DEF (0x000000FF) + +#define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_REG (0x00004790) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_OFF ( 0) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_WID (18) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_MSK (0x0003FFFF) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_MAX (0x0003FFFF) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_Data_DEF (0x00000000) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_OFF (31) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_WID ( 1) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_MSK (0x80000000) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_MAX (0x00000001) + #define MCHBAR_CH1_CR_VISA_CTL_MCMNTS_VORANGE_DEF (0x00000000) + +#pragma pack(pop) +#endif // __McMain_h__ |