diff options
Diffstat (limited to 'ReferenceCode/Chipset/SystemAgent/Protocol')
20 files changed, 1527 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/BdatAccess/BdatAccess.c b/ReferenceCode/Chipset/SystemAgent/Protocol/BdatAccess/BdatAccess.c new file mode 100644 index 0000000..ec43597 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/BdatAccess/BdatAccess.c @@ -0,0 +1,29 @@ +/** @file + Bdat Access Handler Protocol + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#endif +#include EFI_PROTOCOL_DEFINITION (BdatAccess) + +EFI_GUID gBdatAccessGuid = EFI_BDAT_ACCESS_GUID; + +EFI_GUID_STRING(&gBdatAccessGuid, "BDAT ACCESS", "BDAT ACCESS"); diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/BdatAccess/BdatAccess.h b/ReferenceCode/Chipset/SystemAgent/Protocol/BdatAccess/BdatAccess.h new file mode 100644 index 0000000..1d49638 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/BdatAccess/BdatAccess.h @@ -0,0 +1,36 @@ +/** @file + This file abstracts Bdat Access Handler Protocol. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +#ifndef _BDAT_ACCESS_PROTOCOL_H_ +#define _BDAT_ACCESS_PROTOCOL_H_ + +#define EFI_BDAT_ACCESS_GUID \ + { \ + 0xb979746a, 0x8c1f, 0x4a2b, 0x97, 0xe4, 0x78, 0xe9, 0x3a, 0x71, 0xa7, 0xa \ + } + +typedef struct _BDAT_ACCESS_PROTOCOL { + UINTN bdat; +} BDAT_ACCESS_PROTOCOL; + +extern EFI_GUID gBdatAccessGuid; + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/GopComponentName2/GopComponentName2.c b/ReferenceCode/Chipset/SystemAgent/Protocol/GopComponentName2/GopComponentName2.c new file mode 100644 index 0000000..f430cf3 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/GopComponentName2/GopComponentName2.c @@ -0,0 +1,37 @@ +/** @file + Protocol to retrieve the GOP driver version + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#include "Tiano.h" + +/// +/// Include the protocol header file +/// +#include "GopComponentName2.h" + +/// +/// Protocol GUID definition +/// +EFI_GUID gGopComponentName2ProtocolGuid = GOP_COMPONENT_NAME2_PROTOCOL_GUID + +/// +/// Protocol description +/// +EFI_GUID_STRING + (&gGopComponentName2ProtocolGuid, "ComponentName2 Protocol", "Intel(R) DXE Phase Gop Component Name 2 Protocol"); diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/GopComponentName2/GopComponentName2.h b/ReferenceCode/Chipset/SystemAgent/Protocol/GopComponentName2/GopComponentName2.h new file mode 100644 index 0000000..51ff044 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/GopComponentName2/GopComponentName2.h @@ -0,0 +1,72 @@ +/** @file + Protocol to retrieve the GOP driver version + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +#ifndef _GOP_COMPONENT_NAME2_H_ +#define _GOP_COMPONENT_NAME2_H_ +// +// Global ID for the Component Name Protocol +// +#define GOP_COMPONENT_NAME2_PROTOCOL_GUID \ + { \ + 0x651b7ebd, 0xce13, 0x41d0, 0x82, 0xe5, 0xa0, 0x63, 0xab, 0xbe, 0x9b, 0xb6 \ + } + +EFI_FORWARD_DECLARATION (GOP_COMPONENT_NAME2_PROTOCOL); + + +typedef struct _GOP_COMPONENT_NAME2_PROTOCOL GOP_COMPONENT_NAME2_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_NAME) ( + IN GOP_COMPONENT_NAME2_PROTOCOL * This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ); + +typedef +EFI_STATUS +(EFIAPI *GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME) ( + IN GOP_COMPONENT_NAME2_PROTOCOL * This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ); + +typedef +EFI_STATUS +(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_VERSION) ( + IN GOP_COMPONENT_NAME2_PROTOCOL * This, + IN CHAR8 *Language, + OUT CHAR16 **DriverVersion + ); + +struct _GOP_COMPONENT_NAME2_PROTOCOL { + GOP_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName; + GOP_COMPONENT_NAME2_GET_DRIVER_VERSION GetDriverVersion; + GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName; + CHAR8 *SupportedLanguages; +}; + +extern EFI_GUID gGopComponentName2ProtocolGuid; + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/IgdOpRegion/IgdOpRegion.c b/ReferenceCode/Chipset/SystemAgent/Protocol/IgdOpRegion/IgdOpRegion.c new file mode 100644 index 0000000..596c9f5 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/IgdOpRegion/IgdOpRegion.c @@ -0,0 +1,35 @@ +/** @file + This file is part of the IGD OpRegion Implementation. The IGD OpRegion is + an interface between system BIOS, ASL code, and Graphics drivers. The code + in this file will implement a protocol allowing access to the + OpRegion from ASL code. + + Supporting Specifiction: IGD OpRegion/Software SCI BIOS SPEC + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#include "Tiano.h" +#include "IgdOpRegion.h" + +EFI_GUID gIgdOpRegionProtocolGuid = IGD_OPREGION_PROTOCOL_GUID; + +EFI_GUID_STRING + ( + &gIgdOpRegionProtocolGuid, "IGD OpRegion/Software SCI", + "Communication interface between Graphics drivers, ASL code, and system BIOS" + ); diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/IgdOpRegion/IgdOpRegion.h b/ReferenceCode/Chipset/SystemAgent/Protocol/IgdOpRegion/IgdOpRegion.h new file mode 100644 index 0000000..c0b5c06 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/IgdOpRegion/IgdOpRegion.h @@ -0,0 +1,210 @@ +/** @file + This file is part of the IGD OpRegion Implementation. The IGD OpRegion is + an interface between system BIOS, ASL code, and Graphics drivers. + + Supporting Specifiction: IGD OpRegion/Software SCI SPEC + + Note: Data structures defined in this protocol are packed not naturally + aligned. + + GUID forms: + {CDC5DDDF-E79D-41ec-A9B0-6565490DB9D3} + (0xcdc5dddf, 0xe79d, 0x41ec, 0xa9, 0xb0, 0x65, 0x65, 0x49, 0xd, 0xb9, 0xd3); + + Acronyms: + NVS: ACPI Non Volatile Storage + OpRegion: ACPI Operational Region + VBT: Video BIOS Table (OEM customizable data) + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _IGD_OPREGION_PROTOCOL_H_ +#define _IGD_OPREGION_PROTOCOL_H_ + +/// +/// Include files +/// +#include "Tiano.h" + +/// +/// IGD OpRegion protocol GUID +/// +#define IGD_OPREGION_PROTOCOL_GUID \ + { \ + 0xcdc5dddf, 0xe79d, 0x41ec, 0xa9, 0xb0, 0x65, 0x65, 0x49, 0xd, 0xb9, 0xd3 \ + } + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gIgdOpRegionProtocolGuid; + +/// +/// Forward reference for pure ANSI compatability +/// +EFI_FORWARD_DECLARATION (IGD_OPREGION_PROTOCOL); + +// +// Protocol data definitions +// +/// +/// OpRegion structures: +/// Sub-structures define the different parts of the OpRegion followed by the +/// main structure representing the entire OpRegion. +/// +/// Note: These structures are packed to 1 byte offsets because the exact +/// data location is requred by the supporting design specification due to +/// the fact that the data is used by ASL and Graphics driver code compiled +/// separatly. +/// +/// +/// OpRegion header (mailbox 0) structure and #defines. +/// +#pragma pack(1) +typedef struct { + CHAR8 SIGN[0x10]; ///< 0 OpRegion signature + UINT32 SIZE; ///< 16 OpRegion size + UINT32 OVER; ///< 20 OpRegion structure version + UINT8 SVER[0x20]; ///< 24 System BIOS build version + UINT8 VVER[0x10]; ///< 56 Video BIOS build version + UINT8 GVER[0x10]; ///< 72 Graphic driver build version + UINT32 MBOX; ///< 88 Mailboxes supported + UINT32 DMOD; ///< 92 Driver Model + UINT32 PCON; ///< 96 Platform Capabilities + CHAR16 DVER[0x10]; ///< 100 GOP Version + UINT8 RHD1[0x7C]; ///< 132 Reserved +} OPREGION_HEADER; +#pragma pack() +/// +/// OpRegion mailbox 1 (public ACPI Methods). +/// +#pragma pack(1) +typedef struct { + UINT32 DRDY; ///< 0 Driver readiness + UINT32 CSTS; ///< 4 Status + UINT32 CEVT; ///< 8 Current event + UINT8 RM11[0x14]; ///< 12 Reserved + UINT32 DIDL; ///< 32 Supported display devices list + UINT32 DDL2; ///< 8 Devices. + UINT32 DDL3; + UINT32 DDL4; + UINT32 DDL5; + UINT32 DDL6; + UINT32 DDL7; + UINT32 DDL8; + UINT32 CPDL; ///< 64 Currently present display devices list + UINT32 CPL2; ///< 8 Devices. + UINT32 CPL3; + UINT32 CPL4; + UINT32 CPL5; + UINT32 CPL6; + UINT32 CPL7; + UINT32 CPL8; + UINT32 CADL; ///< 96 Currently active display devices list + UINT32 CAL2; ///< 8 Devices. + UINT32 CAL3; + UINT32 CAL4; + UINT32 CAL5; + UINT32 CAL6; + UINT32 CAL7; + UINT32 CAL8; + UINT32 NADL; ///< 128 Next active device list + UINT32 NDL2; ///< 8 Devices. + UINT32 NDL3; + UINT32 NDL4; + UINT32 NDL5; + UINT32 NDL6; + UINT32 NDL7; + UINT32 NDL8; + UINT32 ASLP; ///< 160 ASL sleep timeout + UINT32 TIDX; ///< 164 Toggle table index + UINT32 CHPD; ///< 168 Current hot plug enable indicator + UINT32 CLID; ///< 172 Current lid state indicator + UINT32 CDCK; ///< 176 Current docking state indicator + UINT32 SXSW; ///< 180 Display Switch notification on Sx State resume + UINT32 EVTS; ///< 184 Events supported by ASL + UINT32 CNOT; ///< 188 Current OS Notification + UINT32 NRDY; ///< 192 Reasons for DRDY = 0 + UINT8 RM12[0x3C]; ///< 196 Reserved +} OPREGION_MBOX1; +#pragma pack() +/// +/// OpRegion mailbox 2 (Software SCI Interface). +/// +#pragma pack(1) +typedef struct { + UINT32 SCIC; ///< 0 Software SCI function number parameters + UINT32 PARM; ///< 4 Software SCI additional parameters + UINT32 DSLP; ///< 8 Driver sleep timeout + UINT8 RM21[0xF4]; ///< 12 Reserved +} OPREGION_MBOX2; +#pragma pack() +/// +/// OpRegion mailbox 3 (Power Conservation). +/// +#pragma pack(1) +typedef struct { + UINT32 ARDY; ///< 0 Driver readiness + UINT32 ASLC; ///< 4 ASLE interrupt command / status + UINT32 TCHE; ///< 8 Technology enabled indicator + UINT32 ALSI; ///< 12 Current ALS illuminance reading + UINT32 BCLP; ///< 16 Backlight britness to set + UINT32 PFIT; ///< 20 Panel fitting Request + UINT32 CBLV; ///< 24 Brightness Current State + UINT16 BCLM[0x14]; ///< 28 Backlight Brightness Level Duty Cycle Mapping Table + UINT32 CPFM; ///< 68 Panel Fitting Current Mode + UINT32 EPFM; ///< 72 Enabled Panel Fitting Modes + UINT8 PLUT[0x4A]; ///< 76 Panel Look Up Table + UINT32 PFMB; ///< 150 PWM Frequency and Minimum Brightness + UINT32 CCDV; ///< 154 Color Correction Default Values + UINT32 PCFT; ///< 158 Power Conservation Features + UINT32 SROT; ///< 162 Supported Rotation angle + UINT32 IUER; ///< 166 Intel Ultrabook Event Register + UINT64 FDSP; ///< 170 FFS Display Physical address + UINT32 FDSS; ///< 178 FFS Display Size + UINT8 RM32[0x4A]; ///< 182 Reserved +} OPREGION_MBOX3; +#pragma pack() +/// +/// OpRegion mailbox 4 (VBT). +/// +#pragma pack(1) +typedef struct { + UINT8 GVD1[0x1C00]; ///< Reserved +} OPREGION_VBT; +#pragma pack() +/// +/// Entire OpRegion +/// +#pragma pack(1) +typedef struct { + OPREGION_HEADER Header; ///< OpRegion header + OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods + OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Inteface + OPREGION_MBOX3 MBox3; ///< Mailbox 3: Power Conservation + OPREGION_VBT VBT; ///< VBT: Video BIOS Table (OEM customizable data) +} IGD_OPREGION_STRUC; +#pragma pack() +/// +/// Protocol data structure definition +/// +struct _IGD_OPREGION_PROTOCOL { + IGD_OPREGION_STRUC *OpRegion; +}; + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/IntelSaProtocolLib.inf b/ReferenceCode/Chipset/SystemAgent/Protocol/IntelSaProtocolLib.inf new file mode 100644 index 0000000..594e48b --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/IntelSaProtocolLib.inf @@ -0,0 +1,59 @@ +## @file +# Component description file for the SA protocol library +# +#@copyright +# Copyright (c) 2010 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + + +[defines] +BASE_NAME = IntelSaProtocolLib +COMPONENT_TYPE = LIBRARY + +[sources.common] + MemInfo/MemInfo.h + MemInfo/MemInfo.c + IgdOpRegion/IgdOpRegion.h + IgdOpRegion/IgdOpRegion.c + SaPlatformPolicy/SaPlatformPolicy.h + SaPlatformPolicy/SaPlatformPolicy.c + SaInfo/SaInfo.h + SaInfo/SaInfo.c + BdatAccess/BdatAccess.h + BdatAccess/BdatAccess.c + SaGlobalNvsArea/SaGlobalNvsArea.c + SaGlobalNvsArea/SaGlobalNvsArea.h + PlatformGopPolicy/PlatformGopPolicy.h + PlatformGopPolicy/PlatformGopPolicy.c + GopComponentName2/GopComponentName2.h + GopComponentName2/GopComponentName2.c + +[includes.common] + . + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(EFI_SOURCE)/$(PROJECT_SA_ROOT) + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include + +[nmake.common] +C_STD_INCLUDE= diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/MemInfo/MemInfo.c b/ReferenceCode/Chipset/SystemAgent/Protocol/MemInfo/MemInfo.c new file mode 100644 index 0000000..09e400c --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/MemInfo/MemInfo.c @@ -0,0 +1,33 @@ +/** @file + This file defines global GUID variables for the MemInfo Protocol + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#include "Tiano.h" +#include "MemInfo.h" + +/// +/// Protocol GUID definition +/// +EFI_GUID gMemInfoProtocolGuid = MEM_INFO_PROTOCOL_GUID; + +/// +/// Protocol description +/// +EFI_GUID_STRING + (&gMemInfoProtocolGuid, "Memory Information Protocol", "The MemInfo Protocol returns memory information Data."); diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/MemInfo/MemInfo.h b/ReferenceCode/Chipset/SystemAgent/Protocol/MemInfo/MemInfo.h new file mode 100644 index 0000000..6f0c662 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/MemInfo/MemInfo.h @@ -0,0 +1,99 @@ +/** @file + This protocol provides the memory information data, such as + total physical memory size, memory frequency, memory size + of each dimm and rank. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _MEM_INFO_PROTOCOL_H_ +#define _MEM_INFO_PROTOCOL_H_ + +/// +/// Define the protocol GUID +/// +#define MEM_INFO_PROTOCOL_GUID \ + { \ + 0x6f20f7c8, 0xe5ef, 0x4f21, 0x8d, 0x19, 0xed, 0xc5, 0xf0, 0xc4, 0x96, 0xae \ + } + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gMemInfoProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _MEM_INFO_PROTOCOL MEM_INFO_PROTOCOL; + +// +// Protocol definitions +// +#define NODE_NUM 1 +#define CH_NUM 2 +#define DIMM_NUM 2 +#define RANK_NUM 2 +#define PROFILE_NUM 4 // number of memory profiles supported + +#pragma pack(1) +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRC; ///< Number of tCK cycles for the channel DIMM's minimum active to active/refresh delay time. + UINT16 tRCD; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRP; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. +} MEMORY_TIMING; + +typedef struct { + UINT32 memSize; ///< Total physical memory size + UINT16 ddrFreq; ///< DDR Frequency + UINT16 ddrFreqMax; + UINT8 RefClk; + UINT8 Ratio; + BOOLEAN EccSupport; ///< ECC Support + UINT16 dimmSize[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Dimm Size + BOOLEAN DimmExist[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Dimm Present or not + UINT8 RankInDimm[NODE_NUM * CH_NUM * DIMM_NUM]; ///< No. of ranks in a dimm + UINT8 Reserved[24]; + UINT8 *DimmsSpdData[NODE_NUM * CH_NUM * DIMM_NUM]; + UINT16 VddVoltage[PROFILE_NUM]; + MEMORY_TIMING Timing[PROFILE_NUM]; + UINT8 Profile; ///< Currently running memory profile + UINT8 XmpProfileEnable; ///< 0 = no XMP DIMMs in system +} MEMORY_INFO_DATA; +#pragma pack() + +/// +/// Protocol definition +/// +struct _MEM_INFO_PROTOCOL { + MEMORY_INFO_DATA MemInfoData; +}; + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/PlatformGopPolicy/PlatformGopPolicy.c b/ReferenceCode/Chipset/SystemAgent/Protocol/PlatformGopPolicy/PlatformGopPolicy.c new file mode 100644 index 0000000..7fa5b6f --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/PlatformGopPolicy/PlatformGopPolicy.c @@ -0,0 +1,36 @@ +/** @file + Interface definition for PlatformGopPolicy Protocol. + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#include "Tiano.h" + +/// +/// Include the protocol header file +/// +#include "PlatformGopPolicy.h" + +/// +/// Protocol GUID definition +/// +EFI_GUID gPlatformGopPolicyProtocolGuid = EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID; + +/// +/// Protocol description +/// +EFI_GUID_STRING(&gPlatformGopPolicyProtocolGuid, "PlatformGopPolicy Protocol", "Intel(R) GOP Platform Policy Protocol"); diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/PlatformGopPolicy/PlatformGopPolicy.h b/ReferenceCode/Chipset/SystemAgent/Protocol/PlatformGopPolicy/PlatformGopPolicy.h new file mode 100644 index 0000000..d6c493b --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/PlatformGopPolicy/PlatformGopPolicy.h @@ -0,0 +1,58 @@ +/** @file + Interface definition for PlatformGopPolicy Protocol. + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PLATFORM_GOP_POLICY_PROTOCOL_H_ +#define _PLATFORM_GOP_POLICY_PROTOCOL_H_ + +#define EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID \ + { \ + 0xec2e931b, 0x3281, 0x48a5, 0x81, 0x7, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d \ + } + +#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_01 0x01 + +typedef enum { + LidClosed, + LidOpen, + LidStatusMax +} LID_STATUS; + +typedef +EFI_STATUS +(EFIAPI *GET_PLATFORM_LID_STATUS) ( + OUT LID_STATUS * CurrentLidStatus + ); + +typedef +EFI_STATUS +(EFIAPI *GET_VBT_DATA) ( + OUT EFI_PHYSICAL_ADDRESS * VbtAddress, + OUT UINT32 *VbtSize + ); + +typedef struct _PLATFORM_GOP_POLICY_PROTOCOL { + UINT32 Revision; + GET_PLATFORM_LID_STATUS GetPlatformLidStatus; + GET_VBT_DATA GetVbtData; +} PLATFORM_GOP_POLICY_PROTOCOL; + +extern EFI_GUID gPlatformGopPolicyProtocolGuid; + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaGlobalNvsArea/SaGlobalNvsArea.c b/ReferenceCode/Chipset/SystemAgent/Protocol/SaGlobalNvsArea/SaGlobalNvsArea.c new file mode 100644 index 0000000..2f0725d --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaGlobalNvsArea/SaGlobalNvsArea.c @@ -0,0 +1,31 @@ +/** @file + System Agent Global NVS Area description protocol implementation. + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Mobile Silicon Support Module" and is + licensed for Intel Mobile CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#include "EdkIIGlueDxe.h" + +#include "SaGlobalNvsArea.h" + +EFI_GUID gSaGlobalNvsAreaProtocolGuid = SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL_GUID; + +EFI_GUID_STRING + ( + &gSaGlobalNvsAreaProtocolGuid, "System Agent Global NVS Area Protocol", + "Protocol describing System Agent ACPI NVS memory region used by ACPI subsystem." + ); diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaGlobalNvsArea/SaGlobalNvsArea.h b/ReferenceCode/Chipset/SystemAgent/Protocol/SaGlobalNvsArea/SaGlobalNvsArea.h new file mode 100644 index 0000000..bc38e5e --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaGlobalNvsArea/SaGlobalNvsArea.h @@ -0,0 +1,197 @@ +/** @file + Definition of the System Agent global NVS area protocol. This protocol + publishes the address and format of a global ACPI NVS buffer used as a communications + buffer between SMM/DXE/PEI code and ASL code. + @todo The format is derived from the ACPI reference code, version 0.95. + + Note: Data structures defined in this protocol are not naturally aligned. + +@copyright + Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _SYSTEM_AGENT_GLOBAL_NVS_AREA_H_ +#define _SYSTEM_AGENT_GLOBAL_NVS_AREA_H_ + +/// +/// Includes +/// +/// +/// Forward reference for pure ANSI compatability +/// +EFI_FORWARD_DECLARATION (SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL); + +/// +/// SA Global NVS Area Protocol GUID +/// +#define SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL_GUID \ + { \ + 0x5bd3336f, 0x5406, 0x48a0, 0xb8, 0x58, 0xd5, 0x0f, 0x72, 0x1c, 0x83, 0x57 \ + } + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gSaGlobalNvsAreaProtocolGuid; + +/// +/// Global NVS Area definition +/// +#pragma pack(1) +typedef struct { + UINT32 SaRcRevision; ///< 000 SA RC Revision + /// + /// IGFX relevant fields + /// + UINT32 IgdOpRegionAddress; ///< 004 IGD OpRegion Starting Address + UINT8 GfxTurboIMON; ///< 008 IMON Current Value + UINT8 IgdState; ///< 009 IGD State (Primary Display = 1) + UINT8 CurrentDeviceList; ///< 010 Current Attached Device List + UINT8 PreviousDeviceList; ///< 011 Previous Attached Device List + UINT16 CurrentDisplayState; ///< 012 Current Display State + UINT16 NextDisplayState; ///< 014 Next Display State + UINT32 DeviceId9; ///< 016 Device ID 9 + UINT32 DeviceId10; ///< 020 Device ID 10 + UINT32 DeviceId11; ///< 024 Device ID 11 + UINT8 IgdBootType; ///< 028 IGD Boot Type CMOS option + UINT8 IgdPanelType; ///< 029 IGD Panel Type CMOs option + UINT8 IgdPanelScaling; ///< 030 IGD Panel Scaling + UINT8 IgdBlcConfig; ///< 031 IGD BLC Configuration + UINT8 IgdBiaConfig; ///< 032 IGD BIA Configuration + UINT8 IgdSscConfig; ///< 033 IGD SSC Configuration + UINT8 IgdPowerConservation; ///< 034 IGD Power Conservation Feature Flag + UINT8 IgdDvmtMemSize; ///< 035 IGD DVMT Memory Size + UINT8 IgdFunc1Enable; ///< 036 IGD Function 1 Enable + UINT8 IgdHpllVco; ///< 037 HPLL VCO + UINT32 NextStateDid1; ///< 038 Next state DID1 for _DGS + UINT32 NextStateDid2; ///< 042 Next state DID2 for _DGS + UINT32 NextStateDid3; ///< 046 Next state DID3 for _DGS + UINT32 NextStateDid4; ///< 050 Next state DID4 for _DGS + UINT32 NextStateDid5; ///< 054 Next state DID5 for _DGS + UINT32 NextStateDid6; ///< 058 Next state DID6 for _DGS + UINT32 NextStateDid7; ///< 062 Next state DID7 for _DGS + UINT32 NextStateDid8; ///< 066 Next state DID8 for _DGS + UINT8 IgdSciSmiMode; ///< 070 GMCH SMI/SCI mode (0=SCI) + UINT8 IgdPAVP; ///< 071 IGD PAVP data + UINT8 LidState; ///< 072 Open = 1 + UINT32 AKsv0; ///< 073 First four bytes of AKSV (manufacturing mode) + UINT8 AKsv1; ///< 077 Fifth byte of AKSV (manufacturing mode) + UINT32 IgfxD3F0BarBaseAddress; ///< 078 IGFX Audio D3F0 BAR Base Address + /// + /// Backlight Control Values + /// + UINT8 BacklightControlSupport; ///< 082 Backlight Control Support + UINT8 BrightnessPercentage; ///< 083 Brightness Level Percentage + /// + /// Ambient Light Sensor Values + /// + UINT8 AlsEnable; ///< 084 Ambient Light Sensor Enable + UINT8 AlsAdjustmentFactor; ///< 085 Ambient Light Adjusment Factor + UINT8 LuxLowValue; ///< 086 LUX Low Value + UINT8 LuxHighValue; ///< 087 LUX High Value + UINT8 ActiveLFP; ///< 088 Active LFP + UINT32 AudioWaA; ///< 089 Audio MMIO WA 1 + UINT32 AudioWaB; ///< 093 Audio MMIO WA 2 + UINT32 AudioWaC; ///< 097 Audio MMIO WA 3 + UINT32 DeviceId12; ///< 101 Device ID 12 + UINT32 DeviceId13; ///< 105 Device ID 13 + UINT32 DeviceId14; ///< 109 Device ID 14 + UINT32 DeviceId15; ///< 113 Device ID 15 + UINT32 AudioCodecSaveAddress; ///< 117 Codec Save Address + UINT32 AudioCodecSaveCount; ///< 121 Codec Save Count + /// + /// Add any IGFX relevant fields here and reduce reserved bytes + /// + UINT8 ReservedIgd[75]; ///< 125:199 + + /// + /// Switchable Graphics Info + /// + UINT8 SgMode; ///< 200 SG Mode (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=DGPU Only) + UINT8 SgFeatureList; ///< 201 SG Feature list + UINT8 SgDgpuPwrOK; ///< 202 dGPU PWROK GPIO assigned + UINT8 SgDgpuHoldRst; ///< 203 dGPU HLD RST GPIO assigned + UINT8 SgDgpuPwrEnable; ///< 204 dGPU PWR Enable GPIO assigned + UINT8 SgDgpuPrsnt; ///< 205 dGPU Present Detect GPIO assigned + UINT32 CapStrPresence; ///< 206 PEG Endpoint Capability Structure Presence + UINT8 EndpointPcieCapOffset; ///< 210 PEG Endpoint PCIe Capability Structure Offset + UINT16 EndpointVcCapOffset; ///< 211 PEG Endpoint Virtual Channel Capability Structure Offset + UINT32 XPcieCfgBaseAddress; ///< 213 Any Device's PCIe Config Space Base Address + UINT16 GpioBaseAddress; ///< 217 GPIO Base Address + UINT8 SgGPIOSupport; ///< 219 SG GPIO + UINT32 NvIgOpRegionAddress; ///< 220 NVIG support + UINT32 NvHmOpRegionAddress; ///< 224 NVHM support + UINT32 ApXmOpRegionAddress; ///< 228 AMDA support + UINT8 NumberOfValidDeviceId; ///< 232 Number of Valid Device IDs + UINT32 DeviceId1; ///< 233 Device ID 1 + UINT32 DeviceId2; ///< 237 Device ID 2 + UINT32 DeviceId3; ///< 241 Device ID 3 + UINT32 DeviceId4; ///< 245 Device ID 4 + UINT32 DeviceId5; ///< 249 Device ID 5 + UINT32 DeviceId6; ///< 253 Device ID 6 + UINT32 DeviceId7; ///< 257 Device ID 7 + UINT32 DeviceId8; ///< 261 Device ID 8 + UINT32 OccupiedBuses1; ///< 265 Occupied Buses from 0 to 31 + UINT32 OccupiedBuses2; ///< 269 Occupied Buses from 32 to 63 + UINT32 OccupiedBuses3; ///< 273 Occupied Buses from 64 to 95 + UINT32 OccupiedBuses4; ///< 277 Occupied Buses from 96 to 127 + UINT32 OccupiedBuses5; ///< 281 Occupied Buses from 128 to 159 + UINT32 OccupiedBuses6; ///< 285 Occupied Buses from 160 to 191 + UINT32 OccupiedBuses7; ///< 289 Occupied Buses from 192 to 223 + UINT32 OccupiedBuses8; ///< 293 Occupied Buses from 224 to 255 + UINT8 Peg0LtrEnable; ///< 297 Latency Tolerance Reporting Control for PEG(0:1:0) + UINT8 Peg0ObffEnable; ///< 298 Optimized Buffer Flush and Fill for PEG(0:1:0) + UINT8 Peg1LtrEnable; ///< 299 Latency Tolerance Reporting Control for PEG(0:1:1) + UINT8 Peg1ObffEnable; ///< 300 Optimized Buffer Flush and Fill for PEG(0:1:1) + UINT8 Peg2LtrEnable; ///< 301 Latency Tolerance Reporting Control for PEG(0:1:2) + UINT8 Peg2ObffEnable; ///< 302 Optimized Buffer Flush and Fill for PEG(0:1:2) + UINT16 PegLtrMaxSnoopLatency; ///< 303 SA Peg Latency Tolerance Reporting Control + UINT16 PegLtrMaxNoSnoopLatency; ///< 305 SA Peg Latency Tolerance Reporting Control + UINT8 Peg0PowerDownUnusedBundles; ///< 307 Peg0 Unused Bundle Control + UINT8 Peg1PowerDownUnusedBundles; ///< 308 Peg1 Unused Bundle Control + UINT8 Peg2PowerDownUnusedBundles; ///< 309 Peg2 Unused Bundle Control + UINT8 EdpValid; ///< 310 Check for eDP display device + UINT32 NextStateDidEdp; ///< 311 Next state DID for eDP + UINT32 DeviceIdX; ///< 315 Device ID for eDP device + UINT8 PackageCstateLimit; ///< 319 The lowest C-state for the package + UINT8 C7Allowed; ///< 316 Run-time C7 Allowed feature (0=Disabled, 1=Enabled) + // + // Add any other HG Board Info or anything else here + // +// AMI_OVERRIDE... + UINT8 SgDgpuDisplaySel; ///< 319 dGPU Display Select GPIO assigned + UINT8 SgDgpuEdidSel; ///< 320 dGPU EDID Select GPIO assigned + UINT8 SgDgpuPwmSel; ///< 321 dGPU PWM Select GPIO assigned + UINT32 SgMuxDid1; ///< 322 DID1 Mux Setting + UINT32 SgMuxDid2; ///< 326 DID2 Mux Setting + UINT32 SgMuxDid3; ///< 330 DID3 Mux Setting + UINT32 SgMuxDid4; ///< 334 DID4 Mux Setting + UINT32 SgMuxDid5; ///< 338 DID5 Mux Setting + UINT32 SgMuxDid6; ///< 342 DID6 Mux Setting + UINT32 SgMuxDid7; ///< 346 DID7 Mux Setting + UINT32 SgMuxDid8; ///< 350 DID8 Mux Setting + UINT8 PXFixedDynamicMode; ///< 354 ATI 5.0 Fixed/Dynamic ATI 5.0 Fixed/Dynamic + UINT32 EndpointBaseAddress; ///< 355 Endpoint PCIe Base Address + UINT32 DgpuSsid; ///< 359 dGPU SSID for MSHyBrid restore +// AMI_OVERRIDE...end +} SYSTEM_AGENT_GLOBAL_NVS_AREA; +#pragma pack() +/// +/// System Agent Global NVS Area Protocol +/// +typedef struct _SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL { + SYSTEM_AGENT_GLOBAL_NVS_AREA *Area; +} SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL; + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaInfo/SaInfo.c b/ReferenceCode/Chipset/SystemAgent/Protocol/SaInfo/SaInfo.c new file mode 100644 index 0000000..4ca46f3 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaInfo/SaInfo.c @@ -0,0 +1,41 @@ +/** @file + This file defines the Sa Info Protocol. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +/// +/// Statements that include other files +/// +/// +/// External include files do NOT need to be explicitly specified in real EDKII +/// environment +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#endif + +#include "SaInfo.h" + +/// +/// Protocol GUID definition +/// +EFI_GUID gEfiSaInfoProtocolGuid = EFI_SA_INFO_PROTOCOL_GUID; + +/// +/// Protocol description +/// +EFI_GUID_STRING(&gEfiSaInfoProtocolGuid, "Sa Info Protocol", "Sa Information Protocol"); diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaInfo/SaInfo.h b/ReferenceCode/Chipset/SystemAgent/Protocol/SaInfo/SaInfo.h new file mode 100644 index 0000000..7469119 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaInfo/SaInfo.h @@ -0,0 +1,70 @@ +/** @file + This file defines the SA Info Protocol. + +@copyright + Copyright (c) 2011 - 2014 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _SA_INFO_H_ +#define _SA_INFO_H_ + +/// +/// Define SA INFO protocol GUID +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define EFI_SA_INFO_PROTOCOL_GUID \ + { \ + 0x493b5bac, 0xbb9e, 0x4bf5, 0x83, 0x79, 0x20, 0xe2, 0xac, 0xa9, 0x85, 0x41 \ + } + +#else +#define EFI_SA_INFO_PROTOCOL_GUID \ + { \ + 0x493b5bac, 0xbb9e, 0x4bf5, \ + { \ + 0x83, 0x79, 0x20, 0xe2, 0xac, 0xa9, 0x85, 0x41 \ + } \ + } +#endif +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gEfiSaInfoProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_SA_INFO_PROTOCOL EFI_SA_INFO_PROTOCOL; + +/// +/// Protocol revision number +/// Any backwards compatible changes to this protocol will result in an update in the revision number +/// Major changes will require publication of a new protocol +/// +/// Revision 1: Original version +/// +#define SA_INFO_PROTOCOL_REVISION_1 1 +#define SA_RC_VERSION 0x01090000 + +/// +/// Protocol definition +/// +struct _EFI_SA_INFO_PROTOCOL { + UINT8 Revision; + UINT32 RCVersion; +}; + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaPlatformPolicy/SaPlatformPolicy.c b/ReferenceCode/Chipset/SystemAgent/Protocol/SaPlatformPolicy/SaPlatformPolicy.c new file mode 100644 index 0000000..b843e48 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaPlatformPolicy/SaPlatformPolicy.c @@ -0,0 +1,37 @@ +/** @file + Interface definition details between SystemAgent and platform drivers during DXE phase. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#include "Tiano.h" + +/// +/// Include the protocol header file +/// +#include "SaPlatformPolicy.h" + +/// +/// Protocol GUID definition +/// +EFI_GUID gDxePlatformSaPolicyGuid = DXE_PLATFORM_SA_POLICY_GUID; + +/// +/// Protocol description +/// +EFI_GUID_STRING + (&gDxePlatformSaPolicyGuid, "SaPlatformPolicy Protocol", "Intel(R) DXE Phase SA Platform Policy Protocol"); diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaPlatformPolicy/SaPlatformPolicy.h b/ReferenceCode/Chipset/SystemAgent/Protocol/SaPlatformPolicy/SaPlatformPolicy.h new file mode 100644 index 0000000..5b6793f --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaPlatformPolicy/SaPlatformPolicy.h @@ -0,0 +1,366 @@ +/** @file + Interface definition details between System Agent and platform drivers during DXE phase. + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + +**/ +#ifndef _SA_PLATFORM_POLICY_H_ +#define _SA_PLATFORM_POLICY_H_ + +#include "SaAccess.h" + +/// +/// SA Policy provided by platform for DXE phase {912A2913-42A8-45b0-822F-A94D1EAE9965} +/// +#define DXE_PLATFORM_SA_POLICY_GUID \ + { \ + 0x912a2913, 0x42a8, 0x45b0, 0x82, 0x2f, 0xa9, 0x4d, 0x1e, 0xae, 0x99, 0x65 \ + } + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gDxePlatformSaPolicyGuid; + +/// +/// Protocol revision number +/// Any backwards compatible changes to this protocol will result in an update in the revision number +/// Major changes will require publication of a new protocol +/// +/// Don't change the original DXE_MCH_PLATFORM_POLICY_PROTOCOL_REVISION macro, external +/// modules maybe have consumed this macro in their source code. Directly +/// update the DXE_MCH_PLATFORM_POLICY_PROTOCOL_REVISION version number may cause those +/// external modules to auto mark themselves wrong version info. +/// Always create new version macro for new PlatformMchPolicy protocol interface. +/// +/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION +/// First version +/// +#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION 1 +/// +/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_2 +/// Moved PcieDevsOverride to SampleCode as part of SA_PCIE_CONFIGURATION structure +/// Added SA_PCIE_CONFIGURATION.PcieLtrDevsOverride +/// +#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_2 2 +/// +/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_3 +/// Added DXE_PLATFORM_SA_POLICY_PROTOCOL.VbiosConfig +/// SA_IGD_CONFIGURATION.VbtAddress +/// SA_IGD_CONFIGURATION.Size +/// +#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_3 3 +/// +/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_4 +/// Added SA_IGD_CONFIGURATION.CdClk +/// SA_IGD_CONFIGURATION.CdClkVar +/// +#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_4 4 +/// +/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_5 +/// Added SA_IGD_CONFIGURATION.PlatformConfig +/// +#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_5 5 +/// +/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_6 +/// Added SA_IGD_CONFIGURATION.IuerStatusVal +/// Added SA_MISC_CONFIGURATION.SaHdaVerbTableNum +/// SA_MISC_CONFIGURATION.*SaHdaVerbTable +/// +#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_6 6 +/// +/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_7 +/// Added SA_IGD_CONFIGURATION.GopVersion +/// Added SA_PCIE_CONFIGURATION.PegPwrOpt[SA_PEG_MAX_FUN] +/// +#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_7 7 +/// +/// DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_8 +/// Added SA_PCIE_CONFIGURATION.C7Allowed +/// +#define DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_8 8 + +#define SA_VTD_ENGINE_NUMBER 2 +#define SA_PCIE_DEV_END_OF_TABLE 0xFFFF +/// +/// The data elements should be initialized by a Platform Module. The data structure is for +/// VT-d driver initialization +/// +typedef struct { + BOOLEAN VtdEnable; ///< This field is used to describe whether or not the VT-d function should be enabled + EFI_PHYSICAL_ADDRESS *RmrrUsbBaseAddress; ///< The field is used to describe the platform USB Reserved memory for Intel VT-d support. Platform code should provide this information for Intel VT-d DXE driver use + UINT32 BaseAddress[SA_VTD_ENGINE_NUMBER]; ///< This field is used to describe the base addresses for VT-d function +} SA_VTD_CONFIGURATION; + +/// +/// The Memory Configuration includes DIMM SPD address Map and DIMM Slot Mechanical present bit map. +/// +/// The data elements should be initialized by a Platform Module. Refer to +/// $(PROJECT_SA_ROOT)\SmbiosMemory\Dxe\SmbiosMemory.c for the usage. +/// +typedef struct { +/** + Dimm SPD address + Only Server support 2 channels * 3 slots per channel = 6 sockets totally + The Desktop and mobile only support 2 channels * 2 slots per channel = 4 sockets totally + So there is mapping rule here for Desktop and mobile that there are no more 4 DIMMS totally in a system: + Channel A/ Slot 0 --> Dimm 0 --> SpdAddressTable[0] + Channel A/ Slot 1 --> Dimm 1 --> SpdAddressTable[1] + Channel B/ Slot 0 --> Dimm 2 --> SpdAddressTable[2] + Channel B/ Slot 1 --> Dimm 3 --> SpdAddressTable[3] + Refer to $(PROJECT_SA_ROOT)\SmbiosMemory\Dxe\SmbiosMemory.c for use + If change the mapping rule, please update the Revision number. +**/ + UINT8 *SpdAddressTable; +/** + Channel A DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -> DIMM1, ... + if the bit is 1, the related DIMM slot is present. + E.g. if channel A has 2 DIMMs, ChannelASlotMap = 0x03; + E.g. if channel A has only 1 DIMMs, ChannelASlotMap = 0x01; + Refer to $(PROJECT_SA_ROOT)\SmbiosMemory\Dxe\SmbiosMemory.c +**/ + UINT8 ChannelASlotMap; +/** + Channel B DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -> DIMM1, ... + if the bit is 1, the related DIMM slot is present. + E.g. if channel B has 2 DIMMs, ChannelBSlotMap = 0x03; + E.g. if channel B has only 1 DIMMs, ChannelBSlotMap = 0x01; + Refer to $(PROJECT_SA_ROOT)\SmbiosMemory\Dxe\SmbiosMemory.c +**/ + UINT8 ChannelBSlotMap; + UINT8 RmtBdatEnable; ///< This flag is used by the MRC for DDR3 channel training (default is false). Please refer to the MRC documentation for more details + UINT8 MrcTimeMeasure; ///< Time measure + UINT8 MrcFastBoot; ///< Fast boot +} SA_MEMORY_CONFIGURATION; + +/// +/// The value before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature +/// +typedef enum { + PcieAspmDisabled, + PcieAspmL0s, + PcieAspmL1, + PcieAspmL0sL1, + PcieAspmAutoConfig, + PcieAspmMax +} SA_PCIE_ASPM_CONFIG; + +/// +/// Device List Structure +/// +typedef struct { + UINT16 VendorId; ///< PCI Configuration space offset 0 + UINT16 DeviceId; ///< PCI Configuration space offset 2 + UINT8 RevId; ///< PCI Configuration space offset 8; 0xFF means all steppings + UINT8 RootApmcMask; + UINT8 EndpointApmcMask; +} PCIE_ASPM_DEV_INFO; + +typedef struct { + UINT16 VendorId; ///< PCI Config space offset 0 + UINT16 DeviceId; ///< PCI Config space offset 2 + UINT8 RevId; ///< PCI Config space offset 8; 0xFF means all steppings +/** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BIT[14] - Should be set to 0b + BIT[13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 +**/ + UINT16 SnoopLatency; +/** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BIT[14] - Should be set to 0b + BIT[13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 +**/ + UINT16 NonSnoopLatency; +} PCIE_LTR_DEV_INFO; + +/// +/// PCIE Power Optimizer config +/// +typedef struct { + UINT8 LtrEnable; + UINT16 LtrMaxSnoopLatency; + UINT16 LtrMaxNoSnoopLatency; + UINT8 ObffEnable; +} SA_PCIE_PWR_OPT; + + +/// +/// The PCI Express Configuration info includes PCI Resources Range Base and Limits and the control +/// for PEG ASPM. +/// +/// The data elements should be initialized by a Platform Module. For the data structure for PCI IO +/// and PCI Memory address range info refer to $(PROJECT_SA_ROOT)\PciHostBridge\Dxe\PciHostBridge.c +/// for the usage. +/// +typedef struct { + SA_PCIE_ASPM_CONFIG DmiAspm; ///< This field is used to describe the ASPM control for DMI + SA_PCIE_ASPM_CONFIG PegAspm[SA_PEG_MAX_FUN]; ///< This field is used to describe the ASPM control for PEG Ports + UINT8 PegAspmL0s[SA_PEG_MAX_FUN]; ///< This field is used to describe the PEG L0s advanced control + UINT8 PegDeEmphasis[SA_PEG_MAX_FUN]; ///< This field is used to describe the DeEmphasis control for PEG (-6 dB and -3.5 dB are the options) + BOOLEAN DmiExtSync; ///< This field is used to describe the DMI Extended Sync enable/disable control + UINT8 DmiDeEmphasis; ///< This field is used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are the options) + BOOLEAN DmiIot; ///< This field is used to describe the IOT control for DMI, default is 0 + UINT8 C7Allowed; ///< Enable/Disable C7 allowed for PEG Ports [Run-time control]. 0=Disable (default) and 1=Enable + /// + /// This field is used as a pointer to the ASPM device override table, default points to an + /// existing table, mPcieAspmDevsOverride, in the sample code. Refer to + /// $(PROJECT_SA_ROOT)\Protocol\SaPlatformPolicy\SaPlatformPolicy.h and + /// $(PROJECT_SA_ROOT)\SampleCode\SaPolicyInit\Dxe\SaDxePolicyInit.c for the usage. + /// + /// Note: This exclusion list helps avoid potential system hangs. + /// + PCIE_ASPM_DEV_INFO *PcieAspmDevsOverride; + /// + /// This field is used as a pointer to the LTR device override table, default points to an existing + /// table, mPcieLtrDevsOverride, in the sample code. Refer to + /// $(PROJECT_SA_ROOT)\Protocol\SaPlatformPolicy\SaPlatformPolicy.h and + /// $(PROJECT_SA_ROOT)\SampleCode\SaPolicyInit\Dxe\SaDxePolicyInit.c for the usage. + /// + PCIE_LTR_DEV_INFO *PcieLtrDevsOverride; + SA_PCIE_PWR_OPT PegPwrOpt[SA_PEG_MAX_FUN]; ///< This field is used to describe the PCIe LTR/OBFF relevant settings +} SA_PCIE_CONFIGURATION; + +/// +/// Audio Codec Verb Table +/// +typedef struct { + UINT32 VendorDeviceId; + UINT16 SubSystemId; + UINT8 RevisionId; ///< 0xFF applies to all steppings + UINT8 FrontPanelSupport; + UINT16 NumberOfRearJacks; + UINT16 NumberOfFrontJacks; +} SA_HDA_VERB_TABLE_HEADER; + +typedef struct { + SA_HDA_VERB_TABLE_HEADER VerbTableHeader; + UINT32 *VerbTableData; +} SA_HDA_VERB_TABLE; + +/// +/// This data structure includes IGD related configuration Variables. The data elements should +/// be initialized by a Platform Module. +/// +typedef struct { + UINT8 RenderStandby; ///< This field is used to enable or disable RC6 (Render Standby) + UINT8 DeepRenderStandby; ///< @deprecated + EFI_PHYSICAL_ADDRESS VbtAddress; ///< This field points to the GOP VBT data buffer + UINT32 Size; ///< This field gives the size of the GOP VBT Data buffer + UINT8 CdClk; ///< This field is used to control the Cd Clock Frequency by the user. 0: 337.5Mhz, 1: 450Mhz, 2: 540Mhz + UINT8 CdClkVar; ///< This field gives the Cd Clock Frequencies supported by the system. + UINT8 PlatformConfig; ///< This field gives the Platform Configuration Information (0 = Platform is S0ix Capable for ULT SKUs only, 1 = Platform is not S0ix Capable, 2 = Force Platform is S0ix Capable for All SKUs) + UINT32 IuerStatusVal; ///< This field holds the current status of all the supported Ultrabook events (Intel(R) Ultrabook Event Status bits) + CHAR16 GopVersion[0x10]; ///< This field holds the GOP Driver Version. It is an Output Protocol and updated by the RC + +} SA_IGD_CONFIGURATION; + +/// +/// Subsystem Vendor ID / Subsystem ID +/// +typedef struct { + UINT16 SubSystemVendorId; + UINT16 SubSystemId; +} SA_DEFAULT_SVID_SID; + +/// +/// This data structure includes miscellaneous configuration variables such SA thermal device +/// control. The data elements should be initialized by a Platform Module. +/// +typedef struct { + BOOLEAN ChapDeviceEnable; ///< This field is used to control enable or disable System Agent device (0,7,0) + BOOLEAN Device4Enable; ///< This field is used to control enable or disable System Agent device (0,4,0) + SA_DEFAULT_SVID_SID *DefaultSvidSid; ///< This field contains the Subsystem VendorID and Subsystem ID values to program to SA devices + BOOLEAN CridEnable; ///< This field is used to control enable or disable HSW CRID control (to support Intel(R) SIPP) + BOOLEAN AudioEnable; ///< This field is used to control enable or disable System Agent device (0,3,0) + BOOLEAN FviReport; ///< This field is used to control enable or disable of Firmware Version Info (FVI) reporting. 0: Disable; 1: Enable + UINT8 FviSmbiosType; ///< This field is used to control the FVI type reported + UINT8 SaHdaVerbTableNum;///< This field gives the number of HD Audio verb tables that are loaded + SA_HDA_VERB_TABLE *SaHdaVerbTable; ///< This field points to the current HD Audio verb table +} SA_MISC_CONFIGURATION; + +/// +/// This data structure includes Switchable Graphics VBIOS configuration. The data elements +/// should be initialized by a Platform Module. +/// +typedef struct { + UINT8 LoadVbios : 1; ///< This field is used to describe if the dGPU VBIOS needs to be loaded + UINT8 ExecuteVbios : 1; ///< This field is used to describe if the dGPU VBIOD need to be executed + UINT8 VbiosSource : 1; ///< This field is used to identify the source location of dGPU VBIOS + UINT8 Reserved : 5; +} SA_SG_VBIOS_CONFIGURATION; + +/// +/// SA DXE Platform Policy +/// +/// The DXE_PLATFORM_SA_POLICY_PROTOCOL producer drvier is recommended to +/// set all the DXE_PLATFORM_SA_POLICY_PROTOCOL size buffer zero before init any member parameter, +/// this clear step can make sure no random value for those unknow new version parameters. +/// +/// Make sure to update the Revision if any change to the protocol, including the existing +/// internal structure definations +/// +typedef struct _DXE_PLATFORM_SA_POLICY_PROTOCOL { + /// This field specifies the revision of the protocol. The protocol is expected to change in + /// a backwards compatible manner as the chipset configuration options are added or removed. + /// Major changes will result in new protocol definitions/GUID. The protocol producer must update + /// this field at build time. + /// + /// Please ensure to use DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION macro to define the protocol + /// revision as input for this version. + /// + UINT8 Revision; + SA_VTD_CONFIGURATION *Vtd; ///< This field is used to describe the configuration of VT-d function used by System Agent Reference code + SA_PCIE_CONFIGURATION *PcieConfig; ///< This field is used to describe the PCIE configuration used by System Agent Reference code + SA_MEMORY_CONFIGURATION *MemoryConfig; ///< This field is used to describe the Memory configuration used by System Agent Reference code + SA_IGD_CONFIGURATION *IgdConfig; ///< This field is used to describe the IGD configuration used by System Agent Reference code + SA_MISC_CONFIGURATION *MiscConfig; ///< This field is used to describe some miscellaneous configuration used by System Agent Reference code, such as device enable/disable, CRID support, etc + SA_SG_VBIOS_CONFIGURATION *VbiosConfig; ///< This field is used to describe Switchable Graphics configuration used by System Agent Reference Code +} DXE_PLATFORM_SA_POLICY_PROTOCOL; + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.cif b/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.cif new file mode 100644 index 0000000..22c0c36 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.cif @@ -0,0 +1,26 @@ +<component> + name = "SaProtocolLib" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\SystemAgent\Protocol\" + RefName = "SaProtocolLib" +[files] +"SaProtocolLib.sdl" +"SaProtocolLib.mak" +"MemInfo\MemInfo.c" +"MemInfo\MemInfo.h" +"IgdOpRegion\IgdOpRegion.c" +"IgdOpRegion\IgdOpRegion.h" +"IntelSaProtocolLib.inf" +"SaPlatformPolicy\SaPlatformPolicy.c" +"SaPlatformPolicy\SaPlatformPolicy.h" +"SaInfo\SaInfo.h" +"SaInfo\SaInfo.c" +"BdatAccess\BdatAccess.h" +"BdatAccess\BdatAccess.c" +"PlatformGopPolicy\PlatformGopPolicy.c" +"PlatformGopPolicy\PlatformGopPolicy.h" +"SaGlobalNvsArea\SaGlobalNvsArea.c" +"SaGlobalNvsArea\SaGlobalNvsArea.h" +"GopComponentName2\GopComponentName2.c" +"GopComponentName2\GopComponentName2.h" +<endComponent> diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.mak b/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.mak new file mode 100644 index 0000000..f858243 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.mak @@ -0,0 +1,20 @@ +# MAK file for the ModulePart:IntelSaProtocolLib +all : IntelSaProtocolLib + +$(BUILD_DIR)\IntelSaProtocolLib.lib : IntelSaProtocolLib + +IntelSaProtocolLib : $(BUILD_DIR)\SaProtocolLib.mak IntelSaProtocolLibBin + +$(BUILD_DIR)\SaProtocolLib.mak : $(INTEL_SA_PROTOCOL_LIB_DIR)\$(@B).cif $(INTEL_SA_PROTOCOL_LIB_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(INTEL_SA_PROTOCOL_LIB_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +IntelSaProtocolLib_INCLUDES =\ + $(EDK_INCLUDES) \ + $(INTEL_MCH_INCLUDES) + +IntelSaProtocolLibBin : + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\SaProtocolLib.mak all\ + "MY_INCLUDES=$(IntelSaProtocolLib_INCLUDES)" \ + TYPE=LIBRARY \ + LIBRARY_NAME=$(BUILD_DIR)\IntelSaProtocolLib.lib
\ No newline at end of file diff --git a/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.sdl b/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.sdl new file mode 100644 index 0000000..b5ad7b2 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/Protocol/SaProtocolLib.sdl @@ -0,0 +1,35 @@ +TOKEN + Name = SaProtocolLib_SUPPORT + Value = 1 + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable SaProtocolLib support in Project" +End + +MODULE + Help = "Includes SaProtocolLib.mak to Project" + File = "SaProtocolLib.mak" +End + +PATH + Name = "INTEL_SA_PROTOCOL_LIB_DIR" +End + +ELINK + Name = "/I$(INTEL_SA_PROTOCOL_LIB_DIR)" + Parent = "INTEL_MCH_INCLUDES" + InvokeOrder = AfterParent +End + +ELINK + Name = "INTEL_SA_PROTOCOL_LIB" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "$(BUILD_DIR)\IntelSaProtocolLib.lib" + Parent = "INTEL_SA_PROTOCOL_LIB" + InvokeOrder = AfterParent +End
\ No newline at end of file |