diff options
Diffstat (limited to 'ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt')
9 files changed, 3303 insertions, 0 deletions
diff --git a/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/ApCst.asl b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/ApCst.asl new file mode 100644 index 0000000..3be877d --- /dev/null +++ b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/ApCst.asl @@ -0,0 +1,146 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2011 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + ApCst.asl + +Abstract: + + Intel Processor Power Management ACPI Code + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +--*/ + + +DefinitionBlock ( + "APCST.aml", + "SSDT", + 1, + "PmRef", + "ApCst", + 0x3000 + ) +{ +External(\_PR.CPU1, DeviceObj) +External(\_PR.CPU2, DeviceObj) +External(\_PR.CPU3, DeviceObj) +External(\_PR.CPU4, DeviceObj) +External(\_PR.CPU5, DeviceObj) +External(\_PR.CPU6, DeviceObj) +External(\_PR.CPU7, DeviceObj) +External(\_PR.CPU0._CST) + + Scope(\_PR.CPU1) + { + Method(_CST,0) + { + // + // Return P0's _CST object. + // + Return(\_PR.CPU0._CST) + } + } + + Scope(\_PR.CPU2) + { + Method(_CST,0) + { + // + // Return P0's _CST object. + // + Return(\_PR.CPU0._CST) + } + } + + Scope(\_PR.CPU3) + { + Method(_CST,0) + { + // + // Return P0's _CST object. + // + Return(\_PR.CPU0._CST) + } + } + + Scope(\_PR.CPU4) + { + Method(_CST,0) + { + // + // Return P0's _CST object. + // + Return(\_PR.CPU0._CST) + } + } + + Scope(\_PR.CPU5) + { + Method(_CST,0) + { + // + // Return P0's _CST object. + // + Return(\_PR.CPU0._CST) + } + } + + Scope(\_PR.CPU6) + { + Method(_CST,0) + { + // + // Return P0's _CST object. + // + Return(\_PR.CPU0._CST) + } + } + + Scope(\_PR.CPU7) + { + Method(_CST,0) + { + // + // Return P0's _CST object. + // + Return(\_PR.CPU0._CST) + } + } + +} // End of Definition Block diff --git a/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/ApIst.asl b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/ApIst.asl new file mode 100644 index 0000000..612101c --- /dev/null +++ b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/ApIst.asl @@ -0,0 +1,408 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + ApIst.asl + +Abstract: + + Intel Processor Power Management ACPI Code + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +--*/ + + +DefinitionBlock ( + "APIST.aml", + "SSDT", + 1, + "PmRef", + "ApIst", + 0x3000 + ) +{ + External(\_PR.CPU0._PSS, MethodObj) + External(\_PR.CPU0._PCT, MethodObj) + External(\_PR.CPU0._PPC, IntObj) + External(\_PR.CPU0._PSD, MethodObj) + External(\_PR.CPU1, DeviceObj) + External(\_PR.CPU2, DeviceObj) + External(\_PR.CPU3, DeviceObj) + External(\_PR.CPU4, DeviceObj) + External(\_PR.CPU5, DeviceObj) + External(\_PR.CPU6, DeviceObj) + External(\_PR.CPU7, DeviceObj) + External (CFGD) + External (PDC0) + External (MPMF) + External (TCNT) + + Scope(\_PR.CPU1) + { + Method(_PPC,0) + { + Return(\_PR.CPU0._PPC) // Return P0 _PPC value. + } + + Method(_PCT,0) + { + Return(\_PR.CPU0._PCT) // Return P0 _PCT. + + } + + Method(_PSS,0) + { + //Return the same table as CPU0 for CMP cases. + Return(\_PR.CPU0._PSS) + } + + Name (PSDF, 0) + // + // The _PSD object provides information to the OSPM related + // to P-State coordination between processors in a multi-processor + // configurations. + // + Method(_PSD,0) + { + If ( LNot(PSDF) ) + { + Store (TCNT, Index(DerefOf(Index(HPSD, 0)),4)) + Store (TCNT, Index(DerefOf(Index(SPSD, 0)),4)) + Store (Ones, PSDF) + } + If(And(PDC0,0x0800)) + { + Return(HPSD) + } + Return(SPSD) + } + Name(HPSD,Package() // HW_ALL + { + Package(){5, 0, 0, 0xFE, 0x80} + }) + Name(SPSD,Package() // SW_ALL + { + Package(){5, 0, 0, 0xFC, 0x80} + }) + } + + Scope(\_PR.CPU2) + { + Method(_PPC,0) + { + Return(\_PR.CPU0._PPC) // Return CPU0 _PPC value. + } + + Method(_PCT,0) + { + Return(\_PR.CPU0._PCT) // Return CPU0 _PCT value. + } + + Method(_PSS,0) + { + Return(\_PR.CPU0._PSS) // Return CPU0 _PSS. + } + + Name (PSDF, 0) + // + // The _PSD object provides information to the OSPM related + // to P-State coordination between processors in a multi-processor + // configurations. + // + Method(_PSD,0) + { + If ( LNot(PSDF) ) + { + Store (TCNT, Index(DerefOf(Index(HPSD, 0)),4)) + Store (TCNT, Index(DerefOf(Index(SPSD, 0)),4)) + Store (Ones, PSDF) + } + If(And(PDC0,0x0800)) + { + Return(HPSD) + } + Return(SPSD) + } + Name(HPSD,Package() // HW_ALL + { + Package(){5, 0, 0, 0xFE, 0x80} + }) + Name(SPSD,Package() // SW_ALL + { + Package(){5, 0, 0, 0xFC, 0x80} + }) + } + + + Scope(\_PR.CPU3) + { + Method(_PPC,0) + { + Return(\_PR.CPU0._PPC) // Return CPU0 _PPC value. + } + + Method(_PCT,0) + { + Return(\_PR.CPU0._PCT) // Return CPU0 _PCT value. + } + + Method(_PSS,0) + { + Return(\_PR.CPU0._PSS) // Return CPU0 _PSS. + } + + Name (PSDF, 0) + // + // The _PSD object provides information to the OSPM related + // to P-State coordination between processors in a multi-processor + // configurations. + // + Method(_PSD,0) + { + If ( LNot(PSDF) ) + { + Store (TCNT, Index(DerefOf(Index(HPSD, 0)),4)) + Store (TCNT, Index(DerefOf(Index(SPSD, 0)),4)) + Store (Ones, PSDF) + } + If(And(PDC0,0x0800)) + { + Return(HPSD) + } + Return(SPSD) + } + Name(HPSD,Package() // HW_ALL + { + Package(){5, 0, 0, 0xFE, 0x80} + }) + Name(SPSD,Package() // SW_ALL + { + Package(){5, 0, 0, 0xFC, 0x80} + }) + } + + Scope(\_PR.CPU4) + { + Method(_PPC,0) + { + Return(\_PR.CPU0._PPC) // Return CPU0 _PPC value. + } + + Method(_PCT,0) + { + Return(\_PR.CPU0._PCT) // Return CPU0 _PCT value. + } + + Method(_PSS,0) + { + Return(\_PR.CPU0._PSS) // Return CPU0 _PSS. + } + + Name (PSDF, 0) + // + // The _PSD object provides information to the OSPM related + // to P-State coordination between processors in a multi-processor + // configurations. + // + Method(_PSD,0) + { + If ( LNot(PSDF) ) + { + Store (TCNT, Index(DerefOf(Index(HPSD, 0)),4)) + Store (TCNT, Index(DerefOf(Index(SPSD, 0)),4)) + Store (Ones, PSDF) + } + If(And(PDC0,0x0800)) + { + Return(HPSD) + } + Return(SPSD) + } + Name(HPSD,Package() // HW_ALL + { + Package(){5, 0, 0, 0xFE, 0x80} + }) + Name(SPSD,Package() // SW_ALL + { + Package(){5, 0, 0, 0xFC, 0x80} + }) + } + + Scope(\_PR.CPU5) + { + Method(_PPC,0) + { + Return(\_PR.CPU0._PPC) // Return CPU0 _PPC value. + } + + Method(_PCT,0) + { + Return(\_PR.CPU0._PCT) // Return CPU0 _PCT value. + } + + Method(_PSS,0) + { + Return(\_PR.CPU0._PSS) // Return CPU0 _PSS. + } + + Name (PSDF, 0) + // + // The _PSD object provides information to the OSPM related + // to P-State coordination between processors in a multi-processor + // configurations. + // + Method(_PSD,0) + { + If ( LNot(PSDF) ) + { + Store (TCNT, Index(DerefOf(Index(HPSD, 0)),4)) + Store (TCNT, Index(DerefOf(Index(SPSD, 0)),4)) + Store (Ones, PSDF) + } + If(And(PDC0,0x0800)) + { + Return(HPSD) + } + Return(SPSD) + } + Name(HPSD,Package() // HW_ALL + { + Package(){5, 0, 0, 0xFE, 0x80} + }) + Name(SPSD,Package() // SW_ALL + { + Package(){5, 0, 0, 0xFC, 0x80} + }) + } + + Scope(\_PR.CPU6) + { + Method(_PPC,0) + { + Return(\_PR.CPU0._PPC) // Return CPU0 _PPC value. + } + + Method(_PCT,0) + { + Return(\_PR.CPU0._PCT) // Return CPU0 _PCT value. + } + + Method(_PSS,0) + { + Return(\_PR.CPU0._PSS) // Return CPU0 _PSS. + } + + Name (PSDF, 0) + // + // The _PSD object provides information to the OSPM related + // to P-State coordination between processors in a multi-processor + // configurations. + // + Method(_PSD,0) + { + If ( LNot(PSDF) ) + { + Store (TCNT, Index(DerefOf(Index(HPSD, 0)),4)) + Store (TCNT, Index(DerefOf(Index(SPSD, 0)),4)) + Store (Ones, PSDF) + } + If(And(PDC0,0x0800)) + { + Return(HPSD) + } + Return(SPSD) + } + Name(HPSD,Package() // HW_ALL + { + Package(){5, 0, 0, 0xFE, 0x80} + }) + Name(SPSD,Package() // SW_ALL + { + Package(){5, 0, 0, 0xFC, 0x80} + }) + } + + Scope(\_PR.CPU7) + { + Method(_PPC,0) + { + Return(\_PR.CPU0._PPC) // Return CPU0 _PPC value. + } + + Method(_PCT,0) + { + Return(\_PR.CPU0._PCT) // Return CPU0 _PCT value. + } + + Method(_PSS,0) + { + Return(\_PR.CPU0._PSS) // Return CPU0 _PSS. + } + + Name (PSDF, 0) + // + // The _PSD object provides information to the OSPM related + // to P-State coordination between processors in a multi-processor + // configurations. + // + Method(_PSD,0) + { + If ( LNot(PSDF) ) + { + Store (TCNT, Index(DerefOf(Index(HPSD, 0)),4)) + Store (TCNT, Index(DerefOf(Index(SPSD, 0)),4)) + Store (Ones, PSDF) + } + If(And(PDC0,0x0800)) + { + Return(HPSD) + } + Return(SPSD) + } + Name(HPSD,Package() // HW_ALL + { + Package(){5, 0, 0, 0xFE, 0x80} + }) + Name(SPSD,Package() // SW_ALL + { + Package(){5, 0, 0, 0xFC, 0x80} + }) + } + +} // End of Definition Block diff --git a/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/ApTst.asl b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/ApTst.asl new file mode 100644 index 0000000..13972c2 --- /dev/null +++ b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/ApTst.asl @@ -0,0 +1,481 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + ApTst.asl + +Abstract: + + Intel Processor Power Management ACPI Code + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +--*/ + + +DefinitionBlock( + "APTST.aml", + "SSDT", + 0x01, + "PmRef", + "ApTst", + 0x3000 + ) +{ + External(\_PR.CPU1, DeviceObj) + External(\_PR.CPU2, DeviceObj) + External(\_PR.CPU3, DeviceObj) + External(\_PR.CPU4, DeviceObj) + External(\_PR.CPU5, DeviceObj) + External(\_PR.CPU6, DeviceObj) + External(\_PR.CPU7, DeviceObj) + External(\_PR.CPU0._PTC) + External(\_PR.CPU0._TSS) + External(PDC0) + External(CFGD) + External(TCNT) + + Scope(\_PR.CPU1) + { + Name(_TPC, 0) // All T-States are available + + // + // T-State Control/Status interface + // + Method(_PTC, 0) + { + Return(\_PR.CPU0._PTC) + } + + Method(_TSS, 0) + { + Return(\_PR.CPU0._TSS) + } + + // + // T-State Dependency + // + Method(_TSD, 0) + { + // + // IF four cores are supported/enabled && !(direct access to MSR) + // Report 4 processors and SW_ANY as the coordination + // IF two cores are supported/enabled && !(direct access to MSR) + // Report 2 processors and SW_ANY as the coordination type + // ELSE + // Report 1 processor and SW_ALL as the coordination type (domain 1) + // + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + + If(LNot(And(PDC0,4))) + { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + TCNT // # processors. + } + }) + } + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 1, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + }) + } + } // End of CPU1 + + + Scope(\_PR.CPU2) + { + Name(_TPC, 0) // All T-States are available + + // + // T-State Control/Status interface + // + Method(_PTC, 0) + { + Return(\_PR.CPU0._PTC) + } + + Method(_TSS, 0) + { + Return(\_PR.CPU0._TSS) + } + + // + // T-State Dependency + // + Method(_TSD, 0) + { + // + // IF four cores are supported/enabled && !(direct access to MSR) + // Report 4 processors and SW_ANY as the coordination + // IF two cores are supported/enabled && !(direct access to MSR) + // Report 2 processors and SW_ANY as the coordination type + // ELSE + // Report 1 processor and SW_ALL as the coordination type (domain 2) + // + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + + If(LNot(And(PDC0,4))) + { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + TCNT // # processors. + } + }) + } + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 2, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + }) + } + } // End of CPU2 + + + Scope(\_PR.CPU3) + { + Name(_TPC, 0) // All T-States are available + + // + // T-State Control/Status interface + // + Method(_PTC, 0) + { + Return(\_PR.CPU0._PTC) + } + + Method(_TSS, 0) + { + Return(\_PR.CPU0._TSS) + } + + // + // T-State Dependency + // + Method(_TSD, 0) + { + // + // IF four cores are supported/enabled && !(direct access to MSR) + // Report 4 processors and SW_ANY as the coordination + // IF two cores are supported/enabled && !(direct access to MSR) + // Report 2 processors and SW_ANY as the coordination type + // ELSE + // Report 1 processor and SW_ALL as the coordination type (domain 3) + // + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + + If(LNot(And(PDC0,4))) + { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + TCNT // # processors. + } + }) + } + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 3, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + }) + } + } // End of CPU3 + + Scope(\_PR.CPU4) + { + Name(_TPC, 0) // All T-States are available + + // + // T-State Control/Status interface + // + Method(_PTC, 0) + { + Return(\_PR.CPU0._PTC) + } + + Method(_TSS, 0) + { + Return(\_PR.CPU0._TSS) + } + + // + // T-State Dependency + // + Method(_TSD, 0) + { + // + // IF four cores are supported/enabled && !(direct access to MSR) + // Report 4 processors and SW_ANY as the coordination + // IF two cores are supported/enabled && !(direct access to MSR) + // Report 2 processors and SW_ANY as the coordination type + // ELSE + // Report 1 processor and SW_ALL as the coordination type (domain 3) + // + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + + If(LNot(And(PDC0,4))) + { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + TCNT // # processors. + } + }) + } + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 4, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + }) + } + } // End of CPU4 + + Scope(\_PR.CPU5) + { + Name(_TPC, 0) // All T-States are available + + // + // T-State Control/Status interface + // + Method(_PTC, 0) + { + Return(\_PR.CPU0._PTC) + } + + Method(_TSS, 0) + { + Return(\_PR.CPU0._TSS) + } + + // + // T-State Dependency + // + Method(_TSD, 0) + { + // + // IF four cores are supported/enabled && !(direct access to MSR) + // Report 4 processors and SW_ANY as the coordination + // IF two cores are supported/enabled && !(direct access to MSR) + // Report 2 processors and SW_ANY as the coordination type + // ELSE + // Report 1 processor and SW_ALL as the coordination type (domain 3) + // + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + + If(LNot(And(PDC0,4))) + { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + TCNT // # processors. + } + }) + } + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 5, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + }) + } + } // End of CPU5 + + Scope(\_PR.CPU6) + { + Name(_TPC, 0) // All T-States are available + + // + // T-State Control/Status interface + // + Method(_PTC, 0) + { + Return(\_PR.CPU0._PTC) + } + + Method(_TSS, 0) + { + Return(\_PR.CPU0._TSS) + } + + // + // T-State Dependency + // + Method(_TSD, 0) + { + // + // IF four cores are supported/enabled && !(direct access to MSR) + // Report 4 processors and SW_ANY as the coordination + // IF two cores are supported/enabled && !(direct access to MSR) + // Report 2 processors and SW_ANY as the coordination type + // ELSE + // Report 1 processor and SW_ALL as the coordination type (domain 3) + // + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + + If(LNot(And(PDC0,4))) + { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + TCNT // # processors. + } + }) + } + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 6, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + }) + } + } // End of CPU6 + + Scope(\_PR.CPU7) + { + Name(_TPC, 0) // All T-States are available + + // + // T-State Control/Status interface + // + Method(_PTC, 0) + { + Return(\_PR.CPU0._PTC) + } + + Method(_TSS, 0) + { + Return(\_PR.CPU0._TSS) + } + + // + // T-State Dependency + // + Method(_TSD, 0) + { + // + // IF four cores are supported/enabled && !(direct access to MSR) + // Report 4 processors and SW_ANY as the coordination + // IF two cores are supported/enabled && !(direct access to MSR) + // Report 2 processors and SW_ANY as the coordination type + // ELSE + // Report 1 processor and SW_ALL as the coordination type (domain 3) + // + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + + If(LNot(And(PDC0,4))) + { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + TCNT // # processors. + } + }) + } + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 7, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + }) + } + } // End of CPU7 +} // End of Definition Block + diff --git a/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl new file mode 100644 index 0000000..6c0c48a --- /dev/null +++ b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl @@ -0,0 +1,319 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Cpu0Cst.asl + +Abstract: + + Intel Processor Power Management ACPI Code + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +--*/ + + +#include "PowerMgmtDefinitions.h" + +DefinitionBlock ( + "CPU0CST.aml", + "SSDT", + 1, + "PmRef", + "Cpu0Cst", + 0x3001 + ) +{ +External(\_PR.CPU0, DeviceObj) +External(PWRS) +External(CFGD) +External(PDC0) +External(FMBL) +External(FEMD) +External(PFLV) +External(C3MW) // Mwait Hint value for C3 +External(C6MW) // Mwait Hint value for C6 +External(C7MW) // Mwait Hint value for C7 +External(CDMW) // Mwait Hint value for C8/C9/C10 +External(C3LT) // Latency value for C3 +External(C6LT) // Latency Value for C6 +External(C7LT) // Latency Value for C7 +External(CDLT) // Latency Value for C8/C9/C10 +External(CDLV) // IO Level value for C8/C9/C10 +External(CDPW) // Power value for C8/C9/C10 + +Scope(\_PR.CPU0) +{ + // + // Create Temp packages for each C-state and Initialize them to default IO_LVL + // + // C1 Temp Package (C1 - HLT) + // + Name ( C1TM, Package() + { + ResourceTemplate () {Register(FFixedHW, 0, 0, 0)}, + 1, + C1_LATENCY, + C1_POWER + }) + // + // C3 Temp Package + // + Name ( C3TM, Package() + { + ResourceTemplate () {Register(SystemIO, 8, 0, PCH_ACPI_LV2)}, + 2, + 0, + C3_POWER + }) + // + // C6 Temp Package + // + Name ( C6TM, Package() + { + ResourceTemplate () {Register(SystemIO, 8, 0, PCH_ACPI_LV3)}, + 2, + 0, + C6_POWER + }) + + // + // C7 Temp Package + // + Name ( C7TM, Package() + { + ResourceTemplate () {Register(SystemIO, 8, 0, PCH_ACPI_LV4)}, + 2, + 0, + C7_POWER + }) + + // + // CD Temp Package - Deep C-states - covers C8/C9/C10 + // + Name ( CDTM, Package() + { + ResourceTemplate () {Register(SystemIO, 8, 0, PCH_ACPI_LV4)}, + 3, + 0, + 0 + }) + // + // ResourceTemplate for MWait Extentions Supported. + // + Name ( MWES, ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)}) + // + // Valid/Invalid Flags for ACPI C2 and C3 + // + Name (AC2V, 0) + Name (AC3V, 0) + // + // Package for reporting 3 C-states + // + Name ( C3ST, Package() + { + 3, + Package() {}, + Package() {}, + Package() {} + }) + // + // Package for reporting 2 C-states + // + Name ( C2ST, Package() + { + 2, + Package() {}, + Package() {} + }) + // + // Package for reporting 1 C-state + // + Name ( C1ST, Package() + { + 1, + Package() {} + }) + // + // C-state initialization flag + // + Name(CSTF, 0) + // + // Lake Tiny Gear control setting (deafult value for Gear1) + // + Name (GEAR, 0) + // + // Returns the C-state table based on platform configuration. + // This method is serialized since it uses various global packages and updates them in run time to return the current C-state table. + // + Method (_CST, 0, Serialized) + { + If(LNot(CSTF)) + { + // + // First call to _CST. + // Update Latency Values for C3/C6/C7/CD based on the Latency values passed through PPM NVS + // + Store (C3LT, Index(C3TM, 2)) + Store (C6LT, Index(C6TM, 2)) + Store (C7LT, Index(C7TM, 2)) + Store (CDLT, Index(CDTM, 2)) + // + // Update the IO_LVL and Power values in CD temp package + // + Store (CDPW, Index(CDTM, 3)) + Store (CDLV, Index (DerefOf (Index (CDTM, 0)),7)) + // + // CFGD[11] = 1 - MWAIT extensions supported + // PDCx[9] = 1 - OS supports MWAIT extensions + // PDCx[8] = 1 - OS supports MWAIT for C1 (Inferred from PDCx[9] = 1.) + // + If(LAnd(And(CFGD, PPM_MWAIT_EXT), And(PDC0,0x200))) + { + // + // Processor MWAIT extensions supported and OS supports MWAIT extensions + // 1. Replace the IO LVL ResourceTemplate of C1TM, C3TM, C6TM, C7TM, CDTM with MWAIT EXT ResourceTemplate (FFixedHW) + // 2. Update the Mwait Hint Values for C3/C6/C7/CD based on the Latency values passed through PPM NVS + // + + Store (MWES, Index (C1TM, 0)) + Store (MWES, Index (C3TM, 0)) + Store (MWES, Index (C6TM, 0)) + Store (MWES, Index (C7TM, 0)) + Store (MWES, Index (CDTM, 0)) + + Store (C3MW, Index (DerefOf (Index (C3TM, 0)),7)) + Store (C6MW, Index (DerefOf (Index (C6TM, 0)),7)) + Store (C7MW, Index (DerefOf (Index (C7TM, 0)),7)) + Store (CDMW, Index (DerefOf (Index (CDTM, 0)),7)) + } + ElseIf (LAnd(And(CFGD, PPM_MWAIT_EXT), And(PDC0,0x100))) + { + // + // Update C1 temp package ResourceTemplate if OS supports Mwait for C1 + // + Store (MWES, Index (C1TM, 0)) + } + + Store (Ones, CSTF) + } + // + // Initialize the ACPI C2, C3 Valid/Invalid flags to Invalid (0) + // + Store(Zero, AC2V) + Store(Zero, AC3V) + // + // Create C state Package with Acpi C1= C1,ACPI C2=MaxSupported(C6,C3,C7),ACPI C3=MaxSupported(C8,C9,C10). + // It is safe to assume C1 always supported if we enable C-states. + // + Store (C1TM, Index (C3ST,1)) + + If(And(CFGD,PPM_C7)) + { + Store (C7TM, Index (C3ST,2)) + Store (Ones, AC2V) + }ElseIf(And(CFGD,PPM_C6)) + { + Store (C6TM, Index (C3ST,2)) + Store (Ones, AC2V) + }ElseIf(And(CFGD,PPM_C3)) + { + Store (C3TM, Index (C3ST,2)) + Store (Ones, AC2V) + } + If(And(CFGD,PPM_CD)) { + Store (CDTM, Index (C3ST,3)) + Store (Ones, AC3V) + } + // + // Modify the ACPI C2 and C3 states if LakeTiny GEAR2 or GEAR3. GEAR1- No Change + // + If(LEqual (GEAR, 1)) + { + // + // GEAR2 - Deepest C-state is replaced with C3 and with C1 (if C3 not supported) + // + If (And(CFGD,PPM_C3)) + { + Store (C3TM, Index (C3ST,2)) + Store (Ones, AC2V) + Store (Zero, AC3V) + } + Else + { + Store (Zero, AC2V) + Store (Zero, AC3V) + } + } + If(LEqual (GEAR, 2)) + { + // + // GEAR3 - Replace all C-states with C1 + // + Store (Zero, AC2V) + Store (Zero, AC3V) + } + + // + // Filter and return the final C-state package + // + If(LAnd(AC2V, AC3V)) + { + Return (C3ST) + } + ElseIf(AC2V) + { + Store (DerefOf (Index (C3ST,1)), Index (C2ST,1)) + Store (DerefOf (Index (C3ST,2)), Index (C2ST,2)) + Return (C2ST) + } + ElseIf(AC3V) + { + Store (DerefOf (Index (C3ST,1)), Index (C2ST,1)) + Store (DerefOf (Index (C3ST,3)), Index (C2ST,2)) + Store (2, Index (DerefOf (Index (C2ST, 2)),1)) + Return (C2ST) + } + Else + { + Store (DerefOf (Index (C3ST,1)), Index (C1ST,1)) + Return (C1ST) + } + } +} +} diff --git a/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl new file mode 100644 index 0000000..83b5294 --- /dev/null +++ b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl @@ -0,0 +1,163 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Cpu0Ist.asl + +Abstract: + + Intel Processor Power Management ACPI Code + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +--*/ + + +DefinitionBlock ( + "CPU0IST.aml", + "SSDT", + 0x01, + "PmRef", + "Cpu0Ist", + 0x3000 + ) +{ + External (\_PR.CPU0, DeviceObj) + External (\_PR.CPPC) + External (PDC0) + External (CFGD) + External (TCNT) + External (MPMF) + Scope(\_PR.CPU0) + { + // + // Report supported P-States. + // + Name(_PPC, 0) + + // + // NOTE: For CMP systems; this table is not loaded unless + // the required driver support is present. + // So, we do not check for those cases here. + // + // CFGD[0] = GV3 Capable/Enabled + // PDCx[0] = OS Capable of Hardware P-State control + // + Method(_PCT,0) + { + // Update the _PPC value + // + Store (\_PR.CPPC, \_PR.CPU0._PPC) + + If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001))) + { + Return(Package() // Native Mode + { + ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FfixedHW, 0, 0, 0)} + }) + } + } + + Name(_PSS,Package() + { + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000} + }) + + Name (PSDF, 0) + // + // The _PSD object provides information to the OSPM related + // to P-State coordination between processors in a multi-processor + // configurations. + // + Method(_PSD,0) + { + If ( LNot(PSDF) ) + { + Store (TCNT, Index(DerefOf(Index(HPSD, 0)),4)) + Store (TCNT, Index(DerefOf(Index(SPSD, 0)),4)) + Store (Ones, PSDF) + } + + If(And(PDC0,0x0800)) + { + Return(HPSD) + } + Return(SPSD) + } + Name(HPSD,Package() // HW_ALL + { + Package(){5, 0, 0, 0xFE, 0x80} + }) + Name(SPSD,Package() // SW_ALL + { + Package(){5, 0, 0, 0xFC, 0x80} + }) + } +} // End of Definition Block diff --git a/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl new file mode 100644 index 0000000..a695091 --- /dev/null +++ b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl @@ -0,0 +1,258 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Cpu0Tst.asl + +Abstract: + + Intel Processor Power Management ACPI Code + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +--*/ + + + +#include "PowerMgmtDefinitions.h" + +DefinitionBlock( + "CPU0TST.aml", + "SSDT", + 0x01, + "PmRef", + "Cpu0Tst", + 0x3000 + ) +{ + External(\_PR.CPU0, DeviceObj) + External(PDC0) + External(CFGD) + External(_PSS) + External (TCNT) + + Scope(\_PR.CPU0) + { + Name(_TPC, 0) // All T-States are available + + // + // T-State Control/Status interface + // + Method(_PTC, 0) + { + // + // IF OSPM is capable of direct access to MSR + // Report MSR interface + // ELSE + // Report I/O interface + // + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + If(And(PDC0, 0x0004)) { + + Return(Package() { + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + } + + Return(Package() { + ResourceTemplate(){Register(SystemIO, 5, 0, PCH_ACPI_PBLK)}, + ResourceTemplate(){Register(SystemIO, 5, 0, PCH_ACPI_PBLK)} + }) + } + + // + // _TSS package for fine-grained T-State control. + // "Power" fields are replaced with real values by the first + // call of _TSS method. + // + Name(TSMF, Package() { + Package(){100, 1000, 0, 0x00, 0}, + Package(){ 94, 940, 0, 0x1F, 0}, + Package(){ 88, 880, 0, 0x1E, 0}, + Package(){ 82, 820, 0, 0x1D, 0}, + Package(){ 75, 760, 0, 0x1C, 0}, + Package(){ 69, 700, 0, 0x1B, 0}, + Package(){ 63, 640, 0, 0x1A, 0}, + Package(){ 57, 580, 0, 0x19, 0}, + Package(){ 50, 520, 0, 0x18, 0}, + Package(){ 44, 460, 0, 0x17, 0}, + Package(){ 38, 400, 0, 0x16, 0}, + Package(){ 32, 340, 0, 0x15, 0}, + Package(){ 25, 280, 0, 0x14, 0}, + Package(){ 19, 220, 0, 0x13, 0}, + Package(){ 13, 160, 0, 0x12, 0}, + Package(){ 7, 100, 0, 0x11, 0} + }) + + // + // _TSS package for T-State control (Coarse grained) + // "Power" fields are replaced with real values by the first + // call of _TSS method. + // + Name(TSMC, Package() { + Package(){100, 1000, 0, 0x00, 0}, + Package(){ 88, 875, 0, 0x1E, 0}, + Package(){ 75, 750, 0, 0x1C, 0}, + Package(){ 63, 625, 0, 0x1A, 0}, + Package(){ 50, 500, 0, 0x18, 0}, + Package(){ 38, 375, 0, 0x16, 0}, + Package(){ 25, 250, 0, 0x14, 0}, + Package(){ 13, 125, 0, 0x12, 0} + }) + + Name(TSSF, 0) // Flag for TSIF/TSIC/TSMF/TSMC initialization + Mutex(TSMO, 0) // Mutex object to ensure the _TSS initalization code is only executed once + Method(_TSS, 0) + { + // + // Update "Power" fields of TSIC or TSIF or TSMC or TSMF with the LFM + // power data IF _PSS is available + // Power caluclation: + // n - Number of T-states available + // _TSS(x).power = LFM.Power * (n-x)/n + // + IF (LAnd(LNot(TSSF),CondRefOf(_PSS))) + { + // + // Acquire Mutex to make sure the initialization happens only once. + // + Acquire (TSMO, 0xFFFF) + // + // Only one thread will be able to acquire the mutex at a time, but the other threads which have acquired the mutex previously, will eventually try to execute the TSS initalization code. + // So, let's check if TSS has already been initalized once again. If its initalized, skip the initalization. + // + IF (LAnd(LNot(TSSF),CondRefOf(_PSS))) + { + Name ( LFMI, 0) + Store (SizeOf(_PSS), LFMI) + Decrement(LFMI) // Index of LFM entry in _PSS + Name ( LFMP, 0) //LFM Power from _PSS + Store ( DerefOf(Index(DerefOf(Index(_PSS,LFMI)),1)) , LFMP) + Store (0, Local0) + + // + // Copy reference of appropiate TSS package based on Fine grained T-state support + // We'll update the power in the package directly (via the reference variable Local1) + // + // If Fine Grained T-states is enabled + // TSMF + // ELSE + // TSMC + // + If(And(CFGD,PPM_TSTATE_FINE_GRAINED)) + { + Store ( RefOf(TSMF), Local1 ) + Store ( SizeOf(TSMF),Local2 ) + } + Else + { + Store ( RefOf(TSMC), Local1 ) + Store ( SizeOf(TSMC),Local2 ) + } + + While(LLess(Local0, Local2)) + { + Store(Divide(Multiply(LFMP, Subtract(Local2, Local0)), Local2), + Local4) // Power for this entry + Store(Local4,Index(DerefOf(Index(DerefOf(Local1),Local0)),1)) + Increment(Local0) + } + + Store(Ones, TSSF) // Set flag to indicate TSS table initalization is complete + } + + Release (TSMO) + + } + // + // If Fine Grained T-states is enabled + // Report TSMF + // ELSE + // Report TSMC + // + If(And(CFGD, PPM_TSTATE_FINE_GRAINED)) + { + Return(TSMF) + } + Else + { + Return(TSMC) + } + } + + // + // T-State Dependency + // + Method(_TSD, 0) + { + // + // IF !(direct access to MSR) + // Report SW_ANY as the coordination type + // ELSE + // Report SW_ALL as the coordination type + // + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + If (LNot(And(PDC0,4))) { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + TCNT // # processors. + } + }) + } + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + }) + } + } +} // End of Definition Block + diff --git a/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/CpuPm.asl b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/CpuPm.asl new file mode 100644 index 0000000..2ba3e1b --- /dev/null +++ b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/CpuPm.asl @@ -0,0 +1,1061 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + CpuPm.asl + +Abstract: + + Intel Processor Power Management ACPI Code + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +--*/ + +#include "PowerMgmtDefinitions.h" + +DefinitionBlock ( + "CPUPM.aml", + "SSDT", + 0x01, + "PmRef", + "CpuPm", + 0x3000 + ) +{ + External(\_PR.CPU0, DeviceObj) + External(\_PR.CPU1, DeviceObj) + External(\_PR.CPU2, DeviceObj) + External(\_PR.CPU3, DeviceObj) + External(\_PR.CPU4, DeviceObj) + External(\_PR.CPU5, DeviceObj) + External(\_PR.CPU6, DeviceObj) + External(\_PR.CPU7, DeviceObj) + External(\_PR.CPU0._PPC, IntObj) + External(SMIF) + +Scope(\) +{ + + // Package of pointers to SSDT's + // + // First column is SSDT name, used for debug only. + // (First column must be EXACTLY eight characters.) + // Second column is physical address. + // Third column is table length. + // + // IF modifying this file, see warnings listed in ppminit.asm. + // + Name(SSDT,Package() + { + "CPU0IST ", 0x80000000, 0x80000000, + "APIST ", 0x80000000, 0x80000000, + "CPU0CST ", 0x80000000, 0x80000000, + "APCST ", 0x80000000, 0x80000000 + }) + + Name(\PDC0,0x80000000) // CPU0 _PDC Flags. + Name(\PDC1,0x80000000) // CPU1 _PDC Flags. + Name(\PDC2,0x80000000) // CPU2 _PDC Flags. + Name(\PDC3,0x80000000) // CPU3 _PDC Flags. + Name(\PDC4,0x80000000) // CPU4 _PDC Flags. + Name(\PDC5,0x80000000) // CPU5 _PDC Flags. + Name(\PDC6,0x80000000) // CPU6 _PDC Flags. + Name(\PDC7,0x80000000) // CPU7 _PDC Flags. + + Name(\SDTL,0x00) // Loaded SSDT Flags. +} + +Scope(\_PR) +{ + // + // Define a Processor scope ACPI PPM GlobalNvs NVS Region + // + OperationRegion(PPMT,SystemMemory,0xFFFF0000,0xAA55) + Field(PPMT,AnyAcc,Lock,Preserve) + { + PGRV, 8, // (0) PPM GlobalNvs Revision + CFGD, 32, // CFGD - PpmFlags + Offset(6), // (5) Reserved + // + // Thermal Configuration Values + // + ACRT, 8, // (6) Auto Critical Trip Point + APSV, 8, // (7) Auto Passive Trip Point + AAC0, 8, // (8) Auto Active Trip Point + CPID, 32, // (9) CPUID + // + // ConfigTDP Value + // + CPPC, 8, // (13) Boot Mode vlues for _PPC + // + // ConfigTDP Level settngs + // + CCTP, 8, // (14) Custom ConfigTdp Enabled/Disabled + CLVL, 8, // (15) ConfigTdp Number Of Levels + CBMI, 8, // (16) CTDP Boot Mode Index + PL10, 16, // (17) CTDP Level 0 Power Limit1 + PL20, 16, // (19) CTDP Level 0 Power Limit2 + PLW0, 8, // (21) CTDP Level 0 Power Limit1 Time Window + CTC0, 8, // (22) CTDP Level 0 CTC + TAR0, 8, // (23) CTDP Level 0 TAR + PPC0, 8, // (24) CTDP Level 0 PPC + PL11, 16, // (25) CTDP Level 1 Power Limit1 + PL21, 16, // (27) CTDP Level 1 Power Limit2 + PLW1, 8, // (29) CTDP Level 1 Power Limit1 Time Window + CTC1, 8, // (30) CTDP Level 1 CTC + TAR1, 8, // (31) CTDP Level 1 TAR + PPC1, 8, // (32) CTDP Level 1 PPC + PL12, 16, // (33) CTDP Level 2 Power Limit1 + PL22, 16, // (35) CTDP Level 2 Power Limit2 + PLW2, 8, // (37) CTDP Level 2 Power Limit1 Time Window + CTC2, 8, // (38) CTDP Level 2 CTC + TAR2, 8, // (39) CTDP Level 2 TAR + PPC2, 8, // (40) CTDP Level 2 PPC + // + // Mwait Hints and Latency values for C3/C6/C7/C7S + // + C3MW, 8, // (41) Mwait Hint value for C3 + C6MW, 8, // (42) Mwait Hint value for C6 + C7MW, 8, // (43) Mwait Hint value for C7/C7s + CDMW, 8, // (44) Mwait Hint value for C8/C9/C10 + C3LT, 16, // (45-46) Latency value for C3 + C6LT, 16, // (47-48) Latency Value for C6 + C7LT, 16, // (49-50) Latency Value for C7/C7S + CDLT, 16, // (51-52) Latency Value for C8/C9/C10 + CDLV, 16, // (53-54) IO LVL value for C8/C9/C10 + CDPW, 16, // (55-56) Power value for C8/C9/C10 + MPMF, 8 // (57) MiscPowerManagementFlags + } +} + +Scope(\_PR.CPU0) +{ + // + // Define handles for opregions (used by load.) + // + Name(HI0,0) // Handle to CPU0IST + Name(HC0,0) // Handle to CPU0CST + + Method(_PDC,1) + { + // + // Update the _PPC value + // + if(CondRefOf(\_PR.CPU0._PPC)) { + Store (CPPC, \_PR.CPU0._PPC) + } + // + // Check and extract the _PDC information. + // + Store(CPDC(Arg0), Local0) + // + // Save the capability information and load tables as needed. + // + GCAP(Local0) + // + // Return status. + // + Return (Local0) + } + + Method(_OSC, 4) + { + // + // Check and extract the _OSC information. + // + Store(COSC(Arg0, Arg1, Arg2, Arg3), Local0) + // + // Save the capability information and load tables as needed. + // + GCAP(Local0) + // + // Return status. + // + Return (Local0) + } + + // + // Implement a generic Method to check _PDC information which may be called + // by any of the processor scopes. (The use of _PDC is deprecated in ACPI 3. + // in favor of _OSC. However, for backwards compatibility, _PDC may be + // implemented using _OSC as follows:) + // + Method(CPDC,1) + { + CreateDwordField (Arg0, 0, REVS) + CreateDwordField (Arg0, 4, SIZE) + + // + // Local0 = Number of bytes for Arg0 + // + Store (SizeOf (Arg0), Local0) + + // + // Local1 = Number of Capabilities bytes in Arg0 + // + Store (Subtract (Local0, 8), Local1) + + // + // TEMP = Temporary field holding Capability DWORDs + // + CreateField (Arg0, 64, Multiply (Local1, 8), TEMP) + + // + // Create the Status (STAT) buffer with the first DWORD = 0 + // This is required as per ACPI 3.0 Spec which says the + // first DWORD is used to return errors defined by _OSC. + // + Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00}) + + // + // Concatenate the _PDC capabilities bytes to the STS0 Buffer + // and store them in a local variable for calling OSC + // + Concatenate (STS0, TEMP, Local2) + + Return(COSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2)) + } + + // + // Implement a generic Method to check _OSC information which may be called + // by any of the processor scopes. + // + Method(COSC, 4) + { + // + // Point to Status DWORD in the Arg3 buffer (STATUS) + // + CreateDWordField(Arg3, 0, STS0) + // + // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES) + // + CreateDwordField(Arg3, 4, CAP0) + + // + // _OSC needs to validate the UUID and Revision. + // + // IF Unrecognized UUID + // Return Unrecognized UUID _OSC Failure + // IF Unsupported Revision + // Return Unsupported Revision _OSC Failure + // + // STS0[0] = Reserved + // STS0[1] = _OSC Failure + // STS0[2] = Unrecognized UUID + // STS0[3] = Unsupported Revision + // STS0[4] = Capabilities masked + // + // Note: The comparison method used is necessary due to + // limitations of certain OSes which cannot perform direct + // buffer comparisons. + // + // Create a set of "Input" UUID fields. + // + CreateDwordField(Arg0, 0x0, IID0) + CreateDwordField(Arg0, 0x4, IID1) + CreateDwordField(Arg0, 0x8, IID2) + CreateDwordField(Arg0, 0xC, IID3) + // + // Create a set of "Expected" UUID fields. + // + Name(UID0, ToUUID("4077A616-290C-47BE-9EBD-D87058713953")) + CreateDwordField(UID0, 0x0, EID0) + CreateDwordField(UID0, 0x4, EID1) + CreateDwordField(UID0, 0x8, EID2) + CreateDwordField(UID0, 0xC, EID3) + // + // Verify the input UUID matches the expected UUID. + // + If(LNot(LAnd(LAnd(LEqual(IID0, EID0),LEqual(IID1, EID1)),LAnd(LEqual(IID2, EID2),LEqual(IID3, EID3))))) + { + // + // Return Unrecognized UUID _OSC Failure + // + Store (0x6, STS0) + Return (Arg3) + } + + If(LNot(LEqual(Arg1,1))) + { + // + // Return Unsupported Revision _OSC Failure + // + Store (0xA, STS0) + Return (Arg3) + } + + Return (Arg3) + } + + // + // Get the capability information and load appropriate tables as needed. + // + Method(GCAP, 1) + { + // + // Point to Status DWORD in the Arg0 buffer (STATUS) + // + CreateDWordField(Arg0, 0, STS0) + // + // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES) + // + CreateDwordField(Arg0, 4, CAP0) + + // + // If the UUID was unrecognized or the _OSC revision was unsupported, + // return without updating capabilities. + // + If(LOr(LEqual(STS0,0x6),LEqual(STS0,0xA))) + { + Return() + } + + // + // Check if this is a query (BIT0 of Status = 1). + // If so, mask off the bits we support and return. + // + if (And(STS0, 1)) + { + And(CAP0, 0xBFF, CAP0) + Return() + } + + // + // Store result of PDC. (We clear out the MSB, which was just + // used as a placeholder for the compiler; and then "OR" the + // value in case we get multiple calls, each of which only + // reports partial support.) + // + Or(And(PDC0, 0x7FFFFFFF), CAP0, PDC0) + + // + // Check IF the CST SSDTs should be loaded. + // CFGD[5:1] = C7, C6, C3, C1E, C1 Capable/Enabled + If(And(CFGD, PPM_C_STATES)) + { + // + // Load the CST SSDTs if: + // (1) CMP capable/enabled + // (2) Driver supports multi-processor configurations + // (3) CPU0 CST ISDT is not already loaded + // + // CFGD[9] = Two or more cores enabled + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[4] = OS supports ind. C2/C3 in MP systems + // SDTL[1] = CPU0 CST SSDT Loaded + // + If(LAnd(LAnd(And(CFGD, PPM_CMP),And(PDC0,0x0018)),LNot(And(SDTL,0x02)))) + { + // + // Flag the CST SSDT as loaded for CPU0 + // + Or(SDTL, 0x02, SDTL) + + OperationRegion(CST0,SystemMemory,DeRefOf(Index(SSDT,7)),DeRefOf(Index(SSDT,8))) + Load(CST0, HC0) // Dynamically load the CPU0CST SSDT + } + } + + Return () + } +} + + +Scope(\_PR.CPU1) +{ + // + // Define handles for opregions (used by load.) + // + Name(HI1,0) // Handle to APIST + Name(HC1,0) // Handle to APCST + + Method(_PDC,1) + { + // + // Refer to \_PR.CPU0._PDC for description. + // + Store(\_PR.CPU0.CPDC(Arg0), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(_OSC, 4) + { + // + // Refer to \_PR.CPU0._OSC for description. + // + Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0) + GCAP(Local0) + Return (Local0) + } + + // + // Get the capability information and load appropriate tables as needed. + // + Method(GCAP, 1) + { + // + // Point to Status DWORD in the Arg0 buffer (STATUS) + // + CreateDWordField(Arg0, 0, STS1) + // + // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES) + // + CreateDwordField(Arg0, 4, CAP1) + // + // If the UUID was unrecognized or the _OSC revision was unsupported, + // return without updating capabilities. + // + If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA))) + { + Return() + } + + // + // Check if this is a query (BIT0 of Status = 1). + // If so, mask off the bits we support and return. + // + if (And(STS1, 1)) + { + And(CAP1, 0xBFF, CAP1) + Return() + } + + // + // Store result of PDC. (We clear out the MSB, which was just + // used as a placeholder for the compiler; and then "OR" the + // value in case we get multiple calls, each of which only + // reports partial support.) + // + Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1) + + // + // Attempt to dynamically load the IST SSDTs if: + // (1) Driver supports P-States in MP configurations + // (2) Driver supports direct HW P-State control + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[0] = OS supports direct access of the perf MSR + // + If(LEqual(And(PDC1, 0x0009), 0x0009)) + { + APPT() + } + + // + // Load the CST SSDTs if: + // (1) Driver supports multi-processor configurations + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[4] = OS supports ind. C2/C3 in MP systems + // + If(And(PDC1,0x0018)) + { + APCT() + } + + Store (PDC1, PDC0) + + Return() + } + + // + // Dynamically load the CST SSDTs if: + // (1) C-States are enabled + // (2) SSDT is not already loaded + // + // CFGD[5:1] = Basic C-States supported (C1, C1E, C3, C6, C7) + // SDTL[5] = AP CST SSDT Loaded + // + Method(APCT,0) + { + If(LAnd(And(CFGD,PPM_C_STATES),LNot(And(SDTL,0x20)))) + { + // + // Flag the CST SSDT as loaded for the AP's + // + Or(SDTL, 0x20, SDTL) + // + // Dynamically load the APCST SSDT + // + OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11))) + Load(CST1, HC1) + } + } + + // + // Dynamically load the IST SSDTs if: + // (1) If GV3 capable and enabled + // (2) SSDT is not already loaded + // + // CFGD[0] = GV3 Capable/Enabled + // SDTL[4] = AP IST SSDT Loaded + // + Method(APPT,0) + { + If(LAnd(And(CFGD,PPM_EIST),LNot(And(SDTL,0x10)))) + { + // + // Flag the IST SSDT as loaded for CPU0 + // + Or(SDTL, 0x10, SDTL) + + OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5))) + Load(IST1, HI1) // Dynamically load the CPU1IST SSDT + } + } +} // End CPU1 + + +Scope(\_PR.CPU2) +{ + Method(_PDC,1) + { + // + // Call the _PDC for CPU1. + // + Store(\_PR.CPU0.CPDC(Arg0), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(_OSC, 4) + { + // + // Call the _OSC for CPU1. + // + Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(GCAP,1) + { + // Point to Status DWORD in the Arg0 buffer (STATUS) + CreateDWordField(Arg0, 0, STS2) + + // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES) + CreateDwordField(Arg0, 4, CAP2) + + // + // If the UUID was unrecognized or the _OSC revision was unsupported, + // return without updating capabilities. + // + If(LOr(LEqual(STS2,0x6),LEqual(STS2,0xA))) + { + Return() + } + + // + // Check if this is a query (BIT0 of Status = 1). + // If so, mask off the bits we support and return. + // + if (And(STS2, 1)) + { + And(CAP2, 0xBFF, CAP2) + Return() + } + + // + // Store result of PDC. (We clear out the MSB, which was just + // used as a placeholder for the compiler; and then "OR" the + // value in case we get multiple calls, each of which only + // reports partial support.) + // + Or(And(PDC2, 0x7FFFFFFF), CAP2, PDC2) + // + // Attempt to dynamically load the IST SSDTs if: + // (1) Driver supports P-States in MP configurations + // (2) Driver supports direct HW P-State control + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[0] = OS supports direct access of the perf MSR + // + If(LEqual(And(PDC2, 0x0009), 0x0009)) + { + \_PR.CPU1.APPT() + } + + // + // Load the CST SSDTs if: + // (1) Driver supports multi-processor configurations + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[4] = OS supports ind. C2/C3 in MP systems + // + If(And(PDC2,0x0018)) + { + \_PR.CPU1.APCT() + } + + Store (PDC2, PDC0) + Return() + } +} // End CPU2 + +Scope(\_PR.CPU3) +{ + Method(_PDC,1) + { + // + // Call the _PDC for CPU1. + // + Store(\_PR.CPU0.CPDC(Arg0), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(_OSC, 4) + { + // + // Call the _OSC for CPU1. + // + Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(GCAP,1) + { + // Point to Status DWORD in the Arg0 buffer (STATUS) + CreateDWordField(Arg0, 0, STS3) + + // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES) + CreateDwordField(Arg0, 4, CAP3) + + // + // If the UUID was unrecognized or the _OSC revision was unsupported, + // return without updating capabilities. + // + If(LOr(LEqual(STS3,0x6),LEqual(STS3,0xA))) + { + Return() + } + + // + // Check if this is a query (BIT0 of Status = 1). + // If so, mask off the bits we support and return. + // + if (And(STS3, 1)) + { + And(CAP3, 0xBFF, CAP3) + Return() + } + + // + // Store result of PDC. (We clear out the MSB, which was just + // used as a placeholder for the compiler; and then "OR" the + // value in case we get multiple calls, each of which only + // reports partial support.) + // + Or(And(PDC3, 0x7FFFFFFF), CAP3, PDC3) + // + // Attempt to dynamically load the IST SSDTs if: + // (1) Driver supports P-States in MP configurations + // (2) Driver supports direct HW P-State control + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[0] = OS supports direct access of the perf MSR + // + If(LEqual(And(PDC3, 0x0009), 0x0009)) + { + \_PR.CPU1.APPT() + } + + // + // Load the CST SSDTs if: + // (1) Driver supports multi-processor configurations + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[4] = OS supports ind. C2/C3 in MP systems + // + If(And(PDC3,0x0018)) + { + \_PR.CPU1.APCT() + } + + Store (PDC3, PDC0) + Return() + } +} // End CPU3 + +Scope(\_PR.CPU4) +{ + Method(_PDC,1) + { + // + // Call the _PDC for CPU1. + // + Store(\_PR.CPU0.CPDC(Arg0), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(_OSC, 4) + { + // + // Call the _OSC for CPU1. + // + Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(GCAP,1) + { + // Point to Status DWORD in the Arg0 buffer (STATUS) + CreateDWordField(Arg0, 0, STS4) + + // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES) + CreateDwordField(Arg0, 4, CAP4) + + // + // If the UUID was unrecognized or the _OSC revision was unsupported, + // return without updating capabilities. + // + If(LOr(LEqual(STS4,0x6),LEqual(STS4,0xA))) + { + Return() + } + + // + // Check if this is a query (BIT0 of Status = 1). + // If so, mask off the bits we support and return. + // + if (And(STS4, 1)) + { + And(CAP4, 0xBFF, CAP4) + Return() + } + + // + // Store result of PDC. (We clear out the MSB, which was just + // used as a placeholder for the compiler; and then "OR" the + // value in case we get multiple calls, each of which only + // reports partial support.) + // + Or(And(PDC4, 0x7FFFFFFF), CAP4, PDC4) + // + // Attempt to dynamically load the IST SSDTs if: + // (1) Driver supports P-States in MP configurations + // (2) Driver supports direct HW P-State control + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[0] = OS supports direct access of the perf MSR + // + If(LEqual(And(PDC4, 0x0009), 0x0009)) + { + \_PR.CPU1.APPT() + } + + // + // Load the CST SSDTs if: + // (1) Driver supports multi-processor configurations + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[4] = OS supports ind. C2/C3 in MP systems + // + If(And(PDC4,0x0018)) + { + \_PR.CPU1.APCT() + } + + Store (PDC4, PDC0) + Return() + } +} // End CPU4 + +Scope(\_PR.CPU5) +{ + Method(_PDC,1) + { + // + // Call the _PDC for CPU1. + // + Store(\_PR.CPU0.CPDC(Arg0), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(_OSC, 4) + { + // + // Call the _OSC for CPU1. + // + Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(GCAP,1) + { + // Point to Status DWORD in the Arg0 buffer (STATUS) + CreateDWordField(Arg0, 0, STS5) + + // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES) + CreateDwordField(Arg0, 4, CAP5) + + // + // If the UUID was unrecognized or the _OSC revision was unsupported, + // return without updating capabilities. + // + If(LOr(LEqual(STS5,0x6),LEqual(STS5,0xA))) + { + Return() + } + + // + // Check if this is a query (BIT0 of Status = 1). + // If so, mask off the bits we support and return. + // + if (And(STS5, 1)) + { + And(CAP5, 0xBFF, CAP5) + Return() + } + + // + // Store result of PDC. (We clear out the MSB, which was just + // used as a placeholder for the compiler; and then "OR" the + // value in case we get multiple calls, each of which only + // reports partial support.) + // + Or(And(PDC5, 0x7FFFFFFF), CAP5, PDC5) + // + // Attempt to dynamically load the IST SSDTs if: + // (1) Driver supports P-States in MP configurations + // (2) Driver supports direct HW P-State control + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[0] = OS supports direct access of the perf MSR + // + If(LEqual(And(PDC5, 0x0009), 0x0009)) + { + \_PR.CPU1.APPT() + } + + // + // Load the CST SSDTs if: + // (1) Driver supports multi-processor configurations + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[4] = OS supports ind. C2/C3 in MP systems + // + If(And(PDC5,0x0018)) + { + \_PR.CPU1.APCT() + } + + Store (PDC5, PDC0) + Return() + } +} // End CPU5 + +Scope(\_PR.CPU6) +{ + Method(_PDC,1) + { + // + // Call the _PDC for CPU1. + // + Store(\_PR.CPU0.CPDC(Arg0), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(_OSC, 4) + { + // + // Call the _OSC for CPU1. + // + Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(GCAP,1) + { + // Point to Status DWORD in the Arg0 buffer (STATUS) + CreateDWordField(Arg0, 0, STS6) + + // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES) + CreateDwordField(Arg0, 4, CAP6) + + // + // If the UUID was unrecognized or the _OSC revision was unsupported, + // return without updating capabilities. + // + If(LOr(LEqual(STS6,0x6),LEqual(STS6,0xA))) + { + Return() + } + + // + // Check if this is a query (BIT0 of Status = 1). + // If so, mask off the bits we support and return. + // + if (And(STS6, 1)) + { + And(CAP6, 0xBFF, CAP6) + Return() + } + + // + // Store result of PDC. (We clear out the MSB, which was just + // used as a placeholder for the compiler; and then "OR" the + // value in case we get multiple calls, each of which only + // reports partial support.) + // + Or(And(PDC6, 0x7FFFFFFF), CAP6, PDC6) + // + // Attempt to dynamically load the IST SSDTs if: + // (1) Driver supports P-States in MP configurations + // (2) Driver supports direct HW P-State control + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[0] = OS supports direct access of the perf MSR + // + If(LEqual(And(PDC6, 0x0009), 0x0009)) + { + \_PR.CPU1.APPT() + } + + // + // Load the CST SSDTs if: + // (1) Driver supports multi-processor configurations + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[4] = OS supports ind. C2/C3 in MP systems + // + If(And(PDC6,0x0018)) + { + \_PR.CPU1.APCT() + } + + Store (PDC6, PDC0) + Return() + } +} // End CPU6 + +Scope(\_PR.CPU7) +{ + Method(_PDC,1) + { + // + // Call the _PDC for CPU1. + // + Store(\_PR.CPU0.CPDC(Arg0), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(_OSC, 4) + { + // + // Call the _OSC for CPU1. + // + Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0) + GCAP(Local0) + Return (Local0) + } + + Method(GCAP,1) + { + // Point to Status DWORD in the Arg0 buffer (STATUS) + CreateDWordField(Arg0, 0, STS7) + + // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES) + CreateDwordField(Arg0, 4, CAP7) + + // + // If the UUID was unrecognized or the _OSC revision was unsupported, + // return without updating capabilities. + // + If(LOr(LEqual(STS7,0x6),LEqual(STS7,0xA))) + { + Return() + } + + // + // Check if this is a query (BIT0 of Status = 1). + // If so, mask off the bits we support and return. + // + if (And(STS7, 1)) + { + And(CAP7, 0xBFF, CAP7) + Return() + } + + // + // Store result of PDC. (We clear out the MSB, which was just + // used as a placeholder for the compiler; and then "OR" the + // value in case we get multiple calls, each of which only + // reports partial support.) + // + Or(And(PDC7, 0x7FFFFFFF), CAP7, PDC7) + // + // Attempt to dynamically load the IST SSDTs if: + // (1) Driver supports P-States in MP configurations + // (2) Driver supports direct HW P-State control + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[0] = OS supports direct access of the perf MSR + // + If(LEqual(And(PDC7, 0x0009), 0x0009)) + { + \_PR.CPU1.APPT() + } + + // + // Load the CST SSDTs if: + // (1) Driver supports multi-processor configurations + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[4] = OS supports ind. C2/C3 in MP systems + // + If(And(PDC7,0x0018)) + { + \_PR.CPU1.APCT() + } + + Store (PDC7, PDC0) + Return() + } +} // End CPU7 +} // End of Definition Block diff --git a/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/Ctdp.asl b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/Ctdp.asl new file mode 100644 index 0000000..3ac992f --- /dev/null +++ b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/Ctdp.asl @@ -0,0 +1,310 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Ctdp.asl - Enable CTDP without using a driver or EC, i.e. this is the BIOS only solution. + +Abstract: + + Intel Processor Power Management ACPI Code + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +--*/ + +DefinitionBlock ( + "CTDP.aml", + "SSDT", + 0x01, + "CtdpB", + "CtdpB", + 0x1000 + ) +{ + +External(TCNT, IntObj) +External(PNHM, IntObj) +External(\_SB.PCI0, DeviceObj) +External(\_SB.PCI0.MHBR, FieldUnitObj) +External(\_PR.CPU0, DeviceObj) +External(\_PR.CPU1, DeviceObj) +External(\_PR.CPU2, DeviceObj) +External(\_PR.CPU3, DeviceObj) +External(\_PR.CPU4, DeviceObj) +External(\_PR.CPU5, DeviceObj) +External(\_PR.CPU6, DeviceObj) +External(\_PR.CPU7, DeviceObj) +External(\_PR.CPU0._PPC, IntObj) +External(\_PR.CPU0._PSS, MethodObj) +External(\_SB.PCCD.PENB, IntObj) + +Scope(\_SB.PCI0) +{ + // + // Memory window to the CTDP registers starting at MCHBAR+5000h. + // + OperationRegion (MBAR, SystemMemory, Add(ShiftLeft(MHBR,15),0x5000), 0x1000) + Field (MBAR, ByteAcc, NoLock, Preserve) + { + Offset (0x930), // PACKAGE_POWER_SKU (MCHBAR+0x5930) + PTDP, 15, // TDP Package Power [14:0] + , 1, // reserved [15] + PMIN, 15, // Minimal Package Power [30:16] + , 1, // Reserved [31] + PMAX, 15, // Maximal Package Power [46:32] + , 1, // Reserved [47] + TMAX, 7, // Maximal Time Window [54:48] + Offset (0x938), // PACKAGE_POWER_SKU_UNIT (MCHBAR+0x5938) + PWRU, 4, // Power Units [3:0] + , 4, // Reserved [7:4] + EGYU, 5, // Energy Units [12:8] + , 3, // Reserved [15:13] + TIMU, 4, // Time Units [19:16] + Offset (0x958), // PLATFORM_INFO (MCHBAR+0x5958) + , 32, // [31:0] + LPMS, 1, // LPM Support [32] + CTNL, 2, // CONFIG_TDP_NUM_LEVELS [34:33] + Offset (0x9A0), // TURBO_POWER_LIMIT1 (MCHBAR+0x59A0) + PPL1, 15, // PKG_PWR_LIM_1 [14:0] + PL1E,1, // PKG_PWR_LIM1_EN [15] + , 1, // reserved [16] + PL1T, 7, // PKG_PWR_LIM_1_TIME [23:17] + Offset (0x9A4), // TURBO_POWER_LIMIT2 (MCHBAR+0x59A4) + PPL2, 15, // PKG_PWR_LIM_2 [14:0] + PL2E,1, // PKG_PWR_LIM2_EN [15] + , 1, // reserved [16] + PL2T, 7, // PKG_PWR_LIM_2_TIME [23:17] + Offset (0xF3C), // CONFIG_TDP_NOMINAL (MCHBAR+0x5F3C) + TARN, 8, // TDP Ratio [7:0] + Offset (0xF40), // CONFIG_TDP_LEVEL1 (MCHBAR+0x5F40) + PTD1, 15, // Package TDP [14:0] + , 1, // reserved [15] + TAR1, 8, // TDP Ratio [23:16] + , 8, // reserved [31:24] + PMX1, 15, // Package MAX Power [46:32] + , 1, // reserved [47] + PMN1, 15, // Package MIN Power [62:48] + Offset (0xF48), // CONFIG_TDP_LEVEL2 (MCHBAR+0x5F48) + PTD2, 15, // Package TDP [14:0] + , 1, // reserved [15] + TAR2, 8, // TDP Ratio [23:16] + , 8, // reserved [31:24] + PMX2, 15, // Package MAX Power [46:32] + , 1, // reserved [47] + PMN2, 15, // Package MIN Power [62:48] + Offset (0xF50), // CONFIG_TDP_CONTROL (MCHBAR+0x5F50) + CTCL, 2, // TDP Level [1:0] + , 29, // reserved [30:2] + CLCK, 1, // Config TDP Lock [31] + Offset (0xF54), // TURBO_ACTIVATION_RATIO (MCHBAR+0x5F54) + TAR_, 8, // Max Non Turbo Ratio [7:0] + } + + // CTCU (Config Tdp Control Up) + // + // Program the CTDP Up point. + // + // Arguments: (0) + // None + // Return Value: + // None + // + Method(CTCU) + { + Store(PTD2,PPL1) // Set PL1 + Store(1,PL1E) // Set PL1 enable + Store(CLC2(PTD2),PPL2) // Set PL2 + Store(1,PL2E) // Set PL2 enable + SPPC(1) // Set _PPC + Subtract(TAR2,1,TAR_) // Set TAR + Store(2,CTCL) // Set CTC + } + + // CTCN (Config Tdp Control Nominal) + // + // Program the CTDP Nominal point. + // + // Arguments: (0) + // None + // Return Value: + // None + // + Method(CTCN) + { + If(LEqual(CTCL,1)) // algorithm for going to Nominal from Down + { + Store(PTDP,PPL1) // Set PL1 + Store(1,PL1E) // Set PL1 enable + Store(CLC2(PTDP),PPL2) // Set PL2 + Store(1,PL2E) // Set PL2 enable + NPPC(TARN) // Set _PPC + Subtract(TARN,1,TAR_) // Set TAR + Store(0,CTCL) // Set CTC + } + ElseIf(LEqual(CTCL,2)) // algorithm for going to Nominal from Up + { + Store(0,CTCL) // Set CTC + Subtract(TARN,1,TAR_) // Set TAR + NPPC(TARN) // Set _PPC + Store(CLC2(PTDP),PPL2) // Set PL2 + Store(1,PL2E) // Set PL2 enable + Store(PTDP,PPL1) // Set PL1 + Store(1,PL1E) // Set PL1 enable + } + } + + // CTCD (Config Tdp Control Down) + // + // Program the CTDP Down point. + // + // Arguments: (0) + // None + // Return Value: + // None + // + Method(CTCD) + { + Store(1,CTCL) // Set CTC + Subtract(TAR1,1,TAR_) // Set TAR + NPPC(TAR1) // Set _PPC + Store(CLC2(PTD1),PPL2) // Set PL2 + Store(1,PL2E) // Set PL2 enable + Store(PTD1,PPL1) // Set PL1 + Store(1,PL1E) // Set PL1 enable + } + + // NPPC (Notify _PPC object) + // + // Find the ratio or next highest ratio in the _PSS table and program _PPC with the index of that ratio. + // + // Arguments: (1) + // Arg0 - Turbo Activation Ratio + // Return Value: + // None + // + Method(NPPC,1) + { + Name(TRAT,0) // holder for the target ratio + Name(PRAT,0) // holder for the ratio in _PSS table + Name(TMPI,0) // index + Store(Arg0,TRAT) // init target ratio from caller + Store(SizeOf(\_PR.CPU0._PSS),TMPI) // init index from _PSS + + While(LNotEqual(TMPI,0)){ + Decrement(TMPI) // convert from 1 based count to 0 based count + Store(DeRefOf(Index(DeRefOf(Index(\_PR.CPU0._PSS, TMPI)),4)),PRAT) + ShiftRight(PRAT,8,PRAT) + If(LGreaterEqual(PRAT,TRAT)){ + SPPC(TMPI) + Break + } + } + } + + // SPPC (Set Participant Performance Capability) + // + // Progam the _PPC object and notify the OSPM. + // + // Arguments: (1) + // Arg0 - integer + // Return Value: + // None + // + Method(SPPC,1,Serialized) + { + Store(Arg0, \_PR.CPU0._PPC) // Note: CPU0._PPC is an Integer not a Method + + If(CondRefOf(\_SB.PCCD.PENB)) { // is CPPC enabled in SETUP? + Notify(\_SB.PCCD,0x82) // CPPC notify + } Else { + Switch(ToInteger(TCNT)){ + Case(8){ + Notify(\_PR.CPU0, 0x80) // Tell CPU0 driver to re-eval _PPC + Notify(\_PR.CPU1, 0x80) // Tell CPU1 driver to re-eval _PPC + Notify(\_PR.CPU2, 0x80) // Tell CPU2 driver to re-eval _PPC + Notify(\_PR.CPU3, 0x80) // Tell CPU3 driver to re-eval _PPC + Notify(\_PR.CPU4, 0x80) // Tell CPU4 driver to re-eval _PPC + Notify(\_PR.CPU5, 0x80) // Tell CPU5 driver to re-eval _PPC + Notify(\_PR.CPU6, 0x80) // Tell CPU6 driver to re-eval _PPC + Notify(\_PR.CPU7, 0x80) // Tell CPU7 driver to re-eval _PPC + } + Case(4){ + Notify(\_PR.CPU0, 0x80) // Tell CPU0 driver to re-eval _PPC + Notify(\_PR.CPU1, 0x80) // Tell CPU1 driver to re-eval _PPC + Notify(\_PR.CPU2, 0x80) // Tell CPU2 driver to re-eval _PPC + Notify(\_PR.CPU3, 0x80) // Tell CPU3 driver to re-eval _PPC + } + Case(2){ + Notify(\_PR.CPU0, 0x80) // Tell CPU0 driver to re-eval _PPC + Notify(\_PR.CPU1, 0x80) // Tell CPU1 driver to re-eval _PPC + } + Default{ + Notify(\_PR.CPU0, 0x80) // Tell CPU0 driver to re-eval _PPC + } + } + } + } + + // CLC2 (CaLCulate PL2) + // + // IF Haswell Traditional THEN multiply PL1 by 1.25 to get PL2. + // ELSE IF Haswell ULT THEN use 25 watts as the PL2. + // + // Arguments: (1) + // Arg0 - integer + // Return Value: + // integer + // + Method(CLC2,1) + { + And(PNHM,0x0FFF0FF0,Local0) // remove stepping from CPUID + Switch(Local0){ + Case(0x000306C0){ // Haswell Traditional + Return(Divide(Multiply(Arg0,5),4)) // Multiply a number by 1.25 + } + Case(0x00040650){ // Haswell ULT + Return(Multiply(25,8)) + } + Default{ + Return(Divide(Multiply(Arg0,5),4)) // Multiply a number by 1.25 + } + } + } + +} // end of scope(\_SB.PCI0) +} // end of definition block diff --git a/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/LakeTiny.asl b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/LakeTiny.asl new file mode 100644 index 0000000..1d2922c --- /dev/null +++ b/ReferenceCode/Haswell/PowerManagement/AcpiTables/Ssdt/LakeTiny.asl @@ -0,0 +1,157 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + LakeTiny.asl + +Abstract: + + Intel Processor Power Management ACPI Code - LakeTiny Support + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +--*/ + + +DefinitionBlock ( + "LakeTiny.aml", + "SSDT", + 1, + "PmRef", + "LakeTiny", + 0x3000 + ) +{ +External(\_SB.PCI0.SAT0, DeviceObj) +External(\_SB.PCI0.SAT1, DeviceObj) +External(\PNOT, MethodObj) +External(\_PR.CPU0.GEAR) +External(MPMF) //Bit0: LakeTiny Support Enable/Disable + +Scope(\_SB.PCI0.SAT0) { + // + // Lake Tiny Performance Control Methods + // + Method(SLT1,0, Serialized) + { + If (CondRefOf(\_PR.CPU0.GEAR)) + { + Store (0x00, \_PR.CPU0.GEAR) // Select Lake Tiny CST GEAR 1 + \PNOT () // OS notification for _CST evaluation + } + Return(0) + } + + Method(SLT2,0, Serialized) + { + If (CondRefOf(\_PR.CPU0.GEAR)) + { + Store (0x01, \_PR.CPU0.GEAR) // Select Lake Tiny CST GEAR 2 + \PNOT () // OS notification for _CST evaluation + } + + Return(0) + } + + Method(SLT3,0, Serialized) + { + If (CondRefOf(\_PR.CPU0.GEAR)) + { + Store (0x02, \_PR.CPU0.GEAR) // Select Lake Tiny CST GEAR 3 + \PNOT () // OS notification for _CST evaluation + } + + Return(0) + } + + Method(GLTS,0, Serialized) + { + Store(\_PR.CPU0.GEAR,local0) + ShiftLeft(local0,1,local0) // Bits 1:2 is Gear + Or(local0,0x01,local0) // Bit 0 enable/disable + Return(local0) + } +} + +Scope(\_SB.PCI0.SAT1){ + // + // Lake Tiny Performance Control Methods + // + Method(SLT1,0, Serialized) + { + If (CondRefOf(\_PR.CPU0.GEAR)) + { + Store (0x00, \_PR.CPU0.GEAR) // Select Lake Tiny CST GEAR 1 + \PNOT () // OS notification for _CST evaluation + } + Return(0) + } + + Method(SLT2,0, Serialized) + { + If (CondRefOf(\_PR.CPU0.GEAR)) + { + Store (0x01, \_PR.CPU0.GEAR) // Select Lake Tiny CST GEAR 2 + \PNOT () // OS notification for _CST evaluation + } + + Return(0) + } + + Method(SLT3,0, Serialized) + { + If (CondRefOf(\_PR.CPU0.GEAR)) + { + Store (0x02, \_PR.CPU0.GEAR) // Select Lake Tiny CST GEAR 3 + \PNOT () // OS notification for _CST evaluation + } + + Return(0) + } + + Method(GLTS,0, Serialized) + { + Store(\_PR.CPU0.GEAR,local0) + ShiftLeft(local0,1,local0) // Bits 1:2 is Gear + And(MPMF,01,local1) + Or(local0,local1,local0) // Bit 0 enable/disable + Return(local0) + } +} + +} // End of Definition Block |