diff options
Diffstat (limited to 'ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei')
7 files changed, 661 insertions, 0 deletions
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.c b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.c new file mode 100644 index 0000000..c0badcf --- /dev/null +++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.c @@ -0,0 +1,268 @@ +/** @file + This file is SampleCode for Intel CPU PEI Platform Policy initialization. + +@copyright + Copyright (c) 2010 - 2014 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ +#include "CpuPolicyInitPei.h" + +//(AMI_CHG+)> +VOID CallPeiCpuPolicyInitList( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT PEI_CPU_PLATFORM_POLICY_PPI *PeiCpuPolicyPpi); +//<(AMI_CHG+) +/** + This PEIM performs CPU PEI Platform Policy initialization. + + @param[in] FfsHeader Pointer to Firmware File System file header. + @param[in] PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. +**/ +EFI_STATUS +EFIAPI +CpuPolicyInitPeiEntryPoint ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *CpuPlatformPolicyPpiDesc; + PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi; + CPU_CONFIG_PPI *CpuConfig; + SECURITY_CONFIG_PPI *SecurityConfig; + PFAT_CONFIG *PfatConfig; + POWER_MGMT_CONFIG_PPI *PowerMgmtConfig; + OVERCLOCKING_CONFIG_PPI *OcConfig; + BOOT_GUARD_CONFIG *BootGuardConfig; +#if defined(TXT_SUPPORT_FLAG) && (TXT_SUPPORT_FLAG == 1) + TXT_CONFIG *TxtConfig; +#endif + UINT8 PlatIdStr[] = "SHARK BAY"; + + /// + /// Allocate memory for the CPU Policy Ppi and Descriptor + /// + Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (EFI_PEI_PPI_DESCRIPTOR), &CpuPlatformPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + + Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (PEI_CPU_PLATFORM_POLICY_PPI), &CpuPlatformPolicyPpi); + ASSERT_EFI_ERROR (Status); + + Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (CPU_CONFIG_PPI), &CpuConfig); + ASSERT_EFI_ERROR (Status); + + Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (SECURITY_CONFIG_PPI), &SecurityConfig); + ASSERT_EFI_ERROR (Status); + + Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (PFAT_CONFIG), &PfatConfig); + ASSERT_EFI_ERROR (Status); + + Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (POWER_MGMT_CONFIG_PPI), &PowerMgmtConfig); + ASSERT_EFI_ERROR (Status); + + Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (OVERCLOCKING_CONFIG_PPI), &OcConfig); + ASSERT_EFI_ERROR (Status); + +#if defined(TXT_SUPPORT_FLAG) && (TXT_SUPPORT_FLAG == 1) + Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (TXT_CONFIG), &TxtConfig); + ASSERT_EFI_ERROR (Status); +#endif + + Status = ((*PeiServices)->AllocatePool) (PeiServices, sizeof (BOOT_GUARD_CONFIG), &BootGuardConfig); + ASSERT_EFI_ERROR (Status); + + CpuPlatformPolicyPpi->Revision = PEI_CPU_PLATFORM_POLICY_PPI_REVISION_8; + CpuPlatformPolicyPpi->CpuConfig = CpuConfig; + CpuPlatformPolicyPpi->SecurityConfig = SecurityConfig; + CpuPlatformPolicyPpi->SecurityConfig->PfatConfig = PfatConfig; + CpuPlatformPolicyPpi->PowerMgmtConfig = PowerMgmtConfig; + CpuPlatformPolicyPpi->OverclockingConfig = OcConfig; + CpuPlatformPolicyPpi->CpuPlatformPpiPtr = (UINTN) CpuPlatformPolicyPpi; + +#if defined(TXT_SUPPORT_FLAG) && (TXT_SUPPORT_FLAG == 1) + CpuPlatformPolicyPpi->SecurityConfig->TxtConfig = TxtConfig; +#else + CpuPlatformPolicyPpi->SecurityConfig->TxtConfig = NULL; +#endif + + CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig = BootGuardConfig; + + CpuConfig->CpuRatioOverride = CPU_FEATURE_DISABLE; + CpuConfig->CpuRatio = 63; + CpuConfig->CpuMaxNonTurboRatio = 63; + CpuConfig->BistOnReset = CPU_FEATURE_DISABLE; + CpuConfig->HyperThreading = CPU_FEATURE_ENABLE; + CpuConfig->VmxEnable = CPU_FEATURE_ENABLE; + CpuConfig->ActiveCoreCount = 0; + + /// + /// If CpuConfig->Pfat is set to ENABLE '1' then + /// PlatformData->SmmBwp (found in PchPolicyInitPei.c file) has to be set to ENABLE '1' + /// This is a PFAT Security requirement that needs to be addressed + /// If CpuConfig->Pfat is set to DISABLE '0' then + /// PlatformData->SmmBwp (found in PchPolicyInitPei.c file) value don't care, it can be + /// set to either ENABLE '1' or DISABLE '0' based on customer implementation + /// + CpuConfig->Pfat = CPU_FEATURE_DISABLE; + ZeroMem (&PfatConfig->Ppdt, sizeof (PPDT)); + PfatConfig->Ppdt.PpdtMajVer = PPDT_MAJOR_VERSION; + PfatConfig->Ppdt.PpdtMinVer = PPDT_MINOR_VERSION; + CopyMem (&PfatConfig->Ppdt.PlatId[0], &PlatIdStr[0], sizeof (PlatIdStr)); + PfatConfig->Ppdt.PfatModSvn = PFAT_SVN; + PfatConfig->Ppdt.BiosSvn = 0x01380000; + PfatConfig->Ppdt.ExecLim = 0; + PfatConfig->Ppdt.PlatAttr = 0; + PfatConfig->Ppdt.LastSfam = MIN_SFAM_COUNT - 1; + if (PfatConfig->Ppdt.LastSfam > (MAX_SFAM_COUNT - 1)) { + PfatConfig->Ppdt.LastSfam = MAX_SFAM_COUNT - 1; + } + /// + /// SfamData [LastSfam + 1] + /// + PfatConfig->Ppdt.SfamData[0].FirstByte = 0x00580000; + PfatConfig->Ppdt.SfamData[0].LastByte = 0x0058FFFF; + PfatConfig->Ppdt.PpdtSize = (sizeof (PPDT) - sizeof (PfatConfig->Ppdt.SfamData) + ((PfatConfig->Ppdt.LastSfam + 1) * sizeof (SFAM_DATA))); + PfatConfig->PpdtHash[0] = 0xae7295370672663c; + PfatConfig->PpdtHash[1] = 0x220375c996d23a36; + PfatConfig->PpdtHash[2] = 0x73aaea0f2afded9d; + PfatConfig->PpdtHash[3] = 0x707193b768a0829e; + ZeroMem (&PfatConfig->PupHeader, sizeof (PUP_HEADER)); + PfatConfig->PupHeader.Version = PUP_HDR_VERSION; + CopyMem (&PfatConfig->PupHeader.PlatId[0], &PlatIdStr[0], sizeof (PlatIdStr)); + PfatConfig->PupHeader.PkgAttributes = 0; + PfatConfig->PupHeader.PslMajorVer = PSL_MAJOR_VERSION; + PfatConfig->PupHeader.PslMinorVer = PSL_MINOR_VERSION; + PfatConfig->PupHeader.BiosSvn = PfatConfig->Ppdt.BiosSvn; + PfatConfig->PupHeader.EcSvn = 0; + PfatConfig->PupHeader.VendorSpecific = 0x808655AA; + ZeroMem (&PfatConfig->PfatLog, sizeof (PFAT_LOG)); + PfatConfig->PfatLog.Version = PFAT_LOG_VERSION; + PfatConfig->PfatLog.LastPage = 0; + if (PfatConfig->PfatLog.LastPage > (MAX_PFAT_LOG_PAGE - 1)) { + PfatConfig->PfatLog.LastPage = MAX_PFAT_LOG_PAGE - 1; + } + PfatConfig->PfatLog.LoggingOptions = 0; + PfatConfig->NumSpiComponents = 2; + PfatConfig->ComponentSize[0] = EnumSpiCompSize8MB; + PfatConfig->ComponentSize[1] = EnumSpiCompSize8MB; + PfatConfig->PfatMemSize = 0x05; + + CpuConfig->MlcStreamerPrefetcher = CPU_FEATURE_ENABLE; + CpuConfig->MlcSpatialPrefetcher = CPU_FEATURE_ENABLE; + + PowerMgmtConfig->RatioLimit[0] = 0; + PowerMgmtConfig->RatioLimit[1] = 0; + PowerMgmtConfig->RatioLimit[2] = 0; + PowerMgmtConfig->RatioLimit[3] = 0; + PowerMgmtConfig->TccActivationOffset = 0; + PowerMgmtConfig->VrCurrentLimit = VR_CURRENT_DEFAULT; + PowerMgmtConfig->VrCurrentLimitLock = CPU_FEATURE_DISABLE; + PowerMgmtConfig->Xe = CPU_FEATURE_DISABLE; + PowerMgmtConfig->BootInLfm = CPU_FEATURE_DISABLE; + /// + /// VrMiscIoutSlope = 0x200 default + /// VrMiscIoutOffsetSign = 0 means it's positive offset. 1= negative offset + /// VrMiscIoutOffset = 0 means it's 0%, 625 means 6.25% (range is +6.25% ~ -6.25%) + /// + PowerMgmtConfig->VrMiscIoutSlope = 0x200; + PowerMgmtConfig->VrMiscIoutOffsetSign = 0; + PowerMgmtConfig->VrMiscIoutOffset = 0; + + PowerMgmtConfig->VrMiscMinVid = V_MSR_VR_MISC_CONFIG_MIN_VID_DEFAULT; + PowerMgmtConfig->VrMiscIdleExitRampRate = CPU_FEATURE_ENABLE; + PowerMgmtConfig->VrMiscIdleEntryRampRate = CPU_FEATURE_DISABLE; + PowerMgmtConfig->VrMiscIdleEntryDecayEnable = CPU_FEATURE_ENABLE; + if (GetCpuFamily() == EnumCpuHswUlt) { + PowerMgmtConfig->VrMiscSlowSlewRateConfig = V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_DEFAULT; + PowerMgmtConfig->VrMisc2FastRampVoltage = V_MSR_VR_MISC_CONFIG2_FAST_RAMP_VOLTAGE_DEFAULT; + PowerMgmtConfig->VrMisc2MinC8Voltage = V_MSR_VR_MISC_CONFIG2_MIN_C8_VOLTAGE_DEFAULT; + PowerMgmtConfig->VrPSI4enable = CPU_FEATURE_ENABLE; + } + PowerMgmtConfig->Psi1Threshold = PSI1_THRESHOLD_DEFAULT; + PowerMgmtConfig->Psi2Threshold = PSI2_THRESHOLD_DEFAULT; + PowerMgmtConfig->Psi3Threshold = PSI3_THRESHOLD_DEFAULT; + + PowerMgmtConfig->FivrSscEnable = 1; + PowerMgmtConfig->FivrSscPercent = 62; + + /// + /// Initiate TxT policy + /// +#if defined(TXT_SUPPORT_FLAG) && (TXT_SUPPORT_FLAG == 1) + ZeroMem (TxtConfig, sizeof (TXT_CONFIG)); + CpuConfig->Txt = 0; + TxtConfig->SinitMemorySize = TXT_SINIT_MEMORY_SIZE; + TxtConfig->TxtHeapMemorySize = TXT_HEAP_MEMORY_SIZE; + TxtConfig->TxtDprMemoryBase = 0; + TxtConfig->TxtDprMemorySize = 0; + TxtConfig->BiosAcmBase = 0; + TxtConfig->BiosAcmSize = 0; + TxtConfig->McuUpdateDataAddr = 0; + TxtConfig->TgaSize = TXT_TGA_MEMORY_SIZE; + TxtConfig->TxtLcpPdBase = TXT_LCP_PD_BASE; + TxtConfig->TxtLcpPdSize = TXT_LCP_PD_SIZE; +#endif + /// + /// Initialize Overclocking Data + /// + OcConfig->CoreVoltageOffset = 0; + OcConfig->CoreVoltageOverride = 0; + OcConfig->CoreExtraTurboVoltage = 0; + OcConfig->CoreMaxOcTurboRatio = 0; + OcConfig->ClrVoltageOffset = 0; + OcConfig->ClrVoltageOverride = 0; + OcConfig->ClrExtraTurboVoltage = 0; + OcConfig->ClrMaxOcTurboRatio = 0; + OcConfig->SvidVoltageOverride = 0; + OcConfig->SvidEnable = 0; + OcConfig->FivrFaultsEnable = 0; + OcConfig->FivrEfficiencyEnable = 0; + OcConfig->CoreVoltageMode = 0; + OcConfig->ClrVoltageMode = 0; + OcConfig->OcSupport = 0; + OcConfig->BitReserved = 0; + + // + // Initialize Boot Guard data + // + BootGuardConfig->TpmType = TpmTypeMax; + BootGuardConfig->BypassTpmInit = FALSE; + BootGuardConfig->MeasuredBoot = FALSE; + BootGuardConfig->BootGuardSupport = FALSE; + BootGuardConfig->DisconnectAllTpms = FALSE; + BootGuardConfig->ByPassTpmEventLog = FALSE; + + //AMI_CHG + //UpdatePeiCpuPlatformPolicy (PeiServices, CpuPlatformPolicyPpi); //(AMI_CHG) + CallPeiCpuPolicyInitList(PeiServices, CpuPlatformPolicyPpi); // (AMI_CHG+) + + /// + /// Update the CPU Policy Ppi Descriptor + /// + CpuPlatformPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + CpuPlatformPolicyPpiDesc->Guid = &gPeiCpuPlatformPolicyPpiGuid; + CpuPlatformPolicyPpiDesc->Ppi = CpuPlatformPolicyPpi; + + /// + /// Install the CPU PEI Platform Policy PPI + /// + Status = (**PeiServices).InstallPpi (PeiServices, CpuPlatformPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.dxs b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.dxs new file mode 100644 index 0000000..1e93c04 --- /dev/null +++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.dxs @@ -0,0 +1,41 @@ +/** @file + Dependency expression source file. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + + +// +// Common for R8 and R9 codebase +// +#include "AutoGen.h" +#include "PeimDepex.h" + +// +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase; +// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase. +// +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" +#endif + +#include EFI_PPI_DEPENDENCY (Variable) + +DEPENDENCY_START + PEI_READ_ONLY_VARIABLE_ACCESS_PPI_GUID +DEPENDENCY_END diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.h b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.h new file mode 100644 index 0000000..47a9f2b --- /dev/null +++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.h @@ -0,0 +1,55 @@ +/** @file + Header file for the CpuPeiPolicy PEIM. + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _CPU_POLICY_INIT_PEI_H_ +#define _CPU_POLICY_INIT_PEI_H_ + +/// +/// External include files do NOT need to be explicitly specified in real EDKII +/// environment +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#include "PfatDefinitions.h" +#include EFI_PPI_PRODUCER (CpuPlatformPolicy) +#include "CpuInitPeim.h" +#include "CpuRegs.h" +#include "CpuPlatformLib.h" +#include "PowerMgmtDefinitions.h" +#endif +//#include "CpuPlatformPolicyUpdatePeiLib.h" //(AMI_CHG) + +/// +/// Functions +/// +/** + This PEIM performs CPU PEI Platform Policy initialzation. + + @param[in] FfsHeader Pointer to Firmware File System file header. + @param[in] PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. +**/ +EFI_STATUS +EFIAPI +CpuPolicyInitPeiEntryPoint ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ); +#endif diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.inf b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.inf new file mode 100644 index 0000000..1a07029 --- /dev/null +++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.inf @@ -0,0 +1,87 @@ +## @file +# Component description file for the CpuPolicyInitPei PEIM. +# +#@copyright +# Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = CpuPolicyInitPei +FILE_GUID = 567F05DE-D174-48e4-A7C0-C19868A11F9B +COMPONENT_TYPE = PE32_PEIM + +[sources.common] + CpuPolicyInitPei.h + CpuPolicyInitPei.c +# +# Edk II Glue Driver Entry Point +# + EdkIIGluePeimEntryPoint.c + +[includes.common] + . + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT) + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/CpuInit/Pei +# +# EDK II Glue Library utilizes some standard headers from EDK +# + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Pei/Include + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(PLATFORM_ECP_PACKAGE)/Include + $(PLATFORM_ECP_PACKAGE)/Library/OpensslLib + $(PLATFORM_ECP_PACKAGE)/Library/PeiCryptLib + +[libraries.common] + $(PROJECT_PCH_FAMILY)PpiLib + EdkFrameworkPpiLib + EdkIIGlueBaseIoLibIntrinsic + EdkIIGlueBaseMemoryLib + EdkIIGluePeiDebugLibReportStatusCode + EdkIIGluePeiReportStatusCodeLib + EdkIIGluePeiServicesLib + EdkIIGluePeiMemoryAllocationLib + EdkPpiLib + CpuPpiLib + PlatformPolicyUpdatePeiLib + OpensslLib + PeiCryptLib + CpuPlatformLib + +[nmake.common] + IMAGE_ENTRY_POINT = _ModuleEntryPoint + DPX_SOURCE = CpuPolicyInitPei.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=CpuPolicyInitPeiEntryPoint + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + -D __EDKII_GLUE_BASE_MEMORY_LIB__ \ + -D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_PEI_SERVICES_LIB__ \ + -D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__ diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.cif b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.cif new file mode 100644 index 0000000..c241162 --- /dev/null +++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.cif @@ -0,0 +1,13 @@ +<component> + name = "Cpu Policy PEI" + category = ModulePart + LocalRoot = "ReferenceCode\Haswell\SampleCode\CpuPolicyInit\Pei" + RefName = "Cpu Policy Pei" +[files] +"CpuPolicyPei.sdl" +"CpuPolicyPei.mak" +"CpuPolicyInitPei.c" +"CpuPolicyInitPei.h" +"CpuPolicyInitPei.dxs" +"CpuPolicyInitPei.inf" +<endComponent> diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.mak b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.mak new file mode 100644 index 0000000..3576f9e --- /dev/null +++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.mak @@ -0,0 +1,139 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/Intel Haswell Cpu RC PKG/Cpu Policy PEI/CpuPolicyPei.mak 5 7/02/12 7:23a Davidhsieh $ +# +# $Revision: 5 $ +# +# $Date: 7/02/12 7:23a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/Intel Haswell Cpu RC PKG/Cpu Policy PEI/CpuPolicyPei.mak $ +# +# 5 7/02/12 7:23a Davidhsieh +# +# 4 5/22/12 4:36a Davidhsieh +# Add TXT_SUPPORT_FLAG define +# +# 3 5/14/12 2:20a Davidhsieh +# +# 2 2/23/12 2:46a Davidhsieh +# +# 1 2/07/12 3:56a Davidhsieh +# +# 2 9/21/11 11:22p Davidhsieh +# +# 1 5/06/11 6:06a Davidhsieh +# First release +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** +EDK : CpuPolicyPei + +BUILD_CpuInitPei_DIR = $(BUILD_DIR)\$(CpuPolicyPei_DIR) + +$(BUILD_DIR)\CpuPolicyPei.mak : $(CpuPolicyPei_DIR)\CpuPolicyPei.cif $(BUILD_RULES) + $(CIF2MAK) $(CpuPolicyPei_DIR)\CpuPolicyPei.cif $(CIF2MAK_DEFAULTS) + +CpuPolicyPei : $(BUILD_DIR)\CpuPolicyPei.mak CpuPolicyPeiBin + +CpuPolicyPei_OBJECTS = \ + $(BUILD_CpuInitPei_DIR)\CpuPolicyInitPei.obj + +CpuPolicyPei_MY_INCLUDES= \ + $(EDK_INCLUDES) \ + /I$(PROJECT_CPU_ROOT)\ + /I$(PROJECT_CPU_ROOT)\Include \ + /I$(PROJECT_CPU_ROOT)\Include\Library \ + /I$(PROJECT_CPU_ROOT)\\Library \ + /I$(CpuInitPei_DIR) + +CpuPolicyPei_DEFINES = $(MY_DEFINES)\ + /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=CpuPolicyInitPeiEntryPoint"\ + /D TXT_SUPPORT_FLAG=1 \ + /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + /D __EDKII_GLUE_BASE_LIB__ \ + /D __EDKII_GLUE_BASE_MEMORY_LIB__ \ + /D __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__ \ + /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \ + + +CpuPolicyPei_LIBS =\ + $(PchPlatformLib)\ + $(EfiRuntimeLib_LIB)\ + $(INTEL_PCH_PROTOCOL_LIB)\ + $(EFIRUNTIMELIB)\ + $(EDKFRAMEWORKPPILIB) \ + $(CPUIA32LIB)\ + $(EFIPROTOCOLLIB)\ + $(EdkIIGlueDxeReportStatusCodeLib_LIB)\ + $(EdkIIGluePeiDebugLibReportStatusCode_LIB)\ + $(EdkIIGlueBaseLib_LIB)\ + $(IntelPchPpiLib_LIB)\ + $(EdkIIGlueBaseLibIA32_LIB)\ + $(EdkIIGluePeiHobLib_LIB) \ + $(CpuGuidLib_LIB) \ + $(EdkIIGluePeiServicesLib_LIB) \ + $(EdkIIGluePeiReportStatusCodeLib_LIB) \ + $(PEIHOBLIB) \ + $(EdkIIGlueDxeMemoryAllocationLib_LIB)\ + $(EdkIIGlueBaseIoLibIntrinsic_LIB)\ + $(EdkIIGlueUefiBootServicesTableLib_LIB)\ + $(EdkIIGlueUefiDevicePathLib_LIB)\ + $(EdkIIGlueBasePciLibPciExpress_LIB) \ + $(EdkIIGlueBasePciExpressLib_LIB)\ + $(CPU_PPI_LIB)\ + $(PchPlatformPeiLib_LIB)\ + $(CpuPlatformLib_LIB)\ + $(EFISCRIPTLIB) + +CpuPolicyPeiBin : $(CpuPolicyPei_LIBS) + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\CpuPolicyPei.mak all\ + NAME=CpuPolicyPei\ + MAKEFILE=$(BUILD_DIR)\CpuPolicyPei.mak \ + "MY_INCLUDES=$(CpuPolicyPei_MY_INCLUDES)" \ + "MY_DEFINES=$(CpuPolicyPei_DEFINES)"\ + OBJECTS="$(CpuPolicyPei_OBJECTS)" \ + GUID=0ac2d35d-1c77-1033-a6f8-7ca55df7d0aa\ + ENTRY_POINT=_ModuleEntryPoint \ + TYPE=PEIM \ + EDKIIModule=PEIM\ + DEPEX1=$(CpuPolicyPei_DIR)\CpuPolicyInitPei.dxs \ + DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX \ + COMPRESS=0 + +#--------------------------------------------------------------------------- +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.sdl b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.sdl new file mode 100644 index 0000000..947bdb1 --- /dev/null +++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.sdl @@ -0,0 +1,58 @@ +#**************************************************************************** +#**************************************************************************** +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30071 ** +#** ** +#** Phone (770)-246-8600 ** +#** ** +#**************************************************************************** +#**************************************************************************** +#**************************************************************************** +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/Intel Haswell Cpu RC PKG/Cpu Policy PEI/CpuPolicyPei.sdl 1 2/07/12 3:56a Davidhsieh $ +# +# $Revision: 1 $ +# +# $Date: 2/07/12 3:56a $ +# +#**************************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/Intel Haswell Cpu RC PKG/Cpu Policy PEI/CpuPolicyPei.sdl $ +# +# 1 2/07/12 3:56a Davidhsieh +# +# 1 5/06/11 6:06a Davidhsieh +# First release +# +# +#**************************************************************************** +TOKEN + Name = "CpuPeiPolicySupport" + Value = "1" + Help = "Main switch to enable Cpu Policy Pei support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +PATH + Name = "CpuPolicyPei_DIR" +End + +MODULE + Help = "Includes CpuPeiPolicy.mak to Project" + File = "CpuPolicyPei.mak" +End + +ELINK + Name = "$(BUILD_DIR)\CpuPolicyPei.ffs" + Parent = "FV_BB" + InvokeOrder = AfterParent +End + |