diff options
Diffstat (limited to 'ReferenceCode/Haswell/SampleCode/SecCore/Sec/Ia32/SecCore.inc')
| -rw-r--r-- | ReferenceCode/Haswell/SampleCode/SecCore/Sec/Ia32/SecCore.inc | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/ReferenceCode/Haswell/SampleCode/SecCore/Sec/Ia32/SecCore.inc b/ReferenceCode/Haswell/SampleCode/SecCore/Sec/Ia32/SecCore.inc new file mode 100644 index 0000000..0129cc9 --- /dev/null +++ b/ReferenceCode/Haswell/SampleCode/SecCore/Sec/Ia32/SecCore.inc @@ -0,0 +1,56 @@ +;@file +; SecCore constants and macros +; +;@copyright +; Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +; This software and associated documentation (if any) is furnished +; under a license and may only be used or copied in accordance +; with the terms of the license. Except as permitted by such +; license, no part of this software or documentation may be +; reproduced, stored in a retrieval system, or transmitted in any +; form or by any means without the express written consent of +; Intel Corporation. +; +; This file contains a 'Sample Driver' and is licensed as such +; under the terms of your license agreement with Intel or your +; vendor. This file may be modified by the user, subject to +; the additional terms of the license agreement +; + +; +; Set to 1 to enable debug +; +NO_EVICTION_MODE_DEBUG EQU 1 + +STATUS_CODE MACRO status +IF NO_EVICTION_MODE_DEBUG + mov al, status + out 080h, al +ENDIF +ENDM + +FVHEADER_LEN_OFF EQU 30h +FFSHEADER_LEN EQU 18h + +IMAGE_BASE_ADDRESS EQU 0FFFF0000h + +; +; Set to 1 to enable debug support for "Deterministic BSP selection" +; +AP_ENTRY_DELAY EQU 10h +AP_EXECUTION_DELAY EQU 1000h + +; +; Define the segment used for AP start-up +; It should be on the top of the recovery FV +; Seg = 0100h - (BlockNumber of Recovery FV) +; Here 0FCh = 0100h - 04h +; +AP_SEG EQU 0FFh + +; +; Commands defined in the AP SIPI code +; +AP_SIPI_COLLECT_MAX_RATIO EQU 001h +AP_SIPI_PROGRAM_MAX_RATIO EQU 002h +AP_SIPI_SWITCH_BSP EQU 003h |