From 92cfe6d8628771df1b9d58f281dc92f6afb2a1c7 Mon Sep 17 00:00:00 2001 From: raywu Date: Fri, 15 Jun 2018 23:50:30 +0800 Subject: Bring Up Release 20180615 2350 --- Board/IO/F81866/BSP/PeiIoTable.h | 92 +++++++++++++++++++++++++-------------- CRB/CSP.sdl | 24 ++++++++++ Rom_16MB_Q87.zip | Bin 0 -> 4714829 bytes actionitems.txt | 16 +++---- 4 files changed, 91 insertions(+), 41 deletions(-) create mode 100644 Rom_16MB_Q87.zip diff --git a/Board/IO/F81866/BSP/PeiIoTable.h b/Board/IO/F81866/BSP/PeiIoTable.h index 5bda076..de0a16a 100644 --- a/Board/IO/F81866/BSP/PeiIoTable.h +++ b/Board/IO/F81866/BSP/PeiIoTable.h @@ -26,7 +26,7 @@ // 5 9/16/12 9:38p Elviscai // [TAG] EIPNONE // [Category] Bug Fix -// [Solution] Remove token control, LDN05h index FEh bit7& bit4 to ¡°0¡± +// [Solution] Remove token control, LDN05h index FEh bit7& bit4 to ��0�� // as fixed. // // 4 2/16/12 9:22p Elviscai @@ -195,41 +195,67 @@ SIO_DATA F81866_PEI_Init_Table[] = { //--------------------------------------------------------------------- {F81866_CONFIG_INDEX, 0xFF, 0x26}, {F81866_CONFIG_DATA, 0x3F, F81866_CLOCK << 6}, - #if (F81866_SERIAL_PORT2_PRESENT) - {F81866_CONFIG_INDEX, 0xFF, 0x29}, - {F81866_CONFIG_DATA, 0xCF, 0x30}, - #endif - #if (F81866_SERIAL_PORT3_PRESENT) - {F81866_CONFIG_INDEX, 0xFF, 0x29}, - {F81866_CONFIG_DATA, 0x3F, 0xC0}, - #endif - #if (F81866_MOUSE_PRESENT) - {F81866_CONFIG_INDEX, 0xFF, 0x28}, - {F81866_CONFIG_DATA, 0xEF, 0x00}, - #endif - #if (F81866_SERIAL_PORT4_PRESENT) - {F81866_CONFIG_INDEX, 0xFF, 0x28}, - {F81866_CONFIG_DATA, 0xB3, 0x0C}, - #endif - #if (F81866_SERIAL_PORT5_PRESENT) + //#if (F81866_SERIAL_PORT2_PRESENT) + //{F81866_CONFIG_INDEX, 0xFF, 0x29}, + //{F81866_CONFIG_DATA, 0xCF, 0x30}, + //#endif + //#if (F81866_SERIAL_PORT3_PRESENT) + //{F81866_CONFIG_INDEX, 0xFF, 0x29}, + //{F81866_CONFIG_DATA, 0x3F, 0xC0}, + //#endif + //#if (F81866_MOUSE_PRESENT) + //{F81866_CONFIG_INDEX, 0xFF, 0x28}, + //{F81866_CONFIG_DATA, 0xEF, 0x00}, + //#endif + //#if (F81866_SERIAL_PORT4_PRESENT) + //{F81866_CONFIG_INDEX, 0xFF, 0x28}, + //{F81866_CONFIG_DATA, 0xB3, 0x0C}, + //#endif + //#if (F81866_SERIAL_PORT5_PRESENT) + //{F81866_CONFIG_INDEX, 0xFF, 0x28}, + //{F81866_CONFIG_DATA, 0xBC, 0x03}, + //#endif + //#if (F81866_PARALLEL_PORT_PRESENT) + //{F81866_CONFIG_INDEX, 0xFF, 0x28}, + //{F81866_CONFIG_DATA, 0xDF, 0x00}, + //{F81866_CONFIG_INDEX, 0xFF, 0x2B}, + //{F81866_CONFIG_DATA, 0xFC, 0x00}, + //#endif + //#if (F81866_FLOPPY_PORT_PRESENT) + //{F81866_CONFIG_INDEX, 0xFF, 0x28}, + //{F81866_CONFIG_DATA, 0xB0, 0x00}, + //#endif + // Enable PS/2 KB/MS Wake-up Function + //#if (F81866_KEYBOARD_PRESENT) + //{F81866_CONFIG_INDEX, 0xFF, 0x2D}, + //{F81866_CONFIG_DATA, 0xF7, 0x0F}, + //#endif + {F81866_CONFIG_INDEX, 0xFF, 0x27}, + {F81866_CONFIG_DATA, 0xF3, 0x00}, // GPIO_PROG_SEL = 00b {F81866_CONFIG_INDEX, 0xFF, 0x28}, - {F81866_CONFIG_DATA, 0xBC, 0x03}, - #endif - #if (F81866_PARALLEL_PORT_PRESENT) + {F81866_CONFIG_DATA, 0x80, 0x6F}, + {F81866_CONFIG_INDEX, 0xFF, 0x27}, + {F81866_CONFIG_DATA, 0xF3, 0x04}, // GPIO_PROG_SEL = 01b {F81866_CONFIG_INDEX, 0xFF, 0x28}, - {F81866_CONFIG_DATA, 0xDF, 0x00}, + {F81866_CONFIG_DATA, 0xFC, 0x00}, + {F81866_CONFIG_INDEX, 0xFF, 0x27}, + {F81866_CONFIG_DATA, 0xFE, 0x00}, // CLK_TUNE_PROG_EN = 0b + {F81866_CONFIG_INDEX, 0xFF, 0x29}, + {F81866_CONFIG_DATA, 0xFF, 0xF0}, {F81866_CONFIG_INDEX, 0xFF, 0x2B}, - {F81866_CONFIG_DATA, 0xFC, 0x00}, - #endif - #if (F81866_FLOPPY_PORT_PRESENT) - {F81866_CONFIG_INDEX, 0xFF, 0x28}, - {F81866_CONFIG_DATA, 0xB0, 0x00}, - #endif - // Enable PS/2 KB/MS Wake-up Function - #if (F81866_KEYBOARD_PRESENT) - {F81866_CONFIG_INDEX, 0xFF, 0x2D}, - {F81866_CONFIG_DATA, 0xF7, 0x0F}, - #endif + {F81866_CONFIG_DATA, 0xE3, 0x00}, + {F81866_CONFIG_INDEX, 0xFF, 0x27}, + {F81866_CONFIG_DATA, 0xF2, 0x00}, // GPIO_PROG_SEL = 00b , CLK_TUNE_PROG_EN = 0b + {F81866_CONFIG_INDEX, 0xFF, 0x2C}, + {F81866_CONFIG_DATA, 0xE0, 0x0F}, + {F81866_CONFIG_INDEX, 0xFF, 0x27}, + {F81866_CONFIG_DATA, 0xF2, 0x04}, // GPIO_PROG_SEL = 01b , CLK_TUNE_PROG_EN = 0b + {F81866_CONFIG_INDEX, 0xFF, 0x2C}, + {F81866_CONFIG_DATA, 0x10, 0x6F}, + {F81866_CONFIG_INDEX, 0xFF, 0x27}, + {F81866_CONFIG_DATA, 0xF2, 0x08}, // GPIO_PROG_SEL = 10b , CLK_TUNE_PROG_EN = 0b + {F81866_CONFIG_INDEX, 0xFF, 0x2C}, + {F81866_CONFIG_DATA, 0xFF, 0x01}, //--------------------------------------------------------------------- // Initialize the Serial Port for debug useage. Default is COMA diff --git a/CRB/CSP.sdl b/CRB/CSP.sdl index bcbe442..7531f99 100644 --- a/CRB/CSP.sdl +++ b/CRB/CSP.sdl @@ -620,6 +620,14 @@ TOKEN TargetMAK = Yes Token = "Q87_SKU" "=" "1" End +TOKEN + Name = "H87_SKU" + Value = "0" + Help = "On/Off build this image." + TokenType = Boolean + TargetMAK = Yes + Token = "SELECT_BUILD_PLATFORM" "=" "1" +End ## Board\NB\NB.sdl PCIDEVICE @@ -1286,3 +1294,19 @@ TOKEN TokenType = Boolean TargetH = Yes End + +## Board\IO\F81216\IO_F81216.SDL +TOKEN + Name = "F81216SEC_CLOCK" + Value = "1" + Help = "1/0 for 48Mhz/24MHz" + TokenType = Integer + TargetH = Yes +End +TOKEN + Name = "F81216SEC_CONFIG_MODE_ENTER_VALUE" + Value = "0x67" + Help = "Value to enter Configuration Mode.Please check your hardware\Default is 0x77.\others are 0xA0, 0x87, 0x67" + TokenType = Integer + TargetH = Yes +End diff --git a/Rom_16MB_Q87.zip b/Rom_16MB_Q87.zip new file mode 100644 index 0000000..74d53f4 Binary files /dev/null and b/Rom_16MB_Q87.zip differ diff --git a/actionitems.txt b/actionitems.txt index 110dce5..46ac83f 100644 --- a/actionitems.txt +++ b/actionitems.txt @@ -1,9 +1,9 @@ 2018/06/15 Review decode algorithm - Clock Gen - 2018/06/15 no need - GPIO Multifunction - 2018/06/15 done - VBIOS - 2018/06/15 done - Disable Gbe Controller - 2018/06/15 done +// Clock Gen - 2018/06/15 no need +// GPIO Multifunction - 2018/06/15 done +// VBIOS - 2018/06/15 done +// Disable Gbe Controller - 2018/06/15 done CH7511 Porting Discussion : LAN_DIS PULL H/L Discussion : GPIO32 only GPIO mode @@ -13,7 +13,7 @@ SIO Function Porting SIO PECI / Smart FAN 2018/06/14 - "iAMT_SUPPORT" = 0 - 2018/06/15 done - IntelPTT_SUPPORT = 0 - 2018/06/15 done - review crb.sdl / csp.sdl / xml - 2018/06/15 done - vscc table - 2018/06/15 done \ No newline at end of file +// "iAMT_SUPPORT" = 0 - 2018/06/15 done +// IntelPTT_SUPPORT = 0 - 2018/06/15 done +// review crb.sdl / csp.sdl / xml - 2018/06/15 done +// vscc table - 2018/06/15 done \ No newline at end of file -- cgit v1.2.3