From f48d7df7467a4c801cdbce5cc6cd748979f8baff Mon Sep 17 00:00:00 2001 From: raywu Date: Mon, 17 Sep 2018 10:57:55 +0800 Subject: F81216 ISA/PCI IRQ Share Mode Control --- Board/EM/Platform/AcpiPlatform.c | 6 +++++- .../Library/Protocol/GlobalNvsArea/GlobalNvsArea.h | 1 + Board/IO/F81216/F81216.ASL | 16 ++++++++++++-- Board/IO/F81216/F81216.SD | 9 ++++++++ Board/IO/F81216/F81216.UNI | Bin 12638 -> 13094 bytes Board/IO/F81216/F81216DXE.C | 24 +++++++++++++++++++++ ReferenceCode/AcpiTables/Dsdt/GloblNvs.asl | 1 + 7 files changed, 54 insertions(+), 3 deletions(-) diff --git a/Board/EM/Platform/AcpiPlatform.c b/Board/EM/Platform/AcpiPlatform.c index c0c9bfa..e7cbe97 100644 --- a/Board/EM/Platform/AcpiPlatform.c +++ b/Board/EM/Platform/AcpiPlatform.c @@ -1066,7 +1066,11 @@ AcpiPlatformInit ( } mGlobalNvsArea.Area->Revision = GLOBAL_NVS_AREA_REVISION_1; - + +{ + mGlobalNvsArea.Area->ComIrqShareMode = gSetupData->F81216ComIrqShareMode ; +} + Status = pBS->InstallMultipleProtocolInterfaces (&ImageHandle, &gEfiGlobalNvsAreaProtocolGuid, &mGlobalNvsArea, diff --git a/Board/EM/Platform/Library/Protocol/GlobalNvsArea/GlobalNvsArea.h b/Board/EM/Platform/Library/Protocol/GlobalNvsArea/GlobalNvsArea.h index da4d4ee..0734577 100644 --- a/Board/EM/Platform/Library/Protocol/GlobalNvsArea/GlobalNvsArea.h +++ b/Board/EM/Platform/Library/Protocol/GlobalNvsArea/GlobalNvsArea.h @@ -522,6 +522,7 @@ typedef struct { UINT8 SPST; // (688) SATA port state, Bit0 - Port0, Bit1 - Port1, Bit2 - Port2, Bit3 - Port3 UINT8 ECLP; // (689) EC Low Power Mode: 1 - Enabled, 0 - Disabled UINT8 INSC; // (690) Intel RMT Configuration + UINT8 ComIrqShareMode; } EFI_GLOBAL_NVS_AREA; #pragma pack () diff --git a/Board/IO/F81216/F81216.ASL b/Board/IO/F81216/F81216.ASL index 4158855..6fd12c0 100644 --- a/Board/IO/F81216/F81216.ASL +++ b/Board/IO/F81216/F81216.ASL @@ -415,7 +415,13 @@ Device(SIO2) { // Set IRQ Type:porting according INTT //AMI_TODO: If(And(INTT,0x01)){ - Store(0x18, IRQS) // IRQ Type: Active-Low-Level-Triggered,Shared. + //Store(0x18, IRQS) // IRQ Type: Active-Low-Level-Triggered,Shared. + If( And(INTT, 0x02) ) { + Store(0x19, IRQS) + } + Else { + Store(0x18, IRQS) + } } Else { Store(1, IRQS) // IRQ Type: Active-High-Edge-Triggered,No-Shared(default) } @@ -465,7 +471,13 @@ Device(SIO2) { FindSetRightBit(IRQT, Local0) Subtract(Local0, 1, INTR) //Set IRQ flag,AMI_TODO: bit4:_SHR,bit3:_LL,bit0:_HE - Store(0x01, INTT) //some relative share,active-low/high registers + //Store(0x01, INTT) //some relative share,active-low/high registers + If( LEqual(CISM, 0) ) { + Store(0x01, INTT) + } + Else { + Store(0x03, INTT) + } }Else{ Store(0, INTR) //No IRQ used } diff --git a/Board/IO/F81216/F81216.SD b/Board/IO/F81216/F81216.SD index 37ffad0..d731aa7 100644 --- a/Board/IO/F81216/F81216.SD +++ b/Board/IO/F81216/F81216.SD @@ -64,6 +64,7 @@ /* These definitions will be converted by the build process /* to a definitions of SETUP_DATA fields. /***********************************************************/ + UINT8 F81216ComIrqShareMode ; #endif //SETUP_DATA_DEFINITION //------------------------------------------------------------------------- @@ -187,6 +188,14 @@ endif; #endif + SEPARATOR + oneof varid = SETUP_DATA.F81216ComIrqShareMode,\ + prompt = STRING_TOKEN (STR_IRQ_SHARE_MODE),\ + help = STRING_TOKEN (STR_IRQ_SHARE_MODE),\ + option text = STRING_TOKEN (STR_PCI_SHARE_MODE), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ISA_SHARE_MODE), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + endform;//SIO Form //////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/Board/IO/F81216/F81216.UNI b/Board/IO/F81216/F81216.UNI index 2df933c..f2df75e 100644 Binary files a/Board/IO/F81216/F81216.UNI and b/Board/IO/F81216/F81216.UNI differ diff --git a/Board/IO/F81216/F81216DXE.C b/Board/IO/F81216/F81216DXE.C index 03160b4..4963c1b 100644 --- a/Board/IO/F81216/F81216DXE.C +++ b/Board/IO/F81216/F81216DXE.C @@ -480,6 +480,30 @@ static EFI_STATUS COM_Init( SioCfgMode(dev->Owner, FALSE); dev->VlData.DevIrq1=dev->ResOwner->VlData.DevIrq1; } + + { + EFI_GUID SetupGuid = SETUP_GUID; + UINTN Size = sizeof(SETUP_DATA); + SETUP_DATA SetupData; + + Status = pRS->GetVariable ( L"Setup", \ + &SetupGuid, \ + NULL,\ + &Size, \ + &SetupData ); + + Status=AmiSio->Access(AmiSio,FALSE,FALSE,0x70,&rv); + // PCI Share Mode + if( SetupData.F81216ComIrqShareMode == 0 ) { + rv &= ~(BIT5) ; + rv |= BIT4 ; + } + else { // ISA Share Mode + rv |= BIT5 ; + rv |= BIT4 ; + } + Status=AmiSio->Access(AmiSio,TRUE,FALSE,0x70,&rv); + } break; case isAfterActivate: diff --git a/ReferenceCode/AcpiTables/Dsdt/GloblNvs.asl b/ReferenceCode/AcpiTables/Dsdt/GloblNvs.asl index 07f4381..1c18c04 100644 --- a/ReferenceCode/AcpiTables/Dsdt/GloblNvs.asl +++ b/ReferenceCode/AcpiTables/Dsdt/GloblNvs.asl @@ -424,6 +424,7 @@ SPST, 8, // (688) SATA port state, Bit0 - Port0, Bit1 - Port1, Bit2 - Port2, Bit3 - Port3 ECLP, 8, // (689) EC Low Power Mode: 1 - Enabled, 0 - Disabled INSC, 8, // (690) Intel RMT Configuration + CISM, 8, } #if defined(ASL_Remove_SaSsdt_Data_To_Dsdt) && (ASL_Remove_SaSsdt_Data_To_Dsdt == 1) -- cgit v1.2.3