From b7c51c9cf4864df6aabb99a1ae843becd577237c Mon Sep 17 00:00:00 2001 From: raywu Date: Fri, 15 Jun 2018 00:00:50 +0800 Subject: init. 1AQQW051 --- Board/CPU/Microcode/DESKTOP/DESKTOP.SDL | 1260 ++++++++++++++++++++ Board/CPU/Microcode/DESKTOP/Desktop.CIF | 49 + Board/CPU/Microcode/DESKTOP/M03106A4_00000013.PDB | Bin 0 -> 14336 bytes Board/CPU/Microcode/DESKTOP/M03106A5_0000001B.PDB | Bin 0 -> 10240 bytes Board/CPU/Microcode/DESKTOP/M03206C1_00000006.PDB | Bin 0 -> 6144 bytes Board/CPU/Microcode/DESKTOP/M03206C2_0000001C.PDB | Bin 0 -> 9216 bytes Board/CPU/Microcode/DESKTOP/M07206D1_80000103.PDB | Bin 0 -> 9216 bytes Board/CPU/Microcode/DESKTOP/M0F206D2_8000020A.PDB | Bin 0 -> 15360 bytes Board/CPU/Microcode/DESKTOP/M0F206D3_80000302.PDB | Bin 0 -> 14336 bytes Board/CPU/Microcode/DESKTOP/M1220652_0000000F.PDB | Bin 0 -> 8192 bytes Board/CPU/Microcode/DESKTOP/M12206A1_00000007.PDB | Bin 0 -> 8192 bytes Board/CPU/Microcode/DESKTOP/M12206A2_00000026.PDB | Bin 0 -> 9216 bytes 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24576 bytes Board/CPU/Microcode/MOBILE/M7240650_FFFF000B.PDB | Bin 0 -> 22528 bytes Board/CPU/Microcode/MOBILE/M7240651_00000020.PDB | Bin 0 -> 20480 bytes Board/CPU/Microcode/MOBILE/M9220655_00000005.PDB | Bin 0 -> 3072 bytes Board/CPU/Microcode/MOBILE/MC0306D3_FFFF0010.PDB | Bin 0 -> 17408 bytes Board/CPU/Microcode/MOBILE/MC0306D4_00000025.PDB | Bin 0 -> 17408 bytes Board/CPU/Microcode/MOBILE/MF2306D2_FFFF0009.PDB | Bin 0 -> 17408 bytes Board/CPU/Microcode/MOBILE/MOBILE.SDL | 921 ++++++++++++++ Board/CPU/Microcode/MOBILE/Mobile.CIF | 41 + Board/CPU/Microcode/MPDTable.asm | 16 + Board/CPU/Microcode/MPDTableBB.asm | 16 + Board/CPU/Microcode/Microcode.cif | 15 + Board/CPU/Microcode/Microcode.mak | 195 +++ Board/CPU/Microcode/Microcode.sdl | 150 +++ Board/CPU/Microcode/ServWork/M03106A2_FFFF0019.PDB | Bin 0 -> 11264 bytes Board/CPU/Microcode/ServWork/M03106A4_00000011.PDB | Bin 0 -> 13312 bytes Board/CPU/Microcode/ServWork/M03106A5_0000001B.PDB | Bin 0 -> 10240 bytes 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Board/CPU/Microcode/ServWork/MED306E2_0000020D.PDB | Bin 0 -> 12288 bytes Board/CPU/Microcode/ServWork/MED306E3_00000308.PDB | Bin 0 -> 11264 bytes Board/CPU/Microcode/ServWork/MED306E4_00000428.PDB | Bin 0 -> 13312 bytes Board/CPU/Microcode/ServWork/MED306E6_00000600.PDB | Bin 0 -> 11264 bytes Board/CPU/Microcode/ServWork/MED306E7_0000070D.PDB | Bin 0 -> 15360 bytes Board/CPU/Microcode/ServWork/ServWork.CIF | 42 + Board/CPU/Microcode/ServWork/ServWork.SDL | 1075 +++++++++++++++++ 116 files changed, 3780 insertions(+) create mode 100644 Board/CPU/Microcode/DESKTOP/DESKTOP.SDL create mode 100644 Board/CPU/Microcode/DESKTOP/Desktop.CIF create mode 100644 Board/CPU/Microcode/DESKTOP/M03106A4_00000013.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M03106A5_0000001B.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M03206C1_00000006.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M03206C2_0000001C.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M07206D1_80000103.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M0F206D2_8000020A.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M0F206D3_80000302.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M1220652_0000000F.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M12206A1_00000007.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M12206A2_00000026.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M12206A3_00000008.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M12206A5_00000007.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M12206A6_00000028.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M12206A7_00000029.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M12306A2_00000008.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M12306A4_00000007.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M12306A5_00000007.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M12306A8_00000010.PDB create mode 100644 Board/CPU/Microcode/DESKTOP/M12306A9_0000001C.PDB create mode 100644 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create mode 100644 Board/CPU/Microcode/MOBILE/M32306C3_00000022.PDB create mode 100644 Board/CPU/Microcode/MOBILE/M3240660_FFFF0011.PDB create mode 100644 Board/CPU/Microcode/MOBILE/M3240661_00000017.PDB create mode 100644 Board/CPU/Microcode/MOBILE/M7240650_FFFF000B.PDB create mode 100644 Board/CPU/Microcode/MOBILE/M7240651_00000020.PDB create mode 100644 Board/CPU/Microcode/MOBILE/M9220655_00000005.PDB create mode 100644 Board/CPU/Microcode/MOBILE/MC0306D3_FFFF0010.PDB create mode 100644 Board/CPU/Microcode/MOBILE/MC0306D4_00000025.PDB create mode 100644 Board/CPU/Microcode/MOBILE/MF2306D2_FFFF0009.PDB create mode 100644 Board/CPU/Microcode/MOBILE/MOBILE.SDL create mode 100644 Board/CPU/Microcode/MOBILE/Mobile.CIF create mode 100644 Board/CPU/Microcode/MPDTable.asm create mode 100644 Board/CPU/Microcode/MPDTableBB.asm create mode 100644 Board/CPU/Microcode/Microcode.cif create mode 100644 Board/CPU/Microcode/Microcode.mak create mode 100644 Board/CPU/Microcode/Microcode.sdl create mode 100644 Board/CPU/Microcode/ServWork/M03106A2_FFFF0019.PDB create mode 100644 Board/CPU/Microcode/ServWork/M03106A4_00000011.PDB create mode 100644 Board/CPU/Microcode/ServWork/M03106A5_0000001B.PDB create mode 100644 Board/CPU/Microcode/ServWork/M03206C1_00000006.PDB create mode 100644 Board/CPU/Microcode/ServWork/M03206C2_0000001D.PDB create mode 100644 Board/CPU/Microcode/ServWork/M04206E6_0000000B.PDB create mode 100644 Board/CPU/Microcode/ServWork/M05206E0_FFFF0005.PDB create mode 100644 Board/CPU/Microcode/ServWork/M05206E1_FFFF0006.PDB create mode 100644 Board/CPU/Microcode/ServWork/M05206E2_FFFF0004.PDB create mode 100644 Board/CPU/Microcode/ServWork/M05206E3_FFFF000C.PDB create mode 100644 Board/CPU/Microcode/ServWork/M05206E5_FFFF0016.PDB create mode 100644 Board/CPU/Microcode/ServWork/M05206F0_FFFF0013.PDB create mode 100644 Board/CPU/Microcode/ServWork/M05206F1_00000008.PDB create mode 100644 Board/CPU/Microcode/ServWork/M05206F2_00000039.PDB create mode 100644 Board/CPU/Microcode/ServWork/M07206D0_80000006.PDB create mode 100644 Board/CPU/Microcode/ServWork/M07206D1_80000106.PDB create mode 100644 Board/CPU/Microcode/ServWork/M0F206D2_8000020C.PDB create mode 100644 Board/CPU/Microcode/ServWork/M0F206D3_80000304.PDB create mode 100644 Board/CPU/Microcode/ServWork/M1220652_0000000F.PDB create mode 100644 Board/CPU/Microcode/ServWork/M12206A7_00000029.PDB create mode 100644 Board/CPU/Microcode/ServWork/M12306A9_0000001C.PDB create mode 100644 Board/CPU/Microcode/ServWork/M13106E5_00000008.PDB create mode 100644 Board/CPU/Microcode/ServWork/M13206C0_FFFF0016.PDB create mode 100644 Board/CPU/Microcode/ServWork/M32306C1_FFFF000D.PDB create mode 100644 Board/CPU/Microcode/ServWork/M32306C3_0000001D.PDB create mode 100644 Board/CPU/Microcode/ServWork/M6D206D5_00000513.PDB create mode 100644 Board/CPU/Microcode/ServWork/M6D206D6_00000619.PDB create mode 100644 Board/CPU/Microcode/ServWork/M6D206D7_00000710.PDB create mode 100644 Board/CPU/Microcode/ServWork/MED306E0_00000008.PDB create mode 100644 Board/CPU/Microcode/ServWork/MED306E2_0000020D.PDB create mode 100644 Board/CPU/Microcode/ServWork/MED306E3_00000308.PDB create mode 100644 Board/CPU/Microcode/ServWork/MED306E4_00000428.PDB create mode 100644 Board/CPU/Microcode/ServWork/MED306E6_00000600.PDB create mode 100644 Board/CPU/Microcode/ServWork/MED306E7_0000070D.PDB create mode 100644 Board/CPU/Microcode/ServWork/ServWork.CIF create mode 100644 Board/CPU/Microcode/ServWork/ServWork.SDL (limited to 'Board/CPU/Microcode') diff --git a/Board/CPU/Microcode/DESKTOP/DESKTOP.SDL b/Board/CPU/Microcode/DESKTOP/DESKTOP.SDL new file mode 100644 index 0000000..60e0b90 --- /dev/null +++ b/Board/CPU/Microcode/DESKTOP/DESKTOP.SDL @@ -0,0 +1,1260 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30071 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* +#**************************************************************************** +# $Header: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/DESKTOP/DESKTOP.SDL 114 2/22/17 1:31a Davidhsieh $ +# +# $Revision: 114 $ +# +# $Date: 2/22/17 1:31a $ +# +#**************************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/DESKTOP/DESKTOP.SDL $ +# +# 114 2/22/17 1:31a Davidhsieh +# [TAG] EIP319448 +# [Category] Spec Update +# [Severity] Important +# [Description] Updated Intel(R) Haswell C-0 Stepping(306C3) version 22 +# +# Updated Intel(R) Broadwell-H G-0 Stepping(40671) version 17 +# +# Updated Intel(R) Haswell Perf Halo C-0 Stepping(40661) version 17 +# +# Update Intel(R) Sandy Bridge-E C-1, M-0 Stepping(206D6) version 619 +# +# Updated Intel(R) Broadwell-E R-0 Stepping(406F1) version 0B00001D +# +# Updated Intel(R) Haswell-E R-2 Stepping(306F2) version 38 +# +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 113 6/17/16 4:05p Artems +# [TAG] EIP275143 +# [Category] Improvement +# [Description] Updated Intel(R) Haswell Processor C-0 Stepping version +# 21 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 112 4/29/16 11:53a Artems +# [TAG] EIP266854 +# [Category] Improvement +# [Description] [Aptio 4_MCU] Intel DT microcode update DT_B_100 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 111 4/29/16 11:31a Artems +# [TAG] EIP265620 +# [Category] Improvement +# [Description] [Aptio 4_MCU] Iintel DT microcode update DT_P_106 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 110 2/19/16 2:46p Artems +# [TAG] EIP256973 +# [Category] Improvement +# [Description] [Aptio4_MCU]Intel DT Processors Microcode Update +# DT_P_103 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 109 8/14/15 5:30p Artems +# [TAG] EIP233803 +# [Description] Updated Clarkdale Processor C-2 Stepping version 0F +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 108 8/10/15 4:27p Artems +# [TAG] EIP232434 +# [Description] Updated Clarkdale Processor K-0 Stepping version 05 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 107 8/05/15 12:01p Artems +# [TAG] EIP231326 +# [Description] Updated Gulftown Processor B-1 Stepping version 1C +# Updated Lynnfield Processor B-1 Stepping version 08 +# Updated Bloomfield Processor D-0 Stepping version 1B +# Updated Bloomfield Processor C-0 Stepping version 13 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 106 7/17/15 6:06p Artems +# [TAG] EIP229101 +# [Category] Improvement +# [Description] Updated Broadwell-H Processor G-0 Stepping version 12 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 105 6/17/15 5:40p Artems +# [TAG] EIP223845 +# [Description] Updated Broadwell-H Processor G-0 Stepping version 11 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 104 5/18/15 4:48p Artems +# [TAG] EIP218685 +# [Category] Improvement +# [Description] Added Broadwell-E Processor L-0 Stepping version 10 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 103 5/14/15 5:08p Artems +# [TAG] EIP217911 +# [Category] Improvement +# [Description] Updated Broadwell-H Processor G-0 Stepping version 10 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 102 5/07/15 3:06p Artems +# +# 101 3/17/15 5:32p Artems +# Updated IvyBridge Processor E-1, L-1 Stepping version 1C +# +# 100 1/12/15 6:23p Artems +# Desktop +# Updated Haswell processor( 306CX) C-0 stepping to version 1D +# +# 99 11/25/14 10:32a Markw +# +# 98 11/20/14 6:13p Markw +# Update dependency. +# +# 97 11/20/14 11:10a Mithunraghavs +# Added Broadwell-H (4067X) E-0 stepping version FFFF0003 +# +# 96 11/06/14 2:48p Markw +# Updated Haswell-E M-0, R2 (306F2) to version 29. +# +# 94 7/21/14 2:59p Craigv +# Updated Haswell C-0 (306C3) to version 1C. +# Updated Haswell Perf Halo C-0 (40661) to version 12. +# Updated Haswell-E M-0 (306F2) to version 23. +# +# 93 6/23/14 12:44p Craigv +# Updated Haswell Perf Halo C-0 (40661) to version 10. +# Updated Haswell C-0 (306C3) to version 1A. +# Updated Ivy Bridge E S-1 (306E4) to version 428. +# Updated Ivy Bridge E-1, L-1 (306A9) to version 1B. +# +# 92 5/29/14 1:17p Craigv +# Updated Haswell C-0 (306C3) to version 19. +# Updated Haswell-E (306F2) M-0 to version 1E. +# +# 91 1/30/14 1:46p Craigv +# Updated IvyBridge-E S-1 (306E4) to version 00000424. +# Updated to production status +# +# 90 1/23/14 5:31p Craigv +# Updated Ivy Bridge-E (306E2) L-1, R-1 to version 0000020D. +# Added Haswell-E (306F2) M-0 version 00000007. +# +# 89 10/23/13 10:02a Mithunraghavs +# The microcode for the Haswell-E processor (Haswell-E), Family 6 Model +# 3F Step 1 (L-0) has been updated from 80000011 to 80000013 +# +# 88 10/16/13 11:50a Markw +# Remove non-production from Haswell Perf C-0 (40661). +# +# 87 10/14/13 6:04p Craigv +# Updated Haswell C-0 (306C3) to version 00000017. +# Updated Haswell Perf Halo C-0 (40661) to version 0000000F. +# +# 86 9/23/13 3:10p Craigv +# Added Haswell-E Processor (306F1) version 80000011. +# +# 85 9/13/13 5:05p Markw +# Updated Intel Lynnfield Xeon B-1 (106E5) to version 7. +# +# 84 8/28/13 10:27a Markw +# Fix e-link 306C3 to point to correct microcode version. +# +# 83 8/27/13 11:38a Markw +# Remove non production from 306C3. +# +# 81 7/26/13 4:37p Craigv +# Updated Intel(R) Haswell Perf Halo Processor C-0 (40661) to version +# 0000000E. +# +# 80 7/18/13 12:22p Craigv +# Updated Intel Lynnfield B-1 (106E5) to version 00000006. +# Updated Intel Clarkdale K-0 (20655) to version 00000004. +# Updated Intel Clarkdale C-2 (20652) to version 0000000E. +# Updated Intel Bloomfield D-0 (106A5) to version 00000019. +# Updated Intel Bloomfield C-0 (106A4) to version 00000012. +# Updated Intel Haswell C-0 (306C3) to version 00000012. +# +# 79 7/15/13 11:37a Craigv +# Updated intel Ivy Bridge-E S-1 (306E4) to version 00000416. +# +# 78 7/02/13 1:50p Craigv +# Updated Gulftown B-1 (206C2) to version 0000001A. +# Updated Haswell C-0 (306C3) to version 00000010. +# +# 77 6/26/13 7:18p Craigv +# Updated Intel SandyBridge-E (206D7) C-2, M-1 to version 00000710. +# Updated Intel Sandy Bridge (206A7) Q-0, D-2 to version 00000029. +# Updated Intel Ivy Bridge (306A9) E-1, L-1 to version 00000019. +# +# 76 6/13/13 3:46p Craigv +# Added Intel Ivy Bridge-E S-1 (306E4) version 413. +# +# 75 5/20/13 3:16p Craigv +# Added Intel Haswell Perf Halo C-0 (40661) version 000A. +# +# 74 5/07/13 11:54a Craigv +# Update Haswell C-0 (306C3) to version 009. +# +# 73 3/22/13 11:25a Craigv +# Update Haswell C-0 (306C3) to version 008. +# +# 72 2/22/13 4:15p Craigv +# Updated Ivy Bridge-E (306E2) L-1 and R-1 to version 0000020C. +# +# 71 2/05/13 12:35p Craigv +# Update Haswell C-0 (306C3) to version 7. +# +# 70 1/28/13 11:38a Craigv +# Update Haswell C-0 (306C3) to version 6. +# +# 69 1/17/13 11:30a Craigv +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 17. +# +# 68 1/15/13 9:52p Craigv +# Added Ivy Bridge-E (306E2) version 00000209. +# +# 67 1/08/13 3:26p Markw +# Update Haswell C-0 (306C3) to version 3 +# +# 66 11/16/12 4:43p Craigv +# +# 65 11/16/12 4:40p Craigv +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 16 +# +# 64 10/30/12 10:20p Markw +# Update Haswell B-0 (306C2) to version FFFF_0006. +# +# 63 10/24/12 10:55a Craigv +# Added Haswell Perf Halo B-0 (40660) version FFFF_0011. +# Update Haswell B-0 (306C2) to version FFFF_0006. +# +# 62 9/19/12 6:03p Craigv +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 15. +# +# 61 7/20/12 2:59p Markw +# Update Haswell A-0 (306C1) to version FFFF0013. +# Update Haswell B-0 (306C2) to version FFFF0003. +# +# 60 5/31/12 11:33a Markw +# Updated help string to use tab instead of spaces for consistency. +# +# 59 5/22/12 5:18p Craigv +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 28. +# Update Sandy Bridge-E C-2, M-1 (206D7) to version 70C. +# +# 58 4/24/12 10:46a Markw +# Add NON_PRODUCTION_MICROCODE dependency to Haswell A-0. +# +# 57 4/23/12 10:52a Craigv +# Added Haswell processor A-0 Stepping version FFFF000D +# +# 56 4/17/12 3:02p Craigv +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 12. +# +# 55 3/26/12 3:52p Markw +# Place pack changes from version 53. +# +# 54 3/26/12 1:48p Craigv +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 26. +# +# 53 3/22/12 11:07a Markw +# Rearrange processor tokens to have the later CPUs earlier in the list. +# +# 52 3/19/12 2:29p Craigv +# Update Sandy Bridge-E C-1, M-0 (206D6) to version 616. +# Update Sandy Bridge-E C-2, M-1 (206D7) to version 70B. +# +# 51 2/29/12 11:01a Craigv +# Update Intel(R) Ivy Bridge Processor E-0 and L-0 (306A8) to version 10. +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 10. +# +# 50 2/14/12 12:37p Craigv +# Update Sandy Bridge-E C-1, M-0 (206D6) to version 615. +# Update Sandy Bridge-E C-2, M-1 (206D7) to version 70A. +# +# 49 2/03/12 4:41p Craigv +# Update Intel(R) Ivy Bridge Processor E-0 and L-0 (306A8) to version C. +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version C. +# +# 48 1/19/12 5:29p Markw +# Update Intel(R) Ivy Bridge Processor E-0 and L-0 (306A8) to version A. +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version A. +# +# 47 1/19/12 12:33p Markw +# Update Sandy Bridge-E C-1, M-0 (206D6) to version 610. +# Update Sandy Bridge-E C-2, M-1 (206D7) to version 705. +# +# 46 1/17/12 1:45p Markw +# Update Intel(R) Ivy Bridge Processor E-0 (306A8) to version 8. +# +# 45 1/09/12 5:45p Markw +# Update Ivy Bridge E-1 (306A9) to Version 8. +# +# 44 12/06/11 4:08p Markw +# Update Sandy Bridge-E C-1 (206D6) to version 60F. +# Update Sandy Bridge-E C-2 (206D7) to version 704. +# Update Ivy Bridge E-0 (306A8) to Version 7. +# +# 43 11/09/11 12:55p Markw +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 25. +# Update Sandy Bridge-E C-1 (206D6) to version 60D. +# Update Lynnfield B-1 (106E5) to version 5. +# +# 42 10/26/11 11:03a Markw +# Update Gulftown B-1 (206C2) to Version 15. +# Update Clarkdale C-2 (20652) to Version 0D. +# Update Clarkdale K-0 (20655) to Version 03. +# +# 41 10/11/11 3:50p Markw +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 23. +# Update Sandybridge-E C-0 (206D5) to version 511. +# Update Sandy Bridge-E C-1 (206D6) to version 60C. +# +# 40 9/28/11 6:26p Markw +# Update Sandy Bridge-E C-0 (206D5) to version 511. +# Update Sandy Bridge-E C-0 (206D6) to version 60B. +# Update Intel(R) Ivy Bridge Processor C-0 (306A4) to version 7. +# Update Intel(R) Ivy Bridge Processor C-1 (306A5) to version 7. +# +# 39 8/29/11 2:55p Markw +# Update Sandy Bridge-E C-0 (206D5) to version 50D. +# Update Intel(R) Ivy Bridge Processor C-0 (306A4) to version 5. +# +# 38 8/10/11 7:07p Markw +# Update Sandybridge-E C-0 (206d5) to version 50B. +# +# 37 8/09/11 10:33a Markw +# Revert DESKTOP back to 0 as default as expected. +# +# 36 8/09/11 10:32a Markw +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 1B. +# Update Sandybridge-E C-0 (206d5) to version 50A. +# +# 35 8/04/11 1:15p Markw +# Update Bloomfield D- 0 (106A5) to version 16. +# Update Sandybridge-E C-0 (206d5) to version 509. +# +# 34 7/27/11 1:33p Markw +# Update Sandy Bridge-E C-0 (206D5) to version 508. +# +# 33 7/12/11 11:46a Markw +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 1A. +# +# 32 6/13/11 5:42p Markw +# Update Gulftown B1 (206C2) to Version 14. +# +# 31 6/03/11 12:23p Markw +# Update Intel(R) Ivy Bridge Processor B-0 (306A2) to version 8. +# +# 30 6/03/11 12:07p Markw +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 18. +# +# 29 5/12/11 5:21p Markw +# Update Bloomfield D-0 (106A5) to version 15. +# +# 28 4/27/11 6:29p Markw +# Update Sandy Bridge-E B-1 (206D3) to version 80000302. +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 17. +# +# 27 3/04/11 12:02p Markw +# Update Sandy Bridge-E B0 (206D1) to version 8000020A. +# +# 26 2/15/11 6:57p Markw +# Update Sandy Bridge-E A1 (206D0) to version 80000103. +# Update Sandy Bridge-E B0 (206D1) to version 80000207. +# +# 25 1/27/11 12:35p Markw +# Update Sandy Bridge D1, Q0 (206A7) to version 14. +# +# 24 1/04/11 10:33a Markw +# Update Sandy Bridge D1, Q0 (206A7) to version 12. +# +# 23 12/16/10 11:28a Markw +# Fixed dependency on M12206A7_0000000D.pdb. +# +# 22 11/30/10 10:22a Markw +# Update Sandy Bridge D1, Q0 (206A7) to version D. +# +# 21 10/15/10 4:41p Markw +# Update Sandy Bridge D1 (206A6) to version 28. +# +# 20 10/08/10 10:36a Markw +# Update Sandy Bridge D0 (206a5) to version 7. +# Add Sandy Bridge D2 (206a7) to version 6. +# +# 19 9/15/10 1:51p Markw +# Update Gulftown B1 (206C2) to Version 13. +# +# 18 9/02/10 5:04p Markw +# Update Gulftown B1 (206C2) to Version 10. +# +# 17 8/12/10 11:19a Markw +# +# 16 7/27/10 10:38a Hari +# Updated Microcode version for Clarkdale C2. +# +# 15 7/26/10 11:06a Hari +# Added Microcode for Sandy Bridge D0 +# +# 14 7/12/10 5:24p Hari +# Added M03206C2_0000000F for Westmere EP processor +# +# 13 6/08/10 6:44p Markw +# Update Sandy Bridge C0 stepping to version 8. +# +# 12 5/28/10 10:24a Markw +# Update Lynnfield B1 and add Clarkdale K0. +# +# 11 4/09/10 11:24a Markw +# Add Sandy Bridge B2. +# +# 10 3/04/10 5:07p Markw +# Add Sandy Bridge B0. +# +# 9 1/20/10 9:49a Markw +# Update Gulftown B0 +# +# 8 1/19/10 11:30p Markw +# Update Gulftown B1. +# +# 7 12/30/09 8:13p Markw +# Add Gulftown A1. +# +# 6 11/24/09 1:11p Markw +# Fix description. +# +# 5 11/24/09 1:07p Markw +# Fix filename. +# +# 4 11/24/09 12:37p Markw +# +# 3 11/24/09 12:30p Markw +# +# 2 10/16/09 9:50a Markw +# +# 1 9/29/09 2:51p Markw +#**************************************************************************** +TOKEN + Name = "DESKTOP" + Value = "0" + Help = "Master Desktop CPU uCode Enable" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Range = "On-Off" +End + +TOKEN + Name = "DESKTOP_406FX" + Value = "0" + Help = "Intel(R) Broadwell-E" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_4067X" + Value = "0" + Help = "Intel(R) Broadwell-H" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_4066X" + Value = "0" + Help = "Intel(R) Haswell Perf Halo" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_306FX" + Value = "0" + Help = "Intel(R) Haswell-E" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_306CX" + Value = "0" + Help = "Intel(R) Haswell" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_306EX" + Value = "0" + Help = "Intel(R) Ivy Bridge-E" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_306AX" + Value = "0" + Help = "Intel(R) Ivy Bridge" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_206DX" + Value = "0" + Help = "Intel(R) SandyBridge-E processors" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_206AX" + Value = "0" + Help = "Intel(R) Sandy Bridge" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_106FX" + Value = "0" + Help = "Intel(R) Havendale" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_2065X" + Value = "0" + Help = "Intel(R) Clarkdale" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_106EX" + Value = "0" + Help = "Intel(R) Clarksfield" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_206CX" + Value = "0" + Help = "Intel(R) Gulftown" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_106AX" + Value = "0" + Help = "Intel(R) Bloomfield" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_M03106A4" + Value = "1" + Help = "Bloomfield C-0" + TokenType = Boolean + Token = "DESKTOP_106AX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M03106A5" + Value = "1" + Help = "Bloomfield D-0" + TokenType = Boolean + Token = "DESKTOP_106AX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M13106E0" + Value = "1" + Help = "Intel(R) Clarksfield A-0" + TokenType = Boolean + Token = "DESKTOP_106EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M13106E1" + Value = "1" + Help = "Intel(R) Clarksfield A-2 \CPU Signature 106E1" + TokenType = Boolean + Token = "DESKTOP_106EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M13106E5" + Value = "1" + Help = "Intel(R) Lynnfield B-1" + TokenType = Boolean + Token = "DESKTOP_106EX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M13206C0" + Value = "1" + Help = "Intel(R) Gulftown A-0" + TokenType = Boolean + Token = "DESKTOP_206CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M03206C1" + Value = "1" + Help = "Intel(R) Gulftown B-0" + TokenType = Boolean + Token = "DESKTOP_206CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M03206C2" + Value = "1" + Help = "Intel(R) Gulftown B-1" + TokenType = Boolean + Token = "DESKTOP_206CX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M1320651" + Value = "1" + Help = "Intel(R) Clarkdale C-0" + TokenType = Boolean + Token = "DESKTOP_2065X" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M1220652" + Value = "1" + Help = "Intel(R) Clarkdale C-2" + TokenType = Boolean + Token = "DESKTOP_2065X" "=" "1" +End + +TOKEN + Name = "DESKTOP_M9220655" + Value = "1" + Help = "Intel(R) Clarkdale K-0" + TokenType = Boolean + Token = "DESKTOP_2065X" "=" "1" +End + +TOKEN + Name = "DESKTOP_M13106F1" + Value = "1" + Help = "Intel(R) Havendale B-0" + TokenType = Boolean + Token = "DESKTOP_106FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M12206A1" + Value = "1" + Help = "Intel(R) Sandy Bridge B-0" + TokenType = Boolean + Token = "DESKTOP_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +END + +TOKEN + Name = "DESKTOP_M12206A2" + Value = "1" + Help = "Intel(R) Sandy Bridge B-2" + TokenType = Boolean + Token = "DESKTOP_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +END + +TOKEN + Name = "DESKTOP_M12206A3" + Value = "1" + Help = "Intel(R) Sandy Bridge C-0" + TokenType = Boolean + Token = "DESKTOP_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +END + +TOKEN + Name = "DESKTOP_M12206A5" + Value = "1" + Help = "Intel(R) Sandy Bridge D-0" + TokenType = Boolean + Token = "DESKTOP_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +END + +TOKEN + Name = "DESKTOP_M12206A6" + Value = "1" + Help = "Intel(R) Sandy Bridge D-1" + TokenType = Boolean + Token = "DESKTOP_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +END + +TOKEN + Name = "DESKTOP_M12206A7" + Value = "1" + Help = "Intel(R) Sandy Bridge D-2 and Q-0" + TokenType = Boolean + Token = "DESKTOP_206AX" "=" "1" +END + +TOKEN + Name = "DESKTOP_M07206D1" + Value = "1" + Help = "Intel(R) SandyBridge-E Processor A-1 Stepping" + TokenType = Boolean + Token = "DESKTOP_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M0F206D2" + Value = "1" + Help = "Intel(R) SandyBridge-E Processor B-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M0F206D3" + Value = "1" + Help = "Intel(R) SandyBridge-E Processor B-1 Stepping" + TokenType = Boolean + Token = "DESKTOP_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M6D206D5" + Value = "1" + Help = "Intel(R) SandyBridge-E Processor C-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M6D206D6" + Value = "1" + Help = "Intel(R) SandyBridge-E Processor C-1 and M-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_206DX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M6D206D7" + Value = "1" + Help = "Intel(R) SandyBridge-E Processor C-2 and M-1 Stepping" + TokenType = Boolean + Token = "DESKTOP_206DX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M12306A2" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor B-0" + TokenType = Boolean + Token = "DESKTOP_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M12306A4" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor C-0" + TokenType = Boolean + Token = "DESKTOP_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M12306A5" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor C-1" + TokenType = Boolean + Token = "DESKTOP_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M12306A8" + Value = "1" + Help = "Intel(R) Ivy Bridge E-0 and L-0" + TokenType = Boolean + Token = "DESKTOP_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M12306A9" + Value = "1" + Help = "Intel(R) Ivy Bridge E-1 and L-1" + TokenType = Boolean + Token = "DESKTOP_306AX" "=" "1" +End + +TOKEN + Name = "DESKTOP_MED306E2" + Value = "1" + Help = "Intel(R) Ivy Bridge-E L-1 R-1" + TokenType = Boolean + Token = "DESKTOP_306EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_MED306E4" + Value = "1" + Help = "Intel(R) Ivy Bridge-E S-1" + TokenType = Boolean + Token = "DESKTOP_306EX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M32306C1" + Value = "1" + Help = "Intel(R) Haswell Processor A-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_306CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M32306C2" + Value = "1" + Help = "Intel(R) Haswell Processor B-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_306CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M32306C3" + Value = "1" + Help = "Intel(R) Haswell C-0" + TokenType = Boolean + Token = "DESKTOP_306CX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M3240660" + Value = "1" + Help = "Intel(R) Haswell Perf Halo Processor B-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_4066X" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M3240661" + Value = "1" + Help = "Intel(R) Haswell Perf Halo Processor C-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_4066X" "=" "1" +End + +TOKEN + Name = "DESKTOP_MEF306F1" + Value = "1" + Help = "Intel(R) Haswell-E Processor L-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_306FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_MEF306F2" + Value = "1" + Help = "Intel(R) Haswell-E Processor M-0, R-2 Stepping" + TokenType = Boolean + Token = "DESKTOP_306FX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M2240671" + Value = "1" + Help = "Intel(R) Broadwell-H Processor E-0, G-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_4067X" "=" "1" +End + +TOKEN + Name = "DESKTOP_MEF406F0" + Value = "1" + Help = "Intel(R) Broadwell-E Processor L-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_406FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_MEF406F1" + Value = "1" + Help = "Intel(R) Broadwell-E Processor R-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_406FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +PATH + Name = "MICROCODE_DESKTOP_DIR" +End + +ELINK + Name = "$(Intel_Desktop)" + Parent = "MICROCODE_FILES" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M03106A4_00000013.PDB" + Parent = "$(Intel_Desktop)" + Help = "Bloomfield C0" + Token = "DESKTOP_M03106A4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M03106A5_0000001B.PDB" + Parent = "$(Intel_Desktop)" + Help = "Bloomfield D0" + Token = "DESKTOP_M03106A5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M13106E0_FFFF001F.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Clarksfield A0" + Token = "DESKTOP_M13106E0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M13106E1_FFFF000D.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Clarksfield A2" + Token = "DESKTOP_M13106E1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M13106E5_00000008.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Lynnfield B1" + Token = "DESKTOP_M13106E5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M13206C0_FFFF0016.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Gulftown A0" + Token = "DESKTOP_M13206C0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M03206C1_00000006.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Gulftown B0" + Token = "DESKTOP_M03206C1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M03206C2_0000001C.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Gulftown B1" + Token = "DESKTOP_M03206C2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M1320651_FFFF0012.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Clarkdale C0" + Token = "DESKTOP_M1320651" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M1220652_0000000F.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Clarkdale C2" + Token = "DESKTOP_M1220652" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M9220655_00000005.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Clarkdale K0" + Token = "DESKTOP_M9220655" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M13106F1_FFFF0007.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Havendale B0" + Token = "DESKTOP_M13106F1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12206A1_00000007.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Sandy Bridge B0" + Token = "DESKTOP_M12206A1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12206A2_00000026.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Sandy Bridge B2" + Token = "DESKTOP_M12206A2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12206A3_00000008.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Sandy Bridge C0" + Token = "DESKTOP_M12206A3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12206A5_00000007.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Sandy Bridge D0" + Token = "DESKTOP_M12206A5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12206A6_00000028.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Sandy Bridge D1" + Token = "DESKTOP_M12206A6" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12206A7_00000029.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Sandy Bridge D2 and Q0" + Token = "DESKTOP_M12206A7" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M07206D1_80000103.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) SandyBridge-E Processor A1 Stepping" + Token = "DESKTOP_M07206D1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M0F206D2_8000020A.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) SandyBridge-E Processor B0 Stepping" + Token = "DESKTOP_M0F206D2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M0F206D3_80000302.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) SandyBridge-E Processor B1 Stepping" + Token = "DESKTOP_M0F206D3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M6D206D5_00000512.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) SandyBridge-E Processor C-0 Stepping" + Token = "DESKTOP_M6D206D5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M6D206D6_00000619.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) SandyBridge-E Processor C-1 and M-0 Stepping" + Token = "DESKTOP_M6D206D6" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M6D206D7_00000710.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) SandyBridge-E Processor C-2 and M-1 Stepping" + Token = "DESKTOP_M6D206D7" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12306A2_00000008.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge B-0" + Token = "DESKTOP_M12306A2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12306A4_00000007.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge C-0" + Token = "DESKTOP_M12306A4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12306A5_00000007.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge C-1" + Token = "DESKTOP_M12306A5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12306A8_00000010.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge E-0 and L-0" + Token = "DESKTOP_M12306A8" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12306A9_0000001C.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge E-1 and L-1" + Token = "DESKTOP_M12306A9" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\MED306E2_0000020D.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge-E L-1 and R-1" + Token = "DESKTOP_MED306E2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\MED306E4_00000428.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge-E S-1" + Token = "DESKTOP_MED306E4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M32306C1_FFFF0013.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell Processor A-0" + Token = "DESKTOP_M32306C1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M32306C2_FFFF0006.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell Processor B-0" + Token = "DESKTOP_M32306C2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M32306C3_00000022.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell C-0" + Token = "DESKTOP_M32306C3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M3240660_FFFF0011.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell Perf Halo Processor B-0 Stepping" + Token = "DESKTOP_M3240660" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M3240661_00000017.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell Perf Halo Processor C-0 Stepping" + Token = "DESKTOP_M3240661" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\MEF306F1_80000013.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell-E Processor L-0 Stepping" + Token = "DESKTOP_MEF306F1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M6F306F2_00000038.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell-E Processor M-0, R-2 Stepping" + Token = "DESKTOP_MEF306F2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M2240671_00000017.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Broadwell-H Processor E-0, G-0 Stepping" + Token = "DESKTOP_M2240671" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\MEF406F0_00000010.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Broadwell-E Processor L-0 Stepping" + Token = "DESKTOP_MEF406F0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\MEF406F1_0B00001D.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Broadwell-E Processor R-0 Stepping" + Token = "DESKTOP_MEF406F1" "=" "1" + InvokeOrder = AfterParent +End \ No newline at end of file diff --git a/Board/CPU/Microcode/DESKTOP/Desktop.CIF b/Board/CPU/Microcode/DESKTOP/Desktop.CIF new file mode 100644 index 0000000..0d660fd --- /dev/null +++ b/Board/CPU/Microcode/DESKTOP/Desktop.CIF @@ -0,0 +1,49 @@ + + name = "Desktop CPU uCode Patches" + category = ModulePart + LocalRoot = "Board\CPU\Microcode\DESKTOP" + RefName = "INTEL_DESKTOP" +[files] +"DESKTOP.SDL" = "SDL FILES" +"M03106A4_00000013.PDB" = "Desktop Microcode Update" +"M03106A5_0000001B.PDB" = "Desktop Microcode Update" +"M13106E0_FFFF001F.PDB" = "Desktop Microcode Update" +"M13106E1_FFFF000D.PDB" = "Desktop Microcode Update" +"M13106E5_00000008.PDB" = "Desktop Microcode Update" +"M13106F1_FFFF0007.PDB" = "Desktop Microcode Update" +"M1320651_FFFF0012.PDB" = "Desktop Microcode Update" +"M1220652_0000000F.PDB" = "Desktop Microcode Update" +"M9220655_00000005.PDB" = "Desktop Microcode Update" +"M12206A1_00000007.PDB" = "Desktop Microcode Update" +"M12206A2_00000026.PDB" = "Desktop Microcode Update" +"M12206A3_00000008.PDB" = "Desktop Microcode Update" +"M12206A5_00000007.PDB" = "Desktop Microcode Update" +"M12206A6_00000028.PDB" = "Desktop Microcode Update" +"M12206A7_00000029.PDB" = "Desktop Microcode Update" +"M13206C0_FFFF0016.PDB" = "Desktop Microcode Update" +"M03206C1_00000006.PDB" = "Desktop Microcode Update" +"M03206C2_0000001C.PDB" = "Desktop Microcode Update" +"M07206D1_80000103.PDB" = "Desktop Microcode Update" +"M0F206D2_8000020A.PDB" = "Desktop Microcode Update" +"M0F206D3_80000302.PDB" = "Desktop Microcode Update" +"M6D206D5_00000512.PDB" = "Desktop Microcode Update" +"M6D206D6_00000619.PDB" = "Desktop Microcode Update" +"M6D206D7_00000710.PDB" = "Desktop Microcode Update" +"M12306A2_00000008.PDB" = "Desktop Microcode Update" +"M12306A4_00000007.PDB" = "Desktop Microcode Update" +"M12306A5_00000007.PDB" = "Desktop Microcode Update" +"M12306A8_00000010.PDB" = "Desktop Microcode Update" +"M12306A9_0000001C.PDB" = "Desktop Microcode Update" +"M32306C1_FFFF0013.PDB" = "Desktop Microcode Update" +"M32306C2_FFFF0006.PDB" = "Desktop Microcode Update" +"M32306C3_00000022.PDB" = "Desktop Microcode Update" +"MED306E2_0000020D.PDB" = "Desktop Microcode Update" +"MED306E4_00000428.PDB" = "Desktop Microcode Update" +"MEF306F1_80000013.PDB" = "Desktop Microcode Update" +"M6F306F2_00000038.PDB" = "Desktop Microcode Update" +"M3240660_FFFF0011.PDB" = "Desktop Microcode Update" +"M3240661_00000017.PDB" = "Desktop Microcode Update" +"M2240671_00000017.PDB" = "Desktop Microcode Update" +"MEF406F0_00000010.PDB" = "Desktop Microcode Update" +"MEF406F1_0B00001D.PDB" = "Desktop Microcode Update" + diff --git a/Board/CPU/Microcode/DESKTOP/M03106A4_00000013.PDB b/Board/CPU/Microcode/DESKTOP/M03106A4_00000013.PDB new file mode 100644 index 0000000..073d1d6 Binary files /dev/null and b/Board/CPU/Microcode/DESKTOP/M03106A4_00000013.PDB differ diff --git a/Board/CPU/Microcode/DESKTOP/M03106A5_0000001B.PDB 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** +#************************************************************************* +#************************************************************************* +#**************************************************************************** +# $Header: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/MOBILE/MOBILE.SDL 80 2/22/17 3:05a Davidhsieh $ +# +# $Revision: 80 $ +# +# $Date: 2/22/17 3:05a $ +# +#**************************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/MOBILE/MOBILE.SDL $ +# +# 80 2/22/17 3:05a Davidhsieh +# [TAG] EIP319448 +# [Category] Spec Update +# [Severity] Important +# [Description] +# Updated Intel(R) Haswell C0 Stepping(306C3) version 22 +# Updated Intel(R) Broadwell-H G0 Stepping(40671) version 17 +# Updated Intel(R) Haswell Perf Halo C0 Stepping(40661) version 17 +# Updated Intel(R) Haswell ULT C0/D0 Stepping(40651) version 20 +# Updated Intel(R) Broadwell E0/F0 Stepping(306D4) version 25 +# +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 79 10/04/16 1:38p Artems +# [TAG] EIP295177 +# [Category] Improvement +# [Description] [Aptio4_MCU] Intel NB Processors Microcode Update +# MOB_P_77/MOB_B_90 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 78 6/17/16 4:09p Artems +# [TAG] EIP275143 +# [Category] Improvement +# [Description] Updated Intel(R) Haswell Processor C-0 Stepping version +# 21 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 77 5/17/16 2:17p Artems +# [TAG] EIP268478 +# [Category] Improvement +# [Description] M32306C3_00000020.TXT | Assembly format, Revision +# 00000020 | C-0 (Haswell) +# M7240651_0000001F.TXT | Assembly format, Revision 0000001F | C-0 +# (Haswell ULT) +# M7240651_0000001F.TXT | Assembly format, Revision 0000001F | D-0 +# (Haswell ULT) +# +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 76 2/26/16 2:01p Artems +# [TAG] EIP258108 +# [Category] Improvement +# [Description] [Aptio4_MCU]Intel DT Processors Microcode Update +# MOB_P_67 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 75 8/14/15 5:31p Artems +# [TAG] EIP233803 +# [Description] Updated Arrandale Processor C-2 Stepping version 0F +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 74 8/10/15 4:25p Artems +# [TAG] EIP232434 +# [Description] Updated Arrandale Processor K-0 Stepping version 05 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 73 8/05/15 11:57a Artems +# [TAG] EIP231326 +# [Description] Updated Clarksfield Processor B-1 Stepping version 08 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 72 7/17/15 6:07p Artems +# [TAG] EIP229101 +# [Description] Updated Broadwell-H Processor G-0 Stepping version 12 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 71 6/17/15 5:42p Artems +# [TAG] EIP223845 +# [Description] Updated Broadwell Processor E-0, F-0 Stepping version +# 21 +# Updated Broadwell-H Processor G-0 Stepping version 11 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 70 5/14/15 5:09p Artems +# [TAG] EIP217911 +# [Category] Improvement +# [Description] Updated Broadwell-H Processor G-0 Stepping version 10 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 69 5/07/15 3:54p Artems +# +# 68 5/07/15 3:22p Artems +# +# 67 3/17/15 5:29p Artems +# Updated IvyBridge Processor E-1, L-1 Stepping version 1C +# +# 66 1/12/15 6:22p Artems +# Mobile +# Updated Haswell processor( 306CX) C-0 stepping to version 1D +# +# 65 7/21/14 3:13p Craigv +# Updated Haswell ULT C-0, D-0 (40651) to version 1C. +# +# 64 7/21/14 2:49p Craigv +# Updated Haswell Perf Halo C-0 (30661) to version 12. +# Updated Haswell C-0 (306C3) to version 1C. +# +# 63 6/23/14 11:59a Craigv +# Updated Haswell Perf Halo (40661) to version 10. +# Updated Haswell ULT C-0, D-0 (40651) to version 18. +# Updated Haswell C-0 (306C3) to version 1A. +# Updated Ivy Bridge E-1, L-1 (306A9) to version 1B. +# +# 62 5/29/14 12:34p Craigv +# Updated Haswell C-0 (306C3) to version 19. +# +# 61 10/16/13 11:54a Markw +# Remove non-production from Haswell Perf Halo C-0 (40661). +# +# 60 10/14/13 4:00p Craigv +# Updated Haswell Processor C-0 (306C3) to version 00000017. +# Updated Haswell ULT C-0, D-0 (40651) to version 00000017. +# Updated Haswell Perf Halo C-0 (40661) to version 0000000F. +# +# 59 8/20/13 4:15p Craigv +# Updated Intel Haswell C-0 (306C3) to version 00000016. +# Updated Intel Haswell ULT C-0 (40651) to version 00000016. +# +# 58 7/26/13 4:36p Craigv +# Updated Intel Haswell Perf Halo Processor C-0 (40661) to version +# 0000000E. +# +# 56 7/18/13 11:30a Craigv +# Updated Intel Haswell C-0 (306C3) to version 00000012. +# Updated Intel Haswell ULT C-0 (40651) to version 00000015. +# +# 55 7/15/13 7:32p Markw +# Fix production settings for newly added microcode. +# +# 54 7/15/13 12:17p Craigv +# Updated Intel Clarksfield B-1 (106E5) to version 00000006. +# Added Intel Arrandale C-2 (20652) version 0000000E. +# Added Intel Arrandale K-0 (20655) version 00000004. +# +# 53 7/02/13 1:54p Craigv +# Updated Haswell C-0 (306C3) to version 00000010. +# Updated Haswell ULT C-0 (40651) to version 00000014. +# +# 52 6/26/13 7:36p Craigv +# Updated Ivy Bridge (306A9) E-1, L-1, N-0 to version 00000019. +# Updated Sandy Bridge (206A7) D-2, J-1 to version 00000029. +# +# 51 5/20/13 2:59p Craigv +# Added Intel Haswell Perf Halo C-0 Stepping (M3240661) version 000A. +# +# 50 5/07/13 12:02p Craigv +# Updated Intel(R) Haswell ULT C-0 (40651) to version 010. +# +# 49 4/17/13 5:39p Craigv +# Updated Intel(R) Haswell ULT C-0 (40651) to version 00A. +# +# 48 3/27/13 2:26p Markw +# Update Haswell ULT C-0 (40651) to version 8. +# +# 47 3/25/13 7:04p Craigv +# Updated Haswell ULT (40651) C-0 to version 006. +# +# 46 3/22/13 11:30a Craigv +# Update Haswell C-0 (306C3) to version 008. +# +# 45 2/06/13 11:30a Markw +# Update help string. +# +# 44 2/05/13 12:38p Craigv +# Update Haswell ULT C-0 (40651) to version 5. +# Update Haswell C-0 (306C3) to version 7. +# +# 43 1/28/13 11:41a Craigv +# Update Haswell C-0 (306C3) to version 6. +# +# 42 1/17/13 11:44a Craigv +# Update Intel(R) Ivy Bridge Processor E-1, L-1 (306A9) to version 17. +# +# 41 1/08/13 3:14p Markw +# Update Haswell ULT C-1 (40651) to version 2. +# Update Haswell C-0 (306C3) to version 4. +# +# 40 12/14/12 12:06p Craigv +# Update Haswell ULT B-0 (40650) to version FFFF_000B. +# +# 39 12/04/12 11:18a Craigv +# Update Haswell ULT B-0 (40650) to version FFFF_000A. +# +# 38 11/16/12 4:31p Craigv +# Update Intel(R) Ivy Bridge Processor E-1, L-1, N-0 (306A9) to version +# 16 +# +# 37 10/30/12 4:01p Craigv +# Update Haswell ULT B-0 (40650) to version FFFF_0009 +# +# 36 10/24/12 10:43a Craigv +# Update Haswell Perf Halo B-0 (40660) to version FFFF_0011. +# Update Haswell B-0 (306C2) to version FFFF_0006. +# +# 35 9/07/12 3:58p Craigv +# Update Intel(R) Ivy Bridge Processor E-1, L-1, N-0 (306A9) to version +# 15 +# +# 34 8/27/12 11:48a Craigv +# Update Haswell ULT B-0 (40650) to version FFFF_0007 +# +# 33 8/14/12 12:59p Craigv +# Update Haswell Perf Halo B-0 (40660) to version FFFF_000B. +# +# 32 8/13/12 7:31p Craigv +# Update Intel(R) Ivy Bridge Processor E-1, L-1, N-0 (306A9) to version +# 13 +# +# 31 7/20/12 11:19a Markw +# Update Haswell A-0 (306C1) to version FFFF_000D. +# Update Haswell B-0 (306C2) to version FFFF_0003. +# Update Haswell ULT B-0 (40650) to version FFFF_0004. +# +# 30 7/09/12 10:16a Markw +# Fix default of Haswell B-0 to be disabled. +# +# 29 7/06/12 5:56p Markw +# +# 28 7/06/12 5:22p Craigv +# Added Haswell processor B-0 Stepping version FFFF000A +# +# 27 5/22/12 12:30p Markw +# Add revision 25 changes back into file. +# +# 26 5/21/12 7:06p Craigv +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 28 +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 and N-0 (306A9) to +# version 12 +# +# 25 4/24/12 10:52a Markw +# Add NON_PRODUCTION_MICROCODE dependency to Haswell A-0. +# Rearrange processor tokens to have the later CPUs earlier in the list. +# +# 24 4/23/12 10:42a Craigv +# Added Haswell processor A-0 Stepping version FFFF000D +# +# 23 4/17/12 3:00p Craigv +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 12. +# +# 22 3/26/12 1:50p Craigv +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 26. +# +# 21 2/29/12 10:55a Craigv +# Update Intel(R) Ivy Bridge Processor E-0 and L-0 (306A8) to version 10. +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 10. +# +# 20 2/02/12 2:30p Markw +# Update Intel(R) Ivy Bridge Processor E-0 and L-0 (306A8) to version C. +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version C. +# +# 19 1/19/12 5:24p Markw +# Update Intel(R) Ivy Bridge Processor E-0 and L-0 (306A8) to version A. +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version A. +# +# 18 1/17/12 1:44p Markw +# Update Intel(R) Ivy Bridge Processor E-0 (306A8) to version 8. +# +# 17 1/09/12 5:47p Markw +# Update Ivy Bridge E-1 (306A9) to Version 8. +# +# 16 12/06/11 4:20p Markw +# Update Intel(R) Ivy Bridge Processor E-0 (306A8) to version 7. +# +# 15 11/09/11 12:23p Markw +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 25. +# +# 14 10/11/11 3:58p Markw +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 23. +# +# 13 9/28/11 6:45p Markw +# Update Intel(R) Ivy Bridge Processor C-0 (306A4) to version 7. +# Update Intel(R) Ivy Bridge Processor K-0 (306A5) to version 7. +# +# 12 8/29/11 2:46p Markw +# Update Intel(R) Ivy Bridge Processor C-0 (306A4) to version 5. +# +# 11 8/09/11 10:34a Markw +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 1B. +# +# 10 7/12/11 10:59a Markw +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 1A. +# +# 9 6/03/11 11:58a Markw +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 18. +# Update Intel(R) Ivy Bridge Processor B-0 (306A2) to version 8. +# +# 8 4/27/11 6:35p Markw +# Update Intel(R) Sandy Bridge Processor D2, J1 (206A7) to version 17. +# +# 7 3/07/11 6:55p Markw +# Update Intel(R) Sandy Bridge Processor D2, J1 (206A7) to version 12. +# +# 6 1/03/11 7:10p Markw +# Update Intel(R) Sandy Bridge Processor D2, J1 (206A7) to version 12. +# +# 5 11/30/10 10:54a Markw +# Updated help string 206A3 is for both C0 and P0. +# +# 4 11/30/10 10:50a Markw +# Update Intel(R) Sandy Bridge Processor D0 (206A5) to version 7. +# Update Intel(R) Sandy Bridge Processor D1 (206A6) to version 28. +# Update Intel(R) Sandy Bridge Processor D2, J1 (206A7) to version D. +# +# 3 6/15/10 1:07p Fasihm +# Add Sandy Bridge stepping A0, B2, C0 (206AX) microcode. +# +# 2 11/24/09 1:02p Markw +# Remove incorrect dependency. +# +# 1 9/29/09 2:51p Markw +# +#**************************************************************************** + +TOKEN + Name = "MOBILE" + Value = "0" + Help = "Master Mobile CPU uCode Enable" + TokenType = Boolean + Master = Yes + Range = "On-Off" +End + +TOKEN + Name = "MOBILE_4067X" + Value = "0" + Help = "Intel(R) Broadwell-H" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_4066X" + Value = "0" + Help = "Intel(R) Haswell Perf Halo" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_4065X" + Value = "0" + Help = "Intel(R) Haswell ULT" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_306DX" + Value = "0" + Help = "Intel(R) Broadwell" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_306CX" + Value = "0" + Help = "Intel(R) Haswell" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_306AX" + Value = "0" + Help = "Intel(R) Ivy Bridge" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_206AX" + Value = "0" + Help = "Intel(R) Sandy Bridge" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_2065X" + Value = "0" + Help = "Intel(R) Arrandale Processor" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_106FX" + Value = "0" + Help = "Intel(R) Auburndale Processor" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_106EX" + Value = "0" + Help = "Intel(R) Clarksfield Processor" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_M1320650" + Value = "1" + Help = "Intel(R) Arrandale Processor A0." + TokenType = Boolean + Token = "MOBILE_2065X" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M1320651" + Value = "1" + Help = "Intel(R) Arrandale Processor C0 Stepping." + TokenType = Boolean + Token = "MOBILE_2065X" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M1220652" + Value = "1" + Help = "Intel(R) Arrandale Processor C-2 Stepping." + TokenType = Boolean + Token = "MOBILE_2065X" "=" "1" +End + +TOKEN + Name = "MOBILE_M9220655" + Value = "1" + Help = "Intel(R) Arrandale Processor K-0 Stepping." + TokenType = Boolean + Token = "MOBILE_2065X" "=" "1" +End + +TOKEN + Name = "MOBILE_M13106F1" + Value = "1" + Help = "Intel(R) Auburndale Processor." + TokenType = Boolean + Token = "MOBILE_106FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + + +TOKEN + Name = "MOBILE_M13106E5" + Value = "1" + Help = "Intel(R) Clarksfield Processor." + TokenType = Boolean + Token = "MOBILE_106EX" "=" "1" +End + +TOKEN + Name = "MOBILE_M13106E3" + Value = "1" + Help = "Intel(R) Clarksfield Processor." + TokenType = Boolean + Token = "MOBILE_106EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12206A0" + Value = "1" + Help = "Intel(R) Sandy Bridge Processor A0" + TokenType = Boolean + Token = "MOBILE_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12206A2" + Value = "1" + Help = "Intel(R) Sandy Bridge Processor B2" + TokenType = Boolean + Token = "MOBILE_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12206A3" + Value = "1" + Help = "Intel(R) Sandy Bridge Processor C0, P0" + TokenType = Boolean + Token = "MOBILE_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12206A5" + Value = "1" + Help = "Intel(R) Sandy Bridge Processor D0" + TokenType = Boolean + Token = "MOBILE_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12206A6" + Value = "1" + Help = "Intel(R) Sandy Bridge Processor D1" + TokenType = Boolean + Token = "MOBILE_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12206A7" + Value = "1" + Help = "Intel(R) Sandy Bridge Processor D2, J1" + TokenType = Boolean + Token = "MOBILE_206AX" "=" "1" +End + +TOKEN + Name = "MOBILE_M12306A2" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor B-0" + TokenType = Boolean + Token = "MOBILE_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12306A4" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor C-0" + TokenType = Boolean + Token = "MOBILE_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12306A5" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor K-0" + TokenType = Boolean + Token = "MOBILE_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12306A8" + Value = "1" + Help = "Intel(R) Ivy Bridge E-0 and L-0" + TokenType = Boolean + Token = "MOBILE_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12306A9" + Value = "1" + Help = "Intel(R) Ivy Bridge E-1, L-1, and N-0" + TokenType = Boolean + Token = "MOBILE_306AX" "=" "1" +End + +TOKEN + Name = "MOBILE_M32306C1" + Value = "1" + Help = "Intel(R) Haswell Processor A-0 Stepping" + TokenType = Boolean + Token = "MOBILE_306CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M32306C2" + Value = "1" + Help = "Intel(R) Haswell Processor B-0 Stepping" + TokenType = Boolean + Token = "MOBILE_306CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_MF2306D2" + Value = "1" + Help = "Intel(R) Broadwell Processor C-0" + TokenType = Boolean + Token = "MOBILE_306DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_MC0306D3" + Value = "1" + Help = "Intel(R) Broadwell Processor D-0" + TokenType = Boolean + Token = "MOBILE_306DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_MC0306D4" + Value = "1" + Help = "Intel(R) Broadwell Processor E-0,F-0" + TokenType = Boolean + Token = "MOBILE_306DX" "=" "1" +End + +TOKEN + Name = "MOBILE_M32306C3" + Value = "1" + Help = "Intel(R) Haswell C-0" + TokenType = Boolean + Token = "MOBILE_306CX" "=" "1" +End + +TOKEN + Name = "MOBILE_M7240650" + Value = "1" + Help = "Intel(R) Haswell ULT B-0" + TokenType = Boolean + Token = "MOBILE_4065X" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M7240651" + Value = "1" + Help = "Intel(R) Haswell ULT C-0" + TokenType = Boolean + Token = "MOBILE_4065X" "=" "1" +End + +TOKEN + Name = "MOBILE_M3240660" + Value = "1" + Help = "Intel(R) Haswell Perf Halo Processor B-0 Stepping" + TokenType = Boolean + Token = "MOBILE_4066X" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M3240661" + Value = "1" + Help = "Intel(R) Haswell Perf Halo Processor C-0 Stepping" + TokenType = Boolean + Token = "MOBILE_4066X" "=" "1" +End + +TOKEN + Name = "MOBILE_M2240671" + Value = "1" + Help = "Intel(R) Broadwell-H Processor G-0" + TokenType = Boolean + Token = "MOBILE_4067X" "=" "1" +End + +PATH + Name = "MICROCODE_MOBILE_DIR" +End + +ELINK + Name = "$(Intel_Mobile)" + Parent = "MICROCODE_FILES" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M1320650_FFFF0008.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Arrandale Processor" + Token = "MOBILE_M1320650" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M1320651_FFFF000F.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Arrandale Processor C0 Stepping" + Token = "MOBILE_M1320651" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M1220652_0000000F.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Arrandale Processor C-2 Stepping" + Token = "MOBILE_M1220652" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M9220655_00000005.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Arrandale Processor K-0 Stepping" + Token = "MOBILE_M9220655" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M13106F1_FFFF0007.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Auburndale Processor" + Token = "MOBILE_M13106F1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M13106E5_00000008.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Clarksfield Processor B-1" + Token = "MOBILE_M13106E5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M13106E3_FFFF0006.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Clarksfield Processor" + Token = "MOBILE_M13106E3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12206A0_00000024.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Sandy Bridge A0" + Token = "MOBILE_M12206A0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12206A2_00000026.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Sandy Bridge B2" + Token = "MOBILE_M12206A2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12206A3_00000008.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Sandy Bridge C0, P0" + Token = "MOBILE_M12206A3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12206A5_00000007.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Sandy Bridge D0" + Token = "MOBILE_M12206A5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12206A6_00000028.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Sandy Bridge D-1" + Token = "MOBILE_M12206A6" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12206A7_00000029.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Sandy Bridge D-2, J-1" + Token = "MOBILE_M12206A7" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12306A2_00000008.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Ivy Bridge B-0" + Token = "MOBILE_M12306A2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12306A4_00000007.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Ivy Bridge C-0" + Token = "MOBILE_M12306A4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12306A5_00000007.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Ivy Bridge K-0" + Token = "MOBILE_M12306A5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12306A8_00000010.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Ivy Bridge E-0 and L-0" + Token = "MOBILE_M12306A8" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12306A9_0000001C.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Ivy Bridge E-1, L-1, and N-0" + Token = "MOBILE_M12306A9" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M32306C1_FFFF0013.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell Processor A-0" + Token = "MOBILE_M32306C1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M32306C2_FFFF0006.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell Processor B-0" + Token = "MOBILE_M32306C2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M32306C3_00000022.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell C-0" + Token = "MOBILE_M32306C3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M7240650_FFFF000B.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell ULT Processor B-0 Stepping" + Token = "MOBILE_M7240650" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M7240651_00000020.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell ULT C-0, D-0" + Token = "MOBILE_M7240651" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M3240660_FFFF0011.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell Perf Halo Processor B-0 Stepping" + Token = "MOBILE_M3240660" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M3240661_00000017.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell Perf Halo Processor C-0 Stepping" + Token = "MOBILE_M3240661" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\MF2306D2_FFFF0009.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Broadwell C-0" + Token = "MOBILE_MF2306D2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\MC0306D3_FFFF0010.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Broadwell D-0" + Token = "MOBILE_MC0306D3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\MC0306D4_00000025.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Broadwell E-0,F-0" + Token = "MOBILE_MC0306D4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M2240671_00000017.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Broadwell-H Processor G-0" + Token = "MOBILE_M2240671" "=" "1" + InvokeOrder = AfterParent +End \ No newline at end of file diff --git a/Board/CPU/Microcode/MOBILE/Mobile.CIF b/Board/CPU/Microcode/MOBILE/Mobile.CIF new file mode 100644 index 0000000..4dd59cf --- /dev/null +++ b/Board/CPU/Microcode/MOBILE/Mobile.CIF @@ -0,0 +1,41 @@ + + Name = "Mobile CPU uCode Patches" + Category = MODULEPART + RefName = "INTEL_MOBILE" + LocalRoot = "Board\CPU\Microcode\MOBILE" + +[PROPERTIES] + +[FILES] + "MOBILE.SDL" = "SDL FILES" + "M13106F1_FFFF0007.PDB" = "MOBILE MICROCODE UPDATES" + "M13106E5_00000008.PDB" = "MOBILE MICROCODE UPDATES" + "M13106E3_FFFF0006.PDB" = "MOBILE MICROCODE UPDATES" + "M1320650_FFFF0008.PDB" = "MOBILE MICROCODE UPDATES" + "M1320651_FFFF000F.PDB" = "MOBILE MICROCODE UPDATES" + "M1220652_0000000F.PDB" = "MOBILE MICROCODE UPDATES" + "M9220655_00000005.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A1_00000005.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A0_00000024.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A2_00000026.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A3_00000008.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A5_00000007.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A6_00000028.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A7_00000029.PDB" = "MOBILE MICROCODE UPDATES" + "M12306A2_00000008.PDB" = "MOBILE MICROCODE UPDATES" + "M12306A4_00000007.PDB" = "MOBILE MICROCODE UPDATES" + "M12306A5_00000007.PDB" = "MOBILE MICROCODE UPDATES" + "M12306A8_00000010.PDB" = "MOBILE MICROCODE UPDATES" + "M12306A9_0000001C.PDB" = "MOBILE MICROCODE UPDATES" + "M32306C1_FFFF0013.PDB" = "MOBILE MICROCODE UPDATES" + "M32306C2_FFFF0006.PDB" = "MOBILE MICROCODE UPDATES" + "M32306C3_00000022.PDB" = "MOBILE MICROCODE UPDATES" + "MF2306D2_FFFF0009.PDB" = "MOBILE MICROCODE UPDATES" + "MC0306D3_FFFF0010.PDB" = "MOBILE MICROCODE UPDATES" + "MC0306D4_00000025.PDB" = "MOBILE MICROCODE UPDATES" + "M7240650_FFFF000B.PDB" = "MOBILE MICROCODE UPDATES" + "M7240651_00000020.PDB" = "MOBILE MICROCODE UPDATES" + "M3240660_FFFF0011.PDB" = "MOBILE MICROCODE UPDATES" + "M3240661_00000017.PDB" = "MOBILE MICROCODE UPDATES" + "M2240671_00000017.PDB" = "MOBILE MICROCODE UPDATES" + diff --git a/Board/CPU/Microcode/MPDTable.asm b/Board/CPU/Microcode/MPDTable.asm new file mode 100644 index 0000000..42bbef1 --- /dev/null +++ b/Board/CPU/Microcode/MPDTable.asm @@ -0,0 +1,16 @@ +include token.equ + +ifndef EFIx64 +.model small +endif + +.data + db 'MPDT' ;Microcode Patch Description Table + db 0 ;Revision + db 0 ;[0] = 0 Non boot block, [0] = 1 boot block + db 0 ;CPU Manufacture: 0 = Intel + db 0 ;Reserved + dd MKF_MICROCODE_ALIGNMENT ;Alignment - Include token .equ + dw 0 ;Reserved + dw 16 ;size of Table +END \ No newline at end of file diff --git a/Board/CPU/Microcode/MPDTableBB.asm b/Board/CPU/Microcode/MPDTableBB.asm new file mode 100644 index 0000000..f143f6e --- /dev/null +++ b/Board/CPU/Microcode/MPDTableBB.asm @@ -0,0 +1,16 @@ +include token.equ + +ifndef EFIx64 +.model small +endif + +.data + db 'MPDT' ;Microcode Patch Description Table + db 0 ;Revision + db 1 ;[0] = 0 Non boot block, [0] = 1 boot block + db 0 ;CPU Manufacture: 0 = Intel + db 0 ;Reserved + dd MKF_MICROCODE_ALIGNMENT ;Alignment - Include token .equ + dw 0 ;Reserved + dw 16 ;size of Table +END \ No newline at end of file diff --git a/Board/CPU/Microcode/Microcode.cif b/Board/CPU/Microcode/Microcode.cif new file mode 100644 index 0000000..c2975a4 --- /dev/null +++ b/Board/CPU/Microcode/Microcode.cif @@ -0,0 +1,15 @@ + + name = "Intel Nehalem Microcode" + category = eModule + LocalRoot = "Board\CPU\Microcode\" + RefName = "Intel_Nehalem_Microcode" +[files] +"Microcode.sdl" +"Microcode.mak" +"MPDTable.asm" +"MPDTableBB.asm" +[parts] +"INTEL_MOBILE" +"INTEL_DESKTOP" +"INTEL_SERVWORK" + diff --git a/Board/CPU/Microcode/Microcode.mak b/Board/CPU/Microcode/Microcode.mak new file mode 100644 index 0000000..a9fd4a7 --- /dev/null +++ b/Board/CPU/Microcode/Microcode.mak @@ -0,0 +1,195 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/Microcode.mak 5 12/20/11 2:43p Markw $ +# +# $Revision: 5 $ +# +# $Date: 12/20/11 2:43p $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/Microcode.mak $ +# +# 5 12/20/11 2:43p Markw +# [TAG] EIPNone +# [Category] Improvement +# [Description] Don't build MPDT binary when SDL token MPDTable_CREATED +# is disable. +# Type binary is not supported by 4.6.3 and earlier, and most projects if +# any using 4.6.3 don't support MPDT. +# [Files] Microcode.mak +# +# 4 7/28/11 5:20p Markw +# [TAG] EIP65726 +# [Category] Improvement +# [Description] Support MPDT - Microcode Patch Description Table. This +# table provides a header for AMI utilities. +# +# [Files] Microcode.cif, Microcode.sdl, Microcode.mak, MPDTable.asm, +# MPDTableBB.asm, Startup32.asm, CpuCspLib.c , MicrocodeUpdate.c +# +# 3 8/27/10 10:49a Markw +# Update microcode to support pack microcode without padding, and support +# microcode in the bootblock and updates in main FV. +# +# 2 6/15/10 1:45p Markw +# Update the microcode.bin path in the build process. +# +# 1 9/29/09 2:51p Markw +# +#********************************************************************** +# +# +# Name: MicroCode.mak +# +# Description: Build the microcode file. +# +# +#********************************************************************** + +MICROCODE_BUILD_DIR = $(BUILD_DIR)\$(MICROCODE_DIR) + +all : MICROCODE + +MICROCODE : MICROCODE_CREATE_BUILD_DIR $(BUILD_DIR)\Microcode.ffs \ +!if "$(MICROCODE_SPLIT_BB_UPDATE)"=="1" + $(BUILD_DIR)\Microcode_Blank.ffs +!ENDIF + + + +$(BUILD_DIR)\Microcode.mak : $(MICROCODE_DIR)\Microcode.mak $(MICROCODE_DIR)\Microcode.cif $(BUILD_RULES) + $(CIF2MAK) $(MICROCODE_DIR)\Microcode.cif $(CIF2MAK_DEFAULTS) + + +$(BUILD_DIR)\MPDTable.bin : $(MICROCODE_DIR)\MPDTable.asm $(BUILD_DIR)\Microcode.mak + $(MAKE) /$(MAKEFLAGS)\ + /f $(BUILD_DIR)\Microcode.mak bin\ + OBJECTS=$(BUILD_DIR)\$(MICROCODE_DIR)\MPDTable.obj\ + NAME=MPDTable\ + MAKEFILE=$(BUILD_DIR)\Microcode.mak \ + TYPE=BINARY + +$(BUILD_DIR)\MPDTableBB.bin : $(MICROCODE_DIR)\MPDTableBB.asm $(BUILD_DIR)\Microcode.mak + $(MAKE) /$(MAKEFLAGS)\ + /f $(BUILD_DIR)\Microcode.mak bin\ + OBJECTS=$(BUILD_DIR)\$(MICROCODE_DIR)\MPDTableBB.obj\ + NAME=MPDTableBB\ + MAKEFILE=$(BUILD_DIR)\Microcode.mak \ + TYPE=BINARY + +MICROCODE_GUID = 17088572-377F-44ef-8F4E-B09FFF46A070 + +MICROCODE_CREATE_BUILD_DIR: + if not exist $(MICROCODE_BUILD_DIR) md $(MICROCODE_BUILD_DIR) + +$(MICROCODE_BUILD_DIR)\Microcode.bin : $(MICROCODE_DIR)\Microcode.mak $(BUILD_DIR)\token.mak \ +!IF "$(MPDTable_CREATED)"=="1" + $(BUILD_DIR)\MPDTable.bin $(BUILD_DIR)\MPDTableBB.bin +!ELSE + #BLANK line for line continuation. +!ENDIF + copy << $(BUILD_DIR)\Microcode.ini +output + MICROCODE_FILES($(MICROCODE_BUILD_DIR)\Microcode.bin) +end +group MICROCODE_FILES + upper=0xffffffff +components +!IF "$(MPDTable_CREATED)"=="1" +!IF "$(MICROCODE_SPLIT_BB_UPDATE)"=="0" + file $(BUILD_DIR)\MPDTable.bin binfile=$(BUILD_DIR)\MPDTable.bin end +!ELSE + file $(BUILD_DIR)\MPDTableBB.bin binfile=$(BUILD_DIR)\MPDTableBB.bin end +!ENDIF +!ENDIF + +!IF "$(MICROCODE_SPLIT_BB_UPDATE)"=="0" +blank MICROCODE_PAD + size=$(MICROCODE_PAD_SIZE) +!IF "$(FLASH_ERASE_POLARITY)"=="0" + pattern=(0) +!ELSE + pattern=(0xFF) +!ENDIF +end +!ENDIF +<> $(BUILD_DIR)\Microcode.ini + echo end end >> $(BUILD_DIR)\Microcode.ini + $(MERGE) /s $(BUILD_DIR)\Microcode.ini + +$(BUILD_DIR)\Microcode.ffs : $(MICROCODE_BUILD_DIR)\microcode.bin + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=17088572-377F-44ef-8F4E-B09FFF46A070\ + TYPE=EFI_FV_FILETYPE_RAW \ + FFS_ALIGNMENT=1 FFS_CHECKSUM=1\ + RAWFILE=$** FFSFILE=$@ COMPRESS=0 NAME=$(**B) + +!if "$(MICROCODE_SPLIT_BB_UPDATE)"=="1" +$(MICROCODE_BUILD_DIR)\Microcode_Blank.bin : $(MICROCODE_DIR)\Microcode.mak $(BUILD_DIR)\token.mak + copy << $(BUILD_DIR)\Microcode_Blank.ini +output + MICROCODE_EMPTY($(MICROCODE_BUILD_DIR)\Microcode_Blank.bin) +end +group MICROCODE_EMPTY + upper=0xffffffff + +components + +!IF "$(MPDTable_CREATED)"=="1" + file $(BUILD_DIR)\MPDTable.bin binfile=$(BUILD_DIR)\MPDTable.bin end +!ENDIF + +blank MICROCODE_PAD + size=$(MICROCODE_PAD_SIZE) +!IF "$(FLASH_ERASE_POLARITY)"=="0" + pattern=(0) +!ELSE + pattern=(0xFF) +!ENDIF +end +end +end +< + name = "Server/Workstation CPU uCode Patches" + category = ModulePart + LocalRoot = "Board\CPU\Microcode\ServWork" + RefName = "INTEL_SERVWORK" +[files] +"ServWork.SDL" = "SDL FILES" +"M03106A2_FFFF0019.PDB" = "ServerWork Station Microcode Updates" +"M03106A4_00000011.PDB" = "ServerWork Station Microcode Updates" +"M03106A5_0000001B.PDB" = "ServerWork Station Microcode Updates" +"M13106E5_00000008.PDB" = "ServerWork Station Microcode Updates" +"M1220652_0000000F.PDB" = "ServerWork Station Microcode Updates" +"M12206A7_00000029.PDB" = "ServerWork Station Microcode Updates" +"M13206C0_FFFF0016.PDB" = "ServerWork Station Microcode Updates" +"M03206C1_00000006.PDB" = "ServerWork Station Microcode Updates" +"M03206C2_0000001D.PDB" = "ServerWork Station Microcode Updates" +"M07206D0_80000006.PDB" = "ServerWork Station Microcode Updates" +"M07206D1_80000106.PDB" = "ServerWork Station Microcode Updates" +"M0F206D2_8000020C.PDB" = "ServerWork Station Microcode Updates" +"M0F206D3_80000304.PDB" = "ServerWork Station Microcode Updates" +"M6D206D5_00000513.PDB" = "ServerWork Station Microcode Updates" +"M6D206D6_00000619.PDB" = "ServerWork Station Microcode Updates" +"M6D206D7_00000710.PDB" = "ServerWork Station Microcode Updates" +"M05206E0_FFFF0005.PDB" = "ServerWork Station Microcode Updates" +"M05206E1_FFFF0006.PDB" = "ServerWork Station Microcode Updates" +"M05206E2_FFFF0004.PDB" = "ServerWork Station Microcode Updates" +"M05206E3_FFFF000C.PDB" = "ServerWork Station Microcode Updates" +"M05206E5_FFFF0016.PDB" = "ServerWork Station Microcode Updates" +"M04206E6_0000000B.PDB" = "ServerWork Station Microcode Updates" +"M05206F0_FFFF0013.PDB" = "ServerWork Station Microcode Updates" +"M05206F1_00000008.PDB" = "ServerWork Station Microcode Updates" +"M05206F2_00000039.PDB" = "ServerWork Station Microcode Updates" +"M12306A9_0000001C.PDB" = "ServerWork Station Microcode Updates" +"M32306C1_FFFF000D.PDB" = "ServerWork Station Microcode Updates" +"M32306C3_0000001D.PDB" = "ServerWork Station Microcode Updates" +"MED306E0_00000008.PDB" = "ServerWork Station Microcode Updates" +"MED306E2_0000020D.PDB" = "ServerWork Station Microcode Updates" +"MED306E3_00000308.PDB" = "ServerWork Station Microcode Updates" +"MED306E4_00000428.PDB" = "ServerWork Station Microcode Updates" +"MED306E6_00000600.PDB" = "ServerWork Station Microcode Updates" +"MED306E7_0000070D.PDB" = "ServerWork Station Microcode Updates" + diff --git a/Board/CPU/Microcode/ServWork/ServWork.SDL b/Board/CPU/Microcode/ServWork/ServWork.SDL new file mode 100644 index 0000000..9ab793b --- /dev/null +++ b/Board/CPU/Microcode/ServWork/ServWork.SDL @@ -0,0 +1,1075 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30071 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* +#**************************************************************************** +# $Header: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/SERVWORK/ServWork.SDL 112 8/14/15 5:28p Artems $ +# +# $Revision: 112 $ +# +# $Date: 8/14/15 5:28p $ +# +#**************************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/SERVWORK/ServWork.SDL $ +# +# 112 8/14/15 5:28p Artems +# [TAG] EIP233803 +# [Description] Updated Westmere -EX Processor A-2 Stepping version 39 +# Updated Westmere -EP -WS1S Processor B-1 Stepping version 1D +# Updated Nehalem -EX Processor D-0 Stepping version 0B +# Updated Clarkdale Xeon Processor C-2 Stepping version 0F +# [Files] ServWork.SDL +# ServWork.CIF +# +# 111 8/05/15 12:07p Artems +# [TAG] EIP231326 +# [Description] Updated Westmere -EP -WS1S Processor B-1 Stepping +# version 1C +# Updated Nehalem -EP -WS1S Processor D-0 Stepping version 1B +# Updated Lynnfield Xeon Processor B-1 Stepping version 08 +# [Files] ServWork.SDL +# ServWork.CIF +# +# 110 3/17/15 5:36p Artems +# Updated IvyBridge Processor E-1, L-1 Stepping version 1C +# +# 109 1/12/15 6:24p Artems +# Server +# Updated Haswell processor( 306CX) C-0 stepping to version 1D +# +# 108 7/21/14 3:07p Craigv +# Updated Haswell C-0 (306C3) to version 1C. +# +# 107 6/23/14 1:13p Craigv +# Updated Haswell C-0 (306C3) to version 1A. +# Updated Ivy Bridge E-1, L-1 (306A9) to version 1B. +# Updated Ivy Bridge M-1, S-1 (306E4) to version 428. +# Updated Ivy Bridge EX D-1 (306E7) to version 70D. +# +# 106 5/29/14 12:37p Craigv +# Updated Haswell C-0 (306C3) to version 19. +# Updated Ivy Bridge -EX D-1 (306E7) to version 70C. +# Updated IvyBridge -EX -EP -EN C-0, C-1, S-0, S-1, M-0, M-1 to version +# 427 +# +# 105 2/17/14 9:53a Craigv +# Updated IvyBridge EX (306E7) to version 00000709. +# +# 104 1/30/14 1:47p Craigv +# Updated Ivy Bridge-EP (306E4) to Production. +# Updated Ivy Bridge-EN (306E7) to Production. +# +# 103 1/10/14 3:09p Craigv +# Updated Intel Ivy Bridge -EX -EP =EN C-0, C-1, S-0, S-1, M-0, M-1 +# (306E4) to version 00000424. +# +# 102 10/23/13 10:20a Mithunraghavs +# The microcode update MED306E7_00000704.TXT for the Ivy Bridge-EX +# processor (Ivy Bridge-EX), Family 6 Model 3E Step 7 (D-1) has been +# updated from version 00000703 to 00000704 +# +# 101 10/14/13 6:11p Craigv +# Updated Haswell Processor C-0 (306C3) to version 00000017. +# +# 100 10/01/13 3:39p Craigv +# Updated Ivy Bridge -EX -EP -EN Processor C-0, C-1, S-0, S-1, M-0, M-1 +# to version 00000417 +# +# 99 9/13/13 4:56p Markw +# Updated Intel IvyBridge Processor -EX (306E7) D-1 version 700. +# Updated Intel Lynnfield Xeon B-1 (106E5) to version 7. +# +# 98 8/27/13 11:37a Markw +# Remove non production from 306C3. +# +# 97 8/26/13 1:47p Craigv +# Updated Intel Haswell C-0 (306C3) to version 00000016. +# +# 96 8/01/13 3:57p Craigv +# Added Intel IvyBridge Processor -EX (306E7) D-1 version 00000700. +# +# 95 7/18/13 4:27p Craigv +# Updated Intel(R) Ivy Bridge -EX -EP -EN Processor C-0, C-1, S-0, S-1, +# M-0, M-1 (306E4) to version 00000416. +# +# 94 7/18/13 3:54p Craigv +# Updated Intel Haswell C-0 (306C3) to version 00000012. +# +# 93 7/15/13 7:28p Markw +# Fix Production for 106A5. +# +# 92 7/15/13 12:29p Craigv +# Updated Intel Nehalem EP D-0 (106A5) to version 00000019. +# Updated Intel Lynnfield Xeon B-1 (106E5) to version 00000006. +# Updated Intel Clarkdale Xeon C-2 (20652) to version 0000000E. +# +# 91 7/12/13 5:46p Craigv +# Added Intel(R) Ivy Bridge -EX Processor D-0 Stepping (306E6) version +# 00000600. +# +# 90 7/03/13 11:17p Markw +# Add check-in 88 changes. +# +# 89 7/02/13 1:38p Craigv +# Updated Westmere WS 1S -EP (206C2) to version 0000001A. +# Updated Haswell C-0 (306C3) to version 00000010. +# +# 88 6/27/13 11:44a Markw +# Add TOKEN for SERVWORK_306AX. +# +# 87 6/26/13 7:58p Craigv +# Updated Sandy Bridge (206A7) D-2 to version 00000029. +# Updated Sandy Bridge -EN -EP (206D7) C-2 to version 00000710. +# Updated Westmere -EX (206F2) A-2 to version 00000037. +# Updated Nehalem -EX (206E6) D-0 to version 0000000A. +# Added Ivy Bridge (306A9) E-1, L-1 to version 00000019. +# +# 86 6/21/13 11:23a Craigv +# Updated Ivy Bridge -EX -EP -EN (306E4) C-0, C-1, S-0, S-1, M-0, M-1 to +# version 415. +# +# 85 6/13/13 3:52p Craigv +# Updated Intel Ivy Bridge -EP (306E4) C-0, C-1, M-0, S-0 to version 413. +# +# 84 5/30/13 5:21p Craigv +# Updated Ivy Bridge (306E4) C-0, S-0, M-0 to version 410. +# +# 83 5/30/13 4:43p Craigv +# Update Intel Ivy Bridge -EX Processor (306E4) C-0 to version 40F. +# +# 81 5/20/13 4:21p Craigv +# Added Intel Haswell Processor C-0 (306C3) version 0009. +# +# 80 5/10/13 11:06a Craigv +# Update IvyBridge C-0 (306E4) -EP-EX to version 40D. +# +# 79 4/17/13 5:37p Craigv +# Updated Ivy Bridge (306E4) help string to include -EX processors. +# +# 78 4/05/13 2:50p Craigv +# Update Ivy Bridge-EX -EP -EN Processor B-1, B-2, L-1, L-2, R-0, and R-1 +# (306E2) to version 20D. +# Updated Ivy Bridge-EP -EX Processor (306E3) B-3 to version 308. +# Updated Ivy Bridge-EP processor C-0 (306E4) Stepping Version 40C. +# +# 77 3/25/13 7:01p Craigv +# Updated Ivy Bridge-EP -EX Processor (306E3) B-3 to version 307. +# +# 76 3/21/13 3:22p Craigv +# Added Ivy Bridge-EP processor C-0 Stepping Version 40B. +# +# 75 1/25/13 4:05p Markw +# Update Ivy Bridge-EX -EP B-1, B-2, and L-1 (306E2) to version 20C. +# Update Ivy Bridge-EX -EP B-3 (306E3 to version 306. +# +# 74 12/04/12 11:27a Craigv +# Added Ivy Bridge-EX -EP processor B-1 and L-1 Stepping version +# 00000209. +# +# 73 10/30/12 3:58p Craigv +# Added Ivy Bridge-EX -EP processor B-1 and L-1 Stepping version 00000208 +# +# 72 8/15/12 11:08a Craigv +# Fix for Intel(R) Ivytown A-0 re-added. +# +# 71 8/08/12 12:18p Craigv +# Update IvyTown Processor A-0 (306E0) to version 00000008. +# +# 70 7/09/12 10:05a Markw +# Fix Intel(R) IvyTown Processor A-0 Stepping tokens. +# +# 69 7/06/12 5:25p Craigv +# Added IvyTown processor A-0 Stepping version 00000005. +# +# 68 6/18/12 1:57p Markw +# Update Sandybridge-EP C-1, M-0 (206d6) to version 619. +# Update Sandybridge-EP C-2, M-1 (206d7) to version 70D. +# +# 67 5/22/12 5:23p Craigv +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 28. +# Update Sandy Bridge-E C-2, M-1 (206D7) to version 70C. +# +# 66 4/24/12 10:41a Markw +# Add NON_PRODUCTION_MICROCODE dependency to Haswell A-0. +# +# 65 4/23/12 10:55a Craigv +# Added Haswell processor A-0 Stepping version FFFF000D +# +# 64 4/19/12 11:08a Craigv +# Update Westmere-EX A-2 (206F2) to Version 36. +# Update Westmere EP D0 (206E6) to version 9. +# +# 63 3/19/12 2:26p Craigv +# Update Sandybridge-EP C-1, M-0 (206d6) to version 616. +# Update Sandybridge-EP C-2, M-1 (206d7) to version 70B. +# +# 62 2/14/12 12:35p Craigv +# Update Sandybridge-EP C-1, M-0 (206d6) to version 615. +# Update Sandybridge-EP C-2, M-1 (206d7) to version 70A. +# +# 61 1/31/12 4:20p Markw +# Update Sandybridge-EP C-1, M-0 (206d6) to version 613. +# Update Sandybridge-EP C-2, M-1 (206d7) to version 708. +# +# 60 1/20/12 11:07a Markw +# Update help strings for Sandy Bridge. C-1 microcode is also for M-0, +# and C-2 microcode is also for M-1. +# +# 59 12/23/11 1:12p Markw +# Update Sandybridge-EP C-1 (206d6) to version 610. +# Update Sandybridge-EP C-2 (206d7) to version 705. +# +# 58 12/07/11 10:41a Markw +# Fix SERVWORK_206AX. Default should be off. +# +# 57 12/06/11 3:19p Markw +# Update Sandybridge-EP C-1 (206d6) to version 60F. +# Update Sandybridge-EP C-2 (206d7) to version 704. +# Update Lynnfield B-1 (106e5) to version 5. +# +# 56 11/14/11 4:18p Markw +# Update Sandybridge D-2 (206A7) to version 25. +# +# 55 11/02/11 12:41p Markw +# Update Sandybridge-EP C-0 (206d5) to version 513. +# Update Sandybridge-EP C-1 (206d6) to version 60D. +# +# 54 10/26/11 11:38a Markw +# Update Westmere-EP B-1 (206C2) to Version 15. +# Update Clarkdale Xeon C-2 (20652) to Version 0D. +# Update Westmere-EX A-2 (206F2) to Version 34. +# +# +# 53 10/11/11 4:11p Markw +# Update Sandybridge-EP C-0 (206d5) to version 512. +# Update Sandybridge-EP C-1 (206d6) to version 60C. +# +# 52 9/22/11 2:23p Markw +# Update Sandybridge-EP C-0 (206d5) to version 511. +# Update Sandybridge-EP C-1 (206d6) to version 60B. +# +# 51 9/08/11 1:05p Markw +# Update Sandybridge-EP C-1 (206d6) to version 606. +# +# 50 8/29/11 3:00p Markw +# Update Sandybridge-EP C-0 (206d5) to version 50D. +# +# 49 8/10/11 7:01p Markw +# Update Sandybridge-EP C-0 (206d5) to version 50B. +# +# 48 8/09/11 10:24a Markw +# Update Westmere-EX A-2 (206F2) to version 32. +# Update Sandybridge-EP C-0 (206d5) to version 50A. +# +# 47 8/04/11 1:14p Markw +# Update Nehalem-EP D- 0 (106A5 to version 16. +# Update Sandybridge-EP C-0 (206d5) to version 509. +# Update Sandybridge-EP C-1 (206d6) to version 80000603. +# +# 46 7/13/11 11:27a Markw +# Update Sandybridge EP C0 (206d5) to version 00000508. +# +# 45 7/12/11 11:31a Markw +# Update Sandybridge EP C0 (206d5) to version 00000507. +# +# 44 7/12/11 11:10a Markw +# Update Sandybridge EP C0 (206d5) to version 80000507. +# +# 42 6/16/11 5:15p Markw +# Update Sandybridge EP C0 (206d5) to version 80000502. +# +# 41 6/13/11 5:50p Markw +# Update Westmere EP B1 (206C2) to Version 14. +# +# 40 6/03/11 12:30p Markw +# Update Westmere EX A-2 (206F2) to version 30. +# +# 39 5/12/11 5:32p Markw +# Update Sandybridge EP EN B-0 (206d2) to version 8000020C. +# +# 38 4/29/11 4:52p Markw +# Update Sandybridge EP EN B1 (206d3) to version 80000304. +# +# 37 4/01/11 11:57a Markw +# Update Sandybridge EP EN B0 (206d2) to version 8000020b. +# Update Sandybridge EP EN B1 (206d3) to version 80000302. +# +# 36 3/24/11 10:57a Markw +# Update Nehalem EP D0 (106A5) to version 15. +# +# 35 3/07/11 6:46p Markw +# Update Westmere EX A2 (206F2) to version 26. +# +# 34 3/03/11 3:45p Markw +# Update Sandy Bridge EN,EP, and EX B-0 (206D2) to Version 8000020A +# +# 33 2/14/11 11:57a Markw +# pdate Sandy Bridge EN,EP, and EX B-0 (206D2) to Version 80000206 +# +# 32 1/24/11 6:51p Markw +# Fix default SERVWORK_206DX. +# +# 31 1/24/11 6:50p Markw +# pdate Sandy Bridge EN,EP, and EX B-0 (206D2) to Version 80000206 +# +# 30 1/04/11 10:23a Markw +# Update Westmere EX A2 (206F2) to version 24. +# +# 29 12/14/10 4:47p Markw +# Update Sandy Bridge EN,EP, and EX A-1 (206D1) to Version 80000106. +# +# 28 11/22/10 9:11p Markw +# +# 27 11/22/10 9:07p Markw +# Update Sandy Bridge EP A-1 (206D1) to Version 80000105. +# +# 26 10/21/10 10:41a Markw +# Update Westmere EX A1 (206F1) to version 8. +# Update Westmere EX A2 (206F2) to version 22. +# +# 25 10/15/10 4:25p Markw +# Update Westmere EP D0 (206E6) to version 8. +# +# 24 10/14/10 3:21p Markw +# # 22 9/15/10 1:31p Markw +# Update Sandy Bridge EP 1a (206D1) to Version 80000103.. +# +# 23 9/15/10 2:29p Markw +# Update default token SERVWORK_206DX back to 0. +# +# 22 9/15/10 1:31p Markw +# Update Westmere EP B1 (206C2) to Version 13. +# +# 21 9/13/10 3:43p Markw +# Update SandyBridge EP A1 (206D1) to Version 80000101. +# +# 20 9/02/10 5:03p Markw +# Update Westmere EP B1 (206C2) to Version 10. +# Update SandyBridge EP A0 (206D0) to Version 80000006. +# +# 19 8/30/10 5:42p Markw +# Update Lynnfield B1 (106e5) and Westmere EX A1 (206f1). +# +# 18 8/19/10 10:49a Markw +# Fix build error for microcode Clarkdale 20652 and Westmere 206C2. +# +# 17 8/12/10 11:16a Markw +# +# 16 8/05/10 11:37a Markw +# Add +# Westmere-EX processor A0 Stepping version FFFF0013 +# +# 15 7/27/10 10:36a Hari +# Updated for Westmere EX A1 and clarksdale latest microcode +# +# 14 7/15/10 3:55p Bhimanadhunik +# +# 12 5/27/10 6:35p Markw +# Updated Nehalem-EX D0 to version 7 and Westmere-EX A0 to version +# 0xffff0010. +# +# 10 4/09/10 9:55a Markw +# Add M03206C2_0000000C.PDB +# +# 9 3/02/10 3:39p Markw +# Update Westmere EP B0 microcode to Rev A. +# Nehalem EX D0 to Rev 5. +# +# 8 1/19/10 11:17p Markw +# Add Westmere EP B-1 stepping. +# +# 7 1/19/10 11:03p Markw +# Add Westmere EP B0 Ver 6 +# +# 6 12/18/09 4:12p Markw +# Westmere-EP processor B1 +# +# 5 12/15/09 10:45p Markw +# Add Clarkdale Xeon C2 production and Nehalem EX D0 production. +# +# 4 11/17/09 2:39p Markw +# Added Nehalem EP B0 and Westmere EP B0. +# +# 3 11/05/09 5:32p Markw +# Nehalem EX D0 added. +# +# 2 10/16/09 10:27a Markw +# +# 1 9/29/09 2:51p Markw +# +#**************************************************************************** + +TOKEN + Name = "SERVWORK" + Value = "0" + Help = "Master Server/Workstation CPU uCode Enable" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Range = "On-Off" +End + +TOKEN + Name = "SERVWORK_306EX" + Value = "0" + Help = "Intel(R) IvyTown and Ivy Bridge-EP -EX" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_306CX" + Value = "0" + Help = "Intel(R) Haswell" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_206DX" + Value = "0" + Help = "Intel(R) SandyBridge-EN -EP and -EX processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_206AX" + Value = "0" + Help = "Intel(R) SandyBridge processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_306AX" + Value = "0" + Help = "Intel(R) IvyBridge processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_206FX" + Value = "0" + Help = "Intel(R) Westmere-EX processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_206EX" + Value = "0" + Help = "Intel(R) Nehalem-EX processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_2065X" + Value = "0" + Help = "Intel(R) Clarkdale Xeon processors" + TokenType = Boolean +End + + +TOKEN + Name = "SERVWORK_206CX" + Value = "0" + Help = "Intel(R) Westmere-EP processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_106AX" + Value = "0" + Help = "Intel(R) Nehalem-EP processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_106EX" + Value = "0" + Help = "Intel(R) Lynnfield processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_M03106A2" + Value = "1" + Help = "Intel(R) Nehalem-EP processor B0 Stepping" + TokenType = Boolean + Token = "SERVWORK_106AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M03106A4" + Value = "1" + Help = "Intel(R) Nehalem-EP processor C0 Stepping" + TokenType = Boolean + Token = "SERVWORK_106AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M03106A5" + Value = "1" + Help = "Intel(R) Nehalem-EP processor D0 Stepping" + TokenType = Boolean + Token = "SERVWORK_106AX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M1220652" + Value = "1" + Help = "Intel(R) Clarkdale Xeon processor C2 Stepping" + TokenType = Boolean + Token = "SERVWORK_2065X" "=" "1" +End + +TOKEN + Name = "SERVWORK_M13206C0" + Value = "1" + Help = "Intel(R) Westmere-EP processor A0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M03206C1" + Value = "1" + Help = "Intel(R) Westmere-EP processor B0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M03206C2" + Value = "1" + Help = "Intel(R) Westmere-EP and Westmere-WS 1S B1 Stepping" + TokenType = Boolean + Token = "SERVWORK_206CX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206E0" + Value = "1" + Help = "Intel(R) Nehalem-EX processor A1 Stepping" + TokenType = Boolean + Token = "SERVWORK_206EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206E1" + Value = "1" + Help = "Intel(R) Nehalem-EX processor A2 Stepping" + TokenType = Boolean + Token = "SERVWORK_206EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206E2" + Value = "1" + Help = "Intel(R) Nehalem-EX processor" + TokenType = Boolean + Token = "SERVWORK_206EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206E3" + Value = "1" + Help = "Intel(R) Nehalem-EX processor B0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206E5" + Value = "1" + Help = "Intel(R) Nehalem-EX processor C0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M04206E6" + Value = "1" + Help = "Intel(R) Nehalem-EX processor D0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206EX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M13106E5" + Value = "1" + Help = "Intel(R) Lynnfield Processor B1 Stepping" + TokenType = Boolean + Token = "SERVWORK_106EX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206F0" + Value = "1" + Help = "Intel(R) Westmere-EX Processor A0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206F1" + Value = "1" + Help = "Intel(R) Westmere-EX Processor A1 Stepping" + TokenType = Boolean + Token = "SERVWORK_206FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206F2" + Value = "1" + Help = "Intel(R) Westmere-EX Processor A2 Stepping" + TokenType = Boolean + Token = "SERVWORK_206FX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M07206D0" + Value = "1" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor A0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M07206D1" + Value = "1" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor A1 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M0F206D2" + Value = "1" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor B0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M0F206D3" + Value = "1" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor B1 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M6D206D5" + Value = "1" + Help = "Intel(R) SandyBridge-EP Processor C-0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M6D206D6" + Value = "1" + Help = "Intel(R) SandyBridge-EP Processor C-1 and M-0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M6D206D7" + Value = "1" + Help = "Intel(R) SandyBridge-EN -EP Processor C-2 and M-1 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M12206A7" + Value = "1" + Help = "Intel(R) SandyBridge Processor D-2 Stepping" + TokenType = Boolean + Token = "SERVWORK_206AX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M12306A9" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor E-1, L-1 Stepping" + TokenType = Boolean + Token = "SERVWORK_306AX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M32306C1" + Value = "1" + Help = "Intel(R) Haswell Processor A-0 Stepping" + TokenType = Boolean + Token = "SERVWORK_306CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M32306C3" + Value = "1" + Help = "Intel(R) Haswell Processor C-0 Stepping" + TokenType = Boolean + Token = "SERVWORK_306CX" "=" "1" +End + +TOKEN + Name = "SERVWORK_MED306E0" + Value = "1" + Help = "Intel(R) IvyTown Processor A-0 Stepping" + TokenType = Boolean + Token = "SERVWORK_306EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_MED306E2" + Value = "1" + Help = "Intel(R) Ivy Bridge-EP -EX Processor B-1, B-2, and L-1 Stepping" + TokenType = Boolean + Token = "SERVWORK_306EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_MED306E3" + Value = "1" + Help = "Intel(R) Ivy Bridge-EP -EX Processor B-3" + TokenType = Boolean + Token = "SERVWORK_306EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_MED306E4" + Value = "1" + Help = "Intel(R) Ivy Bridge-EP Processor C-0, M-0, S-0, C-1" + TokenType = Boolean + Token = "SERVWORK_306EX" "=" "1" +End + +TOKEN + Name = "SERVWORK_MED306E6" + Value = "1" + Help = "Intel(R) Ivy Bridge-EP Processor D-0" + TokenType = Boolean + Token = "SERVWORK_306EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_MED306E7" + Value = "1" + Help = "Intel(R) Ivy Bridge-EP Processor D-1" + TokenType = Boolean + Token = "SERVWORK_306EX" "=" "1" +End + +PATH + Name = "MICROCODE_SERVWORK_DIR" +End + +ELINK + Name = "$(Intel_ServWork)" + Parent = "MICROCODE_FILES" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M03106A2_FFFF0019.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EP processor B0 Stepping" + Token = "SERVWORK_M03106A2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M03106A4_00000011.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EP processor C0 Stepping" + Token = "SERVWORK_M03106A4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M03106A5_0000001B.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EP processor D-0 & WS 1S Stepping" + Token = "SERVWORK_M03106A5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M1220652_0000000F.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Clarkdale Xeon processor C-2 Stepping" + Token = "SERVWORK_M1220652" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M13206C0_FFFF0016.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Westmere-EP processor A0 Stepping" + Token = "SERVWORK_M13206C0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M03206C1_00000006.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Westmere-EP processor B0 Stepping" + Token = "SERVWORK_M03206C1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M03206C2_0000001D.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Westmere-EP and Westmere-WS 1S B1 Stepping" + Token = "SERVWORK_M03206C2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206E0_FFFF0005.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EX processor A1 Stepping" + Token = "SERVWORK_M05206E0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206E1_FFFF0006.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EX processor A2 Stepping" + Token = "SERVWORK_M05206E1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206E2_FFFF0004.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EX processor" + Token = "SERVWORK_M05206E2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206E3_FFFF000C.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EX processor B0 Stepping" + Token = "SERVWORK_M05206E3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206E5_FFFF0016.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EX processor C0 Stepping" + Token = "SERVWORK_M05206E5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M04206E6_0000000B.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EX processor D0 Stepping" + Token = "SERVWORK_M04206E6" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206F0_FFFF0013.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Westmere-EX processor A0 Stepping" + Token = "SERVWORK_M05206F0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206F1_00000008.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Westmere-EX processor A1 Stepping" + Token = "SERVWORK_M05206F1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206F2_00000039.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Westmere-EX processor A2 Stepping" + Token = "SERVWORK_M05206F2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M13106E5_00000008.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Lynnfield Processor B-1 Stepping \CPU Signature 106E5" + Token = "SERVWORK_M13106E5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M12206A7_00000029.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge Processor D-2 Stepping" + Token = "SERVWORK_M12206A7" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M12306A9_0000001C.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Ivy Bridge Processor E-1, L-1 Stepping" + Token = "SERVWORK_M12306A9" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M07206D0_80000006.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge EP Processor A0 Stepping" + Token = "SERVWORK_M07206D0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M07206D1_80000106.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor A1 Stepping" + Token = "SERVWORK_M07206D1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M0F206D2_8000020C.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor B0 Stepping" + Token = "SERVWORK_M0F206D2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M0F206D3_80000304.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor B1 Stepping" + Token = "SERVWORK_M0F206D3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M6D206D5_00000513.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge-EP Processor C-0 Stepping" + Token = "SERVWORK_M6D206D5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M6D206D6_00000619.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge-EP Processor C-1 and M-0 Stepping" + Token = "SERVWORK_M6D206D6" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M6D206D7_00000710.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge-EN -EP Processor C-2 and M-1 Stepping" + Token = "SERVWORK_M6D206D7" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M32306C1_FFFF000D.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Haswell Processor A-0 Stepping" + Token = "SERVWORK_M32306C1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M32306C3_0000001D.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Haswell Processor C-0 Stepping" + Token = "SERVWORK_M32306C3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\MED306E0_00000008.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) IvyTown Processor A-0 Stepping" + Token = "SERVWORK_MED306E0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\MED306E2_0000020D.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Ivy Bridge-EP -EX -EN Processor B-1, B-2, L-1, L-2, R-0, and R-1 Stepping" + Token = "SERVWORK_MED306E2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\MED306E3_00000308.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Ivy Bridge-EP -EX Processor B-3 Stepping" + Token = "SERVWORK_MED306E3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\MED306E4_00000428.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Ivy Bridge -EX -EP -EN Processor C-0, C-1, S-0, S-1, M-0, M-1 Stepping" + Token = "SERVWORK_MED306E4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\MED306E6_00000600.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Ivy Bridge -EX Processor D-0 Stepping" + Token = "SERVWORK_MED306E6" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\MED306E7_0000070D.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Ivy Bridge -EX Processor D-1 Stepping" + Token = "SERVWORK_MED306E7" "=" "1" + InvokeOrder = AfterParent +End \ No newline at end of file -- cgit v1.2.3