From b2763ff45dadfee627069d2bf628156ba6ccb74b Mon Sep 17 00:00:00 2001
From: raywu <raywu@aaeon.com>
Date: Fri, 15 Jun 2018 13:14:44 +0800
Subject: Override 1. ME XML

---
 RomImage/XmlFiles/Q87_8Mx2.xml | 59 +++++++++++++++++++++++++-----------------
 1 file changed, 35 insertions(+), 24 deletions(-)

(limited to 'RomImage')

diff --git a/RomImage/XmlFiles/Q87_8Mx2.xml b/RomImage/XmlFiles/Q87_8Mx2.xml
index 19bddf3..1340e4b 100644
--- a/RomImage/XmlFiles/Q87_8Mx2.xml
+++ b/RomImage/XmlFiles/Q87_8Mx2.xml
@@ -6,13 +6,13 @@
 		<BuildCompactImage value="false"/>
 		<RegionOrder value="4321"/>
 		<EndManufacturingBitOverride value="false"/>
-		<SkuType value="Q87"/>
+		<SkuType value="B85"/>
 	</ProgSettings>
 	<Chipset>
 		<Region0 name="Descriptor Region">
 			<RegionLength value="0x00000000" edit="true" visible="true" name="Descriptor region length" help_text="If non-zero, specifies the length of the Descriptor region."/>
 			<DescriptorMap name="Descriptor Map">
-				<NumComponents value="2" edit="true" visible="true" name="Number of Flash Components" help_text="Specifies the number of Flash components that will be installed on the target machine. Valid values are 0,1,2 - 0 causes only ME region to be built."/>
+				<NumComponents value="1" edit="true" visible="true" name="Number of Flash Components" help_text="Specifies the number of Flash components that will be installed on the target machine. Valid values are 0,1,2 - 0 causes only ME region to be built."/>
 				<ComponentBaseAddr value="0x03" edit="false" visible="true" name="Component Base Address" help_text="Identifies address bits [11:4] for the Component portion of the Flash Descriptor."/>
 				<RegionBaseAddr value="0x04" edit="false" visible="true" name="Region base address" help_text="Flash Region Base Address (FRBA). This identifies address bits [11:4] for the Region portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0."/>
 				<MasterBaseAddr value="0x06" edit="false" visible="true" name="Master base address" help_text="Identifies address bits [11:4] for the Master portion of the Flash Descriptor."/>
@@ -27,11 +27,11 @@
 				<ReadStatusFreq value="50MHz" value_list="20MHz,,33MHz,,50MHz" edit="true" visible="true" name="Read ID and Read Status clock frequency" help_text="If more that one Flash component exists, this field must be the lowest common frequency of the different components."/>
 				<WriteEraseFreq value="50MHz" value_list="20MHz,,33MHz,,50MHz" edit="true" visible="true" name="Write and erase clock frequency" help_text="If more that one Flash component exists, this field must be the lowest common frequency of the different components."/>
 				<FastReadFreq value="50MHz" value_list="20MHz,,33MHz,,50MHz" edit="true" visible="true" name="Fast read clock frequency" help_text="This field is undefined if the Fast Read Support is set to false."/>
-				<FastReadSupport value="true" edit="true" visible="true" name="Fast read support" help_text="Enables/disables Fast Read support."/>
+				<FastReadSupport value="false" edit="true" visible="true" name="Fast read support" help_text="Enables/disables Fast Read support."/>
 				<ReadFreq value="20MHz" value_list="20MHz" edit="false" visible="true" name="Read clock frequency" help_text="Sets the Flash read frequency"/>
-				<DensityComp1 value="8MB" value_list="512KB,,1MB,,2MB,,4MB,,8MB,,16MB,,32MB,,64MB" edit="true" visible="true" name="Flash component 1 density" help_text="This field identifies the size of the 1st Flash component."/>
-				<DensityComp2 value="8MB" value_list="512KB,,1MB,,2MB,,4MB,,8MB,,16MB,,32MB,,64MB" edit="true" visible="true" name="Flash component 2 density" help_text="This field identifies the size of the 2nd Flash component."/>
-				<DualOutputFastReadSupport value="true" edit="true" visible="true" name="Dual Output Fast Read Support" help_text="false: Not Supported. true: Dual Output Fast Read instruction is issued in all cases where the the Fast Read would have been issued."/>
+				<DensityComp1 value="16MB" value_list="512KB,,1MB,,2MB,,4MB,,8MB,,16MB,,32MB,,64MB" edit="true" visible="true" name="Flash component 1 density" help_text="This field identifies the size of the 1st Flash component."/>
+				<DensityComp2 value="8MB" value_list="512KB,,1MB,,2MB,,4MB,,8MB,,16MB,,32MB,,64MB" edit="false" visible="true" name="Flash component 2 density" help_text="This field identifies the size of the 2nd Flash component."/>
+				<DualOutputFastReadSupport value="false" edit="true" visible="true" name="Dual Output Fast Read Support" help_text="false: Not Supported. true: Dual Output Fast Read instruction is issued in all cases where the the Fast Read would have been issued."/>
 				<InvalidInst0 value="0x0" edit="true" visible="true" name="Invalid Instruction 0" help_text="Op-code for an invalid instruction that the Flash Controller should protect against chip erase. This byte should be set to 0 if there is no instruction to protect against."/>
 				<InvalidInst1 value="0x0" edit="true" visible="true" name="Invalid Instruction 1" help_text="Op-code for an invalid instruction that the Flash Controller should protect against chip erase. This byte should be set to 0 if there is no instruction to protect against."/>
 				<InvalidInst2 value="0x0" edit="true" visible="true" name="Invalid Instruction 2" help_text="Op-code for an invalid instruction that the Flash Controller should protect against chip erase. This byte should be set to 0 if there is no instruction to protect against."/>
@@ -68,8 +68,8 @@
 				<PchStrap0 name="PCH Strap 0">
 					<BiosBootBlockSize value="64KB" value_list="64KB,,128KB,,256KB,,512KB,,1MB" edit="true" visible="true" name="BIOS Boot Block Size" help_text="Sets BIOS Boot Block Size (BBBS)."/>
 					<DmiReqIdDisable value="false" edit="true" visible="true" name="DMI RequesterID Check Disable" help_text="The purpose is to support server environments with multiple processors where each have a different RequesterID that can each access the flash.  false = DMI RequesterID Checks are enabled.  true = DMI RequesterID Checks are disabled."/>
-					<MacSecDisable value="false" edit="true" visible="true" name="MACsec Disable" help_text="MACsec is a hop-by-hop network security solution. It provides Layer 2 encryption and authenticity/integrity protection for packets traveling between MACsec-enabled nodes of the network."/>
-					<LanPhyPcGp12Sel value="GPIO12 is used in native mode as LANPHYPC" value_list="GPIO12 default is General Purpose (GP) output,,GPIO12 is used in native mode as LANPHYPC" edit="true" visible="true" name="LAN PHY Power Control GPIO12 Select" help_text="Lan Phy Power"/>
+					<MacSecDisable value="true" edit="false" visible="true" name="MACsec Disable" help_text="MACsec is a hop-by-hop network security solution. It provides Layer 2 encryption and authenticity/integrity protection for packets traveling between MACsec-enabled nodes of the network."/>
+					<LanPhyPcGp12Sel value="GPIO12 default is General Purpose (GP) output" value_list="GPIO12 default is General Purpose (GP) output,,GPIO12 is used in native mode as LANPHYPC" edit="false" visible="true" name="LAN PHY Power Control GPIO12 Select" help_text="Lan Phy Power"/>
 					<SmBusEnable value="true" edit="true" visible="true" name="Intel (R) ME SMBus Enable" help_text="Configures if Intel (R) ME SMBus is enabled."/>
 					<SmLink0Enable value="true" edit="true" visible="true" name="SMLink0 Enable" help_text="Configures if SmLink0 is enabled."/>
 					<SmLink1Enable value="true" edit="true" visible="true" name="SMLink1 Enable" help_text="Configures if SmLink1 is enabled."/>
@@ -91,10 +91,10 @@
 					<SmBusAsdAddr value="0x00" edit="true" visible="true" name="Intel (R) ME SMBus ASD Address " help_text="Intel (R) ME SMBus ASD Target Address"/>
 				</PchStrap2>
 				<PchStrap4 name="PCH Strap 4">
-					<GbePhySmBusAddr value="0x64" edit="false" visible="true" name="GbE PHY SMBus Address" help_text="If bit 0 set, OEM programmed SmBus address is assigned to GbE PHY by chipset. This strap must be made available to ME &amp; PMC."/>
-					<GbeSmBusAddr value="0x70" edit="false" visible="true" name="GbE MAC SMBus Address" help_text="This is the SMBus address used by SMT to accept SMBus cycles from the PHY. This must be provided to SMT1,2,3 and GbE This strap must be backed in the RTC well. The recommended flash value for this field is: 1110000b"/>
-					<GbeSmBusAddrEn value="true" edit="false" visible="true" name="GbE MAC SMBus Address Enable" help_text="GbE MAC SMBus Address Enabled"/>
-					<PhyConnectivity value="10: PHY on SMLink0" value_list="00: No PHY connected,,01: PHY on SMBus (use SMT1),,10: PHY on SMLink0,,11: PHY on SMLink2 (use SMT3)" edit="false" visible="true" name="PHY Connectivity" help_text="Defines if PHY is connected to Intel (R) SMBus 2 segment or not."/>
+					<GbePhySmBusAddr value="0x64" edit="true" visible="true" name="GbE PHY SMBus Address" help_text="If bit 0 set, OEM programmed SmBus address is assigned to GbE PHY by chipset. This strap must be made available to ME &amp; PMC."/>
+					<GbeSmBusAddr value="0x70" edit="true" visible="true" name="GbE MAC SMBus Address" help_text="This is the SMBus address used by SMT to accept SMBus cycles from the PHY. This must be provided to SMT1,2,3 and GbE This strap must be backed in the RTC well. The recommended flash value for this field is: 1110000b"/>
+					<GbeSmBusAddrEn value="false" edit="false" visible="true" name="GbE MAC SMBus Address Enable" help_text="GbE MAC SMBus Address Enabled"/>
+					<PhyConnectivity value="00: No PHY connected" value_list="00: No PHY connected,,01: PHY on SMBus (use SMT1),,10: PHY on SMLink0,,11: PHY on SMLink2 (use SMT3)" edit="false" visible="true" name="PHY Connectivity" help_text="Defines if PHY is connected to Intel (R) SMBus 2 segment or not."/>
 					<SataPort5PciePort2Mode value="Statically assigned to SATA Port 5" value_list="Statically assigned to SATA Port 5,,Statically assigned to PCIe Port 2,,Assigned based on the native mode of GPIO49 pin." edit="true" visible="true" name="SATA Port 5 PCIe Port 2 Mode" help_text="If this soft strap is set to '11' then GPIO49 native mode is SATA5_PCIE2#, else the native mode is SATA5GP. This soft strap only has effect if it is allowed by the 'SATA Port 5 PCIe Port 2 Mode' fuse."/>
 				</PchStrap4>
 				<PchStrap7 name="PCH Strap 7">
@@ -103,16 +103,16 @@
 				<PchStrap9 name="PCH Strap 9">
 					<TempAlertSml1AlertSel value="TEMP_ALERT#" value_list="SML1ALERT#,,TEMP_ALERT#" edit="true" visible="true" name="TEMP_ALERT# or SML1ALERT# Select" help_text="This strap determines the native mode operation of GPIO73."/>
 					<SubtractDecodeAgentEn value="true" edit="true" visible="true" name="Subtractive Decode Agent Enable" help_text="Set this bit to 'true' if there is a PCI bridge chip connnected to the PCH, that requires subtractive decode agent. Set to 'false' if the platform has no PCI bridge chip."/>
-					<GbeOverPcieEn value="true" edit="false" visible="true" name="Intel (R) PHY Over PCI Express Enable" help_text="false: GbE MAC/PHY comm. is not enabled over PCIe. true: The port selected by GBE PCIe Port Select is used for GbE MAC/PHY over PCIe comm."/>
+					<GbeOverPcieEn value="false" edit="false" visible="true" name="Intel (R) PHY Over PCI Express Enable" help_text="false: GbE MAC/PHY comm. is not enabled over PCIe. true: The port selected by GBE PCIe Port Select is used for GbE MAC/PHY over PCIe comm."/>
 					<GbePciePortSelect value="010: Port 3" value_list="000: Port 1,,001: Port 2,,010: Port 3,,011: Port 4,,100: Port 5,,101: Port 6,,110: Port 7,,111: Port 8" edit="true" visible="true" name="Intel (R) PHY PCIe Port Select" help_text="Sets the default value of the RPC.GBEPCIERPSEL register which is used to determine which PCIe port to use for GbE MAC/PHY over PCI Express communication."/>
 					<DmiLaneReversal value="false" edit="true" visible="true" name="DMI Lane Reversal" help_text="Sets the default value for the DMI Lane Reversal register."/>
 					<PCIeLaneReversal2 value="false" edit="true" visible="true" name="PCIe Lane Reversal 2" help_text="Sets the default value for the PCIe Port 5, Device 28 Function 4Lane Reversal register."/>
 					<PCIeLaneReversal1 value="false" edit="true" visible="true" name="PCIe Lane Reversal 1" help_text="Sets the default value for the PCIe Port 1, Device 28 Function 0, Lane Reversal register."/>
 					<PCIePortConf2 value="00: 4x1 Ports 5-8 (x1)" value_list="00: 4x1 Ports 5-8 (x1),,01: 1x2, 2x1 Port 5 (x2), Port 6 (disabled), Ports 7, 8 (x1),,10: 2x2 Port 5 (x2), Port 7 (x2), Ports 6, 8 (disabled),,11: 1x4 Port 5 (x4), Ports 6-8 (disabled)" edit="true" visible="true" name="PCIe Port Configuration Strap 2" help_text="These straps set the default value of the PCI Express port Configuration 2 register covering PCIe ports 5-8."/>
 					<PCIePortConf1 value="00: 4x1 Ports 1-4 (x1)" value_list="00: 4x1 Ports 1-4 (x1),,01: 1x2, 2x1 Port 1 (x2), Port 2 (disabled), Ports 3, 4 (x1),,10: 2x2 Port 1 (x2), Port 3 (x2), Ports 2, 4 (disabled),,11: 1x4 Port 1 (x4), Ports 2-4 (disabled)" edit="true" visible="true" name="PCIe Port Configuration Strap 1" help_text="These straps set the default value of the PCI Express Port Configuration 1 register covering PCIe ports 1-4."/>
-					<Usb3Port2PciePort1Mode value="PCIe Lane 1 is statically assigned to USB3 Port 2" value_list="PCIe Lane 1 is statically assigned to PCI Express (or GbE),,PCIe Lane 1 is statically assigned to USB3 Port 2,,PCIe Lane 1 is dynamically assigned to PCI Express or USB3 Port 2." edit="true" visible="true" name="USB3 Port 2 PCIe Port 1 Mode" help_text="This soft strap sets the default value of the USB3 PCI Express Port 1 Mode register that resides in the core well."/>
-					<Usb3Port3PciePort2Mode value="PCIe Lane 2 is statically assigned to USB3 Port 3" value_list="PCIe Lane 2 is statically assigned to PCI Express (or GbE),,PCIe Lane 2 is statically assigned to USB3 Port 3,,PCIe Lane 2 is dynamically assigned to PCI Express or USB3 Port 3." edit="true" visible="true" name="USB3 Port 3 PCIe Port 2 Mode" help_text="This soft strap sets the default value of the USB3 PCI Express Port 2 Mode register that resides in the core well."/>
-					<SataPort4PciePort1Mode value="Assigned based on the native mode of GPIO16 pin." value_list="Statically assigned to SATA Port 4,,Statically assigned to PCIe Port 1,,Assigned based on the native mode of GPIO16 pin." edit="true" visible="true" name="SATA Port 4 PCIe Port 1 Mode" help_text="If this soft strap is set to '11' then GPIO16 native mode is SATA4_PCIE1#, else the native mode is SATA4GP. This soft strap only has effect if it is allowed by the 'SATA Port 4 PCIe Port 1 Mode' fuse."/>
+					<Usb3Port2PciePort1Mode value="PCIe Lane 1 is statically assigned to PCI Express (or GbE)" value_list="PCIe Lane 1 is statically assigned to PCI Express (or GbE),,PCIe Lane 1 is statically assigned to USB3 Port 2,,PCIe Lane 1 is dynamically assigned to PCI Express or USB3 Port 2." edit="true" visible="true" name="USB3 Port 2 PCIe Port 1 Mode" help_text="This soft strap sets the default value of the USB3 PCI Express Port 1 Mode register that resides in the core well."/>
+					<Usb3Port3PciePort2Mode value="PCIe Lane 2 is statically assigned to PCI Express (or GbE)" value_list="PCIe Lane 2 is statically assigned to PCI Express (or GbE),,PCIe Lane 2 is statically assigned to USB3 Port 3,,PCIe Lane 2 is dynamically assigned to PCI Express or USB3 Port 3." edit="true" visible="true" name="USB3 Port 3 PCIe Port 2 Mode" help_text="This soft strap sets the default value of the USB3 PCI Express Port 2 Mode register that resides in the core well."/>
+					<SataPort4PciePort1Mode value="Statically assigned to SATA Port 4" value_list="Statically assigned to SATA Port 4,,Statically assigned to PCIe Port 1,,Assigned based on the native mode of GPIO16 pin." edit="true" visible="true" name="SATA Port 4 PCIe Port 1 Mode" help_text="If this soft strap is set to '11' then GPIO16 native mode is SATA4_PCIE1#, else the native mode is SATA4GP. This soft strap only has effect if it is allowed by the 'SATA Port 4 PCIe Port 1 Mode' fuse."/>
 				</PchStrap9>
 				<PchStrap10 name="PCH Strap 10">
 					<MeBootFromFlash value="false" edit="false" visible="true" name="ME boot from Flash" help_text="If true, ME will boot directly from Flash."/>
@@ -122,7 +122,7 @@
 					<MeDbgLanEmergencyModeEn value="false" edit="true" visible="true" name="ME Debug LAN Emergency Mode" help_text="This bit should be set to 'true' if it is desired to capture events with the ME Debug tool. This bit should be set to 'false' for production platforms."/>
 					<MeDebugExtendedDataEnable value="Disabled (default)" value_list="Disabled (default),,MDES data transmitted over SMBUS by boot path (including ROM)" edit="true" visible="true" name="ME Debug Extended Data Enable" help_text="ME MDES Extended Data enable"/>
 					<MeResetCapture value="false" edit="true" visible="true" name="ME Reset Capture on CLR_RST1#" help_text="true = ME will assert at the CL_RST1# when it resets.  false = ME does not assert."/>
-					<DeepSx value="true" edit="true" visible="true" name="Deep SX Enable" help_text="Deep SX refers to the low power states designated Deep S3, Deep S4, and Deep S5."/>
+					<DeepSx value="false" edit="true" visible="true" name="Deep SX Enable" help_text="Deep SX refers to the low power states designated Deep S3, Deep S4, and Deep S5."/>
 				</PchStrap10>
 				<PchStrap11 name="PCH Strap 11">
 					<SmLink1I2cTargetAddressEnable value="false" edit="true" visible="true" name="SMLink1 I2C Target Address Enable" help_text="SmLink1 I2C Target Address Enabled"/>
@@ -159,6 +159,11 @@
 					<DeviceId0 value="0x40" edit="true" visible="true" name="Device ID 0" help_text="The first device specific byte of the JEDEC ID."/>
 					<DeviceId1 value="0x17" edit="true" visible="true" name="Device ID 1" help_text="The second device specific byte of the JEDEC ID."/>
 				</MeVsccDevice>
+				<MeVsccDevice value="W25Q64FV">
+					<VendorId value="0xEF" edit="true" visible="true" name="Vendor ID" help_text="The vendor specific byte of the JEDEC ID."/>
+					<DeviceId0 value="0x40" edit="true" visible="true" name="Device ID 0" help_text="The first device specific byte of the JEDEC ID."/>
+					<DeviceId1 value="0x18" edit="true" visible="true" name="Device ID 1" help_text="The second device specific byte of the JEDEC ID."/>
+				</MeVsccDevice>
 			</VsccTable>
 			<OemSection name="OEM Section">
 				<InputFile value="" edit="true" visible="true" name="OEM Section Binary input file" help_text="The contents of this file (up to 256 bytes) are copied directly into the OEM section of the Flash Descriptor."/>
@@ -170,13 +175,13 @@
 			<InputFile value="$SourceDir\bios\hsw_lpt_v86_release.rom" edit="true" visible="true" name="BIOS binary input file" help_text="This is the BIOS image binary that will be copied into this region."/>
 		</Region1>
 		<Region3 name="GbE Region">
-			<Enabled value="true" edit="false" visible="false" name="GbE region enabled" help_text=""/>
+			<Enabled value="false" edit="false" visible="false" name="GbE region enabled" help_text=""/>
 			<RegionLength value="0x00000000" edit="true" visible="true" name="GbE LAN region length" help_text="This is the size of the GbE LAN region in bytes. Set this to 0 to make the region length equal to the binary file length (rounded up to 4k). Extra space will be filled with 0xFF."/>
 			<InputFile value="$SourceDir\gbe\nahum6_clarksville_desktop_1_3.bin" edit="true" visible="true" name="GbE binary input file" help_text="This is the Gbe image binary that will be copied into this region."/>
 			<MajorVersion value="0" edit="false" visible="true" name="Major Version" help_text=""/>
 			<MinorVersion value="13" edit="false" visible="true" name="Minor Version" help_text=""/>
 			<ImageId value="4" edit="false" visible="true" name="Image ID" help_text=""/>
-			<LANEn value="true" edit="true" visible="true" name="Intel (R) Integrated LAN Enable" help_text="Intel (R) Integrated LAN related PCH Straps are set up automatically according to this setting."/>
+			<LANEn value="false" edit="false" visible="true" name="Intel (R) Integrated LAN Enable" help_text="Intel (R) Integrated LAN related PCH Straps are set up automatically according to this setting."/>
 		</Region3>
 		<Region4 name="PDR Region">
 			<Enabled value="false" edit="false" visible="false" name="PDR region enabled" help_text=""/>
@@ -192,12 +197,12 @@
 			<Configuration name="Configuration">
 				<ME name="ME">
 					<FwuOemId value="00000000-0000-0000-0000-000000000000" edit="true" visible="true" name="FW Update OEM ID" help_text="Enter UUID or file containing the UUID.  This UUID will make sure that customers can only update a platform with an image coming from the OEM of the platform.  If set to zero than any input is valid (including none) when doing a FW update."/>
-					<LanPowerWell value="3" value_list="0,,1,,2,,3" edit="true" visible="true" name="LAN Power Well Config" help_text="0 = Core Well, 1 = Sus Well, 2 = ME Well, 3 = SLP_LAN# (MGPIO3)"/>
+					<LanPowerWell value="0" value_list="0,,1,,2,,3" edit="true" visible="true" name="LAN Power Well Config" help_text="0 = Core Well, 1 = Sus Well, 2 = ME Well, 3 = SLP_LAN# (MGPIO3)"/>
 					<WlanPowerWell value="0x86" value_list="0x80,,0x82,,0x83,,0x86" edit="true" visible="true" name="WLAN Power Well Config" help_text="0x80 = Disabled, 0x82 = Sus Well, 0x83 = ME Well, 0x86 = WLAN Sleep via SLP_WLAN#"/>
-					<M3PwrRailAvail value="true" edit="true" visible="true" name="M3 Power Rails Availability" help_text="false = Not Available, true = Available"/>
+					<M3PwrRailAvail value="false" edit="true" visible="true" name="M3 Power Rails Availability" help_text="false = Not Available, true = Available"/>
 					<HostMeRegUnlock value="true" edit="true" visible="true" name="Host ME Region Flash Protection Override" help_text="Set this to TRUE if you want the ability to have BIOS write to the ME Region. Set to FALSE to opt out."/>
 					<ProcMissing value="No onboard glue logic" value_list="No onboard glue logic,,Glue logic tied to GPIO24" edit="true" visible="true" name="PROC_MISSING" help_text="This value will determine if there is glue logic present on the platform to detect a missing processor on desktop platforms."/>
-					<ProcEmulation value="EMULATE Intel (R) vPro (TM) capable Processor" value_list="No Emulation,,EMULATE Intel (R) vPro (TM) capable Processor,,EMULATE Intel (R) Core (TM) branded Processor,,EMULATE Intel (R) Celeron (R) branded Processor,,EMULATE Intel (R) Pentium (R) branded Processor,,EMULATE Intel (R) Xeon (R) branded Processor,,EMULATE Intel (R) Xeon (R) Manageability capable Processor" edit="true" visible="true" name="Processor Emulation" help_text="This gives the option to emulate different Intel ME FW behavior by changing the processor type on pre-production silicon. This field has no effect on production silicon."/>
+					<ProcEmulation value="No Emulation" value_list="No Emulation,,EMULATE Intel (R) vPro (TM) capable Processor,,EMULATE Intel (R) Core (TM) branded Processor,,EMULATE Intel (R) Celeron (R) branded Processor,,EMULATE Intel (R) Pentium (R) branded Processor,,EMULATE Intel (R) Xeon (R) branded Processor,,EMULATE Intel (R) Xeon (R) Manageability capable Processor" edit="true" visible="true" name="Processor Emulation" help_text="This gives the option to emulate different Intel ME FW behavior by changing the processor type on pre-production silicon. This field has no effect on production silicon."/>
 					<OemTag value="0x00000000" edit="true" visible="true" name="OEM Tag" help_text="An OEM identification number to describe the flash image represented by the value."/>
 					<HideFwUpdCtrl value="false" edit="true" visible="true" name="Hide FW Update Control" help_text="Setting this parameter to 'true' will not allow end users to 'disable' or 'password protect' the ME FW Update mechanism"/>
 					<DbgSiFeat value="0x00000000" edit="true" visible="true" name="Debug Si Features" help_text="Allows OEM control to enable FW features to assist with debug of the platform.  This control has no effect if used on production silicon."/>
@@ -224,7 +229,7 @@
 					<ATPerm value="No" value_list="No,,Yes" edit="true" visible="true" name="Intel (R) Anti-Theft Technology Permanently Disabled?" help_text="Select whether Intel (R) Anti-Theft Technology is permanently disabled."/>
 					<MeNetworkService value="No" value_list="No,,Yes" edit="true" visible="true" name="Intel (R) ME Network Service Permanently Disabled?" help_text="Select whether Intel (R) ME Network Service is permanently disabled."/>
 					<ServiceAdvDiscovery value="No" value_list="No,,Yes" edit="true" visible="true" name="Service Advertisement and Discovery Permanently Disabled?" help_text="Select whether Service Advertisement and Discovery is permanently disabled."/>
-					<ManageAppShipState value="Enabled" value_list="Enabled,,Disabled" edit="true" visible="true" name="Manageability Application Enable/Disable" help_text="Select whether or not Manageability Application is enabled or disabled."/>
+					<ManageAppShipState value="Disabled" value_list="Enabled,,Disabled" edit="true" visible="true" name="Manageability Application Enable/Disable" help_text="Select whether or not Manageability Application is enabled or disabled."/>
 				</FeaturesSupported>
 				<Nfc name="Intel (R) NFC Capabilities">
 					<NfcActive value="false" edit="true" visible="true" name="Near Field Communication Enabled" help_text="This setting determines whether Near Field Communication is enabled."/>
@@ -752,7 +757,13 @@
 						</Profile>
 					</Defaults>
 					<Custom>
-						<Profile name="UserProfile" base="Standard" selected="TRUE"/>
+						<Profile name="UserProfile" base="Standard" selected="TRUE">
+							<HwRegisters>
+								<SSCCTL_PCHPCIE100 value="0x00000008"/>
+								<OCKEN value="0x700F0F8C"/>
+								<SECOSS value="0x00002216"/>
+							</HwRegisters>
+						</Profile>
 					</Custom>
 					<LockMask value="0:Default"/>
 					<SelectedBy value="SoftStrap"/>
-- 
cgit v1.2.3