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ReleaseNotes

Copyright

Release Notes

© American Megatrends, Inc.


Copyright

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Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2014/05/19
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 1.0
Falcon Ridge - 1.1
BDW-TBT-LP - 1.0
Source Control Label: 4.6.5.3_TBT_013
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_180_048 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_180_033a or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.
TbtOemPorting.asl | This ASL file contains the Thunderbolt OEM related ASL routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_TOOLS_41, Dated: 2013-03-19
Visual eBios: RSS 5.73.0244, Dated: 2013-03-19
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtEnable;
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TbtWakeupSupport;
      UINT8 TbtAICSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtRmvReturnValue
      UINT8 TbtOptionROM;
      UINT8 TbtIOresourceEnable
      UINT8 TbtNVMversion
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtEnable | Indicate the Thunderbolt feature is enable/disable in run time
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtForcePWR | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtAICSupport | Indicate to support Thunderbolt Add-in Card.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtRmvReturnValue | Switch return value for _RMV method in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom
      TbtIOresourceEnable | Enable or disable IO resource workaround for thunderbolt device.

  • TbtBeforeSxExitFlow() - For Cactus Ridge / Redwood Ridge / Falcon Ridge / BDW-TBT-LP chips
    This function will be executed before doing Sx exit flow for Thunderbolt host in PEI phase :

    1. Function for OEM.
      For OEM, You can put any extra action for Thunderbolt before Sx Exit flow.

  • GetHRInfo() - For Cactus Ridge / Redwood Ridge / Falcon Ridge / BDW-TBT-LP chips
    This function is used to get Thunderbolt host chip information :

    1. Report used Thunderbolt host chip series to BIOS
      For OEM, only return used thunderbolt chip series on OEM board

  • SynchSecurityLevel() - For Redwood Ridge / Falcon Ridge / BDW-TBT-LP chips
    This function is used to synchronize Thunderbolt host security level between Thunderbolt FW and BIOS before entering setup page:

    1. BIOS might need to assert GPIO_3(__FORCE_PWR) then do Redwood Ridge handshake to get/set thunderbolt security level
      In this function, BIOS should not set OS_UP command

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For Cactus Ridge / Redwood Ridge / Falcon Ridge / BDW-TBT-LP chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge/Falcon Ridge/BDW-TBT-LP chips
    No. | Security Level | Description
    0x0 | Legacy Mode | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Unique ID | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | One time saved Key | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | DP++ only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0xF:4 | Reserved
    For Redwood Ridge/Falcon Ridge/BDW-TBT-LP Host chips, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • TBFP ASL function in TbtOemPorting.asl
    In Intel Thunderbolt Sample code rev 1.9, BIOS should report TBFP ASL function to control Thunderbolt host GPIO_3__FORCE_PWR pin. In TBFP function, BIOS only need assert/de-assert GPIO_3__FORCE_PWR pin via ASL code.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for Resource
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl
    "DEFAULT_TBT_CHIP" token - TbtOemBoard.sdl
    "TBT_PCI0_INI_SUPPORT" token - TbtDxe.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge / Falcon Ridge / BDW-TBT-LP Host chips (this flow has done in Thunderbolt module, OEM don't need porting)
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.
        If Thunderbolt host is Add-in Card, BIOS need apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx" command.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt BIOS additions - rev.1.9
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Support Thunderbolt AIC at NB PCIE slot.
General Bug Fixes:
when thunderbolt is disable in run time, PCIE device whcih using the same PCIE slot might work abnormal
EIP addressed in this label:
EIP165410 - Support Thunderbolt AIC at NB PCIE slot
EIP167031 - Variable's attribute needs to be reviewed by Variable's attribute needs to be reviewed by Thunderbolt component driver
Files changed for General Bug and EIP Fixe:
[TAG] EIP165410
[Category] New Feature
[Description] Support Thunderbolt AIC at NB PCIE slot
[Files] TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni TbtSetupReset.c

[TAG] EIP167031
[Category] Improvement
[Description] Variable's attribute needs to be reviewed by Variable's attribute needs to be reviewed by Thunderbolt component driver
[Files] TbtSmm.c

[TAG] EIP N/A
[Category] Bug Fix
[Severity] Minor
[Symptom] when thunderbolt is disable in run time, PCIE device whcih using the same PCIE slot might work abnormal
[RootCause] protect thunderbolt device function still work
[Solution] According thunderbolt policy to skip protect function
[Files] TbtDxe.c TbtDxeLib.c

[TAG] EIP N/A
[Category] Improvement
[Description] Using setup item choose return value of _RMV method in ASL code
[Files] TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd TbtSetup.sdl TbtSetup.uni

[TAG] EIP N/A
[Category] Improvement
[Description] Add new PCH-LP device ID
[Files] TbtDxeLib.c

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • According Thunderbolt Spec, the pcie root port which is thunderbolt loacted should not enable advanced error reporting.

  • Thunderbolt doesn't support PCIE root port swap, please make sure "PCIE Root Port Swap" function is disable.

  • About Thunderbolt Add-in card, this module just follows Thunderbolt BIOS Spec to implement code to support this device with basic validation.

  • Now Thunderbolt module doesn't support non Intel RC project, if your Intel platform is without Intel RC and you want support Thunderbolt feature, please double check with module owner first for supporting.

  • For Haswell/Haswell-Refresh platform, the "TBT_PCI0_INI_SUPPORT" token need enable for New Intel PCH RC.

  • Dynamic Thunderbolt AIC location need PCH module co-work, if you want enable this feature, please double check with PCH owner on your platform first.

  • Dynamic Thunderbolt AIC location conflict with fix bus feature.

  • For new Thunderbolt host chip BDW-TBT-LP(WR), this module just follows Thunderbolt BIOS Spec to implement code to support this device without any validation.

  • Please do not set Thunderbolt host default location at any NB PCIE slot.

  • The value range of TbtHostLocation variable start from 0, 0 ~ 1Fh is for SB PCIE slot, 20h and above is for NB PCIE slot.

  • If you found Thunderbolt AIC cannot work under NB PCIE slot on your platform, please refer EIP165410 first.

  • Thunderbolt module will not tack care PCIE root port enable/disable, so you need implement it by yourselves when Thunderbolt AIC is at NB PCIE slot.

Remaining Issues:
None
Unit Testing:
Please refer EIP165410 attachment
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    Thunderbolt - Host Functional Validation Test Specification
    EIP#113859 is test result on Thunderbolt CRB
Release History:
  • 4.6.5.3_TBT_012

  • 4.6.5.3_TBT_011

  • 4.6.5.3_TBT_010

  • 4.6.5.3_TBT_009

  • 4.6.5.3_TBT_008

  • 4.6.5.3_TBT_007

  • 4.6.5.3_TBT_006

  • 4.6.5.3_TBT_005

  • 4.6.5.3_TBT_004

  • 4.6.5.3_TBT_003

  • 4.6.5.3_TBT_002

  • 4.6.5.3_TBT_001

  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2011/12/08
Source Control Label: 4.6.4.1_TBT_085_000
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routines.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Thunderbolt OEM Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemSmm.sdl | This is the AMI SDL File for the Thunderbolt OEM SMM module part.
TbOemtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM SMM module part.
TbtOemSmm.c | This source file contains the Thunderbolt OEM SMM related routines.
TbtOemSmm.dxs | This dependency file describes the dependency expression for the TbtOemSmm.ffs file.

AMI Build Tools:
Tools Label: 4.5.5_Tools_37 , Dated: 2011-09-14
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#

  • TbtGo2SxCallback()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

    2. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • OemProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | 1 | 1
    • Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 250ms period.
Reference or 3rd Party code in this Release:
None
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
None
General Bug Fixes:
None
EIP addressed in this label:
None
Files changed for EIP Fixes:
None
Known issues and limitations in this label:
None
Remaining Issues:
None
Release History:
  • Labeled '4.6.4.1_TBT_085_000' :2011/12/08

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/03/03
Source Control Label: 4.6.4.1_TBT_091_000
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routines.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_37 , Dated: 2011-09-14
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT8 SmiNotifyEnabled;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      SmiNotifyEnabled | Enable or disable SMI/Notify support.

  • ActiveTbtGpio2()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2()
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • ProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | Assert for 250ms | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | Assert for 250ms | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 250ms | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | Assert for 250ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    • Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 250ms period.
  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _L1X method should notify to Windows.
Reference or 3rd Party code in this Release:
  • 489039_Thunderbolt_BIOS_additions_rev.1.1.zip
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Updated Thunderbolt specification to version 0.91
  • Added new setup item "Smi/Notify Support" to enable or disable SMI/Notify support for debugging proposal.
  • Added new setup item "Thunderbolt Wake Delay" to determine delay time when system wakeup from sleep status.
  • Added 489039_Thunderbolt_BIOS_additions_rev.1.1.zip.
  • Added TbtPei, TbtDxeLib and TbtOemLib.
  • Removed TbtOemSmm.
General Bug Fixes:
None
EIP addressed in this label:
None
Files changed for EIP Fixes:
None
Known issues and limitations in this label:
None
Remaining Issues:
None
Release History:
  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/04/16
Source Control Label: 4.6.4.1_TBT_091_001
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routines.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_37 , Dated: 2011-09-14
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT8 SmiNotifyEnabled;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      SmiNotifyEnabled | Enable or disable SMI/Notify support.

  • ActiveTbtGpio2()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2()
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • ProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | Assert for 250ms | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | Assert for 250ms | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 250ms | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | Assert for 250ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    • Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 250ms period.
  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _L1X method should notify to Windows.
Reference or 3rd Party code in this Release:
None
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
None
General Bug Fixes:
None
EIP addressed in this label:
[TAG] EIP 86590
Files changed for EIP Fixes:
[TAG] None
[Category] Improvement
[Description] Improve ASL code, which redefines device name and RMV mothod at same address when project supports RMV method, that might cause conflict.
[Files] TbtDxe.c TbtOemBoard.sdl TbtGpe.asl

[TAG] None
[Category] Improvement
[Description] Fix Programming error at specification 0.91
[Files] TbtSmm.c

[TAG] None
[Category] Improvement
[Description] Fix Programming error at specification 0.90
[Files] TbtPei.c

[TAG] EIP 86590
[Category] Bug Fix
[Description] Only EP#1 can be detected after resume from S3.
[Files] TbtDxe.sdl TbtGpe.asl

Known issues and limitations in this label:
None
Remaining Issues:
None
Release History:
  • 4.6.4.1_TBT_085_000

  • 4.6.4.1_TBT_091_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/05/07
Source Control Label: 4.6.4.1_TBT_092_000
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c/td> | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routines.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_38 , Dated: 2011-09-14
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.

  • ActiveTbtGpio2()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2()
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • ProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | Assert for 250ms | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | Assert for 250ms | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 250ms | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | Assert for 250ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 250ms period.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _L1X method should notify to Windows.
Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.2
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Updated Thunderbolt specification to version 0.92
  • Added new setup item "SwSMI Support" to enable or disable SwSMI support in ASL code for debugging proposal.
  • Added new setup item "Notify Support" to enable or disable Notify support in ASL code for debugging proposal.
  • Added new setup item "Thunderbolt SwSMI Delay" to determine delay time when system calling SMI.
  • Added 489039_Thunderbolt_BIOS_additions_rev.1.2.zip.
General Bug Fixes:
  • fix Thunderbolt function fail in windows 8
EIP addressed in this label:
[TAG] EIP 89207
Files changed for EIP Fixes:
[TAG] EIP89207
[Category] Spec Update
[Description] OPTIONAL workaround for devices that don't support surprise-removal
[Files] TbtSmm.c

[TAG] None
[Category] Bug Fix
[Symptom] Thunderbolt function is broken in windows 8 and sometime EP#6 shows yellow mark in windows device manager
[RootCause] SCI is signaled incorrectly
[Solution] enable GPIO routing
[Files] TbtSmm.c

[TAG] None
[Category] Improvement
[Description] Change SwSMI value avoiding conflict
[Files] TbtSmm.sdl

[TAG] None
[Category] Improvement
[Description] change default value of token, because of it is need SwSMI when S3 resume
[Files] TbtDxe.sdl

[TAG] None
[Category] Improvement
[Description] Add three setup items for debug
[Files] TbtDxe.c TbtGpe.asl TbtSmm.c TbtSetup.sd TbtSetup.uni TbtOemBoard.c TbtOemBoard.h

Known issues and limitations in this label:
None
Remaining Issues:
None
Release History:
  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/05/21
Source Control Label: 4.6.4.1_TBT_093_000
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routines.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_38 , Dated: 2011-09-14
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.

  • ActiveTbtGpio2()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2()
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • ProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | Assert for 250ms | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | Assert for 250ms | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 250ms | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | Assert for 250ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 250ms period.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _L1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value | Suggested default Value in setup menu
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 63 ＊ | 48
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 256 | 128
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 256 | 128
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF8000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 24 | 24
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
Reference or 3rd Party code in this Release:
None
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Updated Thunderbolt specification to version 0.93
General Bug Fixes:
None
EIP addressed in this label:
[TAG] EIP 90003
[TAG] EIP 90169
[TAG] EIP 90334
Files changed for EIP Fixes:
[TAG] EIP90003
[Category] Improvement
[Description] Using TBT devices w/ option rom enabled, system cannot boot to OS.
[Files] TbtDxe.c TbtSmm.c TbtOemBoard.sdl

[TAG] EIP90169
[Category] Spec Update
[Category] Spec Update
[Description] Specificatoin Update 0.93 - BIOS should stall wake process for approximately 2.5 seconds to ensure completeness of TBT link to all endpoint devices.
[Files] TbtSetup.sdl

[TAG] EIP90334
[Category] Improvement
[Description] Implement security level function on CRB
[Files] TbtOemLib.c

[TAG] None
[Category] Improvement
[Description] Fix Programming error at specification 0.92 update
[Files] TbtSmm.c

Known issues and limitations in this label:
None
Remaining Issues:
None
Release History:
  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/05/22
Source Control Label: 4.6.4.1_TBT_094_000
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routines.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_38 , Dated: 2011-09-14
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TBSurpriseRemove;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.

  • ActiveTbtGpio2()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2()
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • ProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | Assert for 250ms | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | Assert for 250ms | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 250ms | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | Assert for 250ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 250ms period.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _L1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value | Suggested default Value in setup menu
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 63 ＊ | 48
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 256 | 128
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 256 | 128
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF8000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 24 | 24
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
Reference or 3rd Party code in this Release:
None
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Updated Thunderbolt specification to version 0.94
  • Add new setup item "Thunderbolt Surprise-Removal" to enable or disable thunderbolt surprise-removal for Thunderbolt specification version 0.94
General Bug Fixes:
None
EIP addressed in this label:
[TAG] EIP 90650
Files changed for EIP Fixes:
[TAG] EIP90650
[Category] Spec Update
[Description] Specificatoin Update 0.94 - The default value of OPTIONAL workaround for devices that don't support surprise-removal should be disable.
[Files] TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni

[TAG] None
[Category] Improvement
[Description] Rollback default value of token
[Files] TbtDxe.sdl

Known issues and limitations in this label:
None
Remaining Issues:
None
Release History:
  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/07/06
Source Control Label: 4.6.4.1_TBT_094_001
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routines.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_39 , Dated: 2012-04-04
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TBSurpriseRemove;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.

  • ActiveTbtGpio2()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2()
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • ProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | Assert for 250ms | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | Assert for 250ms | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 250ms | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | Assert for 250ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 250ms period.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _L1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value | Suggested default Value in setup menu
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 63 ＊ | 48
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 256 | 128
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 256 | 128
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF8000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 24 | 24
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
Reference or 3rd Party code in this Release:
None
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
None
General Bug Fixes:
None
EIP addressed in this label:
None
Files changed for EIP Fixes:
[TAG] None
[Category] Improvement
[Description] Add Thunderbolt version on setup menu
[Files] Thunderbolt.sdl TbtSetup.sd TbtSetup.uni TbtSetup.c

[TAG] None
[Category] Improvement
[Description] clean redundancy code in surprise-removal workaround
[Files] TbtSmm.c

[TAG] None
[Category] Improvement
[Description] Removing registered S1callback function when system entering S1 state
[Files] TbtSmm.c

[TAG] None
[Category] Improvement
[Description] fix programming error
[Files] TbtSmm.dxs

[TAG] None
[Category] Improvement
[Description] Add resource token, it needs the co-ordination of the chipset
[Files] TbtOemBoard.sdl

Known issues and limitations in this label:
None
Remaining Issues:
None
Release History:
  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/07/31
Source Control Label: 4.6.5.3_TBT_100_000
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routines.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_39 , Dated: 2012-04-04
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • ActiveTbtGpio2()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2()
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • ProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 250ms period.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value | minimum default Value in setup menu
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 63 ＊ | 48
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 640 | 353
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 640 | 544
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF8000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 48 | 40
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.3
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Updated Thunderbolt specification to version 1.00
  • Added new setup item "Ignore Thunderbolt Option Rom" to enable or disable ignore Thunderbolt device Option Rom at POST time.
  • Added new setup item "Reseved Mem per phy slot" to decide resources for per slot.
  • Added new setup item "Reseved PMem per phy slot" to decide resources for per slot.
  • Added new setup item "Reseved IO per phy slot" to decide resources for per slot.
  • Added 489039_Thunderbolt_BIOS_additions_rev.1.3.zip.
General Bug Fixes:
None
EIP addressed in this label:
  • [TAG] EIP96350 - Thunderbolt - BIOS support of Thunderbolt devices - rev 1.0
  • [TAG] EIP90644 - Change pre-boot event timing from ready to boot to pci bus finish assigning resources
  • [TAG] EIP91119 - Enable or Disable Thunderbolt device Option Rom
Files changed for EIP Fixes:
[TAG] None
[Category] Spec Update
[Description] Module version number update to 100 for Spec 1.0
[Files] Thunderbolt.sdl

[TAG] EIP96350
[Category] Spec Update
[Description] Updated Thunderbolt specification to version 1.00
[Files] TbtDxe.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni TbtSetup.sdl

[TAG] EIP90644
[Category] Improvement
[Description] Change pre-boot event timing from ready to boot to pci bus finish assigning resources
[Files] TbtDxe.sdl TbtDxe.c TbtDxeLib.c TbtDxeLib.h

[TAG] EIP91119
[Category] Improvement
[Description] Enable/Disable Thunderbolt device option rom at POST time
[Files] TbtDxe.c TbtOemBoard.c TbtOemBoard.h TbtOemBoard..sdl TbtSetup.sdl TbtSetup.sd TbtSetup.uni

[TAG] None
[Category] Improvement
[Description] Adding power button event
[Files] TbtSmm.c

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.
  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port, but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.
Remaining Issues:
None
Release History:
  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/08/17
Source Control Label: 4.6.5.3_TBT_101_000
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routines.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_39 , Dated: 2012-04-04
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • ActiveTbtGpio2()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2()
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • ProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 250ms period.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 63 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 640 | 353 | 736
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 640 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF8000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 48 | 0 | 0
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.4
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Update Thunderbolt specification to version 1.1
  • Add 489039_Thunderbolt_BIOS_additions_rev.1.4.zip.
  • Add Intel Sample code version information to Thunderbolt setup page.
General Bug Fixes:
None
EIP addressed in this label:
  • [TAG] EIP98269 - Thunderbolt - BIOS support of Thunderbolt devices - rev 1.1
Files changed for EIP Fixes:
[TAG] None
[Category] Spec Update
[Description] Module version number update to 100 for Spec 1.1
[Files] Thunderbolt.sdl

[TAG] EIP98269
[Category] Spec Update
[Description] Updated Thunderbolt specification to version 1.1
[Files] TbtSmm.c

[TAG] None
[Category] Improvement
[Description] Add Intel Sample code version information
[Files] Thunderbolt.sdl TbtSetup.c TbtSetup.sd TbtSetup.uni

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.
  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port, but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.
  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark.
Remaining Issues:
None
Release History:
  • 4.6.4.1_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/08/20
Source Control Label: 4.6.5.3_TBT_101_001
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routines.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_39 , Dated: 2012-04-04
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • ActiveTbtGpio2()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2()
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • ProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 250ms period.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 63 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 640 | 353 | 736
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 640 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF8000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 48 | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, the minimum value should be 40

  • Adjust for IO Resource Wrokaround
    TBT_FCTP token(TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.
Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.4
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Fix IO resource workaround is broken at 4C 2prot case.
  • Create a setup item "TBT Host chip's NVM version" for IO resource workaround in 4C 2port case.
General Bug Fixes:
None
EIP addressed in this label:
None
Files changed for EIP Fixes:
[TAG] None
[Category] Improvement
[Description] Fix IO resource workaround broken in 4C 2port case
[Files] TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni

[TAG] None
[Category] Improvement
[Description] Change default value of resources in 4C 2 port case
[Files] TbtOemBoard.sdl

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.
  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port, but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.
  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).
  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.
  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation is EP#6 might can not work if EP#6 need using IO resource. Now this workaround only works fine with resvered IO resource bigger than 40K and host chip's EEEPROM is Rev.17 or latter version.
Remaining Issues:
None
Release History:
  • 4.6.4.1_TBT_101_000

  • 4.6.4.1_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/09/03
Source Control Label: 4.6.5.3_TBT_101_002
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_39 , Dated: 2012-04-04
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • ActiveTbtGpio2()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2()
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • ProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 250ms period.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 63 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 640 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 640 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF8000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 48 | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, the minimum value should be 40

  • Adjust for IO Resource Wrokaround
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.4
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Add new tokens which related resource for 2C and 4C case.
  • Change Thunderbolt smm driver type and dependence for SharkBay platform.
General Bug Fixes:
  • Fix Intel sample code bug
EIP addressed in this label:
None
Files changed for EIP Fixes:
[TAG] None
[Category] Improvement
[Description] Change driver type and dependence for SharkBay platform
[Files] TbtSmm.c TbtSmm.mak TbtSmm.dxs

[TAG] None
[Category] Improvement
[Description] Fix Intel sample code bug
[Files] TbtSmm.c

[TAG] None
[Category] Improvement
[Description] Change default value of resources in 4C 2 port case
[Files] TbtOemBoard.sdl

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port, but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation is EP#5 and EP#6 might can not work normally and show yellow mark(error code:12) in windows device manager if EP#5 and EP#6 need using IO resource. Now this workaround only works fine with resvered IO resource bigger than 40K and host chip's EEEPROM is Rev.17 or latter version.

  • In 4c case, plugging 12 thunderbolt devices then power on system, system will hangs up. This root cause is PciBus will detect device and assign IO resource if device needs, this might cause IO resource not enough.

Remaining Issues:
    None
Release History:
  • 4.6.4.1_TBT_101_001

  • 4.6.4.1_TBT_101_000

  • 4.6.4.1_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/10/05
Source Control Label: 4.6.5.3_TBT_102_000
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_39 , Dated: 2012-04-04
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • ActiveTbtGpio2()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2()
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9()
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9()
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ProgramTbtSecurityLevel() & FinialProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to improve Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 63 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 640 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 640 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF8000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 48 | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for IO Resource Wrokaround
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.4
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Update Thunderbolt specification to version 1.2.
  • Change programming security level timing to save boot time.
General Bug Fixes:
None
EIP addressed in this label:
  • [TAG] EIP102947 - BIOS support of Thunderbolt devices - rev 1.2
Files changed for EIP Fixes:
[TAG] EIP102947
[Category] Spec Update
[Description] Updated Thunderbolt specification to version 1.2
[Files] TbtPei.c TbtOemLib.c TbtOemLib.h

[TAG] None
[Category] Improvement
[Description] Change Spec version number to 102 for Thunderbolt Spec 1.2
[Files] Thunderbolt.sdl

[TAG] None
[Category] Improvement
[Description] Change Programming security level timing for saving boot time
[Files] TbtPei.c TbtDxe.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h

[TAG] None
[Category] Improvement
[Description] Use token to defien thunderbolt chip pins and update sample code
[Files] TbtOemBoard.c TbtOemBoard.sdl

[TAG] None
[Category] Improvement
[Description] Use global definition for genernic
[Files] TbtSmm.c TbtSmm.mak

[TAG] None
[Category] Improvement
[Description] Fix system hangs up at POST time when plugging 12 Thunderbolt devices then powering on system
[Files] TbtDxeLib.c

[TAG] None
[Category] Improvement
[Description] Clone SB PCIE setup item which are related thunderbolt
[Files] TbtSetup.sd TbtSetup.uni

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port, but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.
Remaining Issues:
None
Release History:
  • 4.6.4.1_TBT_101_002

  • 4.6.4.1_TBT_101_001

  • 4.6.4.1_TBT_101_000

  • 4.6.4.1_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/10/29
Source Control Label: 4.6.5.3_TBT_103_000
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_39 , Dated: 2012-04-04
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • ActiveTbtGpio2()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2()
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9()
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9()
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9()
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC()
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC()
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() & FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel()
    By default Thunderbolt host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI | When Thunderbolt domain is on, NHI is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI | When Thunderbolt domain is on, NHI is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI | When Thunderbolt domain is on, NHI is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for IO Resource Wrokaround
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.
        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c
        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.
Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.4
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Update Thunderbolt Spec 1.3 to ready for Redwood Ridge.
  • Create new setup item "Enable Handle TBT's POC" to handle thunderbolt host chip's POC or not.
General Bug Fixes:
None
EIP addressed in this label:
  • [TAG] EIP104870 - BIOS support of Thunderbolt devices - rev 1.3
Files changed for EIP Fixes:
[TAG] None
[Category] Improvement
[Description] Change Spec version number to 103 for Thunderbolt Spec 1.3
[Files] Thunderbolt.sdl

[TAG] EIP104870
[Category] Spec Update
[Severity] Important
[Description] Change sleep flow and wake up flow for Spec 1.2 and Spec 1.3
[Files] TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni

[TAG] None
[Category] Improvement
[Description] Change GPIO routing for SharkBay ULT platform
[Files] TbtDxe.c TbtDxeLib.c TbtDxeLib.h TbtSmm.c TbtGpe.asl

[TAG] None
[Category] Improvement
[Description] Use token to decide to skip thunderbolt device initial
[Files] TbtDxeLib.c TbtOemBoard.sdl

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port, but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.
Remaining Issues:
None
Release History:
  • 4.6.4.1_TBT_102_000

  • 4.6.4.1_TBT_101_002

  • 4.6.4.1_TBT_101_001

  • 4.6.4.1_TBT_101_000

  • 4.6.4.1_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2012/12/12
Source Control Label: 4.6.5.3_TBT_104_000
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Thunderbolt/;
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

AMI Build Tools:
Tools Label: 4.5.5_Tools_39 , Dated: 2012-04-04
Visual eBios: RSS 5.72.0201, Dated: Sep., 2011
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo()
    This function is used to get Thunderbolt host chip information :

    1. BIOS uses asserting GPIO_3(__FORCE_PWR) pin to distinguish Thunderbolt host chip
      That will trigger Host Router

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() & FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel()

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge chip
    No. | Security Level | Description
    0x0 | Normal mode with NHI | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | Redriver only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0x4 | Allow Thunderbolt devices to connect based on user approval - at this mode the connection manager requests connection approval from the host SW.
    0xF:5 | Reserved
    For Redwood Ridge Host chip, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for IO Resource Wrokaround
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.5
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Update Thunderbolt Spec 1.4 and Intel Sample code Rev. 1.5.
  • Add Thunderbolt TSE Setup Reset Hook
General Bug Fixes:
None
EIP addressed in this label:
  • [TAG] EIP108272 - Implement Thunderbolt - BIOS support of Thunderbolt devices - rev 1.4+
Files changed for EIP Fixes:
[TAG] None
[Category] Improvement
[Description] Change Spec version number to 104 for Thunderbolt Spec 1.4 and Sample code version number to 15.
[Files] Thunderbolt.sdl

[TAG] EIP108272
[Category] Spec Update
[Severity] Important
[Description] Update to Spec 1.4 to support Redwood Ridge chip
[Files] TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h

[TAG] None
[Category] Improvement
[Description] Workaround for synchronizing cache line size of Thunderbolt
[Files] TbtSmm.c

[TAG] None
[Category] New Feature
[Description] Add Thunderbolt TSE Setup Reset Hook
[Files] TbtSetup.sdl TbtSetup.mak TbtSetup.cif TbtSetupReset.c
Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port, but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • Security level of Redwood Ridge chip is fail, because Redwood Ride's NVM is still not ready.

Remaining Issues:
None
Release History:
  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2013/01/10
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 0.5
Source Control Label: 4.6.5.3_TBT_000
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_071_091 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo()
    This function is used to get Thunderbolt host chip information :

    1. BIOS uses asserting GPIO_3(__FORCE_PWR) pin to distinguish Thunderbolt host chip
      That will trigger Host Router

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For both of Cactus Ridge and Redwood Ridge chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge chip
    No. | Security Level | Description
    0x0 | Normal mode with NHI | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | Redriver only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0x4 | Allow Thunderbolt devices to connect based on user approval - at this mode the connection manager requests connection approval from the host SW.
    0xF:5 | Reserved
    For Redwood Ridge Host chip, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for IO Resource Wrokaround
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.5
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Thunderbolt Spec 1.6 for Cactus Ridge chip.
  • Thunderbolt Spec 0.5 for Redwood Ridge chip.
General Bug Fixes:
None
EIP addressed in this label:
  • EIP#108272 - Implement Thunderbolt - BIOS support of Thunderbolt devices - rev 1.4
Files changed for EIP Fixes:
[TAG] EIP108272
[Category] Spec Update
[Severity] Important
[Description] Update to Spec 1.6 for Cactus Ridge and Spec 0.5 for Redwood Ridge
[Files] TbtPei.c TbtOemBoard.c TbtOemLib.c TbtOemLib.h TbtSetup.c TbtSetup.sd TbtSetup.uni TbtSetupReset.c

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

Remaining Issues:
None
Unit Testing:
None
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    None
Release History:
Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2013/01/18
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 0.5
Source Control Label: 4.6.5.3_TBT_001
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_090_025 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo()
    This function is used to get Thunderbolt host chip information :

    1. BIOS uses asserting GPIO_3(__FORCE_PWR) pin to distinguish Thunderbolt host chip
      That will trigger Host Router

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For both of Cactus Ridge and Redwood Ridge chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge chip
    No. | Security Level | Description
    0x0 | Normal mode with NHI | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | Redriver only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0x4 | Allow Thunderbolt devices to connect based on user approval - at this mode the connection manager requests connection approval from the host SW.
    0xF:5 | Reserved
    For Redwood Ridge Host chip, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for IO Resource Wrokaround
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.5
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
None
General Bug Fixes:
None
EIP addressed in this label:
None
Files changed for EIP Fixes:
[TAG] EIP N/A
[Category] Improvement
[Description] Improve _RMV ASL code for SharkBay RC
[Files] TbtDxe.sdl TbtDxe.c TbtGpe.asl

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

Remaining Issues:
None
Unit Testing:
None
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    None
Release History:
  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2013/01/27
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 0.5
Source Control Label: 4.6.5.3_TBT_002
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_090_025 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo()
    This function is used to get Thunderbolt host chip information :

    1. BIOS uses asserting GPIO_3(__FORCE_PWR) pin to distinguish Thunderbolt host chip
      That will trigger Host Router

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For both of Cactus Ridge and Redwood Ridge chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge chip
    No. | Security Level | Description
    0x0 | Normal mode with NHI | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | Redriver only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0x4 | Allow Thunderbolt devices to connect based on user approval - at this mode the connection manager requests connection approval from the host SW.
    0xF:5 | Reserved
    For Redwood Ridge Host chip, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for IO Resource Wrokaround
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.5
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
None
General Bug Fixes:
  • Thunderbolt device resource is changed by OS under win8.
  • Thunderbolt debug setup item function fail.
EIP addressed in this label:
None
Files changed for General Bug and EIP Fixe:
[TAG] EIP N/A
[Category] Bug Fix
[Severity] Minor
[Symptom] TBT debug setup item function fail
[RootCause] ASL updating error
[Files] TbtGpe.asl

[TAG] EIP N/A
[Category] Bug Fix
[Severity] Critical
[Symptom] IO resource will be changed by win8
[RootCause] OpROM address location error when assigning OpROM address to PCIE config register
[Files] TbtSmm.c

[TAG] EIP N/A
[Category] Improvement
[Description] Change sample code avoiding side effect
[Files] TbtOemLib.c

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • According Thunderbolt Spec, the pcie root port which is thunderbolt loacted should not enable advanced error reporting.

  • For SharkBay platform, Thunderbolt doesn't support PCIE root port swap, please make sure "PCIE_PORT_SWAP" is disable.

Remaining Issues:
None
Unit Testing:
None
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    None
Release History:
  • 4.6.5.3_TBT_001

  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2013/02/08
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 0.9
Source Control Label: 4.6.5.3_TBT_003
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_090_025 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo()
    This function is used to get Thunderbolt host chip information :

    1. BIOS uses asserting GPIO_3(__FORCE_PWR) pin to distinguish Thunderbolt host chip
      That will trigger Host Router

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For both of Cactus Ridge and Redwood Ridge chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge chip
    No. | Security Level | Description
    0x0 | Normal mode with NHI | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | Redriver only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0x4 | Allow Thunderbolt devices to connect based on user approval - at this mode the connection manager requests connection approval from the host SW.
    0xF:5 | Reserved
    For Redwood Ridge Host chip, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for IO Resource Wrokaround
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.5
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Thunderbolt Spec 0.9 for Redwood Ridge chip.
General Bug Fixes:
None
EIP addressed in this label:
  • EIP114556 - Implement Thunderbolt - RR BIOS Implementation guide - rev 0.9

Files changed for General Bug and EIP Fixe:
[TAG] EIP114556
[Category] Spec Update
[Severity] Normal
[Description] Update to Spec 0.9 for Redwood Ridge
[Files] Thunderbolt.sdl

[TAG] EIP114556
[Category] Spec Update
[Severity] Important
[Description] Change fast link bring-up flow for Thunderbolt RR Spec 0.9
[Files] TbtPei.sdl

[TAG] EIP114556
[Category] Spec Update
[Severity] Minor
[Description] Update RR handshake flow and sample code for Thunderbolt RR Spec 0.9
[Files] TbtOemLib.c

[TAG] EIP114556
[Category] Spec Update
[Severity] Normal
[Description] Add more definition for Thunderbolt RR Spec 0.9
[Files] TbtOemBoard.h

[TAG] EIP N/A
[Category] Improvement
[Description] Following Intel sample code move _INI method of thunderbolt from under PCIE root port to under system bus
[Files] TbtDxe.sdl TbtGpe.asl

Known issues and limitations in this label:
  • For Thunderbolt Logo test, please enable "TBT_PCIBUS_SKIP" token which is in TbtOemBoard.sdl.

  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • According Thunderbolt Spec, the pcie root port which is thunderbolt loacted should not enable advanced error reporting.

  • For SharkBay platform, Thunderbolt doesn't support PCIE root port swap, please make sure "PCIE_PORT_SWAP" is disable.

  • For Redwood Ridge chip, FW security level does not synchronize with setup item in special case.

Remaining Issues:
None
Unit Testing:
None
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    Thunderbolt - Host Functional Validation Test Specification
    EIP#113859 is test result on Thunderbolt CRB
Release History:
  • 4.6.5.3_TBT_002

  • 4.6.5.3_TBT_001

  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2013/04/13
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 0.9
Source Control Label: 4.6.5.3_TBT_004
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_090_025 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo() - For both of Cactus Ridge and Redwood Ridge chips
    This function is used to get Thunderbolt host chip information :

    1. Report used Thunderbolt host chip series to BIOS
      For Oem, only return used thunderbolt chip series on OEM board

  • SynchSecurityLevel() - For Redwood Ridge chip
    This function is used to synchronize Thunderbolt host security level between Thunderbolt FW and BIOS before entering setup page:

    1. BIOS might need to assert GPIO_3(__FORCE_PWR) then do Redwood Ridge handshake to get/set thunderbolt security level
      In this function, BIOS should not set OS_UP command

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For both of Cactus Ridge and Redwood Ridge chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge chip
    No. | Security Level | Description
    0x0 | Legacy Mode | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Unique ID | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | One time saved Key | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | DP++ only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0xF:4 | Reserved
    For Redwood Ridge Host chip, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for Resource
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl
    "DEFAULT_TBT_CHIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.6
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Intel Thunderbolt sample code rev. 1.6
General Bug Fixes:
None
EIP addressed in this label:
  • EIP120580 - Implement Thunderbolt - BIOS additions - rev.1.6

Files changed for General Bug and EIP Fixe:
[TAG] EIP120580
[Category] Spec Update
[Severity] Minor
[Description] Update Intel Thunderbolt sample code to rev. 1.6
[Files] Thunderbolt.sdl TbtSmm.c

[TAG] EIP N/A
[Category] Improvement
[Description] Use token to decide where location of OS_UP command for RR chip is
[Files] TbtDxe.sdl TbtGpe.asl

[TAG] EIP N/A
[Category] Improvement
[Description] Fix might hang up when S3 resuming
[Files] TbtGpe.asl

[TAG] EIP N/A
[Category] Improvement
[Description] Adding a TPTS method into _PTS method in ASL code
[Files] TbtDxe.sdl TbtGpe.asl

[TAG] EIP N/A
[Category] Improvement
[Description] Change reported MMIO address way in ASL code
[Files] TbtGpe.asl

[TAG] EIP N/A
[Category] Improvement
[Description] Fix Thunderbolt ready to boot event does not be excuted on ULT platform
[Files] TbtDxe.c

[TAG] EIP N/A
[Category] Improvement
[Description] Double check Security Level between Thunderbolt host FW and BIOS are same or not for Redwood Ridge chip when entering setup page
[Files] TbtOemLib.c TbtOemLib.h TbtSetupReset.c

[TAG] EIP N/A
[Category] Improvement
[Description] Add cloned PCIE config for ULT platform
[Files] TbtSetup.sd

[TAG] EIP N/A
[Category] Improvement
[Description] Clone PCIE prot swap setup item and set disable by default
[Files] TbtSetup.sdl TbtSetup.sd TbtSetup.uni

[TAG] EIP N/A
[Category] Improvement
[Description] Adding mask definition for reading Redwood Ridge command
[Files] TbtOemBoard.h

[TAG] EIP N/A
[Category] Improvement
[Description] Add new sample code for CRB
[Files] TbtOemLib.c

[TAG] EIP N/A
[Category] Improvement
[Description] Change token default value
[Files] TbtOemBoard.sdl

[TAG] EIP N/A
[Category] Improvement
[Description] Update sample code to fix FW's security level doesn't match BIOS configuration
[Files] TbtOemLib.c

[TAG] EIP N/A
[Category] Improvement
[Description] Fix security level of CR chip not be programming in some case
[Files] TbtPei.c

[TAG] EIP N/A
[Category] Improvement
[Description] Use token decide default thunderbolt Chip
[Files] TbtOemBoard.sdl TbtOemLib.c

Known issues and limitations in this label:
  • For Thunderbolt Logo test, please enable "TBT_PCIBUS_SKIP" token which is in TbtOemBoard.sdl.

  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • According Thunderbolt Spec, the pcie root port which is thunderbolt loacted should not enable advanced error reporting.

  • Thunderbolt doesn't support PCIE root port swap, please make sure "PCIE Root Port Swap" function is disable.

Remaining Issues:
None
Unit Testing:
None
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    Thunderbolt - Host Functional Validation Test Specification
    EIP#113859 is test result on Thunderbolt CRB
Release History:
  • 4.6.5.3_TBT_003

  • 4.6.5.3_TBT_002

  • 4.6.5.3_TBT_001

  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2013/04/24
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 0.9
Source Control Label: 4.6.5.3_TBT_005
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_090_025 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo() - For both of Cactus Ridge and Redwood Ridge chips
    This function is used to get Thunderbolt host chip information :

    1. Report used Thunderbolt host chip series to BIOS
      For Oem, only return used thunderbolt chip series on OEM board

  • SynchSecurityLevel() - For Redwood Ridge chip
    This function is used to synchronize Thunderbolt host security level between Thunderbolt FW and BIOS before entering setup page:

    1. BIOS might need to assert GPIO_3(__FORCE_PWR) then do Redwood Ridge handshake to get/set thunderbolt security level
      In this function, BIOS should not set OS_UP command

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For both of Cactus Ridge and Redwood Ridge chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge chip
    No. | Security Level | Description
    0x0 | Legacy Mode | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Unique ID | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | One time saved Key | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | DP++ only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0xF:4 | Reserved
    For Redwood Ridge Host chip, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for Resource
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl
    "DEFAULT_TBT_CHIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.6
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
None
General Bug Fixes:
None
EIP addressed in this label:
None
Files changed for General Bug and EIP Fixe:
[TAG] EIP N/A
[Category] Improvement
[Description] Using token to decide execute Sx_Exit command of RR in S5 boot path
[Files] TbtPei.c TbtOemBoard.sdl

[TAG] EIP N/A
[Category] Improvement
[Description] Fix programming error
[Files] TbtSmm.c

[TAG] EIP N/A
[Category] Improvement
[Description] Clone APCI PCIE setup item
[Files] TbtSetup.sd TbtSetup.uni

Known issues and limitations in this label:
  • For Thunderbolt Logo test, please enable "TBT_PCIBUS_SKIP" token which is in TbtOemBoard.sdl.

  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • According Thunderbolt Spec, the pcie root port which is thunderbolt loacted should not enable advanced error reporting.

  • Thunderbolt doesn't support PCIE root port swap, please make sure "PCIE Root Port Swap" function is disable.

Remaining Issues:
None
Unit Testing:
None
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    Thunderbolt - Host Functional Validation Test Specification
    EIP#113859 is test result on Thunderbolt CRB
Release History:
  • 4.6.5.3_TBT_004

  • 4.6.5.3_TBT_003

  • 4.6.5.3_TBT_002

  • 4.6.5.3_TBT_001

  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2013/05/27
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 0.9
Source Control Label: 4.6.5.3_TBT_006
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_090_025 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TBWakeupSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo() - For both of Cactus Ridge and Redwood Ridge chips
    This function is used to get Thunderbolt host chip information :

    1. Report used Thunderbolt host chip series to BIOS
      For Oem, only return used thunderbolt chip series on OEM board

  • SynchSecurityLevel() - For Redwood Ridge chip
    This function is used to synchronize Thunderbolt host security level between Thunderbolt FW and BIOS before entering setup page:

    1. BIOS might need to assert GPIO_3(__FORCE_PWR) then do Redwood Ridge handshake to get/set thunderbolt security level
      In this function, BIOS should not set OS_UP command

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For both of Cactus Ridge and Redwood Ridge chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge chip
    No. | Security Level | Description
    0x0 | Legacy Mode | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Unique ID | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | One time saved Key | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | DP++ only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0xF:4 | Reserved
    For Redwood Ridge Host chip, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for Resource
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl
    "DEFAULT_TBT_CHIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.6
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
Support Falcon Ridge chip
General Bug Fixes:
System might auto-wake when using Thunderbolt Lan device waking up system.
EIP addressed in this label:
EIP124914 - Thunderbolt module update for Falcon ridge chip
EIP122882 - System might auto-wake when using Thunderbolt Lan device waking up system
Files changed for General Bug and EIP Fixe:
[TAG] EIP N/A
[Category] Improvement
[Description] add sychronized method to make sure executed sequence is one by one
[Files] TbtGpe.asl

[TAG] EIP124914
[Category] New Feature
[Description] Support Falcon Ridge chip
[Files] TbtPei.c TbtGpe.asl TbtSmm.c TbtOemLib.c TbtSetup.c

[TAG] EIP122882
[Category] Bug Fix
[Severity] Normal
[Symptom] Let system entering sleep status continually and waking up system via Thunderbolt Lan device, system will auto-wake
[Root Cause] PCIE PME status is not cleared by ASL in SB module
[Solution] Clear PCIE PME status again before system entering sleep status
[Files] TbtDxe.sdl TbtGpe.asl

[TAG] EIP N/A
[Category] Improvement
[Description] Fix clone ACPI setup item fail
[Files] TbtSetup.sdl

Known issues and limitations in this label:
  • For Thunderbolt Logo test, please enable "TBT_PCIBUS_SKIP" token which is in TbtOemBoard.sdl.

  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • According Thunderbolt Spec, the pcie root port which is thunderbolt loacted should not enable advanced error reporting.

  • Thunderbolt doesn't support PCIE root port swap, please make sure "PCIE Root Port Swap" function is disable.

Remaining Issues:
None
Unit Testing:
None
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    Thunderbolt - Host Functional Validation Test Specification
    EIP#113859 is test result on Thunderbolt CRB
Release History:
  • 4.6.5.3_TBT_005

  • 4.6.5.3_TBT_004

  • 4.6.5.3_TBT_003

  • 4.6.5.3_TBT_002

  • 4.6.5.3_TBT_001

  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2013/06/20
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 1.0
Falcon Ridge - 1.0
Source Control Label: 4.6.5.3_TBT_007
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_090_025 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TbtWakeupSupport;
      UINT8 TbtAICSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtAICSupport | Indicate to support Thunderbolt Add-in Card.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo() - For Cactus Ridge / Redwood Ridge / Falcon Ridge chips
    This function is used to get Thunderbolt host chip information :

    1. Report used Thunderbolt host chip series to BIOS
      For Oem, only return used thunderbolt chip series on OEM board

  • SynchSecurityLevel() - For Redwood Ridge / Falcon Ridge chips
    This function is used to synchronize Thunderbolt host security level between Thunderbolt FW and BIOS before entering setup page:

    1. BIOS might need to assert GPIO_3(__FORCE_PWR) then do Redwood Ridge handshake to get/set thunderbolt security level
      In this function, BIOS should not set OS_UP command

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For Cactus Ridge / Redwood Ridge / Falcon Ridge chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge/Falcon Ridge chips
    No. | Security Level | Description
    0x0 | Legacy Mode | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Unique ID | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | One time saved Key | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | DP++ only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0xF:4 | Reserved
    For Redwood Ridge/Falcon Ridge Host chips, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for Resource
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl
    "DEFAULT_TBT_CHIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge / Falcon Ridge chips
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.
        If Thunderbolt host is Add-in Card, BIOS need apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx" command.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.7
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
516968 Thunderbolt - RR BIOS Implementation guide - rev 1.0
526563 Thunderbolt - FR BIOS Implementation guide - rev 1.0
General Bug Fixes:
None
EIP addressed in this label:
EIP126581 - Implement Thunderbolt functions for RR/FR chips
Files changed for General Bug and EIP Fixe:
[TAG] EIP120580
[Category] Spec Update
[Severity] Minor
[Description] Update Intel Thunderbolt sample code to rev. 1.7
[Files] TbtSmm.c TbtGpe.asl

[TAG] EIP120580
[Category] Spec Update
[Severity] Minor
[Description] Update Intel Thunderbolt RR/FR BIOS Spec rev 1.0
[Files] Thunderbolt.sdl TbtPei.c TbtDxe.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.c TbtSetup.sd TbtSetup.uni

[TAG] EIP N/A
[Category] Improvement
[Description] Change TBWakeupSupport name
[Files] TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sd

[TAG] EIP N/A
[Category] Improvement
[Description] Change obj file name to avoid ambiguous
[Files] TbtSmm.mak

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • According Thunderbolt Spec, the pcie root port which is thunderbolt loacted should not enable advanced error reporting.

  • Thunderbolt doesn't support PCIE root port swap, please make sure "PCIE Root Port Swap" function is disable.

  • About Thunderbolt Add-in card, this module just follows Thunderbolt BIOS Spec to implement code to support this device without any validation.

Remaining Issues:
  • Build error with no Intel RC project - this issue will be fixed at next label.
Unit Testing:
None
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    Thunderbolt - Host Functional Validation Test Specification
    EIP#113859 is test result on Thunderbolt CRB
Release History:
  • 4.6.5.3_TBT_006

  • 4.6.5.3_TBT_005

  • 4.6.5.3_TBT_004

  • 4.6.5.3_TBT_003

  • 4.6.5.3_TBT_002

  • 4.6.5.3_TBT_001

  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2013/06/24
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 1.0
Falcon Ridge - 1.0
Source Control Label: 4.6.5.3_TBT_008
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_090_025 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TbtWakeupSupport;
      UINT8 TbtAICSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtAICSupport | Indicate to support Thunderbolt Add-in Card.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo() - For Cactus Ridge / Redwood Ridge / Falcon Ridge chips
    This function is used to get Thunderbolt host chip information :

    1. Report used Thunderbolt host chip series to BIOS
      For Oem, only return used thunderbolt chip series on OEM board

  • SynchSecurityLevel() - For Redwood Ridge / Falcon Ridge chips
    This function is used to synchronize Thunderbolt host security level between Thunderbolt FW and BIOS before entering setup page:

    1. BIOS might need to assert GPIO_3(__FORCE_PWR) then do Redwood Ridge handshake to get/set thunderbolt security level
      In this function, BIOS should not set OS_UP command

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For Cactus Ridge / Redwood Ridge / Falcon Ridge chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge/Falcon Ridge chips
    No. | Security Level | Description
    0x0 | Legacy Mode | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Unique ID | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | One time saved Key | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | DP++ only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0xF:4 | Reserved
    For Redwood Ridge/Falcon Ridge Host chips, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for Resource
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl
    "DEFAULT_TBT_CHIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge / Falcon Ridge chips
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.
        If Thunderbolt host is Add-in Card, BIOS need apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx" command.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.7
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
None
General Bug Fixes:
Falcon Ridge security level cannot be change
Build error with non Intel RC project
EIP addressed in this label:
None
Files changed for General Bug and EIP Fixe:
[TAG] EIP N/A
[Category] Bug Fix
[Severity] Minor
[Symptom] Can not change Falcon Ridge security level
[RootCause] Can not regconize Falcon Ridge chip
[Files] TbtSetupReset.c

[TAG] EIP N/A
[Category] Improvement
[Description] Fix build error with non Intel RC project
[Files] Thunderbolt.sdl TbtDxe.c TbtDxe.sdl TbtGpe.asl TbtDxe.h TbtSmm.mak TbtSmm.c TbtOemBoard.h TbtSetup.sd TbtSetupReset.c

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • According Thunderbolt Spec, the pcie root port which is thunderbolt loacted should not enable advanced error reporting.

  • Thunderbolt doesn't support PCIE root port swap, please make sure "PCIE Root Port Swap" function is disable.

  • About Thunderbolt Add-in card, this module just follows Thunderbolt BIOS Spec to implement code to support this device without any validation.

  • If your project code is non Intel RC project, please set "TBT_INTEL_RC_CONFIG" token to 0.

Remaining Issues:
None
Unit Testing:
None
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    Thunderbolt - Host Functional Validation Test Specification
    EIP#113859 is test result on Thunderbolt CRB
Release History:
  • 4.6.5.3_TBT_007

  • 4.6.5.3_TBT_006

  • 4.6.5.3_TBT_005

  • 4.6.5.3_TBT_004

  • 4.6.5.3_TBT_003

  • 4.6.5.3_TBT_002

  • 4.6.5.3_TBT_001

  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2013/07/26
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 1.0
Falcon Ridge - 1.0
Source Control Label: 4.6.5.3_TBT_009
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_090_025 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.
TbtGpeNonRC.asl | This file contains the Thunderbolt ASL related routines for Non Intel RC configuration.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TbtWakeupSupport;
      UINT8 TbtAICSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtAICSupport | Indicate to support Thunderbolt Add-in Card.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo() - For Cactus Ridge / Redwood Ridge / Falcon Ridge chips
    This function is used to get Thunderbolt host chip information :

    1. Report used Thunderbolt host chip series to BIOS
      For Oem, only return used thunderbolt chip series on OEM board

  • SynchSecurityLevel() - For Redwood Ridge / Falcon Ridge chips
    This function is used to synchronize Thunderbolt host security level between Thunderbolt FW and BIOS before entering setup page:

    1. BIOS might need to assert GPIO_3(__FORCE_PWR) then do Redwood Ridge handshake to get/set thunderbolt security level
      In this function, BIOS should not set OS_UP command

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For Cactus Ridge / Redwood Ridge / Falcon Ridge chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge/Falcon Ridge chips
    No. | Security Level | Description
    0x0 | Legacy Mode | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Unique ID | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | One time saved Key | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | DP++ only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0xF:4 | Reserved
    For Redwood Ridge/Falcon Ridge Host chips, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for Resource
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl
    "DEFAULT_TBT_CHIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge / Falcon Ridge chips
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.
        If Thunderbolt host is Add-in Card, BIOS need apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx" command.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt - BIOS additions - rev.1.7
Reference or 3rd Party code updated in this Release:
None
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
None
General Bug Fixes:
Build error at MahoBay/ChiefRiver platform
EIP addressed in this label:
None
Files changed for General Bug and EIP Fixe:
[TAG] EIP N/A
[Category] Improvement
[Description] Fix build error at MahoBay/ChiefRiver platform
[Files] TbtPei.c TbtOemBoard.h

[TAG] EIP N/A
[Category] Improvement
[Description] Initial release for non Intel RC config
[Files] TbtGpeNonRC.asl

[TAG] EIP N/A
[Category] Improvement
[Description] Separate ASL code for Intel RC and non Intel RC
[Files] TbtDxe.sdl TbtDxe.cif

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • According Thunderbolt Spec, the pcie root port which is thunderbolt loacted should not enable advanced error reporting.

  • Thunderbolt doesn't support PCIE root port swap, please make sure "PCIE Root Port Swap" function is disable.

  • About Thunderbolt Add-in card, this module just follows Thunderbolt BIOS Spec to implement code to support this device without any validation.

  • If your project code is non Intel RC project, please set "TBT_INTEL_RC_CONFIG" token to 0.

  • For Haswell platform, the "TBT_PCI0_INI_SUPPORT" token need enable for PCH module which labeled "4.6.5.3_Intel_LPT-RC_161_040".

Remaining Issues:
None
Unit Testing:
None
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    Thunderbolt - Host Functional Validation Test Specification
    EIP#113859 is test result on Thunderbolt CRB
Release History:
  • 4.6.5.3_TBT_008

  • 4.6.5.3_TBT_007

  • 4.6.5.3_TBT_006

  • 4.6.5.3_TBT_005

  • 4.6.5.3_TBT_004

  • 4.6.5.3_TBT_003

  • 4.6.5.3_TBT_002

  • 4.6.5.3_TBT_001

  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2014/01/06
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 1.0
Falcon Ridge - 1.1
Source Control Label: 4.6.5.3_TBT_010
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_170_045a or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.
TbtGpeNonRC.asl | This file contains the Thunderbolt ASL related routines for Non Intel RC configuration.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtEnable;
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TbtWakeupSupport;
      UINT8 TbtAICSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtSurpriseRemove;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtEnable | Indicate the Thunderbolt feature is enable/disable in run time
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtAICSupport | Indicate to support Thunderbolt Add-in Card.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo() - For Cactus Ridge / Redwood Ridge / Falcon Ridge chips
    This function is used to get Thunderbolt host chip information :

    1. Report used Thunderbolt host chip series to BIOS
      For Oem, only return used thunderbolt chip series on OEM board

  • SynchSecurityLevel() - For Redwood Ridge / Falcon Ridge chips
    This function is used to synchronize Thunderbolt host security level between Thunderbolt FW and BIOS before entering setup page:

    1. BIOS might need to assert GPIO_3(__FORCE_PWR) then do Redwood Ridge handshake to get/set thunderbolt security level
      In this function, BIOS should not set OS_UP command

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For Cactus Ridge / Redwood Ridge / Falcon Ridge chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge/Falcon Ridge chips
    No. | Security Level | Description
    0x0 | Legacy Mode | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Unique ID | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | One time saved Key | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | DP++ only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0xF:4 | Reserved
    For Redwood Ridge/Falcon Ridge Host chips, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for Resource
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl
    "DEFAULT_TBT_CHIP" token - TbtOemBoard.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge / Falcon Ridge chips
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.
        If Thunderbolt host is Add-in Card, BIOS need apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx" command.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt BIOS additions - rev.1.8
Reference or 3rd Party code updated in this Release:
  • Thunderbolt BIOS additions - rev.1.8
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Support Thunderbolt feature enable/disable in run time.
  • Support dynamic Thunderbolt AIC location in all SB PCIE root in run time
General Bug Fixes:
Fix thunderbolt device enumerating fail when TBT_PCIBUS_SKIP is disable
EIP addressed in this label:
EIP148198 - Update Intel Thunderbolt sample code to rev. 1.8 and Thunderbolt FR Spec to rev 1.1
Files changed for General Bug and EIP Fixe:
[TAG] EIP148198
[Category] Spec Update
[Severity] Minor
[Description] Update Intel Thunderbolt sample code to rev. 1.8 and Thunderbolt FR Spec to rev 1.1
[Files] TbtSmm.c TbtGpe.asl TbtSetup.sd

[TAG] EIP N/A
[Category] Improvement
[Description] Using token to enable/disable double check TBT host router state in SxSMI/PowerButtonSMI
[Files] TbtSmm.sdl TbtSmm.c

[TAG] EIP N/A
[Category] Improvement
[Description] Support Thunderbolt feature Enable/Disable in run time
[Files] TbtPei.c TbtDxe.c TbtDxeLib.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sd TbtSetup.uni TbtSetupReset.c

[TAG] EIP N/A
[Category] Improvement
[Description] Support dynamic Thunderbolt AIC location in all SB PCIE root ports in run time
[Files] TbtPei.c TbtDxe.c TbtDxeLib.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sd TbtSetup.uni TbtSetupReset.c

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • According Thunderbolt Spec, the pcie root port which is thunderbolt loacted should not enable advanced error reporting.

  • Thunderbolt doesn't support PCIE root port swap, please make sure "PCIE Root Port Swap" function is disable.

  • About Thunderbolt Add-in card, this module just follows Thunderbolt BIOS Spec to implement code to support this device without any validation.

  • If your project code is non Intel RC project, please set "TBT_INTEL_RC_CONFIG" token to 0.

  • For Haswell platform, the "TBT_PCI0_INI_SUPPORT" token need enable for PCH module which labeled "4.6.5.3_Intel_LPT-RC_161_040".

  • Dynamic Thunderbolt AIC location need PCH module co-work, if you want enable this feature, please double check with PCH owner on your platform first.

Remaining Issues:
None
Unit Testing:
None
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    Thunderbolt - Host Functional Validation Test Specification
    EIP#113859 is test result on Thunderbolt CRB
Release History:
  • 4.6.5.3_TBT_009

  • 4.6.5.3_TBT_008

  • 4.6.5.3_TBT_007

  • 4.6.5.3_TBT_006

  • 4.6.5.3_TBT_005

  • 4.6.5.3_TBT_004

  • 4.6.5.3_TBT_003

  • 4.6.5.3_TBT_002

  • 4.6.5.3_TBT_001

  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2014/02/19
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 1.0
Falcon Ridge - 1.1
BDW-TBT-LP - 1.0
Source Control Label: 4.6.5.3_TBT_011
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_170_045a or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.
TbtOemPorting.asl | This ASL file contains the Thunderbolt OEM related ASL routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtEnable;
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TbtWakeupSupport;
      UINT8 TbtAICSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtEnable | Indicate the Thunderbolt feature is enable/disable in run time
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtForcePWR | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtAICSupport | Indicate to support Thunderbolt Add-in Card.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo() - For Cactus Ridge / Redwood Ridge / Falcon Ridge / BDW-TBT-LP chips
    This function is used to get Thunderbolt host chip information :

    1. Report used Thunderbolt host chip series to BIOS
      For Oem, only return used thunderbolt chip series on OEM board

  • SynchSecurityLevel() - For Redwood Ridge / Falcon Ridge / BDW-TBT-LP chips
    This function is used to synchronize Thunderbolt host security level between Thunderbolt FW and BIOS before entering setup page:

    1. BIOS might need to assert GPIO_3(__FORCE_PWR) then do Redwood Ridge handshake to get/set thunderbolt security level
      In this function, BIOS should not set OS_UP command

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For Cactus Ridge / Redwood Ridge / Falcon Ridge / BDW-TBT-LP chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge/Falcon Ridge/BDW-TBT-LP chips
    No. | Security Level | Description
    0x0 | Legacy Mode | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Unique ID | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | One time saved Key | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | DP++ only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0xF:4 | Reserved
    For Redwood Ridge/Falcon Ridge/BDW-TBT-LP Host chips, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • TBFP ASL function in TbtOemPorting.asl
    In Intel Thunderbolt Sample code rev 1.9, BIOS should report TBFP ASL function to control Thunderbolt host GPIO_3__FORCE_PWR pin. In TBFP function, BIOS only need assert/de-assert GPIO_3__FORCE_PWR pin via ASL code.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for Resource
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl
    "DEFAULT_TBT_CHIP" token - TbtOemBoard.sdl
    "TBT_PCI0_INI_SUPPORT" token - TbtDxe.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge / Falcon Ridge / BDW-TBT-LP Host chips (this flow has done in Thunderbolt module, OEM don't need porting)
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.
        If Thunderbolt host is Add-in Card, BIOS need apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx" command.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt BIOS additions - rev.1.9
Reference or 3rd Party code updated in this Release:
  • Thunderbolt BIOS additions - rev.1.9
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Support new Thunderbolt host chip series.
General Bug Fixes:
Fix build error when using PI 1.0
EIP addressed in this label:
EIP152401 - Update Intel Thunderbolt sample code to rev. 1.9 and Thunderbolt WR Spec to rev 1.0
Files changed for General Bug and EIP Fixe:
[TAG] EIP 152401
[Category] Spec Update
[Severity] Minor
[Description] Update Intel Thunderbolt sample code to rev. 1.9 and Thunderbolt WR Spec to rev 1.0
[Files] Thunderbolt.sdl TbtSmm.c TbtGpe.asl TbtOemPorting.asl TbtOemBoard.h TbtOemBoard.sdl TbtOemLib.c TbtSetup.c

[TAG] EIP151867
[Category] Bug Fix
[Severity] Normal
[Symptom] Build error when using PI 1.0
[RootCause] GUID and Protocal do not be defined
[Solution] Using generic GUID and defining correct protocal when using PI 1.0
[Files] TbtSmm.c

[TAG] EIP N/A
[Category] Improvement
[Description] remove useless policy item and setup item
[Files] TbtSmm.c TbtOemBoard.c TbtSetup.sdl TbtSetup.sd TbtSetup.uni

[TAG] EIP N/A
[Category] Improvement
[Description] Release PCIE root port control when Thunderbolt
[Files] TbtOemBoard.c

[TAG] EIP N/A
[Category] Improvement
[Description] Remove TbtGpeNonRC.asl
[Files] TbtDxe.cif

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • According Thunderbolt Spec, the pcie root port which is thunderbolt loacted should not enable advanced error reporting.

  • Thunderbolt doesn't support PCIE root port swap, please make sure "PCIE Root Port Swap" function is disable.

  • About Thunderbolt Add-in card, this module just follows Thunderbolt BIOS Spec to implement code to support this device with basic validation.

  • Now Thunderbolt module doesn't support non Intel RC project, if your Intel platform is without Intel RC and you want support Thunderbolt feature, please double check with module owner first for supporting.

  • For Haswell/Haswell-Refresh platform, the "TBT_PCI0_INI_SUPPORT" token need enable for New Intel PCH RC.

  • Dynamic Thunderbolt AIC location need PCH module co-work, if you want enable this feature, please double check with PCH owner on your platform first.

  • Dynamic Thunderbolt AIC location conflict with fix bus feature.

  • For new Thunderbolt host chip BDW-TBT-LP(WR), this module just follows Thunderbolt BIOS Spec to implement code to support this device without any validation.

Remaining Issues:
None
Unit Testing:
Please refer EIP152401 attachment
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    Thunderbolt - Host Functional Validation Test Specification
    EIP#113859 is test result on Thunderbolt CRB
Release History:
  • 4.6.5.3_TBT_010

  • 4.6.5.3_TBT_009

  • 4.6.5.3_TBT_008

  • 4.6.5.3_TBT_007

  • 4.6.5.3_TBT_006

  • 4.6.5.3_TBT_005

  • 4.6.5.3_TBT_004

  • 4.6.5.3_TBT_003

  • 4.6.5.3_TBT_002

  • 4.6.5.3_TBT_001

  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Release Notes - NDA Required

Component Information:
Component Title: Thunderbolt
Component Reference Name: Thunderbolt
Component Type: eModule
Release Date: 2014/02/20
Thunderbolt BIOS Spec. version: Cactus Ridge - 1.6
Redwood Ridge - 1.0
Falcon Ridge - 1.1
BDW-TBT-LP - 1.0
Source Control Label: 4.6.5.3_TBT_012
Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/Thunderbolt/;
Dependencies
Component Dependencies
    Intel Ivy Bridge Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.4.1_Intel_PPT-RC160_021b or above
    Dependent Source Control Location: SS: Database;$/Path;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.4.1_PF-ACPI_RC_1.60_019a or above
    Dependent Source Control Location: SS: Alaska;$/Alaska/SOURCE/Modules/IVBRefCodes/Platform;

    Intel Haswell Platform:
    ONE
    Dependent Component Title: Intel PCH
    Dependent Component Reference Name: Intel Pch
    Dependent Source Control Label: 4.6.5.3_Intel_LPT-RC_170_045a or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint;
    TWO
    Dependent Component Title: Platform
    Dependent Component Reference Name: AcpiPlatform
    Dependent Source Control Label: 4.6.5.3_PF-ACPI_RC_071_014 or above
    Dependent Source Control Location: SS: ALASKA;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Platform;

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Thunderbolt initialization.
Filename | Description
Thunderbolt.SDL | This is the AMI SDL File for the Thunderbolt module.
ReleaseNotes.chm | This is the AMI CHM file for the Thunderbolt module

Thunderbolt Pei Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtPei.sdl | This is the AMI SDL File for the Thunderbolt Pei module part.
TbtPei.mak | This file contains the NMAKE scripts to build the Thunderbolt Pei module part.
TbtPei.c | This source file contains the Thunderbolt Pei related routines.
TbtPei.dxs | This dependency file describes the dependency expression for the TbtPei.ffs file.

Thunderbolt Dxe Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtDxe.sdl | This is the AMI SDL File for the Thunderbolt DXE module part.
TbtDxe.mak | This file contains the NMAKE scripts to build the Thunderbolt DXE module part.
TbtDxe.c | This source file contains the Thunderbolt DXE related routines.
TbtDxe.dxs | This dependency file describes the dependency expression for the TbtDxe.ffs file.
TbtDxeLib.c | This source file contains the Thunderbolt DXE Lib related routines.
TbtDxeLib.h | This header file contains the Thunderbolt DXE Lib related routines.
TbtGpe.asl | This file contains the Thunderbolt ASL related routines.

Thunderbolt Smm Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSmm.sdl | This is the AMI SDL File for the Thunderbolt SMM module part.
TbtSmm.mak | This file contains the NMAKE scripts to build the Thunderbolt SMM module part.
TbtSmm.c | This source file contains the Thunderbolt SMM related routines.
TbtSmm.dxs | This dependency file describes the dependency expression for the TbtSmm.ffs file.

Thunderbolt OEM Board Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtOemBoard.sdl | This is the AMI SDL File for the Thunderbolt OEM Board module part.
TbtOemBoard.mak | This file contains the NMAKE scripts to build the Thunderbolt OEM Board module part.
TbtOemBoard.c | This source file contains the Thunderbolt OEM Board related routine.
TbtOemBoard.dxs | This dependency file describes the dependency expression for the TbtOemBoard.ffs file.
TbtOemBoard.h | This header file contains the Thunderbolt OEM Board related constants and type definitions.
TbtOemLib.c | This source file contains the Thunderbolt OEM Lib related routines.
TbtOemLib.h | This header file contains the Thunderbolt OEM Lib related routines.
TbtOemPorting.asl | This ASL file contains the Thunderbolt OEM related ASL routines.

Thunderbolt Setup Module Part
This is the top level of the component. This contains NMAKE File Script and AMI SDL file. This also contains global files regarding the component. The following are the global files present in this module at this level:
Filename | Description
TbtSetup.sdl | This is the AMI SDL File for the Thunderbolt Setup module part.
TbtSetup.mak | This file contains the NMAKE scripts to build the Thunderbolt Setup module part.
TbtSetup.c | This file contains the Thunderbolt Setup related routines.
TbtSetupReset.c | This file contains the Thunderbolt Setup related routines.
TbtSetup.h | This header file contains the Thunderbolt Setup related constants and type definitions.
TbtSetup.sd | This file contains the setup options and information displayed in bios setup.
TbtSetup.uni | This file contains strings that are displayed in Setup.

Non-Compiled BIN and LIB File(s) in Flavor:
N0NE
AMI Build Tools:
Tools Label: 4.5.5_Tools_40 , Dated: 2012-07-03
Visual eBios: RSS 5.73.0239, Dated: 2012-06-21
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
Porting Notes:
  • TbtOemBoard_Init()
    User should Install the protocol for provide the necessary information for thunderbolt initialize.
    • GUID
      #define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID \
      { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }

    • Prototype
      typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
      UINT8 TbtEnable;
      UINT8 TbtGO2SX;
      UINT8 TbtForcePWR;
      UINT8 TbtHotPlugEvt;
      UINT8 TbtOK2GO2SX_N;
      UINT8 CacheLineSize;
      UINT8 TbtWakeupSupport;
      UINT8 TbtAICSupport;
      UINT8 TbtHandlePOC;
      UINT8 TbtSecurityLevel;
      UINT8 Bus;
      UINT8 Dev;
      UINT8 Fun;
      UINT16 ReserveMemoryPerSlot;
      UINT16 ReservePMemoryPerSlot;
      UINT8 ReserveIOPerSlot;
      UINT8 SmiNotifyEnabled;
      UINT8 SwSmiEnabled;
      UINT8 NotifyEnabled;
      UINT8 TbtOptionROM;
      } AMI_TBT_PLATFORM_POLICY_PROTOCOL;

    • Parameters
      Parameter | Description
      TbtEnable | Indicate the Thunderbolt feature is enable/disable in run time
      TbtGO2SX | Indicate the GPIO pin number connected to GPIO_2__GO2SX
      TbtForcePWR | Indicate the GPIO pin number connected to GPIO_3__FORCE_PWR
      TbtHotPlugEvt | Indicate the GPIO pin number connected to GPIO_5__CIO_PLUG_EVENT
      TbtOK2GO2SX_N | Indicate the GPIO pin number connected to GPIO_9__OK2GO2SX_N_OD
      CacheLineSize | Indicate PCIe cache line size.
      TBWakeupSupport | Indicate the wake from TBT is enabled/disabled.
      TbtAICSupport | Indicate to support Thunderbolt Add-in Card.
      TbtHandlePOC | Indicate to handle thunderbolt host POC is enabled/disabled.
      TbtSecurityLevel | Indicate the desired TBT security level.
      Bus | Indicate the TBT connected Root Port Bus#
      Dev | Indicate the TBT connected Root Port Device#
      Fun | Indicate the TBT connected Root Port Function#
      ReserveMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReservePMemoryPerSlot | Resource for per physical slot under Thunderbolt
      ReserveIOPerSlot | Resource for per physical slot under Thunderbolt
      SmiNotifyEnabled | Enable or disable SMI/Notify support.
      SwSmiEnabled | Enable or disable SwSMI support in ASL code.
      NotifyEnabled | Enable or disable Notify support in ASL code.
      TbtOptionRom | Enable or disable Ignore Thunderbolt Device Option Rom

  • GetHRInfo() - For Cactus Ridge / Redwood Ridge / Falcon Ridge / BDW-TBT-LP chips
    This function is used to get Thunderbolt host chip information :

    1. Report used Thunderbolt host chip series to BIOS
      For Oem, only return used thunderbolt chip series on OEM board

  • SynchSecurityLevel() - For Redwood Ridge / Falcon Ridge / BDW-TBT-LP chips
    This function is used to synchronize Thunderbolt host security level between Thunderbolt FW and BIOS before entering setup page:

    1. BIOS might need to assert GPIO_3(__FORCE_PWR) then do Redwood Ridge handshake to get/set thunderbolt security level
      In this function, BIOS should not set OS_UP command

  • ActiveTbtGpio2() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should assert GO2Sx pin
      That will trigger Host Router to prepare underlying devices

  • InactiveTbtGpio2() - For Cactus Ridge chip
    Wake flow is reversal of sleep flow:

    1. BIOS should deassert GO2Sx pin to wake HR.
      When BIOS decides to wake system the first step that should be performed is deasserting of GO2Sx pin to wake HR.

  • PollTbtGpio9() - For Cactus Ridge chip
    The following flow should be performed as a last step before instructing the platform to enter Sx state:

    1. BIOS should poll OK2GO2SX_N_OD pin
      Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry.

  • PullDownTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should pull down OK2GO2SX_N_OD pin
      BIOS should pull down OK2GO2SX_N_OD pin first before stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • ReleaseTbtGpio9() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function
    The step of Wake flow that need to be completed if remembered Host Router state was active:

    1. BIOS should release OK2GO2SX_N_OD pin which is pulled down before
      BIOS should release OK2GO2SX_N_OD pin which is pulled down previous after stall 2.5 seconds to ensure completeness of Thunderbolt link to all endpoint devices.

  • PowerOnPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function(Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power on POC when system exiting sleep status.
      If BIOS need handle the POC, BIOS should power on POC when system exiting sleep status.

  • PowerOffPOC() - For Cactus Ridge chip and not support "Wake up from Thunderbolt Device" function (Optional)
    If system does not support "Wake from thunderbolt device" and POC is stand alone:

    1. BIOS might need power off POC before system entering Sleep status.
      If BIOS need handle the POC, BIOS should power off POC before system entering sleep status.

  • ProgramTbtSecurityLevel() - For Cactus Ridge / Redwood Ridge / Falcon Ridge / BDW-TBT-LP chips &
    FinialProgramTbtSecurityLevel() / PeiFinialProgramTbtSecurityLevel() - Only for Cactus Ridge chip

    Security level definition for Cactus Ridge chip
    By default Thunderbolt Cactus Ridge host router operates in a mode that enables all its features, including PCIe tunneling and Native Host Interface (NHI) device.
    To reduce the risk of unexpected intrusion into the system, BIOS should provide security modes selection (user choice) and communicate to the Host Router thru dedicated GPIO's.
    For Cactus Ridge (CR) Host Router component, those GPIO's should be connected to the following pins:
    • GPIO_3(__FORCE_PWR) - active high
    • GPIO_6_OD__CIO_SDA_OD - active high
    • GPIO_7_OD__CIO_SCL_OD - active high
    BIOS should supply security level menu with the following options
    No. | Security Level | Description | Gpio3 | Gpio6 | Gpio7
    1 | Normal mode with NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is available | Assert for 400ms | 1 | 1
    2 | Normal mode without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled | Assert for 400ms | 0 | 0
    3 | Directly connected devices without NHI(HIA) | When Thunderbolt domain is on, NHI(HIA) is disabled and CM will configure only Thunderbolt devices that are directly connected to Host system (single depth) | Assert for 400ms | 0 | 1
    4 | Redriver only | No PCIe/NHI(HIA) support by Thunderbolt, only DP++ redriver | Assert for 400ms | 1 | 0
    5 | Off | System will not provide power to Thunderbolt subsystem
    6 | Thunderbolt debug | Same as #1, not dependant on Thunderbolt cable presence | Assert and keep asserted | 1 | 1
    Security level should be communicated to Thunderbolt Host Router controller at every initial power-up (Cactus Ridge POC power cycle) and/or any level setting change.
    Set GPIO6 and GPIO7 to the desired levels and assert GPIO3 for at least 400ms period.

    In order to saving Boot time, so we separate steps of programming security level into PEI and DXE phases.
    In PEI phase, after BIOS wakeup thunderbolt host chip, BIOS bases on setup item value of the security level to initial and program related thunderbolt GPIO pin.
    In DXE phase, BIOS will finish final step of programming security level to deassert GPIO_3(__FORCE_PWR) pin according the HOB information which is created in PEI phase

    If your system does not support "wake up from thunderbolt device" function, it needs programming security level every time when system exit from sleep status, so you might need porting PeiFinialProgramTbtSecurityLevel() for system at S3 resume path

    Security level definition for Redwood Ridge/Falcon Ridge/BDW-TBT-LP chips
    No. | Security Level | Description
    0x0 | Legacy Mode | Allow legacy Thunderbolt devices auto connect - at this mode the connection manager auto connects to a new device plugged in.
    0x1 | Unique ID | Allow Unique ID devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval may be given based on the Unique ID of the connecting device.
    0x2 | One time saved Key | Allow One time saved key devices at minimum - at this mode the connection manager requests connection approval from the host SW, auto approval is only given if the host challenge to the device is acceptable.
    0x3 | DP++ only | Allow only DP sinks to be connected(re-driver or DP tunnel, no PCIe tunneling) - at this mode no tunneling is done for PCIe devices.
    0xF:4 | Reserved
    For Redwood Ridge/Falcon Ridge/BDW-TBT-LP Host chips, Thunderbolt default setting is no security.
    Upon security change request, BIOS needs drive GPIO_3_FORCE_PWR, if no device is attached this will also power up the Thunderbolt HR, if a device was connected Thunderbolt HR is already up.
    Security configuration setting from BIOS:
    • BIOS enumerate the HR
    • BIOS apple Redwood Ridge "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Set_Security_Level" command and corresponding security level in "data" parameter.
    • CM gets the new security setting, checks if GPIO_3_FORCE_PWR is set, if so CM updates the security level in the NVM.

  • \GPE._L01 method changes
    Remove call to Notify([TBT Slot], 0) ACPI method. No need in this Notify call because of HR notifies about link establishment by asserting GPIO X, and accordingly only _E1X method should notify to Windows.

  • TBFP ASL function in TbtOemPorting.asl
    In Intel Thunderbolt Sample code rev 1.9, BIOS should report TBFP ASL function to control Thunderbolt host GPIO_3__FORCE_PWR pin. In TBFP function, BIOS only need assert/de-assert GPIO_3__FORCE_PWR pin via ASL code.

  • Adjust Reserved Resource
    No. | File | Token Name | Original Value | Suggested Value for 2C1P | minimum default Value in setup menu for 2C1P | minimum default Value in setup menu for 4C2P
    1 | SB.sdl | PCH_PCIE_TEMP_RP_BUS_NUM_MAX | 4 | 200
    2 | SB.sdl | MAX_EXTRA_BUS_RESERVED | 7 | 56 ＊ | 56 | 106
    3 | SB.sdl | MAX_PCIE_MEM_RESERVED | 20 | 353 | 353 | 737
    4 | SB.sdl | MAX_PCIE_PF_MEM_RESERVED | 20 | 544 | 544 | 1184
    5 | NB.sdl | PCIEX_BASE_ADDRESS | 0xF8000000 | 0xF0000000 ＊
    6 | sb.sd | SETUP_DATA.PcieIoRsvd[OFFSET_x] | 20 | 0 ✔ | 0 ✔ | 0 ✔
    ＊: If reserved bus number is larger than 63, then PCIE Base Address should be adjusted together
    ✔: If IO resource workaround is enabling, one EP needs 4K IO resource basiclly. If you connect six devices in daisy-chained way, the minimum of reserved IO resource is 24K. In 4C 2port case, IO resource workaround does not support thunderbolt docking device, and it will assign first 24K resvered IO resource to thunderbolt port1, then assign remnan resvered IO resource to thunderbolt port2 if reserved IO resource lager than 24K.

  • Adjust for Resource
    TBT_FCTP token(in TbtOemBoard.sdl): If your Board is 4C 2 port thunderbolt case, please enable it. it will adjust max of resources which are defined in TbtOemBoard.sdl
    TBT Host chip's NVM version setup item: Because of thunderbolt host chip behavior is different between the Rev.17 and previous version at 4C 2 port case, so this is using for different resource assigned algorithm in workaround at 4C 2 port case.

  • Token overwirte
    PCIEX_BASE_ADDRESS token and MAX_ADDITIONAL_P2P_BRIDGES token which are new tokens in TbtOemBoard.sdl will overwrite the original token defined in NB.sdl and CSM.sdl

    At PCH labeled "4.6.4.1_Intel_PPT-RC_160_021b" or latter version on MahoBay/ChiefRiver platform, the max resource of thunderbolt port will be controled by TBT_MAX_EXTRA_BUS_RESERVED token, TBT_MAX_PCIE_MEM_RESERVED token, TBT_MAX_PCIE_PF_MEM_RESERVED token and TBT_MAX_PCIE_IO_RESERVED token that are defined in TbtOemBoard.sdl

    Token need change for Oem: "TBT_UP_PORT_FUNC" token - TbtOemBoard.sdl
    "TBT_GO2SX" token - TbtOemBoard.sdl
    "TBT_ForcePWR" token - TbtOemBoard.sdl
    "TBT_OK2GO2SX_N" token - TbtOemBoard.sdl
    "TBT_HotPlugEvt" token - TbtOemBoard.sdl
    "TBT_FCTP" token - TbtOemBoard.sdl → for 4C 2 ports case
    "TBT_HR_PWR" token - TbtOemBoard.sdl → for thunderbolt HW has this pin
    "TBT_PCIBUS_SKIP" token - TbtOemBoard.sdl
    "DEFAULT_TBT_CHIP" token - TbtOemBoard.sdl
    "TBT_PCI0_INI_SUPPORT" token - TbtDxe.sdl

  • Cloned Setup item definition
    In this thunderbolt label has clone the setup item definitions of PCIE root port resource which are related thunderbolt, like the numbers of reserved bus, the size of reserved memory... etc. So if thunderbolt enabling, all configurations sholud control by Thunderbolt module

  • Sleep flow & Wake up flow for Cactus Ridge chip
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Assert GO2Sx pin.
          Oem sholud finish porting "ActiveTbtGpio2" function which is in OemBoardLib.c
        2. Poll OK2GO2SX_N_OD pin.
          Oem sholud finish porting "PollTbtGpio9" function which is in OemBoardLib.c

      Wake flow:
        1. Deassert GO2Sx pin.
          Oem sholud finish porting "InactiveTbtGpio2" function which is in OemBoardLib.c
        2. According HR status to delay 2.5 seconds or not

    If system does not support "Wake up from Thunderbolt Device" function:
    Please double confirm the POC of Thunderbolt host chip is following the system power or stand alone and controlled by GPIO pin first.
      sleep flow:
        1. Power off POC.
          If POC is stand alone, Oem should finish porting "PowerOffPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

      Wake flow:
        1. Power on POC.
          If POC is stand alone, Oem should finish porting "PowerOnPOC" function which is in OemBoardLib.c
          If POC is following system power, Oem does not need porting PowerOffPOC function.

        2. If HR status is active, Pull down GPIO_9__OK2GO2SX_N_OD.
          Oem sholud finish porting "PullDownTbtGpio9" function which is in OemBoardLib.c

        3. If HR status is active, Delay 2.5 seconds.

        4. If HR status is active, pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
          Oem sholud finish porting "ReleaseTbtGpio9" function which is in OemBoardLib.c

      PS. The wake flow should be excuted in 100ms after powering on POC, so if POC is following system power, it need double comfirm the time from power on system to can controll thunderbolt's GPIO. For the CRB code base, it can meet this requirement.

  • Sleep flow & Wake up flow for Redwood Ridge / Falcon Ridge / BDW-TBT-LP Host chips (this flow has done in Thunderbolt module, OEM don't need porting)
    If system support "Wake up from Thunderbolt Device" function:
      sleep flow:
        It does not require any custom GPIO manipulation by BIOS.
        If Thunderbolt host is Add-in Card, BIOS need apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx" command.

      Wake flow:
        1. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

    If system does not support "Wake up from Thunderbolt Device" function:
      sleep flow:
        1. Apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Go2Sx_No_Wake" command.

      Wake flow:
        1. If HR status is active, BIOS should add 500 ms delay.
        2. If HR status is active, apply "PCIE2TBT <-> TBT2PCIE handshake" procedure with "Sx_Exit_TBT_Connected" command.
        3. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
        If Thunderbolt host is Add-in Card, BIOS need set T218 field (bits [1:0]) of PCH PM_CFG register to 11b – 10 ms (default value is 0b – 10 us)

Reference or 3rd Party code in this Release:
  • 489039 Thunderbolt BIOS additions - rev.1.9
Reference or 3rd Party code updated in this Release:
  • Thunderbolt BIOS additions - rev.1.9
Files changed in the Reference or 3rd Party Code:
None
New features added in this label:
  • Support new Thunderbolt host chip series.
General Bug Fixes:
Fix build error when using PI 1.0
EIP addressed in this label:
EIP152401 - Update Intel Thunderbolt sample code to rev. 1.9 and Thunderbolt WR Spec to rev 1.0
Files changed for General Bug and EIP Fixe:
[TAG] EIP 152401
[Category] Spec Update
[Severity] Minor
[Description] Update Intel Thunderbolt sample code to rev. 1.9 and Thunderbolt WR Spec to rev 1.0
[Files] Thunderbolt.sdl TbtSmm.c TbtGpe.asl TbtOemPorting.asl TbtOemBoard.h TbtOemBoard.sdl TbtOemLib.c TbtSetup.c

[TAG] EIP151867
[Category] Bug Fix
[Severity] Normal
[Symptom] Build error when using PI 1.0
[RootCause] GUID and Protocal do not be defined
[Solution] Using generic GUID and defining correct protocal when using PI 1.0
[Files] TbtSmm.c

[TAG] EIP N/A
[Category] Improvement
[Description] remove useless policy item and setup item
[Files] TbtSmm.c TbtOemBoard.c TbtSetup.sdl TbtSetup.sd TbtSetup.uni

[TAG] EIP N/A
[Category] Improvement
[Description] Release PCIE root port control when Thunderbolt feature disable in run time
[Files] TbtOemBoard.c

[TAG] EIP N/A
[Category] Improvement
[Description] fix TBT host chip information record incorrect in SMM
[Files] TbtSmm.c

[TAG] EIP N/A
[Category] Improvement
[Description] Remove TbtGpeNonRC.asl
[Files] TbtDxe.cif

Known issues and limitations in this label:
  • If your code project has CsmOptOut module and it is labeled 4.6.5.4_Csm_OptOut_03, it made Thunerbolt setup item "Ignore Thunderbolt Option Rom" fail. Please update CsmOptOut.c to revision 14.

  • Because Thunderbolt - BIOS additions - rev.1.3 need check resources alignment of PCIE root port(The alignment of Reserved memroy is 64MB, the alignment of Prefeteched memory is 256MB), but 4.6.4.1_Intel_PPT-RC_160_021a SB chipset eModule not has these items in setup menu, please update SB module to label "4.6.4.1_Intel_PPT-RC_160_021b" or later, or update sb.sd, sb.uni, PciHotplug.c which are attached in EIP96350.

  • Because Thunderbolt - BIOS additions - rev.1.4 has remove the IO resource, if the thunderbolt devices use the IO resource, it will not work under windows and show yellow mark(error code:12).

  • If your Board is 4C 2port case, please enble "TBT_FCTP" token which is in TbtOemBoard.sdl to adjust max resource value.

  • IO resource workaround is not a standard for Thunderbolt BIOS suppot Spec, so it should be disable by default, and its limiation are not support dokcing device in 4C 2 ports case, and if reserved IO resource is not enough, it will show yellow mark in windows device manager.

  • Intel GOP driver can not light up Apple Thunderbolt monitor, this is GOP driver issue. But according Intel feedback, Apple Thunderbolt monitor is not a standard test device for Thunderbolt Logo test.

  • According Thunderbolt Spec, the pcie root port which is thunderbolt loacted should not enable advanced error reporting.

  • Thunderbolt doesn't support PCIE root port swap, please make sure "PCIE Root Port Swap" function is disable.

  • About Thunderbolt Add-in card, this module just follows Thunderbolt BIOS Spec to implement code to support this device with basic validation.

  • Now Thunderbolt module doesn't support non Intel RC project, if your Intel platform is without Intel RC and you want support Thunderbolt feature, please double check with module owner first for supporting.

  • For Haswell/Haswell-Refresh platform, the "TBT_PCI0_INI_SUPPORT" token need enable for New Intel PCH RC.

  • Dynamic Thunderbolt AIC location need PCH module co-work, if you want enable this feature, please double check with PCH owner on your platform first.

  • Dynamic Thunderbolt AIC location conflict with fix bus feature.

  • For new Thunderbolt host chip BDW-TBT-LP(WR), this module just follows Thunderbolt BIOS Spec to implement code to support this device without any validation.

Remaining Issues:
None
Unit Testing:
Please refer EIP152401 attachment
Validation Testing:
For Cactus Ridge chip:
    507659 Thunderbolt (Host) Pre-Certification Checklist
    EIP#97638 is test result on Thunderbolt CRB
For Redwood Ridge chip:
    Thunderbolt - Host Functional Validation Test Specification
    EIP#113859 is test result on Thunderbolt CRB
Release History:
  • 4.6.5.3_TBT_011

  • 4.6.5.3_TBT_010

  • 4.6.5.3_TBT_009

  • 4.6.5.3_TBT_008

  • 4.6.5.3_TBT_007

  • 4.6.5.3_TBT_006

  • 4.6.5.3_TBT_005

  • 4.6.5.3_TBT_004

  • 4.6.5.3_TBT_003

  • 4.6.5.3_TBT_002

  • 4.6.5.3_TBT_001

  • 4.6.5.3_TBT_000

Labeled Module Before Source Safe Path Changed

  • 4.6.5.3_TBT_104_BETA

  • 4.6.5.3_TBT_103_000

  • 4.6.5.3_TBT_102_000

  • 4.6.5.3_TBT_101_002

  • 4.6.5.3_TBT_101_001

  • 4.6.5.3_TBT_101_000

  • 4.6.5.3_TBT_100_000

  • 4.6.4.1_TBT_094_001

  • 4.6.4.1_TBT_094_000

  • 4.6.4.1_TBT_093_000

  • 4.6.4.1_TBT_092_000

  • 4.6.4.1_TBT_091_001

  • 4.6.4.1_TBT_091_000

  • 4.6.4.1_TBT_085_000

© American Megatrends Inc.


Function by File Name

AMIBIOS Function Reference

By File Name

The following is a list of the source files.
For a list in alphabetical order, see In Alphabetical Order.

  • TbtDxe.c
  • TbtDxe.mak
  • TbtDxeLib.c
  • TbtOemBoard.c
  • TbtOemBoard.mak
  • TbtOemLib.c
  • TbtPei.c
  • TbtPei.mak
  • TbtSetup.c
  • TbtSetup.h
  • TbtSetup.mak
  • TbtSetup.sd
  • TbtSetupReset.c
  • TbtSmm.c
  • TbtSmm.mak
Built on 21:27:40 05/19/14


TbtDxe.c

The following functions are used in the file: TbtDxe.c.

Function | Description
CreateTbtAcpiCallback | This function will create all ACPI components for SB when ACPI support protocol is available.
DisableTbtDeviceRomCallback | Disable all Tbt devices option ROM to aviod S4 resume problem.
DsdtTableUpdate | Update the DSDT table
InvokeSmiHandlerBeforeBoot | To invoke SW SMI befor boot for reaource adjust.
TbtDxe_Init | This function is the entry point for this DXE.


CreateTbtAcpiCallback in the TbtDxe.c

Function : CreateTbtAcpiCallback

File: TbtDxe.c
Description:
This function will create all ACPI components for SB when
ACPI support protocol is available.
Input:
Event   - Event of callback
Context - Context of callback.
Output:
None


DisableTbtDeviceRomCallback in the TbtDxe.c

Function : DisableTbtDeviceRomCallback

File: TbtDxe.c
Description:
Disable all Tbt devices option ROM to aviod S4 resume problem.
Input:
Event   - Event of callback
Context - Context of callback.
Output:
None


DsdtTableUpdate in the TbtDxe.c

Function : DsdtTableUpdate

File: TbtDxe.c
Description:
Update the DSDT table
Input:
DsdtTable   - The table points to DSDT table.
Output:
None


InvokeSmiHandlerBeforeBoot in the TbtDxe.c

Function : InvokeSmiHandlerBeforeBoot

File: TbtDxe.c
Description:
To invoke SW SMI befor boot for reaource adjust.
Input:
Event   - Event of callback
Context - Context of callback.
Output:
None


TbtDxe_Init in the TbtDxe.c

Function : TbtDxe_Init

File: TbtDxe.c
Description:
This function is the entry point for this DXE.
Input:
ImageHandle - Image handle
SystemTable - Pointer to the system table
Output:
Return Status based on errors that occurred while waiting for
time to expire.


TbtDxe.mak

Description:


TbtDxeLib.c

The following functions are used in the file: TbtDxeLib.c.

Function | Description
IsULTPchSeries | This function is to get PCH series is ULT series or not
TbtDxeInvokeSmiHandler | Invoke SW SMI befor boot for reaource adjust.
TbtProtectedPciDevice | This function is called by PCI Bus Driver before configuring or disabling any PCI device. This function should examine the Vendor/Device ID or PCI Bus, Device and Function numbers to make sure it is not a south bridge device or any other device which should no be configured by PCI Bus Driver.


IsULTPchSeries in the TbtDxeLib.c

Function : IsULTPchSeries

File: TbtDxeLib.c
Description:
This function is to get PCH series is ULT series or not
Input:
None
Output:
None


TbtDxeInvokeSmiHandler in the TbtDxeLib.c

Function : TbtDxeInvokeSmiHandler

File: TbtDxeLib.c
Description:
Invoke SW SMI befor boot for reaource adjust.
Input:
None
Output:
None


TbtProtectedPciDevice in the TbtDxeLib.c

Function : TbtProtectedPciDevice

File: TbtDxeLib.c
Description:
This function is called by PCI Bus Driver before configuring
or disabling any PCI device. This function should examine the
Vendor/Device ID or PCI Bus, Device and Function numbers to
make sure it is not a south bridge device or any other device
which should no be configured by PCI Bus Driver.
Input:
*PciDevice - Pointer to PCI Device Info structure.
Output:
EFI_STATUS
   EFI_SUCCESS     - SKIP this device, do not touch
                     PCI Command register.
   EFI_UNSUPPORTED - DON'T SKIP this device do complete
                     enumeration as usual.


TbtOemBoard.c

The following functions are used in the file: TbtOemBoard.c.

Function | Description
TbtOemBoard_Init | This function is the entry point for TbtOemBoard.


TbtOemBoard_Init in the TbtOemBoard.c

Function : TbtOemBoard_Init

File: TbtOemBoard.c
Description:
This function is the entry point for TbtOemBoard.
Input:
ImageHandle - Image handle
SystemTable - Pointer to the system table
Output:
Return Status based on errors that occurred while waiting for
time to expire.


TbtOemBoard.mak

Description:


TbtOemLib.c

The following functions are used in the file: TbtOemLib.c.

Function | Description
ActiveTbtGpio2 | BIOS should assert GO2Sx pin That will trigger Host Router to prepare underlying devices For Thunderbolt host is CR chip This function only work for Thunderbolt Cactus Ridge chip
FinialProgramTbtSecurityLevel | BIOS should depend on Security Level to pull low FORCE_PWR pin or not This function only work for Thunderbolt Cactus Ridge chip
GetHRInfo | Pull High GPIO_3 and assign temp bus to get Thunderbolt Host Chip Series for distinguishing Thunderbolt host is Cactus Ridge or Redwood Ridge If your case is only support Redwood Ridge or only support Cactus Ridge, you can just return Thunderbolt Host number which is defined in TbtOemBoard.h According test result, the dynamic detect Thunderbolt HR series still has fail rate, so we don't suggest you using the same way to decide HR series. sample code is just for testing !!!
InactiveTbtGpio2 | BIOS should deassert GO2Sx pin That will trigger Host Router to prepare underlying devices This function only work for Thunderbolt Cactus Ridge chip
PeiFinialProgramTbtSecurityLevel | if system does not support "Wake from Thunderbolt device" function, BIOS should depend on Security Level and BootMod to pull low FORCE_PWR pin or not in PEI phase This function only work for Thunderbolt Cactus Ridge chip and system doesn't support wake up from Thunderbolt Device
PollTbtGpio9 | BIOS should poll OK2GO2SX_N_OD pin Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry. This function only work for Thunderbolt Cactus Ridge chip
PowerOffPOC | Power off POC to cut off thunderbolt power This function is optional and only work for Thunderbolt Cactus Ridge chip and system doesn't support wake up from Thunderbolt Device.
PowerOnPOC | Power on POC to wake up thunderbolt This function is optional and only work for Thunderbolt Cactus Ridge chip and system doesn't support wake up from Thunderbolt Device.
ProgramTbtSecurityLevel | This function is configure the Thunderbolt security level. OEM Porting required !!!.
PullDownTbtGpio9 | BIOS should pull down OK2GO2SX_N_OD pin in Wake flow if remebered Host Router state was active. This function only work for Thunderbolt Cactus Ridge chip and system doesn't support wake up from Thunderbolt Device
ReleaseTbtGpio9 | BIOS should release pull down OK2GO2SX_N_OD pin in Wake flow if remebered Host Router state was active This function only work for Thunderbolt Cactus Ridge chip and system doesn't support wake up from Thunderbolt Device
SynchSecurityLevel | When entering Setup page, double check Security Level setting is same or not between Thunderbolt host Fw and BIOS. This function only work for Thunderbolt Redwood Ridge chip
TbtBeforeSxExitFlow |
TbtSetPCIe2TBTCommand | This snipped code contains PCIE2TBT <-> TBT2PCIE handshake procedure and all related methods called directly or underectly by TbtSetPCIe2TBTCommand. This function is Intel Sample code(Rev. 1.5).


ActiveTbtGpio2 in the TbtOemLib.c

Function : ActiveTbtGpio2

File: TbtOemLib.c
Description:
BIOS should assert GO2Sx pin
That will trigger Host Router to prepare underlying devices
For Thunderbolt host is CR chip

This function only work for Thunderbolt Cactus Ridge chip
Input:
None
Output:
EFI_STATUS


FinialProgramTbtSecurityLevel in the TbtOemLib.c

Function : FinialProgramTbtSecurityLevel

File: TbtOemLib.c
Description:
BIOS should depend on Security Level to pull low FORCE_PWR pin
or not

This function only work for Thunderbolt Cactus Ridge chip
Input:
AMI_TBT_PLATFORM_POLICY_PROTOCOL *PlatformPolocy
Output:
None


GetHRInfo in the TbtOemLib.c

Function : GetHRInfo

File: TbtOemLib.c
Description:
Pull High GPIO_3 and assign temp bus to get Thunderbolt Host
Chip Series for distinguishing Thunderbolt host is Cactus Ridge
or Redwood Ridge

If your case is only support Redwood Ridge or only support Cactus
Ridge, you can just return Thunderbolt Host number which is defined
in TbtOemBoard.h

According test result, the dynamic detect Thunderbolt HR series
still has fail rate, so we don't suggest you using the same way
to decide HR series. sample code is just for testing !!!
Input:
None
Output:
UINT8 - Thunderbolt Host chip Series
       1 - Cactus Ridge
       2 - Redwood Ridge
       3 - Falcon Ridge


InactiveTbtGpio2 in the TbtOemLib.c

Function : InactiveTbtGpio2

File: TbtOemLib.c
Description:
BIOS should deassert GO2Sx pin
That will trigger Host Router to prepare underlying devices

This function only work for Thunderbolt Cactus Ridge chip
Input:
None
Output:
EFI_STATUS


PeiFinialProgramTbtSecurityLevel in the TbtOemLib.c

Function : PeiFinialProgramTbtSecurityLevel

File: TbtOemLib.c
Description:
if system does not support "Wake from Thunderbolt device"
function, BIOS should depend on Security Level and BootMod to
pull low FORCE_PWR pin or not in PEI phase

This function only work for Thunderbolt Cactus Ridge chip and
system doesn't support wake up from Thunderbolt Device
Input:
UINT8           TbtSecurityLevel
Output:
None


PollTbtGpio9 in the TbtOemLib.c

Function : PollTbtGpio9

File: TbtOemLib.c
Description:
BIOS should poll OK2GO2SX_N_OD pin
Upon completion of all preparations, Host Router will assert
this pin to indicate readiness for Sx entry.

This function only work for Thunderbolt Cactus Ridge chip
Input:
None
Output:
EFI_STATUS


PowerOffPOC in the TbtOemLib.c

Function : PowerOffPOC

File: TbtOemLib.c
Description:
Power off POC to cut off thunderbolt power

This function is optional and only work for Thunderbolt Cactus
Ridge chip and system doesn't support wake up from Thunderbolt
Device.
Input:
None
Output:
EFI_STATUS


PowerOnPOC in the TbtOemLib.c

Function : PowerOnPOC

File: TbtOemLib.c
Description:
Power on POC to wake up thunderbolt

This function is optional and only work for Thunderbolt Cactus
Ridge chip and system doesn't support wake up from Thunderbolt
Device.
Input:
None
Output:
EFI_STATUS


ProgramTbtSecurityLevel in the TbtOemLib.c

Function : ProgramTbtSecurityLevel

File: TbtOemLib.c
Description:
This function is configure the Thunderbolt security level.
OEM Porting required !!!.
Input:
UINT8           TbtSecurityLevel
UINT8           TBTHostSeries
UINT8           TbtHostLocation
BOOLEAN         IsPei
Output:
None


PullDownTbtGpio9 in the TbtOemLib.c

Function : PullDownTbtGpio9

File: TbtOemLib.c
Description:
BIOS should pull down OK2GO2SX_N_OD pin in Wake flow
if remebered Host Router state was active.

This function only work for Thunderbolt Cactus Ridge chip and
system doesn't support wake up from Thunderbolt Device
Input:
None
Output:
EFI_STATUS


ReleaseTbtGpio9 in the TbtOemLib.c

Function : ReleaseTbtGpio9

File: TbtOemLib.c
Description:
BIOS should release pull down OK2GO2SX_N_OD pin in Wake flow
if remebered Host Router state was active

This function only work for Thunderbolt Cactus Ridge chip and
system doesn't support wake up from Thunderbolt Device
Input:
None
Output:
EFI_STATUS


SynchSecurityLevel in the TbtOemLib.c

Function : SynchSecurityLevel

File: TbtOemLib.c
Description:
When entering Setup page, double check Security Level setting
is same or not between Thunderbolt host Fw and BIOS.

This function only work for Thunderbolt Redwood Ridge chip
Input:
UINT8           BiosSecurityLevel
UINT8           TbtHostLocation
Output:
UINT8           0 - Security Level synchnized without change
               1 - Security Level synchnized with programming
                   again
               2 - Error


TbtBeforeSxExitFlow in the TbtOemLib.c

Function : TbtBeforeSxExitFlow

File: TbtOemLib.c
Description:

Input:

EFI_PEI_SERVICES - **PeiServices
UINT8            - TbtHostSeries

Output:

None


TbtSetPCIe2TBTCommand in the TbtOemLib.c

Function : TbtSetPCIe2TBTCommand

File: TbtOemLib.c
Description:
This snipped code contains PCIE2TBT <-> TBT2PCIE handshake
procedure and all related methods called directly or underectly
by TbtSetPCIe2TBTCommand.
This function is Intel Sample code(Rev. 1.5).
Input:
UINT8 - UpPortBus
UINT8 - Data
UINT8 - Command
UINTN - Timeout
Output:
BOOLEAN


TbtPei.c

Description:

The following functions are used in the file: TbtPei.c.

Function | Description
TbtCRSxExitFlow | Thunderbolt host Sx Exit Flow for Cactus Ridge chip
TbtPeiAfterNbPcieReady | When Thunderbolt host is at NB PCIE slot, we do Sx_Exit flow here avoiding chipset limitation
TbtPeiEntry | This function is the main PEI phase entry point for the Thunderbolt module.
TbtSxExitFlow | Thunderbolt host Sx Exit Flow for Redwood Ridge, Falcon Ridge and Win Ridge(BDW-TBT-LP) chips


TbtCRSxExitFlow in the TbtPei.c

Function : TbtCRSxExitFlow

File: TbtPei.c
Description:
Thunderbolt host Sx Exit Flow for Cactus Ridge chip
Input:
EFI_PEI_SERVICES             **PeiServices
Output:
EFI_STATUS


TbtPeiAfterNbPcieReady in the TbtPei.c

Function : TbtPeiAfterNbPcieReady

File: TbtPei.c
Description:
When Thunderbolt host is at NB PCIE slot, we do Sx_Exit flow
here avoiding chipset limitation
Input:
EFI_PEI_SERVICES             **PeiServices
EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor
VOID                         *InvokePpi
Output:
EFI_STATUS


TbtPeiEntry in the TbtPei.c

Function : TbtPeiEntry

File: TbtPei.c
Description:
This function is the main PEI phase entry point for the Thunderbolt
module.
Input:
IN EFI_FFS_FILE_HEADER *FfsHeader
   -- FFS file header pointer
IN EFI_PEI_SERVICES **PeiServices
   -- PEI Services table pointer
Output:
EFI_STATUS (Return Value)
   = EFI_SUCCESS if successful
   = or other valid EFI error code
Notes:


TbtSxExitFlow in the TbtPei.c

Function : TbtSxExitFlow

File: TbtPei.c
Description:
Thunderbolt host Sx Exit Flow for Redwood Ridge, Falcon Ridge
and Win Ridge(BDW-TBT-LP) chips
Input:
EFI_PEI_SERVICES             **PeiServices
Output:
EFI_STATUS


TbtPei.mak

Description:


TbtSetup.c

The following functions are used in the file: TbtSetup.c.

Function | Description
InitiTbtInfo | Initializes Thunderbolt Setup String


InitiTbtInfo in the TbtSetup.c

Function : InitiTbtInfo

File: TbtSetup.c
Description:
Initializes Thunderbolt Setup String
Input:
HiiHandle - Handle to HII database
Class - Indicates the setup class
Output:
None
Notes:
PORTING REQUIRED


TbtSetup.h

Description:
Header file for iFfsSetup module.


TbtSetup.mak

Description:
Makfile for TBT Setup module.


TbtSetup.sd

Description:
Setup for Thunderbolt Setup.


TbtSetupReset.c

Description:
Setup Reset Rountines

The following functions are used in the file: TbtSetupReset.c.

Function | Description
TbtProcessEnterSetup | This function is a hook called when TSE determines that it has to load the boot options in the boot order. This function is available as ELINK.
TbtSetupResetHook | This function is a hook called after some control modified in the setup utility by user. This function is available as ELINK.


TbtProcessEnterSetup in the TbtSetupReset.c

Function : TbtProcessEnterSetup

File: TbtSetupReset.c
Description:
This function is a hook called when TSE determines
that it has to load the boot options in the boot
order. This function is available as ELINK.
Input:
VOID
Output:
VOID


TbtSetupResetHook in the TbtSetupReset.c

Function : TbtSetupResetHook

File: TbtSetupReset.c
Description:
This function is a hook called after some control
modified in the setup utility by user. This
function is available as ELINK.
Input:
VOID
Output:
VOID


TbtSmm.c

The following functions are used in the file: TbtSmm.c.

Function | Description
InSmmFunction | Installs TBT SMM Child Dispatcher Handler.
IsTBTDevice | Check device is Thunderbolt device or not Parameters: UINT16 - DeviceID
SmiDivU64x32 | This routine allows a 64 bit value to be divided with a 32 bit value returns 64bit result and the Remainder.
SmiStall | Stalls for the Required Amount of MicroSeconds Parameters: Usec - UINTN
TbtGo2SxCallback | The following flow should be performed as a last step before instructing the platform to enter Sx state: BIOS should assert GO2Sx pin That will trigger Host Router to prepare underlying devices BIOS should poll OK2GO2SX_N_OD pin Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry At this stage BIOS should continue with legacy Sx entry steps
TbtHotplugPinSciRouting | Find the Offset to a given Capabilities ID CAPID list: 0x01 = PCI Power Management Interface 0x04 = Slot Identification 0x05 = MSI Capability 0x10 = PCI Express Capability Parameters: UINT8 Bus - Pci Bus Number UINT8 Dev - Pci Device Number UINT8 Fun - Pci Function Number UINT8 CapId - CAPID to search for
TbtPowerButtonCallback | The following flow should be performed as a last step before instructing the platform to enter Sx state: BIOS should assert GO2Sx pin That will trigger Host Router to prepare underlying devices BIOS should poll OK2GO2SX_N_OD pin Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry At this stage BIOS should continue with legacy Sx entry steps
TbtSmm_Init | Installs TBT SMM Child Dispatcher Handler.
ThunderboltSwSmiCallback | This is a TBT software SMI Handler for Porting.


InSmmFunction in the TbtSmm.c

Function : InSmmFunction

File: TbtSmm.c
Description:
Installs TBT SMM Child Dispatcher Handler.
Input:
ImageHandle  - Image handle
*SystemTable - Pointer to the system table
Output:
EFI_STATUS


IsTBTDevice in the TbtSmm.c

Function : IsTBTDevice

File: TbtSmm.c
Description:
Check device is Thunderbolt device or not

Parameters:  UINT16 - DeviceID
Returns:
BOOLEAN - TRUE
         FALSE


SmiDivU64x32 in the TbtSmm.c

Function : SmiDivU64x32

File: TbtSmm.c
Description:
This routine allows a 64 bit value to be divided with a 32 bit
value returns  64bit result and the Remainder.
Input:
UINT64  Dividend
UINT64  Divisor
Output:
UINTN   *Remainder OPTIONAL


SmiStall in the TbtSmm.c

Function : SmiStall

File: TbtSmm.c
Description:
Stalls for the Required Amount of MicroSeconds

Parameters:  Usec - UINTN
Returns:
None


TbtGo2SxCallback in the TbtSmm.c

Function : TbtGo2SxCallback

File: TbtSmm.c
Description:
The following flow should be performed as a last step before
instructing the platform to enter Sx state:
  BIOS should assert GO2Sx pin
That will trigger Host Router to prepare underlying devices
  BIOS should poll OK2GO2SX_N_OD pin
Upon completion of all preparations, Host Router will assert
this pin to indicate readiness for Sx entry
At this stage BIOS should continue with legacy Sx entry steps
Input:
DispatchHandle   - SMI dispatcher handle
*DispatchContext - Pointer to the dispatch context
Output:
Nothing
Notes:
This function does not need to put the system to sleep.  This is
handled by PutToSleep.


TbtHotplugPinSciRouting in the TbtSmm.c

Function : TbtHotplugPinSciRouting

File: TbtSmm.c
Description:
Find the Offset to a given Capabilities
ID CAPID list:
   0x01 = PCI Power Management Interface
   0x04 = Slot Identification
   0x05 = MSI Capability
   0x10 = PCI Express Capability

Parameters:  UINT8 Bus     - Pci Bus Number
UINT8 Dev     - Pci Device Number
UINT8 Fun     - Pci Function Number
UINT8 CapId   - CAPID to search for
Returns:
UINT8    0        - CAPID not found
UINT8    Other    - CAPID found, Offset of desired CAPID


TbtPowerButtonCallback in the TbtSmm.c

Function : TbtPowerButtonCallback

File: TbtSmm.c
Description:
The following flow should be performed as a last step before
instructing the platform to enter Sx state:
  BIOS should assert GO2Sx pin
That will trigger Host Router to prepare underlying devices
  BIOS should poll OK2GO2SX_N_OD pin
Upon completion of all preparations, Host Router will assert
this pin to indicate readiness for Sx entry
At this stage BIOS should continue with legacy Sx entry steps
Input:
DispatchHandle   - SMI dispatcher handle
*DispatchContext - Pointer to the dispatch context
Output:
Nothing
Notes:
This function does not need to put the system to sleep.  This is
handled by PutToSleep.


TbtSmm_Init in the TbtSmm.c

Function : TbtSmm_Init

File: TbtSmm.c
Description:
Installs TBT SMM Child Dispatcher Handler.
Input:
ImageHandle  - Image handle
*SystemTable - Pointer to the system table
Output:
EFI_STATUS


ThunderboltSwSmiCallback in the TbtSmm.c

Function : ThunderboltSwSmiCallback

File: TbtSmm.c
Description:
This is a TBT software SMI Handler for Porting.
Input:
DispatchHandle  - EFI Handle
DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
Output:
None


TbtSmm.mak

Description:


Functions in Alphabetical Order

In Alphabetical Order

The following topics provide a list in alphabetical order.
For a list by file name, see By File Name.

  • A
  • C
  • D
  • F
  • G
  • I
  • P
  • R
  • S
  • T


Functions in Alphabetical Order

A

Function | Description
ActiveTbtGpio2 | BIOS should assert GO2Sx pin That will trigger Host Router to prepare underlying devices For Thunderbolt host is CR chip This function only work for Thunderbolt Cactus Ridge chip


Functions in Alphabetical Order

C

Function | Description
CreateTbtAcpiCallback | This function will create all ACPI components for SB when ACPI support protocol is available.


Functions in Alphabetical Order

D

Function | Description
DisableTbtDeviceRomCallback | Disable all Tbt devices option ROM to aviod S4 resume problem.
DsdtTableUpdate | Update the DSDT table


Functions in Alphabetical Order

F

Function | Description
FinialProgramTbtSecurityLevel | BIOS should depend on Security Level to pull low FORCE_PWR pin or not This function only work for Thunderbolt Cactus Ridge chip


Functions in Alphabetical Order

G

Function | Description
GetHRInfo | Pull High GPIO_3 and assign temp bus to get Thunderbolt Host Chip Series for distinguishing Thunderbolt host is Cactus Ridge or Redwood Ridge If your case is only support Redwood Ridge or only support Cactus Ridge, you can just return Thunderbolt Host number which is defined in TbtOemBoard.h According test result, the dynamic detect Thunderbolt HR series still has fail rate, so we don't suggest you using the same way to decide HR series. sample code is just for testing !!!


Functions in Alphabetical Order

I

Function | Description
InactiveTbtGpio2 | BIOS should deassert GO2Sx pin That will trigger Host Router to prepare underlying devices This function only work for Thunderbolt Cactus Ridge chip
InitiTbtInfo | Initializes Thunderbolt Setup String
InSmmFunction | Installs TBT SMM Child Dispatcher Handler.
InvokeSmiHandlerBeforeBoot | To invoke SW SMI befor boot for reaource adjust.
IsTBTDevice | Check device is Thunderbolt device or not Parameters: UINT16 - DeviceID
IsULTPchSeries | This function is to get PCH series is ULT series or not


Functions in Alphabetical Order

P

Function | Description
PeiFinialProgramTbtSecurityLevel | if system does not support "Wake from Thunderbolt device" function, BIOS should depend on Security Level and BootMod to pull low FORCE_PWR pin or not in PEI phase This function only work for Thunderbolt Cactus Ridge chip and system doesn't support wake up from Thunderbolt Device
PollTbtGpio9 | BIOS should poll OK2GO2SX_N_OD pin Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry. This function only work for Thunderbolt Cactus Ridge chip
PowerOffPOC | Power off POC to cut off thunderbolt power This function is optional and only work for Thunderbolt Cactus Ridge chip and system doesn't support wake up from Thunderbolt Device.
PowerOnPOC | Power on POC to wake up thunderbolt This function is optional and only work for Thunderbolt Cactus Ridge chip and system doesn't support wake up from Thunderbolt Device.
ProgramTbtSecurityLevel | This function is configure the Thunderbolt security level. OEM Porting required !!!.
PullDownTbtGpio9 | BIOS should pull down OK2GO2SX_N_OD pin in Wake flow if remebered Host Router state was active. This function only work for Thunderbolt Cactus Ridge chip and system doesn't support wake up from Thunderbolt Device


Functions in Alphabetical Order

R

Function | Description
ReleaseTbtGpio9 | BIOS should release pull down OK2GO2SX_N_OD pin in Wake flow if remebered Host Router state was active This function only work for Thunderbolt Cactus Ridge chip and system doesn't support wake up from Thunderbolt Device


Functions in Alphabetical Order

S

Function | Description
SmiDivU64x32 | This routine allows a 64 bit value to be divided with a 32 bit value returns 64bit result and the Remainder.
SmiStall | Stalls for the Required Amount of MicroSeconds Parameters: Usec - UINTN
SynchSecurityLevel | When entering Setup page, double check Security Level setting is same or not between Thunderbolt host Fw and BIOS. This function only work for Thunderbolt Redwood Ridge chip


Functions in Alphabetical Order

T

Function | Description
TbtBeforeSxExitFlow |
TbtCRSxExitFlow | Thunderbolt host Sx Exit Flow for Cactus Ridge chip
TbtDxe_Init | This function is the entry point for this DXE.
TbtDxeInvokeSmiHandler | Invoke SW SMI befor boot for reaource adjust.
TbtGo2SxCallback | The following flow should be performed as a last step before instructing the platform to enter Sx state: BIOS should assert GO2Sx pin That will trigger Host Router to prepare underlying devices BIOS should poll OK2GO2SX_N_OD pin Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry At this stage BIOS should continue with legacy Sx entry steps
TbtHotplugPinSciRouting | Find the Offset to a given Capabilities ID CAPID list: 0x01 = PCI Power Management Interface 0x04 = Slot Identification 0x05 = MSI Capability 0x10 = PCI Express Capability Parameters: UINT8 Bus - Pci Bus Number UINT8 Dev - Pci Device Number UINT8 Fun - Pci Function Number UINT8 CapId - CAPID to search for
TbtOemBoard_Init | This function is the entry point for TbtOemBoard.
TbtPeiAfterNbPcieReady | When Thunderbolt host is at NB PCIE slot, we do Sx_Exit flow here avoiding chipset limitation
TbtPeiEntry | This function is the main PEI phase entry point for the Thunderbolt module.
TbtPowerButtonCallback | The following flow should be performed as a last step before instructing the platform to enter Sx state: BIOS should assert GO2Sx pin That will trigger Host Router to prepare underlying devices BIOS should poll OK2GO2SX_N_OD pin Upon completion of all preparations, Host Router will assert this pin to indicate readiness for Sx entry At this stage BIOS should continue with legacy Sx entry steps
TbtProcessEnterSetup | This function is a hook called when TSE determines that it has to load the boot options in the boot order. This function is available as ELINK.
TbtProtectedPciDevice | This function is called by PCI Bus Driver before configuring or disabling any PCI device. This function should examine the Vendor/Device ID or PCI Bus, Device and Function numbers to make sure it is not a south bridge device or any other device which should no be configured by PCI Bus Driver.
TbtSetPCIe2TBTCommand | This snipped code contains PCIE2TBT <-> TBT2PCIE handshake procedure and all related methods called directly or underectly by TbtSetPCIe2TBTCommand. This function is Intel Sample code(Rev. 1.5).
TbtSetupResetHook | This function is a hook called after some control modified in the setup utility by user. This function is available as ELINK.
TbtSmm_Init | Installs TBT SMM Child Dispatcher Handler.
TbtSxExitFlow | Thunderbolt host Sx Exit Flow for Redwood Ridge, Falcon Ridge and Win Ridge(BDW-TBT-LP) chips
ThunderboltSwSmiCallback | This is a TBT software SMI Handler for Porting.


General Information