American Megatrends, Inc.

PciBus

Copyright

Release Notes

© American Megatrends, Inc.


eModule Release Notes

AMIBIOS Component Release Notes

Component Information:
Component Name: PCIBus
Component Type: eModulePart
Release Date: 2011/12/16
Source Control Label: Binaries - Core 4652_PCIBUSBIN_25_2; Sources - 4652_PCIBUSSRC_25_2
;
Binary Source Control Location: SS:ALASKA;$/Alaska/BIN/Core\Modules/PciBus;4652
Sources Source Control Location: SS:ALASKA;$/Alaska/BIN/Core\Modules/PciBus;4652
Component Description:
Pci Bus Sources Subcomponent (Part of "Core Sources" component)
Filename | Description
PciBusSrc.sdl | "PciBusSources" Module's SDL tokens file (modified by VeB)
PciBusSrc.mak | PCI Bus Sources Module MAK file (builds Module and all it's components)
PciBus.c | Main PCI Bus Driver file. It has Pci Bus Driver entry point and PciIo Protocol implementation.
PciHostBridge.c | Pci Root Bridge Driver file. Has Implementation of PciRootBridgeIo Protocol.
DeviceIo.c | Implementation of DeviceIo Protocol for compatibility sake. This protocol does not supported by UEFI anymore.
PCI Bus Subcomponent (Part of Core component)
Filename | Description
PciBus.sdl | "PciBus" Module SDL tokens file (modified by VeB)
PciBus.mak | "PciBus" Module MAK file (builds Module and all it's components)
PciBus.sd | "PciBus" Module Setup Definitions (SD) file (Provides PciBus Driver Setup Screen)
PciBus.uni | "PciBus" Module Setup Strings used by SD file.
PciBusSetup.c | "PciBus" Module Strings override routines to dynamically change Setup options.
PciPort.c | "PciBus" Driver porting file.
PciSetup.h | "PciBus" Driver Setup types definitions. Separates board specific setup data from Generic Pci Bus Driver code.
PciBoard.asm | Assembly Language file which includes all VeB auto-generated files.
PciBusSrc.lib | 32bit version of PciBus Library used to build final Driver Image (removed in v2.5.0 and up).
PciBusSrcx64.lib | 64bit version of PciBus Library used to build final Driver Image (removed in v2.5.0 and up).
PciPort.h | Definition file of available Porting Functions.
PciRootBridge.dxs | Dependency expression file for PCI Root Bridge Driver..
PciBusIncludes Subcomponent (Part of PCI Bus Component)
Filename | Description
PciBus.h | "PciBus" Driver private types and data definitions
PciHostbridge.h | "PciRootBridge" Driver private types and data definitions
PciBusEx.h | PCI Bus Extended Protocol interface declarations and data types
PCIe30.h | PCI Express Specification version definitions.
AMI Build Tools:
Tools Label: 4.5.5_TOOLS_34, Dated: 2010-10-06
Visual eBios: RSS.5.70.0171, Dated: 2010-10-04
Compiler Tool(s): WinDDK 7600.16385.1; DDK 3790.1830
General Information About this Label:
  • NewFeatures
    • EIP 71380
    Core support for CSM opt-out feature
    Files: PciBus.c; PciPort.c; PciBus.sd; PciBus.uni; PciSetup.h;
    EIP 54911
    Reconnect -r issue fixed for cards with OFF board option ROMs.
    Files: PciBus.c
    EIP 54911
    Added changes for module to be compliant with UEFI specification v 2.3.1.
    Files: PciBus.c
    Added some MORE debug messages.
    Added IO 3C0-3DF reservation release when Legacy VGA attributes set
    Fixed build issue when PCI_EXPRESS_GEN2_SUPPORT token set to OFF.
  • Bug Fixes
    • Minor bug fixes not related to any eip EIP. Code cleanup.
    Fixed bug in PcieRetrainLink function it was not doing other attempts to retrain link because of missing else statement.
    Fixed potential bug in PcieSetSlotProperties() routine. It was using uninitialized RCI_ADDRESS var this may cause system HUNG .
    Changed size of access to the ROM BAR register in GetOpRom() from 1 byte to 4 - some cards could hang the system if 1 byte is used.
    According to AMD GOP Driver GetBarAttributes() must return _GRA field set as a bar type NOT A RESOURCE TYPE
    EIP 72803: Incorrect Max Payload setting
    RootCause: The issue was that recorded MPL value was updated before PcieProgramPayloadUp() function was invoked. In that function we check condition again since it was needed to maintain loop exit. But control newer enter the loop since conditions were not met at that point for reason stated above.
    Solution: Move code that updates recorded MPL with a new value after call to PcieProgramPayloadUp().
    Files: PciBus.c
    EIP 71694: Option ROM is corrupted when copied from device on Rosecity Core 4.6.5.1.
    RootCause: MemCopy routine was updated to use 64 bit access but PCI BAR. Copy can not handle this.
    Solution: Introduced MemCpy32 routine to handle fast copy 4 byte at a time
    Files: PciBus.c
    EIP 66216: Hotplug resource padding not working for ROOT bridges other than 0.
    RootCause: Hot plug slots was incorrectly associated always with the RootBridge #0.
    Solution: Changed algorithm to beter distinguish between Root Bridges. Added debug messagers to monitor HPC_LOCATION_DATA.
    Files: PciBus.c; PciHostBridge.c.
  • Update Instructions
  • This release id part of Core 4652. Follow Core 4652 update instructions.
  • For Out of Resources condition handling get 4650_PCI_BRD_RES_01A component from $/Alaska/BIN/Modules/Template/PciPlatformResources/
  • See PCI Porting Guide on AMI Share Portal for more details and coding examples. Updated Porting Guide corresponding current label also attached to EIP 55759
    • Revision History:
  • Core 4651_PCIBUSBIN_25_1:
  • NewFeatures
    • Genericaly supported token PCI_DEV_REVERSE_SCAN_ORDER. If set to ON Pci Bus Driver will scan devices on PCI Bus in reverce order (from 31 to 0 default is from 0 to 31).
    Added LinkSpeed trace when link reset or retrain called.
    EIP 57664
    Aptio PI 1.2; UEFI 2.3.1 Support Extended PCI bus driver functionality
    Files: DevicePath.h; LoadFile2.h; PciBus.h; PciBus.c.
    EIP 58702
    Aptio PI 1.2; UEFI 2.3.1 Support Changes in Bus Drivers protocols (PCI bus driver)
    Files: PciBus.c
    EIP 53475
    PCI Express support issue fixed
    Files: PciBus.c
    EIP 54911
    Reconnect -r issue fixed.
    Files: PciBus.c
    EIP 61311
    PCI Express controllers may not be correctly initialized, because of missing delays, while resetting the link. Added delay code and tokens PCI_T_RST and PCI_T_RST_RECOVERY.
    Files: PciBus.c
    EIP 63430
    Replace use of PciIo->MemRead with MemCpy() for Option ROMs.
    Files: PciBus.c
    EIP 61101
    The secondary bus reset in the link retraining code causes downstream PLX bridges to disappear. Added BridgeRestoreBuses() function.
    Files: PciBus.c
  • Bug Fixes
    • Minor bug fixes not related to any eip EIP. Code cleanup.
    Fixed bug in PcieRetrainLink function it was not doing other attempts to retrain link because of missing else statement.
    EIP 54911
    Calling Stop function was causing ASSERT. Caused by Incorrect setting of the attributes and handling Stop function for Device of Type tRootBridge.
    Files: PciBus.c
    EIP 54911
    Calling Stop function was causing ASSERT. Caused by Incorrect setting of the attributes and handling Stop function for Device of Type tRootBridge.
    Files: PciBus.c
    EIP 61310
    Unable to enter OpROM on Adaptec 1430 card. OpROM executes, attached drives will boot but pressing Ctrl A to enter utility hangs system. Considered DID==0 as a valid option meaning all devices.
    Files: PciBus.c
    EIP 60123
    Resource padding is not functional for PCIe hot-plug. Caused by In hot plug function was missed changes in BusXlat. Fixed AmiBoardInfo driver to correctly update HP slot info.
    Files: PciHostBridge.c; PciBoard.c; AmiBoardInfo.c.
  • Update Instructions
  • This release id part of Core 4651. Follow Core 4651 update instructions.
  • For Out of Resources condition handling get 4650_PCI_BRD_RES_01A component from $/Alaska/BIN/Modules/Template/PciPlatformResources/
  • See PCI Porting Guide on AMI Share Portal for more details and coding examples. Updated Porting Guide corresponding current label also attached to EIP 55759
    • 4650_PCIBUSBIN_25_0:
  • NewFeatures
    • EIP 38174
    Generic support to handle PCI OUT OF RESOURDCES conditions
    Files: PciBus.c; PciHostBridge.c;
    EIP 53475
    Generic PCI Express 3.0 support.
    Files: PciBus.c; PciBus.uni; PciBus.sd
  • Bug Fixes
    • Minor bug fixes not related to any eip EIP. Code cleanup.
  • Update Instructions
  • Remove old PciBUs Module (Sources and Binaries)
  • Download new 4650_PCIBUSSRC_25_0; 4650_PCIBUSBIN_25_0
  • Update following Core Files: AcpiRes.c(checkin #36 or up); AcpiRes.h(#16); Setup.h(#36)
  • Check EIP 57650. If EIP is closed get latest TSE Binaries, if not use attaced to that EIP bootflow.c and booflow.h.
  • For Out of Resources condition handling get 4650_PCI_BRD_RES_01A component from $/Alaska/BIN/Modules/Template/PciPlatformResources/
  • See PCI Porting Guide on AMI Share Portal for more details and coding examples. Updated Porting Guide corresponding current label also attached to EIP 55759
    • 4650_PCIBUS_24_0
  • NewFeatures:
    • EIP48290:
    Added PCI_AMI_COMBINE_MEM_PMEM32 token that tells to map 32 bit sized PF MMIO BARs trough NON PF MMIO Bridge registers.
    Files: PciBus.c; PciBus.sdl;
    EIP43879:
    Added PciPortOemGetOptRom() OEM Hook to override content of the PCI Device Option ROM.
    Files: PciBus.c; PciPort.c; PciPort.h; PciBus.mak; PciBus.sdl
  • Improvements
    • EIP43879:
    Added PciPortOemGetOptRom() OEM Hook to override content of the PCI Device Option ROM.
    Files: PciBus.c; PciPort.c; PciPort.h; PciBus.mak; PciBus.sdl
    EIP45278:
    Changed default resource allocation algorithm to work more efficiently.
    Files: PciBus.c; PciHostBridge.c
    EIP49743:
    Workaround for devices which having Link Retrain bit "sticky".
    Files: PciBus.c
    EIP50097:
    Fixed issue when with PCI_FIXED_BUS_ASSIGNMENT==1 system was ASSERTING. Reason was that with complicated PCI structure next bridge XLAT entry that used to determine Subordinate bus #, selected incorrectly.
    Files: PciBus.c
    Removed Setup Option "Selectable DeEmphasis" since it is HwInit Bit.
  • Bug Fixes
    • EIP49743
    Incorrect initialization complicated PCI infrastructure wrong condition to breake {do while loop}.
    Files: PciBus.c
    EIP49743
    In the PcieCalcLatency(), the do-while loop condition have issue in this.
    It may be a condition when while loop in function PcieCalcLatency(), will never break.
    Files: PciBus.c
    Fixed bug in PcieCalcLatency() function. It was not calculating L1 latency correctly.
    4640_PCIBUS_24_0
    Features and Bug Fixes:
    PciHostBridge.c
  • Updated CreateRootBusData to call HbCspDoesRootBrgExist to determine whether to updated the BusXlat table for the particular host device.
  • Updated ClaimMmioResources to use MMIO resources as-is if AllocType is set to EfiGcdAllocateAddress. For this chipset, each root bridge is programmed with base and limit values for 32bit and 64bit MMIO. The root bridge will only decode addresses within these ranges. For this reason, the Base and Limit values passed to the PCI Bus driver should be used as-is and not modified.
    • PciBus.c
  • EIP 41687: The PciBus.c had workaround code for patching bad PCI or PCIe device list. Bad Pci list only could not cover device reource that requested more than one MMIO resources.
  • New Incompatibility Type Sypport: icBad64BitBar - Device has a bar that is 64bit capable, but the card does not function properly when it is allocated with an address above 4G.
  • Freeing all Memory when exiting with ERROR from EnumerateBus() function.
  • Fixed UEFI Option ROM Size miscalculation.
  • EIP 40554: Fixed WDK Build Issue.
  • EIP 38289: Minor fix for Klocwork Issues II.
  • Improved logic to select matching PCI Bus Xlat table entry.
  • Fixed condition to disable device using 64 bit resource threshold.
  • Fixed bug in DoubleCheckOpRom() when OpROM is a Single Image ROM.
  • Fixed build error with SRIOV token ON.
    • MPL Programming:
  • Bug fix in PcieProgramPayloadUp() function, canged order when recording calculated PayLoad.
  • It use to recursive call was made after reduced value of MPL was recorded. It was preventing function to program MPL correctly.
  • Fixed InitDevCahain() function Logic.
  • Fixed issue with PCIe Switches and MPL programming UP.
  • Fixed Possible issue with incorrect MPL Programming.
  • Introduced a New Csp Hook to overwrite global ASPM Settings.
    • PciPort.c; PciPort.h
  • Introduced a New Csp Hook to overwrite global ASPM Settings.
    • 4640_PCIBUS_24_0_TEST
    1. This Label is ONLY compatible with Core 4.6.4.0!
    2. This PCI Bus Driver Label also requires separately labeled Core.AmiBoardInfo Component and ACPI Module Label 32 or later.
    3. This label uses new, "C" style output of the AMI SDL. It is required update VeB and AMI SDL tool to version 5.68.0116 or Higher .
    4. In this label has competely redesigned an Algorithm used to initialize PCI Express Features including customers suggestions.
    5. Generic Support of PCI Express Base Specification ver. 2.1 was added.
    6. PCI Setup Screen was changed to separate PCI Express 1.1 Features and 2.1 (Generation 2).
    7. Label theoretically support ARI Forwarding... BUT No testing has been done since there are no ARI Hardware available yet.
    8. A generic Hot-Plug support also was improved in this label.
    9. PCI Root Bridge Driver uses information generated by VeB and some tokens from PciBus.sdl automatically produces MULTY ROOT infrastructure.
    10.When updating make sure you have followed update instructions from 4636_PCIBUS_23_0_TEST in project's Chipset files.
    11.New Chipset template will have all needed parts referenced in NEW ACPI ROOT Resource Allocation.
    Update Instructions
    1. Make sure your project has CORE 4640.
    2. Update AmiBoardInfo Sub Component with 4640_AMI_BOARD_0100.
    3. Get PCI Bus Driver Module From SS Label 4640_PCIBUSBIN_240_TEST.
    4 If your project has Sources: Get PCI Bus Driver Module From SS Label 4640_PCIBUSSRC_240_TEST.
    5. Verify that you have followed update instructuins from 4636_PCIBUS_23_0_TEST in project's Chipset files.
    6. Enjoy!
    4636_PCIBUS_23_0_TEST
    New Features and Bug Fixes
    PciBus.c
    1. P2P Bridge Spec. v1.1 requires to set INT Line Register to 0xFF. PCI spec 3.0 require to set it to 0xFF - means not connected for x86 architecture. Values of 0..0x0F indicating IRQ0..15 values 0x10..0xFE reserved.
    2. Fixed (~0LU) statement to (0ULL). This is correct statement for 64 bit Value.
    3. Component Name protocol implementation is updated to support both Component Name and ComponentName2 protocols (based on value of the EFI_SPECIFICATION_VERSION SDL token).
    4. Fixed: EIP 19106 If 1 Bus set to be padded in Setup, PCI Bus driver still creates 1 BUS for this bridge instead of 2.
    5. Moved DisableBridgeDecoding() call before Disable device decoding since it could decode 0-4K of IO and 0-1M of Memory.
    6. Fixed conditions in ApplyAcpiResources() where function assumes validity of Resource Range. In case of Fixed Resource Allocation Resource window allocated by custom unction might be bigger than actual hardware resource request.
    7. Fixed EIP 26787. If P2P Bridge has Expansion ROM BAR, value that has to go there was programmed as Secondary Interface Forward Range.
    PciHostBridge.c
    1. Added Print out Message in DEBUG_MODE with PCI BUS Driver Version.
    2. Added Initialization of ImageHandle field in Host Bridge and Root Bridge Structures. (New PciHostBridge.h required).
    3. Generic support for multiple root bridges resources reporting to ACPI DSDT Root Bridge Object (EIP 23548 Support MMIO allocation above 4GB, if devices are capable).
    PciPort.c and PciPort.h
    1. Added infrastructure to ELINKs as porting Functions delivered from Platform and Chipset files. Now you can port PCI Bus driver without modifying Core files
    PciHostBridge.h
    1. Added definitions to support changes for EIP 23548 (Support MMIO allocation above 4GB).
    PciBus.sdl
    1. PCI Bus Driver Version Changes.
    2. Added Parenting eLinks "OEM_SKIP_PCI_DEVICE"; "OEM_PROGRAM_PCI_DEVICE"; "OEM_PCI_ATTRIBUTES". To implement PCI Bus Driver hooks invocation w/o modifying Generic Files.
    PciBus.mak Changes
    1. Added Definitions for OEM_PCI_PROGRAM_DEVICE_CALLBACK_LIST; OEM_PCI_SKIP_DEVICE_CALLBACK_LIST and OEM_PCI_DEVICE_ATTRIBUTES_LIST to support adding porting hooks trough eLinks.
    Update Instructions
    Get PCI Bus Driver Module From SS. If your Project has CORE Earlier than 4.6.3.6, You need to upgrade to Core 4.6.3.6. first. Please follow instructions listed in here in "Revision History" Section or CORE CHM.
    PCI Bus Driver Version 2.3.0 Assumes that following modules are present in the Project.
    1. AmiBoardInfo eModule Part (Part Of Core BIN Starting from "SS: Alaska;$/Alaska/BIN/Core\Modules/BoardInfo;4.6.3.6" )
    2. ACPI Module Label 32. Upgrade from earlier Module Possible by following Steps below:
    a)Get updated OSCM.ASL from ACPI 32 (it must be included from each ROOT BRIDGE Device Scope)
    b)Get New file RbRes.asl from ACPI 32 (it must be included from each ROOT BRIDGE Device Scope)
    c)Get Updated AMLUPD.ASL (Some place holders no longer needed)
    d)Make sure each implementation of ROOT PCI Object in ASL Like "PCI0" "PCI1"(usually it is Nb.asl and Nb2.asl) must include following:

        include("Core\\Em\\ACPI\\RbRes.ASL")
        include("Core\\Em\\ACPI\\OSCM.ASL")
    e)Make sure to comment out all related to ROOT BRIDGE _CRS Method Objects from OEM_DSDT.ASL.
    f)If your project uses multiple ROOT BRIDGEs and predefined resource splitting. Use following code as reference for implementation of Resource Allocating routine

    //-----------------------------------------------------------------------
//CSP Function invoked in PCI Host Bridge Driver when time to ask GCD
//for resources. You can overwrite a default algorithm used to allocate
//resources for the Root Bridge.
EFI_STATUS HbCspAllocateResources( PCI_HOST_BRG_DATA *HostBrgData,
                                    PCI_ROOT_BRG_DATA *RootBrgData,
                                    UINTN RootBrgIndex)
{
    EFI_STATUS					Status=EFI_UNSUPPORTED;
//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
//Any Additional Variables goes here

    UINTN						i;
    ASLR_QWORD_ASD				*res;
    UINT64						a=0;
    UINT64						AddressLimit=0;
    DXE_SERVICES				*dxe;
    EFI_IOH_UDS_PROTOCOL  		*mIohUds; //Platform/Chipset Sapecifik interface provoding information about resource Split between Multiple ROOTs.
    EFI_GUID 					gEfiIohUdsProtocolGuid = EFI_IOH_UDS_PROTOCOL_GUID;

    // ported for two IOHs

  // koti : TO_DO : further improvement on resources based on setup options, if one IOH requires more than other and
    // Checking for error conditions on not to assign a more than qpi decode range.
    if (RootBrgIndex > (NUMBER_IOH_SOCKETS-1)) return Status;
    Status = pBS->LocateProtocol(
                            &gEfiIohUdsProtocolGuid,
                            NULL,
                            &mIohUds);
    ASSERT_EFI_ERROR (Status);
    if (EFI_ERROR(Status))
        return Status;

    Status=LibGetDxeSvcTbl(&dxe);
    if(EFI_ERROR(Status)) return Status;

    //Feel out needed structures.
    if(RootBrgData->AcpiRbRes[raIo].Min==0){ //do it only ones
        RootBrgData->AcpiRbRes[raIo].Min=mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceIoBase;
        RootBrgData->AcpiRbRes[raIo].Max=mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceIoLimit;
        RootBrgData->AcpiRbRes[raIo].Len=RootBrgData->AcpiRbRes[raIo].Max-RootBrgData->AcpiRbRes[raIo].Min+1;
        RootBrgData->AcpiRbRes[raIo].AddrUsed=mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceIoLimit+1;
        RootBrgData->AcpiRbRes[raIo].AllocType=EfiGcdAllocateMaxAddressSearchTopDown;

        RootBrgData->AcpiRbRes[raMmio32].Min=mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceMem32Base;
        RootBrgData->AcpiRbRes[raMmio32].Max=mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceMem32Limit;
        RootBrgData->AcpiRbRes[raMmio32].Len=RootBrgData->AcpiRbRes[raMmio32].Max-RootBrgData->AcpiRbRes[raMmio32].Min+1;
        RootBrgData->AcpiRbRes[raMmio32].AddrUsed=mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceMem32Limit+1;
        RootBrgData->AcpiRbRes[raMmio32].AllocType=EfiGcdAllocateMaxAddressSearchTopDown;

        RootBrgData->AcpiRbRes[raMmio64].Min=mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceMem64Base;
        RootBrgData->AcpiRbRes[raMmio64].Max=mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceMem64Limit;
        RootBrgData->AcpiRbRes[raMmio64].Len=RootBrgData->AcpiRbRes[raMmio64].Max-RootBrgData->AcpiRbRes[raMmio64].Min+1;
        RootBrgData->AcpiRbRes[raMmio64].AddrUsed=mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceMem64Limit+1;
        RootBrgData->AcpiRbRes[raMmio64].AllocType=EfiGcdAllocateMaxAddressSearchTopDown;
    }

    for(i=0; iResCount; i++){
        res=RootBrgData->RbRes[i];
        if(res->Type==ASLRV_SPC_TYPE_BUS) {
            TRACE((-1, "PciRB: #%X BUS _MIN=0x%lX; _MAX=0x%lX; _LEN=0x%lX\n",
                        RootBrgIndex,res->_MIN,res->_MAX,res->_LEN, res->_GRA));
            continue;
        }
        // update io and memory values from qpi rc output.
        //Allocate IO
        if(res->Type==ASLRV_SPC_TYPE_IO){

        //
        //Set Resource starting address for IO based on which RB it is.
        // Update Root Bridge with UDS resource information
        //
            RootBrgData->AcpiRbRes[raIo].Gra=res->_MAX;
            a = mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceIoBase;
            AddressLimit = mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceIoLimit;
            AddressLimit = AddressLimit + 1; // make power of 2
            TRACE((-1,"PciRB: #%X Resources Type=%X; routed by QPI: Address base = %lX; AddressLimit=%lX; \n",
            RootBrgIndex, res->Type, a, AddressLimit));

            TRACE((-1, "PciRB: #%X IO ",RootBrgIndex));
            //Use prefered method to allocate resources for
            Status=dxe->AllocateIoSpace(EfiGcdAllocateMaxAddressSearchTopDown,
                            EfiGcdIoTypeIo,
                            AlignFromGra((UINTN)res->_MAX),
                            res->_LEN,
                            &AddressLimit,
                            RootBrgData->ImageHandle,
                            RootBrgData->RbHandle);
            if(EFI_ERROR(Status)) {
                TRACE((-1,"PciRB: IO Allocation Failed: _LEN=%lX; _GRA=l%X.\n",res->_LEN, res->_MAX));
                ASSERT_EFI_ERROR(Status);
                return Status;
            }
        }
        //Allocate MMIO
        else if( res->Type==ASLRV_SPC_TYPE_MEM){
            //First root or Second one????
            if(res->_GRA==32){
                a = mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceMem32Base;
                AddressLimit = mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceMem32Limit;
                AddressLimit = AddressLimit + 1; // make power of 2
                TRACE((-1, "PciRB: #%X MMIO32",RootBrgIndex));
                RootBrgData->AcpiRbRes[raMmio32].Gra=res->_MAX;
            } else {
                a = mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceMem64Base;
                AddressLimit = mIohUds->IohUdsPtr->PlatformData.IOH_resource[RootBrgIndex].PciResourceMem64Limit;
                AddressLimit = AddressLimit + 1; // make power of 2
                TRACE((-1, "PciRB: #%X MMIO64",RootBrgIndex));
                RootBrgData->AcpiRbRes[raMmio64].Gra=res->_MAX;
            }

            TRACE((-1,"PciRB: #%X Resources Type=%X; routed by QPI: _GRA=%lX; Address base = %lX; AddressLimit=%lX; \n",
            RootBrgIndex, res->Type, res->_GRA, a, AddressLimit));

            Status=dxe->AllocateMemorySpace(EfiGcdAllocateMaxAddressSearchTopDown,
                            EfiGcdMemoryTypeMemoryMappedIo,
                            AlignFromGra((UINTN)res->_MAX),
                            res->_LEN,
                            &AddressLimit,
                            RootBrgData->ImageHandle,
                            RootBrgData->RbHandle);
            if(EFI_ERROR(Status)) {
                TRACE((-1,"PciRootBrg: Memory Allocation Failed: Length: %lX\n",res->_LEN));
                return Status;
            }

            //Set this region as WT cache if it is PREFETCHABLE
            if(res->TFlags.MEM_FLAGS._MEM!=ASLRV_MEM_UC)
            {
                TRACE((-1,"P"));
                Status=dxe->SetMemorySpaceAttributes(AddressLimit,res->_LEN,EFI_MEMORY_WT);
                //if attempt to set WT attributes has filed, let's try UC
                if(EFI_ERROR(Status))
                {
                    TRACE((-1,"PciHostBridge: Setting of WT attributes for prefetchable memory has failed(%r). UC is used.\n",Status));
                    Status=dxe->SetMemorySpaceAttributes(AddressLimit,res->_LEN,EFI_MEMORY_UC);
                }
            }
            else Status=dxe->SetMemorySpaceAttributes(AddressLimit,res->_LEN,EFI_MEMORY_UC);
            ASSERT_EFI_ERROR(Status);
            if(EFI_ERROR(Status)) return Status;

        }
        res->_MIN = AddressLimit;
//		TRACE((-1,"PciRB: #%X Resources: Type=%X; TFlags=%X; GCD asssigned address _MIN=%lX; _MAX=%lX; _GRA=%lX; _LEN=%lX.\n",
//        RootBrgIndex, res->Type, res->TFlags.TFLAGS,res->_MIN, res->_MAX, res->_GRA, res->_LEN ));
        TRACE((-1, ": _MIN=0x%lX; _MAX=0x%lX; _LEN=0x%lX; _GRA=0x%lX\n",
        res->_MIN,res->_MAX,res->_LEN, res->_GRA ));

        //No need to change this and lose Granularity Value... will preserve it.
        //res->_MAX=res->_MIN+res->_LEN-1;
    }

//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
    return Status;
}
    g)If you are using Standard(Single Root Project) or you want to use dynamic (default) resource allocation Algorithm, have HbCspAllocateResources() function return EFI_UNSUPPORTED. If so, default resource allocation algorithm will be used.
    h)Replace function UpdateAml() at ACPICore.c with following code:

//
//----------------------------------------------------------------------------
//  Procedure:   UpdateAml
//
//  Description:
//  This function updates AML objects with values provided in ACPI_AML_UPD_INFO
//  structure
//
//  Input:
//  IN ACPI_AML_UPD_INFO *AmlUpdInfo - pointer to ACPI_AML_UPD_INFO structure
//
//  Output:
//  EFI_SUCCESS - AML objects updated successfully
//  EFI_ERROR - some error occured during update process
//
//----------------------------------------------------------------------------
//

EFI_STATUS UpdateAml(ACPI_AML_UPD_INFO	*AmlUpdInfo)
{
    UINTN			i;
    ACPI_HDR 	*Dsdt;
    EFI_STATUS		Status = 0;

//-------------------------

    for(i = 0; i < 2; i++){
        if (i) Dsdt = (ACPI_HDR*)AmlUpdInfo->Dsdt1Addr;
        else Dsdt = (ACPI_HDR*)AmlUpdInfo->Dsdt2Addr;
        if (Dsdt){
            //Update TOPM Object
            Status = UpdateAslNameObject(Dsdt, "TOPM", AmlUpdInfo->TopOfMemory);
            ASSERT_EFI_ERROR (Status)
            if (EFI_ERROR(Status)) return Status;

            //Update ROMS Object
            //Status = UpdateNameObject(Dsdt, AML_NAME_ROMS, AmlUpdInfo->RomStart);
            //ASSERT_EFI_ERROR(Status)
            //if(EFI_ERROR(Status)) return Status;
//TODO: IOST and SSx Objects update
            //Update IOST Object
            Status = UpdateAslNameObject(Dsdt, "IOST", (UINT64)AmlUpdInfo->SioDevStatusVar.DEV_STATUS);
            ASSERT_EFI_ERROR(Status)
            if(EFI_ERROR(Status)) return Status;

            Status = UpdateAslNameObject(Dsdt, "SS4", (UINT64)AmlUpdInfo->SS4);
            ASSERT_EFI_ERROR(Status)
            if(EFI_ERROR(Status)) return Status;

            Status = UpdateAslNameObject(Dsdt, "SS3", (UINT64)AmlUpdInfo->SS3);
            ASSERT_EFI_ERROR(Status)

            if(EFI_ERROR(Status)) return Status;
            Status = UpdateAslNameObject(Dsdt, "SS2", (UINT64)AmlUpdInfo->SS2);
            ASSERT_EFI_ERROR(Status)

            if(EFI_ERROR(Status)) return Status;
            Status = UpdateAslNameObject(Dsdt, "SS1", (UINT64)AmlUpdInfo->SS1);
            ASSERT_EFI_ERROR(Status)
            if(EFI_ERROR(Status)) return Status;

            Dsdt->Checksum = 0;
            Dsdt->Checksum = ChsumTbl((UINT8*)Dsdt, Dsdt->Length);
        }
    }
    return Status;
}
    i) Comment out function CollectPciAmlUpdInfo(ACPI_AML_UPD_INFO *AmlUpdInfo).
    j) Comment call to function CollectPciAmlUpdInfo() from CollectAmlUpdInfo() function. This functionality moved into PciHostBridge.c:

//	Status=CollectPciAmlUpdInfo(Aui);
//	ASSERT_EFI_ERROR(Status);
    4633_PCIBUS_2_2:
    Fixes:
    1. Fixed minor issues, related to PCI IRQ entries usage and update.
    2. Potential issue when optimizing resources EIP 21366. Extra BAR Length value could overflow if initial eBar->Length totally used by other resource requests.
    3. Fixed potential Memory corruption issue when assigning Ext->XlatEntry->BusRun for bridges not having corresponded XlatTbl Entry.
    4. Fixed issue with Multi Root support and incorrect bus allocation for the secondary Root(s) if they have advanced (more than 1) bus structure.
    5. Fixed issue in AssignBridgeResources() function when there are no bars to program function was returning ERROR Status.
    6. Other Minor bug fixes and code cleanup.
    New Features in Release:
    1. Separated from PCI Bus Driver all PCI Bus related auto generated output files.
    2. Made PciBus and PCI Root Bridge Driver use New "AMI Board Info" Protocol.
    3. Added Generic Support for PERR#, SERR# and VGA Palette Snoop settings.
    4. Added PCI Porting Hooks to overwrite setting Device Attributes.
    5. Added Generic Support and Setup Question on how to handle resource requests Above 4G.
    6. Added "Semi-Automatic" Support for PCI Express Hot-Plug controlled by the BIOS. Supported only if AMI_ROOT_BRIDGE_SUPPORT token set to ON. will work only with Recent CHIPSET Template and ACPI label higher than 30.
    7. Added Setup Form to configure Hot-Plug settings.
    Files Changed In this Label.
    Removed: PciBoard.asm; PciBoard.h; PciBusSrcRbx64; PciBusSrcRb
    Added: PciPort.h; PciBusSrc.chm
    PciBus.c:
    1. Changed name and initialization of mMaxBusLen global variable to mMaxBusScan.
    2. Added Debug messages when updating IRQ routing table.
    3. Added Dump of PIC and APIC IRQ Routing Tables dump at the end of enumeration.
    4. Added fix in OptimizeBrgResource() function
    5. Changes related to removing PciBoard.h and usage of <Protocol\AmiBoardInfo.h>
    PciBus.h:
    1. PCI_DEV_INFO added new fields and Data types.
    PciHostridge.c
    1. Changes related to production of Root HP Controller Initialization Protocol.
    2. Changes related to removing PciBoard.h and PciBoard.asm from Root Bridge driver.
    PciPort.h; PciPort.c:
    1.Added new porting hooks prototypes and implementations
    PciBus.mak;PciBusSrc.mak:
    1. Changes related to removing/adding files to/from component.
    PciBus.sdl;PciBusSrc.sdl:
    1. Changes related to the new features implementation. Some eLinks was removed since they don't needed anymore.
    PciBusSetup.h; PciBus.sd; PciBus.uni:
    1. Changes related to the new features implementation.
    Update Instructions.
    1. Upgrade PciBus Component.
    2. If your project contains "Core Sources" module, upgrade PciBus sources component.
    3. Two additional parameters have been added to HbCspMapRootBrgToHost function in NbPciCsp.c (Function HbCspMapRootBrgToHost was introduced in PCI Bus Driver Label 21). On most of the projects current definition of the function can simply be replaced with the one below. Multi-host projects may require additional porting.

//<AMI_PHDR_START>/----------------------------------------------------------------------------
//
// Procedure:   HbCspMapRootBrgToHost
//
// Description:	Chipset specific function that returns Host Bridge Number for
//              the corresponded Root Bridge.
//
// Input:
//  IN PCI_BUS_XLAT_HDR*  RootBrgXlatHdr - Root Bridge XLAT table entry
//
// Output:
//      UINTN - Number of the Host Bridge that root bridge identified by RootBrgXlatHdr belongs to.
//
// Note:
//  THIS FUNCTION MUST BE PORTED FOR MULTI-HOST SYSTEMS
//
//  HOST bridge handle supports:
//    - ResourceAllocation Protocol (REQUIRED);
//    - RootHotplugControllerInitialization Protocol (OPTIONAL);
//    - PciPlatform Protocol (OPTIONAL).
//  ROOT bridge handle supports:
//    -PciRootBridgeIo Protocol (REQUIRED).
//----------------------------------------------------------------------------
//<AMI_PHDR_END>
UINTN HbCspMapRootBrgToHost(IN PCI_BUS_XLAT_HDR *RootBrgXlatHdr,
                            UINT64              *AllocationAttr,
                            UINT64              *RbSuportedAttr)
{
//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//

//Usually even server chipsets use only one PCI HOST abstraction
//but if  chipset has more than one HOST we have to specify
//which ROOT from PciBusXlat table belongs to which HOST.

    //Check if we need to update/change Allocation Attributes Passed to this function...
    //Here we have ability to override Automaticaly generated Attributes based on
    //SDL tokens COMBINE_MEM_PMEM and ABOVE_4G_PCI_DECODE
    //bits currently defined for Allocation Attributes is:
    //  EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
    //  EFI_PCI_HOST_BRIDGE_MEM64_DECODE
    //Usually nothing needs to be done sor SINGLE HOST-SINGLE-ROOT systems
    //NOTE: this function could be called more than one time for each HOST
    // if you updating AllocationAttr only last data will be valid.
    //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    // PCI HostBridge Driver sets DEFAULT allocation attributes.
    // Add code only if you need to overwrite it.

    //if i.e. second root does not support PF_MMIO
    //if(RootBrgXlatHdr->BusBuild == 0x80 ) *AllocationAttr &= ~(EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM);
    //else *RbSuportedAttr = ....;

    //Check that in VeB PCI Wizard this Root creates bus 0
    //This is usualy a compatibility bus
    //Set the Compatibility bus Attributes it must decode Legacy resources
    //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    // PCI HostBridge Driver sets DEFAULT Supported ROOT BRIDGE Attributes.
    // Add code only if you need to overwrite it.

    //if(RootBrgXlatHdr->BusBuild==0) *RbSuportedAttr=
    //(EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |	EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO| \
    //EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO  | \
    //EFI_PCI_ATTRIBUTE_VGA_MEMORY | EFI_PCI_ATTRIBUTE_VGA_IO | \
    //EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO);
    //else *RbSuportedAttr=0;

    //Returning Host Number for Root Bridge corresponded to the Root
    //ported as RootBrgXlatHdr->BusBuild from BusXLat Table
    //for single SINGLEHOST-SINGLE-ROOT system this value always 0
    //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    // If your system MULTY-HOST/MULTY-ROOTs system
    //you need to add code here to correctly map each ROOT referenced in VeB wizard
    //to it's corresponded host

    return 0;

//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
}
    4. Add the following definition of the new function HbCspAllocateResources to NbPciCsp.c.

//-----------------------------------------------------------------------
//CSP Function invoked in PCI Host Bridge Driver when time to ask GCD
//for resources. You can overwrite a default algorithm used to allocate
//resources for the Root Bridge.
EFI_STATUS HbCspAllocateResources( PCI_HOST_BRG_DATA *HostBrgData,
                                PCI_ROOT_BRG_DATA *RootBrgData,
                                UINTN RootBrgIndex)
{
    EFI_STATUS	Status=EFI_UNSUPPORTED;
//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
//Any Additional Variables goes here
/*
    UINTN				i;
    ASLR_QWORD_ASD		*res;
    UINT64				a=0;
    DXE_SERVICES		*dxe;
//------------------------------------
    Status=LibGetDxeSvcTbl(&dxe);
    if(EFI_ERROR(Status)) return Status;

    for(i=0; iResCount; i++){
        res=RootBrgData->RbRes[i];
        if(res->Type==ASLRV_SPC_TYPE_BUS) continue;

        //Allocate IO
        if(res->Type==ASLRV_SPC_TYPE_IO){
            //First root or Second one????
            //Set Resource starting address for IO based on which RB it is.
            if(RootBrgIndex==0) a= 0xB000;
            else a=0xc000;

            //Use prefered method to allocate resources for
            Status=dxe->AllocateIoSpace(EfiGcdAllocateMaxAddressSearchBottomUp,
                            EfiGcdIoTypeIo,
                            AlignFromGra((UINTN)res->_MAX),
                            res->_LEN,
                            &a,
                            RootBrgData->RbHandle, NULL);
            if(EFI_ERROR(Status)) {
                PCI_TRACE((TRACE_PCI,"PciRootBrg: IO Allocation Failed: Length: %lX\n",res->_LEN));
                return Status;
            }
        }

        //Allocate MMIO
        else if( res->Type==ASLRV_SPC_TYPE_MEM){

            //None PF memeory Will Have TypeSpecific Flag Different.

            //First root or Second one????
            if(res->_GRA==32){
                if(RootBrgIndex==0 ) a= 0xB0000000; //Set Resource starting address for IO
                else a=0xC0000000;
            } else {
                if(RootBrgIndex==0 ) a= 0x800000000; //Set Resource starting address for IO
                else a=0x1000000000;
            }

            Status=dxe->AllocateMemorySpace(EfiGcdAllocateMaxAddressSearchBottomUp,
                            EfiGcdMemoryTypeMemoryMappedIo,
                            AlignFromGra((UINTN)res->_MAX),
                            res->_LEN,
                            &a,
                            RootBrgData->RbHandle, NULL);
            if(EFI_ERROR(Status)) {
                PCI_TRACE((TRACE_PCI,"PciRootBrg: Memory Allocation Failed: Length: %lX\n",res->_LEN));
                return Status;
            }

            //Set this region as WT cache if it is PREFETCHABLE
            if(res->TFlags.MEM_FLAGS._MEM!=ASLRV_MEM_UC)
            {
                Status=dxe->SetMemorySpaceAttributes(a,res->_LEN,EFI_MEMORY_WT);
                //if attempt to set WT attributes has filed, let's try UC
                if(EFI_ERROR(Status))
                {
                    PCI_TRACE((TRACE_DXE_CHIPSET,"PciHostBridge: Setting of WT attributes for prefetchable memory has failed(%r). UC is used.\n",Status));
                    Status=dxe->SetMemorySpaceAttributes(a,res->_LEN,EFI_MEMORY_UC);
                }
            }
            else Status=dxe->SetMemorySpaceAttributes(a,res->_LEN,EFI_MEMORY_UC);
            ASSERT_EFI_ERROR(Status);
            if(EFI_ERROR(Status)) return Status;

        }
        res->_MIN=a;
        res->_MAX=res->_MIN+res->_LEN-1;
    }
*/

//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
    return Status;
}
    5. Remove definitions of the following four variables from NbPciCsp.c (the variables are no longer needed).
      •
UINTN	gRbCountTbl[NB_NUMBER_OF_HOST_BRG]={
    1, 	//Number of root bridges produced by Host #0
        //Number of root bridges produced by Host #1
        //Number of root bridges produced by Host #2
        //Number of root bridges produced by Host #3
};

      •
UINT64 gHbAllocAttribTbl[NB_NUMBER_OF_HOST_BRG]={
// Changed next line to 0 because screen would go blank early
// during EFI Vista installation
//	EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM,	//Allocation Attributes of Host #0
    0,	//Allocation Attributes of Host #0
        //Allocation Attributes of Host #1
        //Allocation Attributes of Host #2
        //Allocation Attributes of Host #3
        // And so on
};

      •
ASLR_QWORD_ASD	gRbBusesTbl[]={
//for Root 0 at Host 0
    {0x8A, 0x2B,ASLRV_SPC_TYPE_BUS, 0,0,  	0x1, 	0x00, 	0xFF, 	0, 		0x100 }//Bus
//for Root 1 at Host 0 if any

//for Root 0 at Host 1 if any
};

      •
UINT64	gRbSupportsTbl[]={
//for Root 0 at Host 0
    (EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |	EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO| \
     EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO  | \
     EFI_PCI_ATTRIBUTE_VGA_MEMORY | EFI_PCI_ATTRIBUTE_VGA_IO | \
     EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO),
//for Root 1 at Host 0 if any

//for Root 0 at Host 1 if any

// and so on...
};
    6. Update implementation of function HbCspStartBusEnumeration in NbPciCsp.c. Older versions of PCI host bridge driver expected this function to create ACPI resource descriptor that defines available range of buses. It is no longer necessary. The information about available bus range is derived from the data generated by VeB PCI routing wizard. The function implementation must be replaced with the following code:

EFI_STATUS HbCspStartBusEnumeration(
        PCI_HOST_BRG_DATA *HostBrgData,PCI_ROOT_BRG_DATA *RootBrgData,UINTN RootBrgIndex)
{
    EFI_STATUS	Status=EFI_SUCCESS;
//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
//!!!!!ATTENTION!!!!!!!!!!ATTENTION!!!!!!!!!!ATTENTION!!!!!!!!!!ATTENTION!!!!!
//!!!!!NO NEED IMPLEMENTING THIS FUNCTION AMYMORE.
//IT MAY BE IMPLEMENTED IF YOU NEED TO OWERWRITE INITIAL BUILD TIME BUS ASSIGNMENT.
//USE RootBrgData->RbRes[i] of type ASLR_QWORD_ASD with Type field ==ASLRV_SPC_TYPE_BUS

//Any Additional Variables goes here

//------------------------------------

//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
//PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING////PORTING//
    return Status;
}
    7. Update declaration of HbCspMapRootBrgToHost function in NbCspLib.h:

UINTN HbCspMapRootBrgToHost(PCI_BUS_XLAT_HDR    *RootBrgXlatHdr,
                            UINT64              *AllocationAttr,
                            UINT64              *RbSuportedAttr);
    8. Add the following declaration of HbCspAllocateResources function to NbCspLib.h:

EFI_STATUS HbCspAllocateResources( PCI_HOST_BRG_DATA *HostBrgData,
                                PCI_ROOT_BRG_DATA *RootBrgData,
                                UINTN RootBrgIndex);
    NOTE #1: Sub Component is compatible with Core 4.6.3.6 or later.
    NOTE #2: To use PciBus Subcomponent of version 2.2.0 with the older versions of CORE, you need to add "AmiBoardInfo" MODULEPART from Core 4.6.3.6 to your project and update "Protocol" module part to get AmiBoardInfo.h header.
    NOTNOTE #3: If You updating to PciBus Driver v2.2.0 to have Generic PCIExpress Hot-Plug Support, you will need ACPI Label higher than 30 and most recent CHIPSET template. See AMI_Aptio_4.x_PCI_Porting_Guide_NDA_rev_03 on SHAREPORTAL for instructions how to port project for Hot Plug Support.
    4633_PCIBUS_21_2:
    Fixes:
    1. Fixed PCI Express MaxPayload and ReadRequest Size calculation algorithm. EIP #17947.
    2. Potential issue with name collision in PciHostBridge.c and PciBus.c. Renamed some global variables used.
    3. Added changes to support /W4 build switch.
    4. Added fix to break the PCI Express Extended Capability header access if read returns 0xFFFF. EIP #19144.
    New Features:
    Added "PciPortSkipThisDevice()" to handle PCI Devices which not suppose to be "Touched" during enumeration Process. EIP #8874
    4633_PCIBUS_21_1: Minor bug fixes label
    Fixes:
    1. Fixed "Connect -r" issue EIP #17740..
    2. Fixed Start function of the PCI Bus Driver. It use to return EFI_SUCCESS even
    when all devices were STARTTED. Now it returning EFI_ALREADY_STARTED. This will
    help save some time when CORE attempts to start ALREADY STARTED devices since
    Start() function returned SUCCESS.
    New Features:
    2. None.
    4633_PCIBUS_21: First independent label of the subcomponent.
    Fixes:
    1. Fixed SRIOV support.
    2. Added changes to pass PCI SIG Compliance test.
    3. Changes in PciBusEx Protocol. Some functions there moved to AMI Board Info Interface
    4. Fixed Stop() function in DriverBinding Protocol of the PCI Bus Driver.
    5. Removed EFI_DEADLOOP() used for debugging in PciBus.c and PciHostBridge.c
    New Features:
    1. PCI Root Bridge Driver Installs AMI Board Information Protocol now. It groups together all.
    2. Added Definitions for AMI Board Information Protocol.
    3. Corresponded changes in Make files since PCI RootBridge Driver has to start to install AMI_BOARD_INFO Protocol even when AMI_ROOT_BRIDGE_SUPPORT token is OFF.
    4. Introduced changes to Extended PCI Bus Protocol interface
    5. Added New PciBusSrcRb.Lib and PciBusSrcRbx64.lib build with AMI_ROOT_BRIDGE_SUPPORT set to OFF. Helps to reduce size of the PCI Module when using non-AMI RootBridge driver.

    © American Megatrends Inc.


Function by File Name

AMIBIOS Function Reference

By File Name

The following is a list of the source files.
For a list in alphabetical order, see In Alphabetical Order.

  • PciBus.h
  • PciBus.mak
  • PciBus.sd
  • PciBusEx.h
  • PciBusSetup.c
  • PCIE30.h
  • PciHostBridge.h
  • PciPort.c
  • PciRootBridge.dxs
  • PciSetup.h
Built on 17:56:11 12/16/11


PciBus.h

Description:
This header file contains Data Type Definitions for
        the PCI Bus Driver Private Data

Tabsize:		4

The following data structures are used in the file: PciBus.h.

Variable | Description
BRG_ALIGN_INFO | This Structure used to store information about PCI Bridge alignment requirements since behind the bridge could be more than one device.
MBRG_RES_DSC | Structure used to access and store PCI Device Resource Requirements in a form of QWORD ACPI Resource Descriptor.
MRES_TYPE | This ENUM value definitions used to identify PCI Device different Resource types.
PCI_BAD_BAR | This structure used to identify Incapable PCI Devices which has some BAR irregularity.
PCI_BAR | This Structure used to store information about PCI Device Base Address Register (BAR)
PCI_BAR_TYPE | This ENUM value used to identify PCI Device different BAR types.
PCI_BRG_CNT_REG | UNION of UINT16 and a Structure used to access and store PCI COMMAND REGISTER values.
PCI_BRG_EXT | PCI Bridge Extended Data Structure. This Structure used to store Hosts and PCI to PCI Bridges additional data. It must follow exactly after the PCI_DEV_INFO data structure of the device identified as a Bridge.
PCI_BRG_INFO | PCI Bridge Private Data Structure.
PCI_BUS_OVERRIDE_DATA | This Structure used to store information about PCI Device's EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL Instance, if any.
PCI_CFG_ADDR | UNION of UINT64 and a Structure used to access and store PCI Device Address.
PCI_CMD_REG | UNION of UINT16 and a Structure used to access and store PCI COMMAND REGISTER values.
PCI_DEV_CLASS | UNION of UINT32 and a Structure used to access and store PCI Device BaseClass, SubClass, ProgrammingInterface and RevisionId values.
PCI_DEV_ID | UNION of UINT32 and a Structure used to access and store PCI Device VendorId and DeviceId values.
PCI_DEV_INFO | This Structure is the main data structure associated with the PCI Device. It holds all device specific data and references all other data srtuctures defined in "PciBus.h".
PCI_DEVICE_TYPE | This ENUM definition used to identify PCI Device different BAR types
PCI_HOST_INFO | Root Srtucture of the PCI Subsystem.
PCI_INCOMPATIBILITY_TYPE | ENUM used to specify PCI Device Incompatibility Type for Device that doesn't comply with defined in PCI Spec enumeration algorithm.
PCI_SPACE_TYPE | This ENUM value definitions used to identify PCI Device's different Space types.
PCI_STA_REG | UNION of UINT16 and a Structure used to access and store PCI COMMAND REGISTER values.
PCIE2_DATA | This Structure used to store Device's PCI Express Gen2 Specific Data.
PCIE_DATA | This Structure used to store Device's PCI Express Specific Data.
PCIE_EXT_DATA_HDR | This Structure used to store PCI Express Device's Extended Data Structure Header. It is the same for all data types.
PCIX_DATA | This Structure used to store Device's PCI-X Specific Data.
RES_CONV_TYPE | This ENUM used to identify PCI Device Resource Conversion Type
VC_DATA | This Structure used to store PCI Express Device's Virtual Channel Data.
VC_RES_DATA | This Structure used to store PCI Express Device's Virtual Channel Resource Data.


BRG_ALIGN_INFO in the PciBus.h

Variable : BRG_ALIGN_INFO

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
MaxGran | UINT64 | Maximum Granularity of the Resources Behind the Bridge
ResGran | UINT64 | Granularity that will apply after Bridge Resources would be assigned
MinGran | UINT64 | Minimum Granularity supported by the Bridge
PCI_BAR | ExtraRes | Resource window Padded in order to support Granularity of the next allocation

Description:
This Structure used to store information about PCI Bridge
alignment requirements since behind the bridge could be more than one
device.


MBRG_RES_DSC in the PciBus.h

Variable : MBRG_RES_DSC

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
Res | ASLR_QWORD_ASD | An "rtMaxRes" array of all possible Resources
EndDsc | ASLR_EndTag | Array terminator

Description:
Structure used to access and store PCI Device Resource Requirements
in a form of QWORD ACPI Resource Descriptor.
Notes:
See ACPI Specification 3.0 for details on ACPI Resource Descriptors.
    See definition of MRES_TYPE for definitions of rtMaxRes.


MRES_TYPE in the PciBus.h

Variable : MRES_TYPE

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
rtBus | ENUM | Bus resources
rtIo16 | ENUM | I/O 16bit Resources
rtIo32 | ENUM | I/O 32bit Resources
rtMmio32 | ENUM | MMIO 32bit Resources
rtMmio32p | ENUM | Prefetchable MMIO 32bit
rtMmio64 | ENUM | MMIO 64bit Resources
rtMmio64p | ENUM | Prefetchable MMIO 64bit
rtMaxRes | ENUM | Last valid value of this ENUM

Description:
This ENUM value definitions used to identify PCI Device different Resource types.


PCI_BAD_BAR in the PciBus.h

Variable : PCI_BAD_BAR

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
IncompType | PCI_INCOMPATIBILITY_TYPE | Type of PCI Device Incompatibility
VendorId | UINT16 | Vedor ID of the PCI Device (PCI CFG OFFSET 0x00)
DeviceId | UINT16 | Device ID of the PCI Device (PCI CFG OFFSET 0x02)
DeviceIdMask | UINT16 | AND MASK to apply to Device ID value to include wider variety of the devices from the same VENDOR
Reserved | UINT16 | Must be ZERO
BarType | PCI_BAR_TYPE | PCI Device Bar Type which is Incompatible to include all device BARs of the same type Only tBarIo, tBarMem and tBarMaxType allowed.
BarOffset | UINTN | If BarType==tBarMaxType this field specifies BAR offset. Ignored if BarType!=tBarMaxType.
BarBase | UINT64 | this field will be ignored at all times Fixed Base feature not implemented yet
BarLength | UINT64 | If IncompType==icBarFixedSize this field will indicate actual resource length for the BAR. Ignored if IncompType!=icBarFixedSize.

Description:
This structure used to identify Incapable PCI Devices which
has some BAR irregularity.


PCI_BAR in the PciBus.h

Variable : PCI_BAR

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
Type | PCI_BAR_TYPE | Type of PCI Device BAR may be converted
DiscoveredType | PCI_BAR_TYPE | Actual Type of PCI Device BAR
Base | UINT64 | Base Address of the Resource assigned to this BAR
Length | UINT64 | Length of the Resource assigned to this BAR in bytes
Gran | UINT64 | Grenularity of the Resource assigned to this BAR - a value that was read back after all ONEs was applied to the BAR.
Offset | UINT8 | Offset of the PCI Config Space where this bar Located
Reserved | UINT8 | 7 Reserved Byte Fields to make structure 4 byte aligned
BarAttr | UINT64 | PCI BAR Attributes see EFI 1.1 spec for details
*Owner | PCI_DEV_INFO | Pointer to Device Private data Structure of the device who owns this structure.

Description:
This Structure used to store information about PCI Device
Base Address Register (BAR)


PCI_BAR_TYPE in the PciBus.h

Variable : PCI_BAR_TYPE

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
tBarUnused | ENUM | BAR is not used to Specify Device Resources(empty)
tBarBus | ENUM | Virtual BAR type to use the same mechanism to clame BUS resources for the device used in bridge specific resourse routines
tBarIo16 | ENUM | BAR is used to Specify Device's I/O 16bit Resources
tBarIo32 | ENUM | BAR is used to Specify Device's I/O 32bit Resources
tBarMmio32 | ENUM | BAR is used to Specify Device's MMIO 32bit Resources
tBarMmio32pf | ENUM | BAR is used to Specify Device's Prefetchable MMIO 32bit
tBarMmio64 | ENUM | BAR is used to Specify Device's MMIO 64bit Resources
tBarMmio64pf | ENUM | BAR is used to Specify Device's Prefetchable MMIO 64bit
tBarIo | ENUM | A superset of PCI_BAR_TYPE tBarIo16 and tBarIo32
tBarMem | ENUM | A superset of PCI_BAR_TYPE tBarMmio32 and tBarMmio64
tBarMemPf | ENUM | A superset of PCI_BAR_TYPE tBarMmio32pf and tBarMmio64pf
tBarMaxType | ENUM | Last valid value of this ENUM

Description:
This ENUM value used to identify PCI Device different BAR types.


PCI_BRG_CNT_REG in the PciBus.h

Variable : PCI_BRG_CNT_REG

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
CMD_REG | UINT16 | Content of entire PCI COMMAND Register.
struct | UINT16 | Bit field definition of COMMAND register bits.

Description:
UNION of UINT16 and a Structure used to access and store PCI
COMMAND REGISTER values.


PCI_BRG_EXT in the PciBus.h

Variable : PCI_BRG_EXT

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
Res | PCI_BAR | An Array of "rtMaxRes" PCI_BAR structures to hold resource requirements of bridge secondary interface
Pad | PCI_BAR | An Array of "rtMaxRes" PCI_BAR structures to hold resource Padding requirements of bridge secondary interface
Align | BRG_ALIGN_INFO | An Array of "rtMaxRes" BRG_ALIGN_INFO structures to hold Resource Alignment requirements of bridge secondary interface
BarOrder | BRG_RES_ORDER | An Array of "rtMaxRes" BRG_RES_ORDER structures to hold BAR Order of bridge secondary interface
PaddAttr | EFI_HPC_PADDING_ATTRIBUTES | Resource Padding Attributes.
AllocAttr | UINT64 | Resource Allocation Attributes.
InitialCount | UINTN | To make this and 2 following fields look like T_ITEM_LIST.
ChildCount | UINTN | Number of PCI Devices descovered on Bridge's secondary interface.
**ChildList | PCI_DEV_INFO | Pointer to the array of pointers on Child Devices Private Data.
Padded | BOOLEAN | Indicaes that resources Vas Padded for that Bridge.

Description:
PCI Bridge Extended Data Structure. This Structure used to store
Hosts and PCI to PCI Bridges additional data. It must follow exactly after the
PCI_DEV_INFO data structure of the device identified as a Bridge.
Notes:
See PCI.h for details;


PCI_BRG_INFO in the PciBus.h

Variable : PCI_BRG_INFO

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
Common | PCI_DEV_INFO | Data Structure which common for all Objects. See PCI_DEV_INFO.
Bridge | PCI_BRG_EXT | PCI Bridge additional information. See PCI_BRG_EXT.

Description:
PCI Bridge Private Data Structure.


PCI_BUS_OVERRIDE_DATA in the PciBus.h

Variable : PCI_BUS_OVERRIDE_DATA

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
BusOverride | EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL | EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL instance.
*OverrideHandles | EFI_HANDLE | Pointer to the EFI_HANDLEs Buffer gets overriden by the inctance of EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL above.
OhCount | UINTN | Number of EFI_HANDLEs in "OverrideHandles" buffer
*Owner | PCI_DEV_INFO | Pointer to Device Private data Structure of the device who owns this structure.

Description:
This Structure used to store information about PCI Device's
EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL Instance, if any.


PCI_CFG_ADDR in the PciBus.h

Variable : PCI_CFG_ADDR

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
ADDR | UINT64 | All Fields together as a single value
Addr | EFI_PCI_CONFIGURATION_ADDRESS | PCI Device Address Structure

Description:
UNION of UINT64 and a Structure used to access
and store PCI Device	Address.


PCI_CMD_REG in the PciBus.h

Variable : PCI_CMD_REG

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
CMD_REG | UINT16 | Content of entire PCI COMMAND Register.
struct | UINT16 | Bit field definition of COMMAND register bits.

Description:
UNION of UINT16 and a Structure used to access and store PCI
COMMAND REGISTER values.


PCI_DEV_CLASS in the PciBus.h

Variable : PCI_DEV_CLASS

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
DEV_CLASS | UINT32 | BaseClass, SubClass, ProgrammingInterface and RevisionId all together
RevisionId | UINT8 | RevisionId value
ProgInterface | UINT8 | ProgInterface value
SubClassCode | UINT8 | SubClassCode value
BaseCalssCode | UINT8 | BaseCalssCode value

Description:
UNION of UINT32 and a Structure used to access and store PCI
Device BaseClass, SubClass, ProgrammingInterface and RevisionId values.


PCI_DEV_ID in the PciBus.h

Variable : PCI_DEV_ID

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
DEV_VEN_ID | UINT32 | VendorId and DeviceId all together.
VenId | UINT16 | VendorId value.
DevId | UINT16 | DeviceId value.

Description:
UNION of UINT32 and a Structure used to access and store PCI
Device VendorId and DeviceId values.


PCI_DEV_INFO in the PciBus.h

Variable : PCI_DEV_INFO

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
PciIo | EFI_PCI_IO_PROTOCOL | An instance of the EFI_PCI_IO_PROTOCOL for This Device.
BusOvrData | PCI_BUS_OVERRIDE_DATA | An instance of PCI_BUS_OVERRIDE_DATA structure for This Device.
*DevicePath | EFI_DEVICE_PATH_PROTOCOL | A pointer to an instance of EFI_DEVICE_PATH_PROTOCOL for This Device.
*RbIo | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL | A pointer to an instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL of This Device's Root Bridge.
*ParentBrg | PCI_DEV_INFO | Pointer to a private datastructure of This Device's "Parent" Bridge.
*HostData | PCI_HOST_INFO | Pointer to This Device's Host Bridge private data.
Type | PCI_DEVICE_TYPE | Type of This Device. See PCI_DEVICE_TYPE for details.
Started | BOOLEAN | Flag to indicate that device has been Registred with HandleDatabase and has its EFI_PCI_IO_PROTOCOL installed. Device is READY TO USE
Assigned | BOOLEAN | Flag to indicate that resources requested by this Device was assigned to it and corresponded BARs were programmed.
Discovered | BOOLEAN | Flag to indicate that resource requested information of This Device has been gethered and recorded.
Discovered | BOOLEAN | Flag to indicate that that This Device was enumerated and it's Address; ClassCode; Type and DevID/VendId data recorded.
Address | PCI_CFG_ADDR | Address on the PCI Bus of This Device.
Handle | EFI_HANDLE | This Device Handle.
DevVenId | PCI_DEV_ID | This Device Identification - Contents of DevID and VendorID Registers
Class | PCI_DEV_CLASS | This Device RevisionId Cllas, Sub Class and ProgrInterface Code.
Bar | PCI_BAR | PCI_MAX_BAR_NO+1 Bar Registers if Device has implemented Option ROM BAR it is also covered.
Capab | UINT64 | This Device Capabilities.
Attrib | UINT64 | This Device Attributes.
PmiCapOffs | UINTN | This Device Power Management Capabilities Header Offset in PCI Config Space.
*PciExpress | PCIE_DATA | If This Device has PCI Express features this field will have pointer to the PCI Express Data Structure.
*PciX | PCIX_DATA | If This Device has PCI-X or PCI-X2 features this field will have pointer to the PCI X Data Structure.
*HotPlug | PCI_HPC_INFO | If This Device is a Hot Plug Controller or the bridge behind which Hot Plug Slots located this field will have a Pointer to a member of PCI_HOST_INFO.HpcList[?].
Incompatible | BOOLEAN | Flag to indicaste that This Device's VendorID DeviceID was found in Bad Pci Device Table.
RbError | BOOLEAN | Flag to indicaste that Root Bridge Access failed during initialization.
RomBarError | BOOLEAN | Flag to indicaste that Option ROM BAR implemented but Invalid.
DebugPort | BOOLEAN | Flag to indicaste that This Device is reserved as a Debug Port.

Description:
This Structure is the main data structure associated with the PCI Device.
It holds all device specific data and references all other data srtuctures defined in "PciBus.h".
Notes:
See "PCI.h" for details;


PCI_DEVICE_TYPE in the PciBus.h

Variable : PCI_DEVICE_TYPE

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
tPciUnknown | ENUM | PCI Bus Driver wasn't able to Identify the Device
tPciRootBrg | ENUM | Device is a PCI Root Bridge Device (A virtual device the root of PCI tree)
tPci2PciBrg | ENUM | Device is a PCI to PCI Bridge Device
tPci2CrdBrg | ENUM | Device is a PCI to CARD Bus Bridge Device
tPciHostDev | ENUM | Device is a PCI Host Bridge Device (North Bridge)
tUncompatibleDevice | ENUM | Device is an Uncompatible PCI Device
tPciMaxDevice | ENUM | Last valid value of this ENUM

Description:
This ENUM definition used to identify PCI Device different BAR types
Notes:
Don't cange the order! Some PCI Bus internal routines rely on it!


PCI_HOST_INFO in the PciBus.h

Variable : PCI_HOST_INFO

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
*VgaDev | PCI_DEV_INFO | Pointer on curently selected Legacy VGA device.
*PriIde | PCI_DEV_INFO | Pointer on curently selected Legacy Primary IDE device.
*SecIde | PCI_DEV_INFO | Pointer on curently selected Legacy Secondary IDE device.
RbInitCount | UINTN | To make this and 2 following fields look like T_ITEM_LIST.
RbCount | UINTN | Number of Root Bridges in the System.
**RootBridges | PCI_DEV_INFO | Pointer to the array of pointers on PCI Root Bridge PCI Devices Private Data.
HostHandle | EFI_HANDLE | Handle of the PCI Host Bridge Associated with this Root Bridge
*ResAllocProt | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL | Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL Instance.
*PlatformProt | EFI_PCI_PLATFORM_PROTOCOL | Pointer to the EFI_PCI_PLATFORM_PROTOCOL Instance.
*IncompDevProt | EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL | Pointer to the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL Instance.
*HpInitProt | EFI_PCI_HOT_PLUG_INIT_PROTOCOL | Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL Instance.
RhpcInitCnt | UINTN | To make this and 2 following fields look like T_ITEM_LIST.
RhpcCount | UINTN | Number of Root Hot plug Controllers in the System.
**RhpcList | PCI_HPC_INFO | Pointer to the array of pointers on PCI Root Hot Plug Controller Private Data. See PCI_HPC_INFO.
InitRhpcCount | UINTN | Number of Initialized PCI Root Hot Plug Controllers
Updated | BOOLEAN | Flag to indicate that Host information has been collected.
Enumerated | BOOLEAN | Flag to indicate that This Host infrastructure has been enumerated.

Description:
Root Srtucture of the PCI Subsystem.


PCI_INCOMPATIBILITY_TYPE in the PciBus.h

Variable : PCI_INCOMPATIBILITY_TYPE

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
icNone | ENUM | Device is Compatible with PCI Spec
icBarBad | ENUM | Device doesn't set all implemented bits as "1" after writing there all "1"s. Setting icBadBar will notify PCI bus Driver that it could be a sizing problems with this BAR and it should treat this BAR differently.
icBarFixedSize | ENUM | Device could hang the system if all "1s" will be written in corresponded BAR register. Setting icBarFixedSize will notify PCI bus Driver to use Value provided in Incompatible Devices table intead of querying the Device.
icNotBar | ENUM | Device has a read/write register implemented but this register must not be enumerated. So the PCI Bus Driver will not consider this BAR as valid and will skip it.
icBad64BitBar | ENUM | Device has a bar that is 64bit capable, but the card does not function properly when it is allocated with an address above 4G.
icMaxIncompatibility | ENUM | Last valid value of this ENUM

Description:
ENUM used to specify PCI Device Incompatibility Type for Device that
doesn't comply with defined in PCI Spec enumeration algorithm.


PCI_SPACE_TYPE in the PciBus.h

Variable : PCI_SPACE_TYPE

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
stMemSpace | ENUM | Memory Space
stIoSpace | ENUM | I/O Space
stMemIoSpace | ENUM | Memory and I/O Space
stOptRomSpace | ENUM | PCI Option ROM Space
stDisableAll | ENUM | Disable all possinble decoding
stMaxType | ENUM | Last valid value of this ENUM

Description:
This ENUM value definitions used to identify PCI Device's different Space types.


PCI_STA_REG in the PciBus.h

Variable : PCI_STA_REG

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
STA_REG | UINT16 | Content of entire PCI STATUS Register.
struct | UINT16 | Bit field definition of STATUS register bits.

Description:
UNION of UINT16 and a Structure used to access and store PCI
COMMAND REGISTER values.


PCIE2_DATA in the PciBus.h

Variable : PCIE2_DATA

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
PcieOffs | UINT16 | Offset in Standard PCI Configuration Space of the PCI Express Capability header
DeviceCap | PCIE_DEV_CAP2_REG | Contents of PCI Express Device Capability 2 Register
LinkCap | PCIE_LNK_CAP2_REG | Contents of PCI Express Link Capability 2 Register
SlotCap | PCIE_SLT_CAP2_REG | Contents of PCI Express Slot Capability 2 Register
*Owner | PCI_DEV_INFO | Pointer to Device Private data Structure of the Device who owns this structure.

Description:
This Structure used to store Device's PCI Express Gen2 Specific Data.
Notes:
See PCIE.h for details on PCIE_PCIE_CAP_REG, PCIE_DEV_CAP_REG,
    PCIE_LNK_CAP_REG, PCIE_SLT_CAP_REG;
    See AmiDxeLib.h for details on T_ITEM_LIST;


PCIE_DATA in the PciBus.h

Variable : PCIE_DATA

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
PcieOffs | UINT16 | Offset in Standard PCI Configuration Space of the PCI Express Capability header
PcieCap | PCIE_PCIE_CAP_REG | Contents of PCI Express Capability Register
DeviceCap | PCIE_DEV_CAP_REG | Contents of PCI Express Device Capability Register
LinkCap | PCIE_LNK_CAP_REG | Contents of PCI Express Link Capability Register
SlotCap | PCIE_SLT_CAP_REG | Contents of PCI Express Slot Capability Register
CommonClk | BOOLEAN | Flag to record Device's Link Clock Configuration
ClockSet | BOOLEAN | Flag to mark PCI Express Initialization Process steps
PayloadSet | BOOLEAN | Flag to mark PCI Express Initialization Process steps
AspmSet | BOOLEAN | Flag to mark PCI Express Initialization Process steps
*VcData | VC_DATA | Pointer to Device's Virtual Channel Data Structure
*Owner | PCI_DEV_INFO | Pointer to Device Private data Structure of the Device who owns this structure.

Description:
This Structure used to store Device's PCI Express Specific Data.
Notes:
See PCIE.h for details on PCIE_PCIE_CAP_REG, PCIE_DEV_CAP_REG,
    PCIE_LNK_CAP_REG, PCIE_SLT_CAP_REG;
    See AmiDxeLib.h for details on T_ITEM_LIST;


PCIE_EXT_DATA_HDR in the PciBus.h

Variable : PCIE_EXT_DATA_HDR

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
VcResOffset | UINT16 | Offset in PCI Express Extanded Configuration Space of the Virtual Channel Resources header.
Reserved | UINT8 | 2 Reserved bytes to make structure 4 byte aligned.
VcResCap | PCIE_VC_RESCAP_REG | Contents of Virtual Channel Capability Register.

Description:
This Structure used to store PCI Express Device's Extended
Data Structure Header. It is the same for all data types.
Notes:
See PCIE.h for details on PCIE_VC_RESCAP_REG.


PCIX_DATA in the PciBus.h

Variable : PCIX_DATA

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
PcixOffs | UINT16 | Offset in Standard PCI Configuration Space of the PCI-X Capability header
PcixDevStatus | PCIX_DEV_STA_REG | Contents of PCI-X Device Status Register
PcixSecStatus | PCIX_SEC_STA_REG | Contents of PCI-X Device Secondary Status Register
*Owner | PCI_DEV_INFO | Pointer to Device Private data Structure of the Device who owns this structure.

Description:
This Structure used to store Device's PCI-X Specific Data.
Notes:
See PCIX.h for details on PCIX_DEV_STA_REG, PCIX_SEC_STA_REG;


RES_CONV_TYPE in the PciBus.h

Variable : RES_CONV_TYPE

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
rcNone | ENUM | Device doesn't supports any width of IO, MMIO, or PF MMIO.
rcOneOf | ENUM | If Device has any "wide" addressing resources it must considered as "narrow" if any "narrow" resources also present. (I.e. if Device has Mmio64pf and Mmio32pf on the same bridge - consider Mmio64pf resources as Mmio32pf. However if Device doesn't have any 32bit resources but only 64bit, 64bit resources for the bridge will be considered).
rcNarrow | ENUM | Device doesn't supports "wide" resources. So if Device has any Io32 or Mmio64, it must be addressed as Io16 and Mmio32 resources correspondently.
rcBoth | ENUM | Device has facilities to support both type of resources "wide" and "narrow" at the same time (i.e. Io16 is supported as well as Io32).

Description:
This ENUM used to identify PCI Device Resource Conversion Type
Notes:
Standard P2P bridge supports 16 or 32 bit IO(rcOneOf) only 32
    bit MMIO(rcNarrow) and One Of PF MMIO either 64 or 32 bit (rcOneOf).


VC_DATA in the PciBus.h

Variable : VC_DATA

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
VcResOffset | UINT16 | Offset in extanded PCI Express Extanded Configuration Space of the Virtual Channel Capability header
Reserved | UINT8 | 2 Reserved bytes to make structure 4 byte aligned
VcCap1 | PCIE_PORTVC_CAP_REG1 | Contents of Virtual Channel Port Capability Register 1
VcCap2 | PCIE_PORTVC_CAP_REG2 | Contents of Virtual Channel Port Capability Register 2
InitCnt | UINTN | to make this and 2 following fields look like T_ITEM_LIST
VcCount | UINTN | Number of VC resource Headers found in this Device
**VcResData | VC_RES_DATA | Pointer on Array of "VcCount" pointers on the Devices VC_RES_DATA structure.

Description:
This Structure used to store PCI Express Device's Virtual Channel Data.
Notes:
See PCIE.h for details on PCIE_PORTVC_CAP_REG1, PCIE_PORTVC_CAP_REG2.
    See AmiDxeLib.h for details on T_ITEM_LIST;


VC_RES_DATA in the PciBus.h

Variable : VC_RES_DATA

File: PciBus.h
Fields:

Name | Type | Description
Name | Type | Description
VcResOffset | UINT16 | Offset in PCI Express Extanded Configuration Space of the Virtual Channel Resources header.
Reserved | UINT8 | 2 Reserved bytes to make structure 4 byte aligned.
VcResCap | PCIE_VC_RESCAP_REG | Contents of Virtual Channel Capability Register.

Description:
This Structure used to store PCI Express Device's Virtual
Channel Resource Data.
Notes:
See PCIE.h for details on PCIE_VC_RESCAP_REG.


PciBus.mak

Description:
Make file to build PciBus Driver


PciBus.sd

Description:
PCI/PCIExpress/PCIX settings


PciBusEx.h

Description:
Defines PciBus Extended protocol Interface to provide
additional PCI Bus related functions.


PciBusSetup.c

Description:
Pci Bus Setup Routines

NOTE: Use this hook to dynamically change PCI BUS Driver Setup screen
Strings.

The following functions are used in the file: PciBusSetup.c.

Function | Description
InitBoardStrings | This function initializes the board related setup option values


InitBoardStrings in the PciBusSetup.c

Function : InitBoardStrings

File: PciBusSetup.c
Description:
This function initializes the board related setup option values
Input:
HiiHandle	Handle to HII database
        Class		Indicates the setup class
Output:
None


PCIE30.h

Description:
PCI-E 3.0/3.x Declarations.


PciHostBridge.h

The following data structures are used in the file: PciHostBridge.h.

Variable | Description
EFI_PCI_CFG_ADDRESS | Macro defining PCI Config Spase access UCING PCI Express Base
HPC_LOCATION_DATA | Private HostBridge Data Structure. It holds all information related to HPC and HPB Location in the System.
PCI_HOST_BRG_DATA | Private HostBridge Data Structure. This is the Starting point for PCI Subsystem.
PCI_HPC_DATA | Private HostBridge Data Structure. It holds all Hot Plug related Information. Used to Produce EFI_PCI_HOT_PLUG_INIT_PROTOCOL.
PCI_ROOT_BRG_DATA | Private RootBridge Data Structure
PCI_ROOT_BRIDGE_MAPPING | Structure used to specify RootBridge Specific Mapping Information for DMA transfere.


EFI_PCI_CFG_ADDRESS in the PciHostBridge.h

Variable : EFI_PCI_CFG_ADDRESS

File: PciHostBridge.h
Description:
Macro defining PCI Config Spase access UCING PCI Express Base
Notes:


HPC_LOCATION_DATA in the PciHostBridge.h

Variable : HPC_LOCATION_DATA

File: PciHostBridge.h
Fields:

Name | Type | Description
Name | Type | Description
HpcLocation | EFI_HPC_LOCATION | HPC Location Information in terms of Device Path.
Owner | *PCI_HOST_BRG_DATA | Back Pointer to Locate this Data structure Owner.
SlotHdr | PCI_BUS_XLAT_HDR | AMI SDL Generated SLOT Bus Xlat Information (AmiBoardInfoProtocol).
Padding | UINTN64 | Array, holding Padding Information for particular Resource type.

Description:
Private HostBridge Data Structure. It holds all information
related to HPC and HPB Location in the System.


PCI_HOST_BRG_DATA in the PciHostBridge.h

Variable : PCI_HOST_BRG_DATA

File: PciHostBridge.h
Fields:

Name | Type | Description
Name | Type | Description
ResAllocProtocol | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL | This PCI Host Bridge Resource Allocation Protocol Instance.
HbHandle | EFI_HANDLE | This PCI Host Bridge EFI_HANDLE.
RbInitCnt | UINTN | To make this and following 2 fields look like T_ITEM_LIST type.
RootBridgeCount | UINTN | Number of PCI_ROOT_BRG_DATA structures (Root Bridges) this host will group.
RootBridges | **PCI_ROOT_BRG_DATA | Pointer to the array of pointers at the private PCI Root Bridge Data Structure.
AllocPhase | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE | Current Phase of PCI Bus Enumeration.
AllocAttrib | UINT64 | This PCI Host Bridge Allocation Attributes.
EnumStarted | BOOLEAN | Flag to indicate that PCI Bus Enumeration has started.
Reserved | 3 | ] UINT8 Reserved fields to make this structure end at 4 byte alignment.

Description:
Private HostBridge Data Structure. This is the Starting
point for PCI Subsystem.


PCI_HPC_DATA in the PciHostBridge.h

Variable : PCI_HPC_DATA

File: PciHostBridge.h
Fields:

Name | Type | Description
Name | Type | Description
RootHotplugProtocol | EFI_PCI_HOT_PLUG_INIT_PROTOCOL | This PCI Root Hot Plug Controller Initialization Protocol Instance.
HbHandle | EFI_HANDLE | This PCI Host Bridge EFI_HANDLE.
HpclInitCnt | UINTN | To make this and following 2 fields look like T_ITEM_LIST type.
HpcLocCount | UINTN | Number of Root Bridges Hot Plug Location Data Structures Associated with THIS HOST.
HpcLocData | **HPC_LOCATION_DATA | Pointer to the array of pointers at the private PCI Hot Plug Controller Location Data.
Owner | *PCI_HOST_BRG_DATA | Back Pointer to Locate this Data structure Owner.

Description:
Private HostBridge Data Structure. It holds all Hot Plug
related Information. Used to Produce EFI_PCI_HOT_PLUG_INIT_PROTOCOL.


PCI_ROOT_BRG_DATA in the PciHostBridge.h

Variable : PCI_ROOT_BRG_DATA

File: PciHostBridge.h
Fields:

Name | Type | Description
Name | Type | Description
RbIoProtocol | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL | This PCI Root Bridge IO Protocol Instance.
RbHandle | EFI_HANDLE | This PCI Root Bridge EFI_HANDLE.
DevPath | *EFI_DEVICE_PATH_PROTOCOL | This PCI Root Bridge Device Path Protocol instance.
Owner | *PCI_HOST_BRG_DATA | Pointer on the Host Bridge Private Data Structure who owns this Root Bridge.
DevIoProtocol | *EFI_DEVICE_IO_INTERFACE | This PCI Root Bridge Device IO Protocol instance.
Supports | UINT64 | Set of Attirbutes Supported by this PCI Root Bridge.
Attributes | UINT64 | Set of currently supported Attirbutes by this PCI Root Bridge.
ResInitCnt | UINTN | To make this and following 2 fields look like T_ITEM_LIST type.
ResCount | UINTN | Number of ACPI QWord Resource descriptors of this PCI Root Bridge.
RbRes | **ASLR_QWORD_ASD | Pointer to the array of pointers at the resource descriptors of this PCI Root Bridge.
Mapping | *PCI_ROOT_BRIDGE_MAPPING | When Mapping is set this pointer points on Private RB Mapping Structure.
BusesSet | BOOLEAN | Flag to indicate that Bus Allocation Phase is over.
ResSubmited | BOOLEAN | Flag to indicate that Resources were submited by the PciBus Driver.
ResAsquired | BOOLEAN | Flag to indicate that Resource request was sutisfied by the GCD.
Reserved | UINT8 | Reserved field to make this structure end at 4 byte alignment.
BusXlatEntry | *PCI_BUS_XLAT_HDR | Pointer at AMI SDL Generated Bus Translate table corresponded to THIS Root Bridge.
RbAslName | *CHAR8 | Pointer to the String of THIS Root Bridge Device in ACPI Name Space.
AcpiRbRes | ACPI_RES_DATA | Array holding THIS Root Bridge Resource Information for ACPI

Description:
Private RootBridge Data Structure


PCI_ROOT_BRIDGE_MAPPING in the PciHostBridge.h

Variable : PCI_ROOT_BRIDGE_MAPPING

File: PciHostBridge.h
Fields:

Name | Type | Description
Name | Type | Description
Operation | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION | PciRoot Bridge IO Operation Description.
NumBytes | UINTN | Number Of Bytes in Mapping Buffer.
HostAddr | EFI_PHYSICAL_ADDRESS | Buffer Address of the device who initiated BM transfere.
DeviceAddr | EFI_PHYSICAL_ADDRESS | Buffer Address of the device who receives BM transfere.

Description:
Structure used to specify RootBridge Specific Mapping
Information for DMA transfere.


PciPort.c

Description:
PCI porting

The following functions are used in the file: PciPort.c.

Function | Description
BrdGetPciSetupData | Porting function which collects all PCI Bus Driver specific SETUP configuration data and returns it to the PCI Bus Driver.
PciPortSkipThisDevice | Porting function which collects all Pci Specific configuration data return it to the PCI Bus Driver.

The following data structures are used in the file: PciPort.c.

Variable | Description
FixedBusAssign | Variable to replace PCI_FIXED_BUS_ASSIGNMENT token.
HotPlugSupport | Variable to replace HOTPLUG_SUPPORT token.
NbDmiAspmSupport | Variable to replace NB_DMI_ASPM_SUPPORT token.
NbDmiL0ExitLatency | Variable to replace NB_DMI_L0_EXIT_LATENCY token.
NbDmiL1ExitLatency | Variable to replace NB_DMI_L1_EXIT_LATENCY token.
PciExpressSupport | Variable to replace PCI_EXPRESS_SUPPORT token.
PciXSupport | Variable to replace PCI_X_SUPPORT token.
S3VideoRepost | Variable to replace S3_VIDEO_REPOST_SUPPORT token.
SbDmiAspmSupport | Variable to replace SB_DMI_ASPM_SUPPORT token.
SbDmiL0ExitLatency | Variable to replace SB_DMI_L0_EXIT_LATENCY token.
SbDmiL1ExitLatency | Variable to replace SB_DMI_L1_EXIT_LATENCY token.
SbInternalDelay | Variable to replace SB_INTERNAL_DELAY token.
ScanFullBusRange | Variable to replace PCI_SCAN_FULL_BUS_RANGE token.
SriovSupport | Variable to replace SRIOV_SUPPORT token.
Use4KBar | Variable to replace PCI_4K_RESOURCE_ALIGNMENT token.


BrdGetPciSetupData in the PciPort.c

Function : BrdGetPciSetupData

File: PciPort.c
Description:
Porting function which collects all PCI Bus Driver specific
SETUP configuration data and returns it to the PCI Bus Driver.
Input:
PCI_SETUP_DATA*   PciSetupData  Pointer to the Pci Bus specific setup data buffer.
Output:
Nothing


FixedBusAssign in the PciPort.c

Variable : FixedBusAssign

File: PciPort.c
Description:
Variable to replace PCI_FIXED_BUS_ASSIGNMENT token.
Notes:
const BOOLEAN


HotPlugSupport in the PciPort.c

Variable : HotPlugSupport

File: PciPort.c
Description:
Variable to replace HOTPLUG_SUPPORT token.
Notes:
const BOOLEAN


NbDmiAspmSupport in the PciPort.c

Variable : NbDmiAspmSupport

File: PciPort.c
Description:
Variable to replace NB_DMI_ASPM_SUPPORT token.
Notes:
const UINT16


NbDmiL0ExitLatency in the PciPort.c

Variable : NbDmiL0ExitLatency

File: PciPort.c
Description:
Variable to replace NB_DMI_L0_EXIT_LATENCY token.
Notes:
const UINT16


NbDmiL1ExitLatency in the PciPort.c

Variable : NbDmiL1ExitLatency

File: PciPort.c
Description:
Variable to replace NB_DMI_L1_EXIT_LATENCY token.
Notes:
const UINT16


PciExpressSupport in the PciPort.c

Variable : PciExpressSupport

File: PciPort.c
Description:
Variable to replace PCI_EXPRESS_SUPPORT token.
Notes:
const BOOLEAN


PciPortSkipThisDevice in the PciPort.c

Function : PciPortSkipThisDevice

File: PciPort.c
Description:
Porting function which collects all Pci Specific configuration
data return it to the PCI Bus Driver.
Input:
PCI_DEV_INFO    *Device   Pointer to the Pci Bus Driver Private data buffer.
Output:
EFI_STATUS
EFI_SUCCESS     - SKIP this device, do not touch PCI Command register.
EFI_UNSUPPORTED - DON'T SKIP this device do complete enumeration as usual.

NOTE:
If device decodes or requires some resources to function properely,
allocating and and reporting this reaources to GCD is a total responsibility
of this hook. If this FUNCTION RETURNS EFI_SUCCESS PciBus Driver assumes that
RESOURCES ARE ALLOCATED AND REPORTED TO THE GCD DXE SERVICES.
Reporting resources to GCD Services is important to avoid same resource range
been allocated twice.
If device you want to skip is PCI2PCI or PCI2CRD bus bridge 1 bus will be allocated


PciXSupport in the PciPort.c

Variable : PciXSupport

File: PciPort.c
Description:
Variable to replace PCI_X_SUPPORT token.
Notes:
const BOOLEAN


S3VideoRepost in the PciPort.c

Variable : S3VideoRepost

File: PciPort.c
Description:
Variable to replace S3_VIDEO_REPOST_SUPPORT token.
Notes:
const BOOLEAN


SbDmiAspmSupport in the PciPort.c

Variable : SbDmiAspmSupport

File: PciPort.c
Description:
Variable to replace SB_DMI_ASPM_SUPPORT token.
Notes:
const UINT16


SbDmiL0ExitLatency in the PciPort.c

Variable : SbDmiL0ExitLatency

File: PciPort.c
Description:
Variable to replace SB_DMI_L0_EXIT_LATENCY token.
Notes:
const UINT16


SbDmiL1ExitLatency in the PciPort.c

Variable : SbDmiL1ExitLatency

File: PciPort.c
Description:
Variable to replace SB_DMI_L1_EXIT_LATENCY token.
Notes:
const UINT16


SbInternalDelay in the PciPort.c

Variable : SbInternalDelay

File: PciPort.c
Description:
Variable to replace SB_INTERNAL_DELAY token.
Notes:
const UINT16


ScanFullBusRange in the PciPort.c

Variable : ScanFullBusRange

File: PciPort.c
Description:
Variable to replace PCI_SCAN_FULL_BUS_RANGE token.
Notes:
const BOOLEAN
This option exists for testing purposes. If System will have additional
PCI devices which don't have tree strucuture it might be Pci Device Path
conflict


SriovSupport in the PciPort.c

Variable : SriovSupport

File: PciPort.c
Description:
Variable to replace SRIOV_SUPPORT token.
Notes:
const BOOLEAN


Use4KBar in the PciPort.c

Variable : Use4KBar

File: PciPort.c
Description:
Variable to replace PCI_4K_RESOURCE_ALIGNMENT token.
Notes:
const BOOLEAN


PciRootBridge.dxs

Description:


PciSetup.h

Description:


Functions in Alphabetical Order

In Alphabetical Order

The following topics provide a list in alphabetical order.
For a list by file name, see By File Name.

  • B
  • E
  • F
  • H
  • I
  • M
  • N
  • P
  • R
  • S
  • U
  • V


Functions in Alphabetical Order

B

Function | Description
BrdGetPciSetupData | Porting function which collects all PCI Bus Driver specific SETUP configuration data and returns it to the PCI Bus Driver.

Data Structure | Description
BRG_ALIGN_INFO | This Structure used to store information about PCI Bridge alignment requirements since behind the bridge could be more than one device.

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Functions in Alphabetical Order

E

Data Structure | Description
EFI_PCI_CFG_ADDRESS | Macro defining PCI Config Spase access UCING PCI Express Base

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Functions in Alphabetical Order

F

Data Structure | Description
FixedBusAssign | Variable to replace PCI_FIXED_BUS_ASSIGNMENT token.

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Functions in Alphabetical Order

H

Data Structure | Description
HotPlugSupport | Variable to replace HOTPLUG_SUPPORT token.
HPC_LOCATION_DATA | Private HostBridge Data Structure. It holds all information related to HPC and HPB Location in the System.

Built on 17:56:10 12/16/11


Functions in Alphabetical Order

I

Function | Description
InitBoardStrings | This function initializes the board related setup option values

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Functions in Alphabetical Order

M

Data Structure | Description
MBRG_RES_DSC | Structure used to access and store PCI Device Resource Requirements in a form of QWORD ACPI Resource Descriptor.
MRES_TYPE | This ENUM value definitions used to identify PCI Device different Resource types.

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Functions in Alphabetical Order

N

Data Structure | Description
NbDmiAspmSupport | Variable to replace NB_DMI_ASPM_SUPPORT token.
NbDmiL0ExitLatency | Variable to replace NB_DMI_L0_EXIT_LATENCY token.
NbDmiL1ExitLatency | Variable to replace NB_DMI_L1_EXIT_LATENCY token.

Built on 17:56:10 12/16/11


Functions in Alphabetical Order

P

Function | Description
PciPortSkipThisDevice | Porting function which collects all Pci Specific configuration data return it to the PCI Bus Driver.

Data Structure | Description
PCI_BAD_BAR | This structure used to identify Incapable PCI Devices which has some BAR irregularity.
PCI_BAR | This Structure used to store information about PCI Device Base Address Register (BAR)
PCI_BAR_TYPE | This ENUM value used to identify PCI Device different BAR types.
PCI_BRG_CNT_REG | UNION of UINT16 and a Structure used to access and store PCI COMMAND REGISTER values.
PCI_BRG_EXT | PCI Bridge Extended Data Structure. This Structure used to store Hosts and PCI to PCI Bridges additional data. It must follow exactly after the PCI_DEV_INFO data structure of the device identified as a Bridge.
PCI_BRG_INFO | PCI Bridge Private Data Structure.
PCI_BUS_OVERRIDE_DATA | This Structure used to store information about PCI Device's EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL Instance, if any.
PCI_CFG_ADDR | UNION of UINT64 and a Structure used to access and store PCI Device Address.
PCI_CMD_REG | UNION of UINT16 and a Structure used to access and store PCI COMMAND REGISTER values.
PCI_DEV_CLASS | UNION of UINT32 and a Structure used to access and store PCI Device BaseClass, SubClass, ProgrammingInterface and RevisionId values.
PCI_DEV_ID | UNION of UINT32 and a Structure used to access and store PCI Device VendorId and DeviceId values.
PCI_DEV_INFO | This Structure is the main data structure associated with the PCI Device. It holds all device specific data and references all other data srtuctures defined in "PciBus.h".
PCI_DEVICE_TYPE | This ENUM definition used to identify PCI Device different BAR types
PCI_HOST_BRG_DATA | Private HostBridge Data Structure. This is the Starting point for PCI Subsystem.
PCI_HOST_INFO | Root Srtucture of the PCI Subsystem.
PCI_HPC_DATA | Private HostBridge Data Structure. It holds all Hot Plug related Information. Used to Produce EFI_PCI_HOT_PLUG_INIT_PROTOCOL.
PCI_INCOMPATIBILITY_TYPE | ENUM used to specify PCI Device Incompatibility Type for Device that doesn't comply with defined in PCI Spec enumeration algorithm.
PCI_ROOT_BRG_DATA | Private RootBridge Data Structure
PCI_ROOT_BRIDGE_MAPPING | Structure used to specify RootBridge Specific Mapping Information for DMA transfere.
PCI_SPACE_TYPE | This ENUM value definitions used to identify PCI Device's different Space types.
PCI_STA_REG | UNION of UINT16 and a Structure used to access and store PCI COMMAND REGISTER values.
PCIE2_DATA | This Structure used to store Device's PCI Express Gen2 Specific Data.
PCIE_DATA | This Structure used to store Device's PCI Express Specific Data.
PCIE_EXT_DATA_HDR | This Structure used to store PCI Express Device's Extended Data Structure Header. It is the same for all data types.
PciExpressSupport | Variable to replace PCI_EXPRESS_SUPPORT token.
PCIX_DATA | This Structure used to store Device's PCI-X Specific Data.
PciXSupport | Variable to replace PCI_X_SUPPORT token.


Functions in Alphabetical Order

R

Data Structure | Description
RES_CONV_TYPE | This ENUM used to identify PCI Device Resource Conversion Type


Functions in Alphabetical Order

S

Data Structure | Description
S3VideoRepost | Variable to replace S3_VIDEO_REPOST_SUPPORT token.
SbDmiAspmSupport | Variable to replace SB_DMI_ASPM_SUPPORT token.
SbDmiL0ExitLatency | Variable to replace SB_DMI_L0_EXIT_LATENCY token.
SbDmiL1ExitLatency | Variable to replace SB_DMI_L1_EXIT_LATENCY token.
SbInternalDelay | Variable to replace SB_INTERNAL_DELAY token.
ScanFullBusRange | Variable to replace PCI_SCAN_FULL_BUS_RANGE token.
SriovSupport | Variable to replace SRIOV_SUPPORT token.


Functions in Alphabetical Order

U

Data Structure | Description
Use4KBar | Variable to replace PCI_4K_RESOURCE_ALIGNMENT token.


Functions in Alphabetical Order

V

Data Structure | Description
VC_DATA | This Structure used to store PCI Express Device's Virtual Channel Data.
VC_RES_DATA | This Structure used to store PCI Express Device's Virtual Channel Resource Data.


General Information


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