/*++ This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement --*/ /*++ Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Module Name: Dmar.act Abstract: This file describes the contents of the ACPI DMA address Remapping --*/ #include "Dmar.h" EFI_ACPI_DMAR_TABLE DmarTable = { EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE, sizeof (EFI_ACPI_DMAR_TABLE), EFI_ACPI_DMAR_TABLE_REVISION, // // Checksum will be updated at runtime // 0x00, // // It is expected that these values will be programmed at runtime // 'I', 'N', 'T', 'E', 'L', ' ', EFI_ACPI_DMAR_OEM_TABLE_ID, 0x1, EFI_ACPI_DMAR_OEM_CREATOR_ID, 1, // // DMAR table specific entries below: // // // 39-bit addressing Host Address Width // 38, // // Flags // 0, // // Reserved fields // 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // // First DRHD structure, VT-d Engine #1 // { 0, // Type = 0 (DRHD) sizeof (EFI_ACPI_DRHD_ENGINE1_STRUCT), // Length of structure 0, // Flag - Do not include all - bugbug - not clear what this means 0, // Reserved fields 0, // Segment 0x00000000, // Base address of DMA-remapping hardware - Updated at boot time // // Device Scopes // { 1, // Type sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Segment number 0, // Reserved 0, // Start bus number {2, 0} // PCI path } }, //Second DRHD structure VT-d Engine# 2 { 0, // Type = 0 (DRHD) sizeof(EFI_ACPI_DRHD_ENGINE2_STRUCT), // Length of strucure. 1, // Flag - Include all 0, // Reserved 0, // Segment Number 0x00000000, // Base address of DMA-remapping hardware. { // // Device Scopes // { 3, // Type=IO APIC sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 2, // Enumeration ID 0xF0, // Start bus number {31, 0} // PCI path }, // // Device Scopes // { 4, // Type=HPET sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 0, // Enumeration ID 0xF0, // Start bus number {15, 0} // PCI path } , // // Device Scopes - I2C0 // { 5, // Type=ACPI_NAMESPACE_DEVICE sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 1, // Enumeration ID 0, // Start bus number {21, 1} // PCI path }, // // Device Scopes - I2C1 // { 5, // Type=ACPI_NAMESPACE_DEVICE sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 2, // Enumeration ID 0, // Start bus number {21, 2} // PCI path }, // // Device Scopes - SPI0 // { 5, // Type=ACPI_NAMESPACE_DEVICE sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 3, // Enumeration ID 0, // Start bus number {21, 3} // PCI path }, // // Device Scopes - SPI1 // { 5, // Type=ACPI_NAMESPACE_DEVICE sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 4, // Enumeration ID 0, // Start bus number {21, 4} // PCI path }, // // Device Scopes - UART0 // { 5, // Type=ACPI_NAMESPACE_DEVICE sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 5, // Enumeration ID 0, // Start bus number {21, 5} // PCI path }, // // Device Scopes - UART1 // { 5, // Type=ACPI_NAMESPACE_DEVICE sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 6, // Enumeration ID 0, // Start bus number {21, 6} // PCI path }, // // Device Scopes - SDIO // { 5, // Type=ACPI_NAMESPACE_DEVICE sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 7, // Enumeration ID 0, // Start bus number {23, 0} // PCI path } } }, //RMRR structure for USB devices. { 0x1, // Type 1 - RMRR structure sizeof(EFI_ACPI_RMRR_USB_STRUC), // Length 0x0000, // Reserved 0x0000, // Segment Num 0x00000000000E0000, // RMRR Base address - Updated in runtime. 0x00000000000EFFFF, // RMRR Limit address - Updated in runtime. { { 1, // Type sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 0, // Enum ID 0, // Start bus number {29, 0} // PCI path }, { 1, // Type sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 0, // Enum ID 0, // Start bus number {26, 0} // PCI path }, { 1, // Type sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 0, // Enum ID 0, // Start bus number {20, 0} // PCI path } } }, //RMRR structure for IGD device. { 1, // Type 1 - RMRR structure sizeof(EFI_ACPI_RMRR_IGD_STRUC), // Length 0x0000, // Reserved 0x0000, // Segment Num 0x0000000000000000, // RMRR Base address - Updated in runtime. 0x0000000000000000, // RMRR Limit address - Updated in runtime. { { 1, // Type sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length 0, // Reserved 0, // Enum ID 0, // Start bus number {2, 0} // PCI path } } } , // ANDD structure. { 4, // Type 4 - ANDD structure sizeof(EFI_ACPI_ANDD_STRUC), // Length 0, 0, 0, // Reserved [3] 1, "\\_SB.PCI0.I2C0" }, // ANDD structure. { 4, // Type 4 - ANDD structure sizeof(EFI_ACPI_ANDD_STRUC), // Length 0, 0, 0, // Reserved [3] 2, "\\_SB.PCI0.I2C1" }, // ANDD structure. { 4, // Type 4 - ANDD structure sizeof(EFI_ACPI_ANDD_STRUC), // Length 0, 0, 0, // Reserved [3] 3, "\\_SB.PCI0.SPI0" }, // ANDD structure. { 4, // Type 4 - ANDD structure sizeof(EFI_ACPI_ANDD_STRUC), // Length 0, 0, 0, // Reserved [3] 4, "\\_SB.PCI0.SPI1" }, // ANDD structure. { 4, // Type 4 - ANDD structure sizeof(EFI_ACPI_ANDD_STRUC), // Length 0, 0, 0, // Reserved [3] 5, "\\_SB.PCI0.UA00" }, // ANDD structure. { 4, // Type 4 - ANDD structure sizeof(EFI_ACPI_ANDD_STRUC), // Length 0, 0, 0, // Reserved [3] 6, "\\_SB.PCI0.UA01" }, // ANDD structure. { 4, // Type 4 - ANDD structure sizeof(EFI_ACPI_ANDD_STRUC), // Length 0, 0, 0, // Reserved [3] 7, "\\_SB.PCI0.SDHC" } }; // // Dummy function required for build tools // int main ( VOID ) { return 0; }