/** @file This file was automatically generated. Modify at your own risk. @copyright Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement **/ #ifndef __McIoData_h__ #define __McIoData_h__ #pragma pack(push, 1) #include "MrcTypes.h" typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_DDRCRVREFCONTROL_STRUCT; typedef union { struct { U32 VssHiCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_DDRCRVSSHICONTROL_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH0_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATACH1_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH0_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA0CH1_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH0_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA1CH1_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH0_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA2CH1_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH0_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA3CH1_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH0_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA4CH1_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH0_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA5CH1_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH0_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA6CH1_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH0_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_DDRCRVREFCONTROL_STRUCT; typedef union { struct { U32 VssHiCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_DDRCRVSSHICONTROL_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA7CH1_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH0_CR_DDRCRVREFADJUST1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_RXTRAINRANK0_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_RXTRAINRANK1_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_RXTRAINRANK2_STRUCT; typedef union { struct { U32 RxRcvEnPi : 9; // Bits 8:0 U32 RxDqsPPi : 6; // Bits 14:9 U32 RxEq : 5; // Bits 19:15 U32 RxDqsNPi : 6; // Bits 25:20 U32 RxVref : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_RXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_RXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_RXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_RXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_RXPERBITRANK3_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_TXTRAINRANK0_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_TXTRAINRANK1_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_TXTRAINRANK2_STRUCT; typedef union { struct { U32 TxDqDelay : 9; // Bits 8:0 U32 TxDqsDelay : 9; // Bits 17:9 U32 Spare0 : 2; // Bits 19:18 U32 TxEqualization : 6; // Bits 25:20 U32 Spare1 : 6; // Bits 31:26 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_TXTRAINRANK3_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_TXPERBITRANK0_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_TXPERBITRANK1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_TXPERBITRANK2_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_TXPERBITRANK3_STRUCT; typedef union { struct { U32 RcompDrvUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompDrvDown : 6; // Bits 14:9 U32 VTComp : 5; // Bits 19:15 U32 TcoComp : 6; // Bits 25:20 U32 SlewRateComp : 5; // Bits 30:26 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_RCOMPDATA0_STRUCT; typedef union { struct { U32 RcompOdtUp : 6; // Bits 5:0 U32 Spare0 : 3; // Bits 8:6 U32 RcompOdtDown : 6; // Bits 14:9 U32 Spare1 : 1; // Bits 15:15 U32 PanicDrvDn : 6; // Bits 21:16 U32 PanicDrvUp : 6; // Bits 27:22 U32 LevelShifterComp : 3; // Bits 30:28 U32 Spare2 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_RCOMPDATA1_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_TXXTALK_STRUCT; typedef union { struct { U32 Lane0 : 4; // Bits 3:0 U32 Lane1 : 4; // Bits 7:4 U32 Lane2 : 4; // Bits 11:8 U32 Lane3 : 4; // Bits 15:12 U32 Lane4 : 4; // Bits 19:16 U32 Lane5 : 4; // Bits 23:20 U32 Lane6 : 4; // Bits 27:24 U32 Lane7 : 4; // Bits 31:28 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_RXOFFSETVDQ_STRUCT; typedef union { struct { U32 Spare : 32; // Bits 31:0 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_DDRDATARESERVED_STRUCT; typedef union { struct { U32 DataTrainFeedback : 9; // Bits 8:0 U32 Spare : 23; // Bits 31:9 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_DATATRAINFEEDBACK_STRUCT; typedef union { struct { U32 RunTest : 1; // Bits 0:0 U32 Load : 1; // Bits 1:1 U32 ModeHVM : 1; // Bits 2:2 U32 ModeDV : 1; // Bits 3:3 U32 ModeADC : 1; // Bits 4:4 U32 LoadCount : 10; // Bits 14:5 U32 CountStatus : 10; // Bits 24:15 U32 Spare : 7; // Bits 31:25 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_DLLPITESTANDADC_STRUCT; typedef union { struct { U32 DqDrvUpCompOffset : 6; // Bits 5:0 U32 DqDrvDownCompOffset : 6; // Bits 11:6 U32 DqOdtUpCompOffset : 5; // Bits 16:12 U32 DqOdtDownCompOffset : 5; // Bits 21:17 U32 DqTcoCompOffset : 5; // Bits 26:22 U32 DqSlewRateCompOffset : 5; // Bits 31:27 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_STRUCT; typedef union { struct { U32 RefPi : 4; // Bits 3:0 U32 DllMask : 2; // Bits 5:4 U32 DllWeakLock : 1; // Bits 6:6 U32 SdllSegmentDisable : 3; // Bits 9:7 U32 RxBiasCtl : 3; // Bits 12:10 U32 OdtDelay : 4; // Bits 16:13 U32 OdtDuration : 3; // Bits 19:17 U32 SenseAmpDelay : 4; // Bits 23:20 U32 SenseAmpDuration : 3; // Bits 26:24 U32 BurstEndODTDelay : 3; // Bits 29:27 U32 LpDdrLongOdtEn : 1; // Bits 30:30 U32 Rsvd1 : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_DDRCRDATACONTROL1_STRUCT; typedef union { struct { U32 RxStaggerCtl : 5; // Bits 4:0 U32 ForceBiasOn : 1; // Bits 5:5 U32 ForceRxOn : 1; // Bits 6:6 U32 LeakerComp : 2; // Bits 8:7 U32 RxDqsAmpOffset : 4; // Bits 12:9 U32 RxClkStgNum : 5; // Bits 17:13 U32 WlLongDelEn : 1; // Bits 18:18 U32 Spare : 13; // Bits 31:19 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_DDRCRDATACONTROL2_STRUCT; typedef union { struct { U32 VssHiOrVrefCtl : 24; // Bits 23:0 U32 OutputCode : 8; // Bits 31:24 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_STRUCT; typedef union { struct { U32 RcvEnOffset : 6; // Bits 5:0 U32 RxDqsOffset : 6; // Bits 11:6 U32 TxDqOffset : 6; // Bits 17:12 U32 TxDqsOffset : 6; // Bits 23:18 U32 VrefOffset : 7; // Bits 30:24 U32 Spare : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_STRUCT; typedef union { struct { U32 RxTrainingMode : 1; // Bits 0:0 U32 WLTrainingMode : 1; // Bits 1:1 U32 RLTrainingMode : 1; // Bits 2:2 U32 SenseampTrainingMode : 1; // Bits 3:3 U32 TxOn : 1; // Bits 4:4 U32 RfOn : 1; // Bits 5:5 U32 RxPiOn : 1; // Bits 6:6 U32 TxPiOn : 1; // Bits 7:7 U32 InternalClocksOn : 1; // Bits 8:8 U32 RepeaterClocksOn : 1; // Bits 9:9 U32 TxDisable : 1; // Bits 10:10 U32 RxDisable : 1; // Bits 11:11 U32 TxLong : 1; // Bits 12:12 U32 RxDqsCtle : 2; // Bits 14:13 U32 RxReadPointer : 3; // Bits 17:15 U32 DriverSegmentEnable : 1; // Bits 18:18 U32 DataVccddqHi : 1; // Bits 19:19 U32 ReadRFRd : 1; // Bits 20:20 U32 ReadRFWr : 1; // Bits 21:21 U32 ReadRFRank : 2; // Bits 23:22 U32 ForceOdtOn : 1; // Bits 24:24 U32 OdtSampOff : 1; // Bits 25:25 U32 DisableOdtStatic : 1; // Bits 26:26 U32 DdrCRForceODTOn : 1; // Bits 27:27 U32 LPDDR_Mode : 1; // Bits 28:28 U32 EnReadPreamble : 1; // Bits 29:29 U32 OdtSampExtendEn : 1; // Bits 30:30 U32 EarlyRleakEn : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_DDRCRDATACONTROL0_STRUCT; typedef union { struct { U32 CAVrefCtl : 7; // Bits 6:0 U32 Ch1VrefCtl : 7; // Bits 13:7 U32 Ch0VrefCtl : 7; // Bits 20:14 U32 EnDimmVrefCA : 1; // Bits 21:21 U32 EnDimmVrefCh1 : 1; // Bits 22:22 U32 EnDimmVrefCh0 : 1; // Bits 23:23 U32 HiZTimerCtrl : 2; // Bits 25:24 U32 VccddqHiQnnnH : 1; // Bits 26:26 U32 Rsvd : 2; // Bits 28:27 U32 caSlowBW : 1; // Bits 29:29 U32 ch0SlowBW : 1; // Bits 30:30 U32 ch1SlowBW : 1; // Bits 31:31 } Bits; U32 Data; U16 Data16[2]; U8 Data8[4]; } DDRDATA8CH1_CR_DDRCRVREFADJUST1_STRUCT; #define DDRDATA_CR_RXTRAINRANK0_REG (0x00003600) #define DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA_CR_RXTRAINRANK1_REG (0x00003604) #define DDRDATA_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA_CR_RXTRAINRANK2_REG (0x00003608) #define DDRDATA_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA_CR_RXTRAINRANK3_REG (0x0000360C) #define DDRDATA_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA_CR_RXPERBITRANK0_REG (0x00003610) #define DDRDATA_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK1_REG (0x00003614) #define DDRDATA_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK2_REG (0x00003618) #define DDRDATA_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK3_REG (0x0000361C) #define DDRDATA_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA_CR_TXTRAINRANK0_REG (0x00003620) #define DDRDATA_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA_CR_TXTRAINRANK1_REG (0x00003624) #define DDRDATA_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA_CR_TXTRAINRANK2_REG (0x00003628) #define DDRDATA_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA_CR_TXTRAINRANK3_REG (0x0000362C) #define DDRDATA_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA_CR_TXPERBITRANK0_REG (0x00003630) #define DDRDATA_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK1_REG (0x00003634) #define DDRDATA_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK2_REG (0x00003638) #define DDRDATA_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK3_REG (0x0000363C) #define DDRDATA_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA_CR_RCOMPDATA0_REG (0x00003640) #define DDRDATA_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA_CR_RCOMPDATA1_REG (0x00003644) #define DDRDATA_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA_CR_TXXTALK_REG (0x00003648) #define DDRDATA_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA_CR_RXOFFSETVDQ_REG (0x0000364C) #define DDRDATA_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA_CR_DDRDATARESERVED_REG (0x00003650) #define DDRDATA_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA_CR_DATATRAINFEEDBACK_REG (0x00003654) #define DDRDATA_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA_CR_DLLPITESTANDADC_REG (0x00003658) #define DDRDATA_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_REG (0x0000365C) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL1_REG (0x00003660) #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL2_REG (0x00003664) #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFCONTROL_REG (0x00003668) #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_OFF ( 0) #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_WID (24) #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_MSK (0x00FFFFFF) #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_MAX (0x00FFFFFF) #define DDRDATA_CR_DDRCRVREFCONTROL_VrefCtl_DEF (0x000E453A) #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_OFF (24) #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA_CR_DDRCRVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA_CR_DDRCRVSSHICONTROL_REG (0x0000366C) #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_OFF ( 0) #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_WID (24) #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_MSK (0x00FFFFFF) #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_MAX (0x00FFFFFF) #define DDRDATA_CR_DDRCRVSSHICONTROL_VssHiCtl_DEF (0x004D8238) #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_OFF (24) #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_WID ( 8) #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA_CR_DDRCRVSSHICONTROL_OutputCode_DEF (0x00000000) #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000366C) #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_REG (0x00003670) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_REG (0x00003674) #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFADJUST1_REG (0x00003678) #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATACH0_CR_RXTRAINRANK0_REG (0x00003000) #define DDRDATACH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATACH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATACH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATACH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATACH0_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATACH0_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATACH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATACH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATACH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATACH0_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATACH0_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATACH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATACH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATACH0_CR_RXTRAINRANK1_REG (0x00003004) #define DDRDATACH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATACH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATACH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATACH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATACH0_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATACH0_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATACH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATACH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATACH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATACH0_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATACH0_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATACH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATACH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATACH0_CR_RXTRAINRANK2_REG (0x00003008) #define DDRDATACH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATACH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATACH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATACH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATACH0_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATACH0_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATACH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATACH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATACH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATACH0_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATACH0_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATACH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATACH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATACH0_CR_RXTRAINRANK3_REG (0x0000300C) #define DDRDATACH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATACH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATACH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATACH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATACH0_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATACH0_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATACH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATACH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATACH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATACH0_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATACH0_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATACH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATACH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATACH0_CR_RXPERBITRANK0_REG (0x00003010) #define DDRDATACH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATACH0_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATACH0_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATACH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATACH0_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATACH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATACH0_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATACH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATACH0_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATACH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATACH0_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATACH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATACH0_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATACH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATACH0_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATACH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK1_REG (0x00003014) #define DDRDATACH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATACH0_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATACH0_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATACH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATACH0_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATACH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATACH0_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATACH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATACH0_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATACH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATACH0_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATACH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATACH0_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATACH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATACH0_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATACH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK2_REG (0x00003018) #define DDRDATACH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATACH0_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATACH0_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATACH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATACH0_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATACH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATACH0_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATACH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATACH0_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATACH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATACH0_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATACH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATACH0_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATACH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATACH0_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATACH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK3_REG (0x0000301C) #define DDRDATACH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATACH0_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATACH0_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATACH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATACH0_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATACH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATACH0_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATACH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATACH0_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATACH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATACH0_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATACH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATACH0_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATACH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATACH0_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATACH0_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATACH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATACH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATACH0_CR_TXTRAINRANK0_REG (0x00003020) #define DDRDATACH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATACH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATACH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATACH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATACH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATACH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATACH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATACH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATACH0_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATACH0_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATACH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATACH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATACH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATACH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATACH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATACH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATACH0_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATACH0_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATACH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATACH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATACH0_CR_TXTRAINRANK1_REG (0x00003024) #define DDRDATACH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATACH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATACH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATACH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATACH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATACH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATACH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATACH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATACH0_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATACH0_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATACH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATACH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATACH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATACH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATACH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATACH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATACH0_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATACH0_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATACH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATACH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATACH0_CR_TXTRAINRANK2_REG (0x00003028) #define DDRDATACH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATACH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATACH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATACH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATACH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATACH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATACH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATACH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATACH0_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATACH0_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATACH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATACH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATACH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATACH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATACH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATACH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATACH0_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATACH0_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATACH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATACH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATACH0_CR_TXTRAINRANK3_REG (0x0000302C) #define DDRDATACH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATACH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATACH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATACH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATACH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATACH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATACH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATACH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATACH0_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATACH0_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATACH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATACH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATACH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATACH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATACH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATACH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATACH0_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATACH0_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATACH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATACH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATACH0_CR_TXPERBITRANK0_REG (0x00003030) #define DDRDATACH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATACH0_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATACH0_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATACH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATACH0_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATACH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATACH0_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATACH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATACH0_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATACH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATACH0_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATACH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATACH0_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATACH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATACH0_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATACH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK1_REG (0x00003034) #define DDRDATACH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATACH0_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATACH0_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATACH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATACH0_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATACH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATACH0_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATACH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATACH0_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATACH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATACH0_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATACH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATACH0_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATACH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATACH0_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATACH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK2_REG (0x00003038) #define DDRDATACH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATACH0_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATACH0_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATACH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATACH0_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATACH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATACH0_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATACH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATACH0_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATACH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATACH0_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATACH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATACH0_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATACH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATACH0_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATACH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK3_REG (0x0000303C) #define DDRDATACH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATACH0_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATACH0_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATACH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATACH0_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATACH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATACH0_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATACH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATACH0_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATACH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATACH0_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATACH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATACH0_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATACH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATACH0_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATACH0_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATACH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATACH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATACH0_CR_RCOMPDATA0_REG (0x00003040) #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATACH0_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATACH0_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATACH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATACH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATACH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATACH0_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATACH0_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATACH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATACH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATACH0_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATACH0_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATACH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATACH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATACH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATACH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATACH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATACH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATACH0_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATACH0_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATACH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATACH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATACH0_CR_RCOMPDATA1_REG (0x00003044) #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATACH0_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATACH0_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATACH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATACH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATACH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATACH0_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATACH0_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATACH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATACH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATACH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATACH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATACH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATACH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATACH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATACH0_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATACH0_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATACH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATACH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATACH0_CR_TXXTALK_REG (0x00003048) #define DDRDATACH0_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATACH0_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATACH0_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATACH0_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATACH0_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATACH0_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATACH0_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATACH0_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATACH0_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATACH0_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATACH0_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATACH0_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATACH0_CR_TXXTALK_Lane3_OFF (12) #define DDRDATACH0_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATACH0_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATACH0_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATACH0_CR_TXXTALK_Lane4_OFF (16) #define DDRDATACH0_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATACH0_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATACH0_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATACH0_CR_TXXTALK_Lane5_OFF (20) #define DDRDATACH0_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATACH0_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATACH0_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATACH0_CR_TXXTALK_Lane6_OFF (24) #define DDRDATACH0_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATACH0_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATACH0_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATACH0_CR_TXXTALK_Lane7_OFF (28) #define DDRDATACH0_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATACH0_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATACH0_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATACH0_CR_RXOFFSETVDQ_REG (0x0000304C) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATACH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATACH0_CR_DDRDATARESERVED_REG (0x00003050) #define DDRDATACH0_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATACH0_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATACH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATACH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATACH0_CR_DATATRAINFEEDBACK_REG (0x00003054) #define DDRDATACH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATACH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATACH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATACH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATACH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATACH0_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATACH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATACH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATACH0_CR_DLLPITESTANDADC_REG (0x00003058) #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATACH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATACH0_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATACH0_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATACH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATACH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATACH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATACH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATACH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATACH0_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATACH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATACH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATACH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATACH0_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATACH0_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATACH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATACH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000305C) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATACH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_REG (0x00003060) #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATACH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATACH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATACH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATACH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATACH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL2_REG (0x00003064) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATACH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATACH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATACH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000306C) #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATACH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00003070) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_REG (0x00003074) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATACH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_REG (0x00003078) #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATACH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATACH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATACH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATACH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATACH1_CR_RXTRAINRANK0_REG (0x00003100) #define DDRDATACH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATACH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATACH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATACH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATACH1_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATACH1_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATACH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATACH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATACH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATACH1_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATACH1_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATACH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATACH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATACH1_CR_RXTRAINRANK1_REG (0x00003104) #define DDRDATACH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATACH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATACH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATACH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATACH1_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATACH1_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATACH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATACH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATACH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATACH1_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATACH1_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATACH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATACH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATACH1_CR_RXTRAINRANK2_REG (0x00003108) #define DDRDATACH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATACH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATACH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATACH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATACH1_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATACH1_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATACH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATACH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATACH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATACH1_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATACH1_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATACH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATACH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATACH1_CR_RXTRAINRANK3_REG (0x0000310C) #define DDRDATACH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATACH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATACH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATACH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATACH1_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATACH1_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATACH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATACH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATACH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATACH1_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATACH1_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATACH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATACH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATACH1_CR_RXPERBITRANK0_REG (0x00003110) #define DDRDATACH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATACH1_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATACH1_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATACH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATACH1_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATACH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATACH1_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATACH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATACH1_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATACH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATACH1_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATACH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATACH1_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATACH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATACH1_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATACH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK1_REG (0x00003114) #define DDRDATACH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATACH1_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATACH1_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATACH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATACH1_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATACH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATACH1_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATACH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATACH1_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATACH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATACH1_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATACH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATACH1_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATACH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATACH1_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATACH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK2_REG (0x00003118) #define DDRDATACH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATACH1_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATACH1_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATACH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATACH1_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATACH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATACH1_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATACH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATACH1_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATACH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATACH1_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATACH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATACH1_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATACH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATACH1_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATACH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK3_REG (0x0000311C) #define DDRDATACH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATACH1_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATACH1_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATACH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATACH1_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATACH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATACH1_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATACH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATACH1_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATACH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATACH1_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATACH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATACH1_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATACH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATACH1_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATACH1_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATACH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATACH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATACH1_CR_TXTRAINRANK0_REG (0x00003120) #define DDRDATACH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATACH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATACH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATACH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATACH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATACH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATACH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATACH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATACH1_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATACH1_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATACH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATACH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATACH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATACH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATACH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATACH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATACH1_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATACH1_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATACH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATACH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATACH1_CR_TXTRAINRANK1_REG (0x00003124) #define DDRDATACH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATACH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATACH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATACH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATACH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATACH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATACH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATACH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATACH1_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATACH1_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATACH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATACH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATACH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATACH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATACH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATACH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATACH1_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATACH1_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATACH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATACH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATACH1_CR_TXTRAINRANK2_REG (0x00003128) #define DDRDATACH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATACH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATACH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATACH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATACH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATACH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATACH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATACH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATACH1_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATACH1_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATACH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATACH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATACH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATACH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATACH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATACH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATACH1_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATACH1_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATACH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATACH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATACH1_CR_TXTRAINRANK3_REG (0x0000312C) #define DDRDATACH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATACH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATACH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATACH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATACH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATACH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATACH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATACH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATACH1_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATACH1_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATACH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATACH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATACH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATACH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATACH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATACH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATACH1_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATACH1_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATACH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATACH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATACH1_CR_TXPERBITRANK0_REG (0x00003130) #define DDRDATACH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATACH1_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATACH1_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATACH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATACH1_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATACH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATACH1_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATACH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATACH1_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATACH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATACH1_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATACH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATACH1_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATACH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATACH1_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATACH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK1_REG (0x00003134) #define DDRDATACH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATACH1_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATACH1_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATACH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATACH1_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATACH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATACH1_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATACH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATACH1_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATACH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATACH1_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATACH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATACH1_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATACH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATACH1_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATACH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK2_REG (0x00003138) #define DDRDATACH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATACH1_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATACH1_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATACH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATACH1_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATACH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATACH1_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATACH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATACH1_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATACH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATACH1_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATACH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATACH1_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATACH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATACH1_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATACH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK3_REG (0x0000313C) #define DDRDATACH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATACH1_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATACH1_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATACH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATACH1_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATACH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATACH1_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATACH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATACH1_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATACH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATACH1_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATACH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATACH1_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATACH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATACH1_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATACH1_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATACH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATACH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATACH1_CR_RCOMPDATA0_REG (0x00003140) #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATACH1_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATACH1_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATACH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATACH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATACH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATACH1_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATACH1_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATACH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATACH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATACH1_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATACH1_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATACH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATACH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATACH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATACH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATACH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATACH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATACH1_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATACH1_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATACH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATACH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATACH1_CR_RCOMPDATA1_REG (0x00003144) #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATACH1_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATACH1_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATACH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATACH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATACH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATACH1_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATACH1_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATACH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATACH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATACH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATACH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATACH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATACH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATACH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATACH1_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATACH1_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATACH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATACH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATACH1_CR_TXXTALK_REG (0x00003148) #define DDRDATACH1_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATACH1_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATACH1_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATACH1_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATACH1_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATACH1_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATACH1_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATACH1_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATACH1_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATACH1_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATACH1_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATACH1_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATACH1_CR_TXXTALK_Lane3_OFF (12) #define DDRDATACH1_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATACH1_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATACH1_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATACH1_CR_TXXTALK_Lane4_OFF (16) #define DDRDATACH1_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATACH1_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATACH1_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATACH1_CR_TXXTALK_Lane5_OFF (20) #define DDRDATACH1_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATACH1_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATACH1_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATACH1_CR_TXXTALK_Lane6_OFF (24) #define DDRDATACH1_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATACH1_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATACH1_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATACH1_CR_TXXTALK_Lane7_OFF (28) #define DDRDATACH1_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATACH1_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATACH1_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATACH1_CR_RXOFFSETVDQ_REG (0x0000314C) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATACH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATACH1_CR_DDRDATARESERVED_REG (0x00003150) #define DDRDATACH1_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATACH1_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATACH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATACH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATACH1_CR_DATATRAINFEEDBACK_REG (0x00003154) #define DDRDATACH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATACH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATACH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATACH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATACH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATACH1_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATACH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATACH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATACH1_CR_DLLPITESTANDADC_REG (0x00003158) #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATACH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATACH1_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATACH1_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATACH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATACH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATACH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATACH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATACH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATACH1_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATACH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATACH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATACH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATACH1_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATACH1_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATACH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATACH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000315C) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATACH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_REG (0x00003160) #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATACH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATACH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATACH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATACH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATACH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL2_REG (0x00003164) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATACH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATACH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATACH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000316C) #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATACH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00003170) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_REG (0x00003174) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATACH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_REG (0x00003178) #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATACH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATACH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATACH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATACH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA0CH0_CR_RXTRAINRANK0_REG (0x00000000) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA0CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA0CH0_CR_RXTRAINRANK1_REG (0x00000004) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA0CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA0CH0_CR_RXTRAINRANK2_REG (0x00000008) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA0CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA0CH0_CR_RXTRAINRANK3_REG (0x0000000C) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA0CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA0CH0_CR_RXPERBITRANK0_REG (0x00000010) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA0CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK1_REG (0x00000014) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA0CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK2_REG (0x00000018) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA0CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK3_REG (0x0000001C) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA0CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXTRAINRANK0_REG (0x00000020) #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA0CH0_CR_TXTRAINRANK1_REG (0x00000024) #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA0CH0_CR_TXTRAINRANK2_REG (0x00000028) #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA0CH0_CR_TXTRAINRANK3_REG (0x0000002C) #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA0CH0_CR_TXPERBITRANK0_REG (0x00000030) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA0CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK1_REG (0x00000034) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA0CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK2_REG (0x00000038) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA0CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK3_REG (0x0000003C) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA0CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA0CH0_CR_RCOMPDATA0_REG (0x00000040) #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA0CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA0CH0_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA0CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA0CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA0CH0_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA0CH0_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA0CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA0CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA0CH0_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA0CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA0CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA0CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA0CH0_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA0CH0_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA0CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA0CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA0CH0_CR_RCOMPDATA1_REG (0x00000044) #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA0CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA0CH0_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA0CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA0CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA0CH0_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA0CH0_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA0CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA0CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA0CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA0CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA0CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA0CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA0CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA0CH0_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA0CH0_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA0CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA0CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA0CH0_CR_TXXTALK_REG (0x00000048) #define DDRDATA0CH0_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA0CH0_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA0CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA0CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA0CH0_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA0CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA0CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA0CH0_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA0CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA0CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA0CH0_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA0CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA0CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA0CH0_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA0CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA0CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA0CH0_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA0CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA0CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA0CH0_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA0CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA0CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA0CH0_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA0CH0_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA0CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA0CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXOFFSETVDQ_REG (0x0000004C) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA0CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA0CH0_CR_DDRDATARESERVED_REG (0x00000050) #define DDRDATA0CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA0CH0_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA0CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA0CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG (0x00000054) #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA0CH0_CR_DLLPITESTANDADC_REG (0x00000058) #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA0CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA0CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA0CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA0CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA0CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA0CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA0CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA0CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA0CH0_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA0CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA0CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA0CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000005C) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG (0x00000060) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG (0x00000064) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000006C) #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA0CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000070) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_REG (0x00000074) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_REG (0x00000078) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA0CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA0CH1_CR_RXTRAINRANK0_REG (0x00000100) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA0CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA0CH1_CR_RXTRAINRANK1_REG (0x00000104) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA0CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA0CH1_CR_RXTRAINRANK2_REG (0x00000108) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA0CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA0CH1_CR_RXTRAINRANK3_REG (0x0000010C) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA0CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA0CH1_CR_RXPERBITRANK0_REG (0x00000110) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA0CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK1_REG (0x00000114) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA0CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK2_REG (0x00000118) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA0CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK3_REG (0x0000011C) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA0CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXTRAINRANK0_REG (0x00000120) #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA0CH1_CR_TXTRAINRANK1_REG (0x00000124) #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA0CH1_CR_TXTRAINRANK2_REG (0x00000128) #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA0CH1_CR_TXTRAINRANK3_REG (0x0000012C) #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA0CH1_CR_TXPERBITRANK0_REG (0x00000130) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA0CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK1_REG (0x00000134) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA0CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK2_REG (0x00000138) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA0CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK3_REG (0x0000013C) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA0CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA0CH1_CR_RCOMPDATA0_REG (0x00000140) #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA0CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA0CH1_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA0CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA0CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA0CH1_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA0CH1_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA0CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA0CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA0CH1_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA0CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA0CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA0CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA0CH1_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA0CH1_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA0CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA0CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA0CH1_CR_RCOMPDATA1_REG (0x00000144) #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA0CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA0CH1_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA0CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA0CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA0CH1_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA0CH1_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA0CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA0CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA0CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA0CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA0CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA0CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA0CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA0CH1_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA0CH1_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA0CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA0CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA0CH1_CR_TXXTALK_REG (0x00000148) #define DDRDATA0CH1_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA0CH1_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA0CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA0CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA0CH1_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA0CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA0CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA0CH1_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA0CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA0CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA0CH1_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA0CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA0CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA0CH1_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA0CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA0CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA0CH1_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA0CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA0CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA0CH1_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA0CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA0CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA0CH1_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA0CH1_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA0CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA0CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXOFFSETVDQ_REG (0x0000014C) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA0CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA0CH1_CR_DDRDATARESERVED_REG (0x00000150) #define DDRDATA0CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA0CH1_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA0CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA0CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG (0x00000154) #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA0CH1_CR_DLLPITESTANDADC_REG (0x00000158) #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA0CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA0CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA0CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA0CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA0CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA0CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA0CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA0CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA0CH1_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA0CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA0CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA0CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000015C) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_REG (0x00000160) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG (0x00000164) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000016C) #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA0CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000170) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_REG (0x00000174) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_REG (0x00000178) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA0CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA1CH0_CR_RXTRAINRANK0_REG (0x00000200) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA1CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA1CH0_CR_RXTRAINRANK1_REG (0x00000204) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA1CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA1CH0_CR_RXTRAINRANK2_REG (0x00000208) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA1CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA1CH0_CR_RXTRAINRANK3_REG (0x0000020C) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA1CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA1CH0_CR_RXPERBITRANK0_REG (0x00000210) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA1CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK1_REG (0x00000214) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA1CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK2_REG (0x00000218) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA1CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK3_REG (0x0000021C) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA1CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXTRAINRANK0_REG (0x00000220) #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA1CH0_CR_TXTRAINRANK1_REG (0x00000224) #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA1CH0_CR_TXTRAINRANK2_REG (0x00000228) #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA1CH0_CR_TXTRAINRANK3_REG (0x0000022C) #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA1CH0_CR_TXPERBITRANK0_REG (0x00000230) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA1CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK1_REG (0x00000234) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA1CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK2_REG (0x00000238) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA1CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK3_REG (0x0000023C) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA1CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA1CH0_CR_RCOMPDATA0_REG (0x00000240) #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA1CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA1CH0_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA1CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA1CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA1CH0_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA1CH0_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA1CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA1CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA1CH0_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA1CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA1CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA1CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA1CH0_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA1CH0_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA1CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA1CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA1CH0_CR_RCOMPDATA1_REG (0x00000244) #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA1CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA1CH0_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA1CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA1CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA1CH0_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA1CH0_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA1CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA1CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA1CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA1CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA1CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA1CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA1CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA1CH0_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA1CH0_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA1CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA1CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA1CH0_CR_TXXTALK_REG (0x00000248) #define DDRDATA1CH0_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA1CH0_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA1CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA1CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA1CH0_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA1CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA1CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA1CH0_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA1CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA1CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA1CH0_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA1CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA1CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA1CH0_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA1CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA1CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA1CH0_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA1CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA1CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA1CH0_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA1CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA1CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA1CH0_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA1CH0_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA1CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA1CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXOFFSETVDQ_REG (0x0000024C) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA1CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA1CH0_CR_DDRDATARESERVED_REG (0x00000250) #define DDRDATA1CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA1CH0_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA1CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA1CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG (0x00000254) #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA1CH0_CR_DLLPITESTANDADC_REG (0x00000258) #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA1CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA1CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA1CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA1CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA1CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA1CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA1CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA1CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA1CH0_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA1CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA1CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA1CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000025C) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_REG (0x00000260) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG (0x00000264) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000026C) #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA1CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000270) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_REG (0x00000274) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_REG (0x00000278) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA1CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA1CH1_CR_RXTRAINRANK0_REG (0x00000300) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA1CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA1CH1_CR_RXTRAINRANK1_REG (0x00000304) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA1CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA1CH1_CR_RXTRAINRANK2_REG (0x00000308) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA1CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA1CH1_CR_RXTRAINRANK3_REG (0x0000030C) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA1CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA1CH1_CR_RXPERBITRANK0_REG (0x00000310) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA1CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK1_REG (0x00000314) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA1CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK2_REG (0x00000318) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA1CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK3_REG (0x0000031C) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA1CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXTRAINRANK0_REG (0x00000320) #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA1CH1_CR_TXTRAINRANK1_REG (0x00000324) #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA1CH1_CR_TXTRAINRANK2_REG (0x00000328) #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA1CH1_CR_TXTRAINRANK3_REG (0x0000032C) #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA1CH1_CR_TXPERBITRANK0_REG (0x00000330) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA1CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK1_REG (0x00000334) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA1CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK2_REG (0x00000338) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA1CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK3_REG (0x0000033C) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA1CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA1CH1_CR_RCOMPDATA0_REG (0x00000340) #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA1CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA1CH1_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA1CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA1CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA1CH1_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA1CH1_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA1CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA1CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA1CH1_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA1CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA1CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA1CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA1CH1_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA1CH1_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA1CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA1CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA1CH1_CR_RCOMPDATA1_REG (0x00000344) #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA1CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA1CH1_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA1CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA1CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA1CH1_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA1CH1_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA1CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA1CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA1CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA1CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA1CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA1CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA1CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA1CH1_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA1CH1_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA1CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA1CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA1CH1_CR_TXXTALK_REG (0x00000348) #define DDRDATA1CH1_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA1CH1_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA1CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA1CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA1CH1_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA1CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA1CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA1CH1_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA1CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA1CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA1CH1_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA1CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA1CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA1CH1_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA1CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA1CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA1CH1_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA1CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA1CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA1CH1_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA1CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA1CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA1CH1_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA1CH1_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA1CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA1CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXOFFSETVDQ_REG (0x0000034C) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA1CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA1CH1_CR_DDRDATARESERVED_REG (0x00000350) #define DDRDATA1CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA1CH1_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA1CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA1CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_REG (0x00000354) #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA1CH1_CR_DLLPITESTANDADC_REG (0x00000358) #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA1CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA1CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA1CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA1CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA1CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA1CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA1CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA1CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA1CH1_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA1CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA1CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA1CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000035C) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_REG (0x00000360) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_REG (0x00000364) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000036C) #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA1CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000370) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_REG (0x00000374) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_REG (0x00000378) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA1CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA2CH0_CR_RXTRAINRANK0_REG (0x00000400) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA2CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA2CH0_CR_RXTRAINRANK1_REG (0x00000404) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA2CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA2CH0_CR_RXTRAINRANK2_REG (0x00000408) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA2CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA2CH0_CR_RXTRAINRANK3_REG (0x0000040C) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA2CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA2CH0_CR_RXPERBITRANK0_REG (0x00000410) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA2CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK1_REG (0x00000414) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA2CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK2_REG (0x00000418) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA2CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK3_REG (0x0000041C) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA2CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXTRAINRANK0_REG (0x00000420) #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA2CH0_CR_TXTRAINRANK1_REG (0x00000424) #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA2CH0_CR_TXTRAINRANK2_REG (0x00000428) #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA2CH0_CR_TXTRAINRANK3_REG (0x0000042C) #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA2CH0_CR_TXPERBITRANK0_REG (0x00000430) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA2CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK1_REG (0x00000434) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA2CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK2_REG (0x00000438) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA2CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK3_REG (0x0000043C) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA2CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA2CH0_CR_RCOMPDATA0_REG (0x00000440) #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA2CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA2CH0_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA2CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA2CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA2CH0_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA2CH0_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA2CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA2CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA2CH0_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA2CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA2CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA2CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA2CH0_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA2CH0_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA2CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA2CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA2CH0_CR_RCOMPDATA1_REG (0x00000444) #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA2CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA2CH0_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA2CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA2CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA2CH0_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA2CH0_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA2CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA2CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA2CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA2CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA2CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA2CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA2CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA2CH0_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA2CH0_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA2CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA2CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA2CH0_CR_TXXTALK_REG (0x00000448) #define DDRDATA2CH0_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA2CH0_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA2CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA2CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA2CH0_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA2CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA2CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA2CH0_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA2CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA2CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA2CH0_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA2CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA2CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA2CH0_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA2CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA2CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA2CH0_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA2CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA2CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA2CH0_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA2CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA2CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA2CH0_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA2CH0_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA2CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA2CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXOFFSETVDQ_REG (0x0000044C) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA2CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA2CH0_CR_DDRDATARESERVED_REG (0x00000450) #define DDRDATA2CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA2CH0_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA2CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA2CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_REG (0x00000454) #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA2CH0_CR_DLLPITESTANDADC_REG (0x00000458) #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA2CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA2CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA2CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA2CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA2CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA2CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA2CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA2CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA2CH0_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA2CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA2CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA2CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000045C) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_REG (0x00000460) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_REG (0x00000464) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000046C) #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA2CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000470) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_REG (0x00000474) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_REG (0x00000478) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA2CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA2CH1_CR_RXTRAINRANK0_REG (0x00000500) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA2CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA2CH1_CR_RXTRAINRANK1_REG (0x00000504) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA2CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA2CH1_CR_RXTRAINRANK2_REG (0x00000508) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA2CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA2CH1_CR_RXTRAINRANK3_REG (0x0000050C) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA2CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA2CH1_CR_RXPERBITRANK0_REG (0x00000510) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA2CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK1_REG (0x00000514) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA2CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK2_REG (0x00000518) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA2CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK3_REG (0x0000051C) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA2CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXTRAINRANK0_REG (0x00000520) #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA2CH1_CR_TXTRAINRANK1_REG (0x00000524) #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA2CH1_CR_TXTRAINRANK2_REG (0x00000528) #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA2CH1_CR_TXTRAINRANK3_REG (0x0000052C) #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA2CH1_CR_TXPERBITRANK0_REG (0x00000530) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA2CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK1_REG (0x00000534) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA2CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK2_REG (0x00000538) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA2CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK3_REG (0x0000053C) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA2CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA2CH1_CR_RCOMPDATA0_REG (0x00000540) #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA2CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA2CH1_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA2CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA2CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA2CH1_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA2CH1_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA2CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA2CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA2CH1_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA2CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA2CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA2CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA2CH1_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA2CH1_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA2CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA2CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA2CH1_CR_RCOMPDATA1_REG (0x00000544) #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA2CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA2CH1_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA2CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA2CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA2CH1_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA2CH1_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA2CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA2CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA2CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA2CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA2CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA2CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA2CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA2CH1_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA2CH1_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA2CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA2CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA2CH1_CR_TXXTALK_REG (0x00000548) #define DDRDATA2CH1_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA2CH1_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA2CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA2CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA2CH1_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA2CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA2CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA2CH1_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA2CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA2CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA2CH1_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA2CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA2CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA2CH1_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA2CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA2CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA2CH1_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA2CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA2CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA2CH1_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA2CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA2CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA2CH1_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA2CH1_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA2CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA2CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXOFFSETVDQ_REG (0x0000054C) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA2CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA2CH1_CR_DDRDATARESERVED_REG (0x00000550) #define DDRDATA2CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA2CH1_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA2CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA2CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_REG (0x00000554) #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA2CH1_CR_DLLPITESTANDADC_REG (0x00000558) #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA2CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA2CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA2CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA2CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA2CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA2CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA2CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA2CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA2CH1_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA2CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA2CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA2CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000055C) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_REG (0x00000560) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_REG (0x00000564) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000056C) #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA2CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000570) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_REG (0x00000574) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_REG (0x00000578) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA2CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA3CH0_CR_RXTRAINRANK0_REG (0x00000600) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA3CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA3CH0_CR_RXTRAINRANK1_REG (0x00000604) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA3CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA3CH0_CR_RXTRAINRANK2_REG (0x00000608) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA3CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA3CH0_CR_RXTRAINRANK3_REG (0x0000060C) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA3CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA3CH0_CR_RXPERBITRANK0_REG (0x00000610) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA3CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK1_REG (0x00000614) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA3CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK2_REG (0x00000618) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA3CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK3_REG (0x0000061C) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA3CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXTRAINRANK0_REG (0x00000620) #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA3CH0_CR_TXTRAINRANK1_REG (0x00000624) #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA3CH0_CR_TXTRAINRANK2_REG (0x00000628) #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA3CH0_CR_TXTRAINRANK3_REG (0x0000062C) #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA3CH0_CR_TXPERBITRANK0_REG (0x00000630) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA3CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK1_REG (0x00000634) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA3CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK2_REG (0x00000638) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA3CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK3_REG (0x0000063C) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA3CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA3CH0_CR_RCOMPDATA0_REG (0x00000640) #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA3CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA3CH0_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA3CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA3CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA3CH0_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA3CH0_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA3CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA3CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA3CH0_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA3CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA3CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA3CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA3CH0_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA3CH0_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA3CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA3CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA3CH0_CR_RCOMPDATA1_REG (0x00000644) #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA3CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA3CH0_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA3CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA3CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA3CH0_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA3CH0_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA3CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA3CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA3CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA3CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA3CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA3CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA3CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA3CH0_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA3CH0_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA3CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA3CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA3CH0_CR_TXXTALK_REG (0x00000648) #define DDRDATA3CH0_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA3CH0_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA3CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA3CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA3CH0_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA3CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA3CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA3CH0_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA3CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA3CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA3CH0_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA3CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA3CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA3CH0_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA3CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA3CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA3CH0_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA3CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA3CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA3CH0_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA3CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA3CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA3CH0_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA3CH0_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA3CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA3CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXOFFSETVDQ_REG (0x0000064C) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA3CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA3CH0_CR_DDRDATARESERVED_REG (0x00000650) #define DDRDATA3CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA3CH0_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA3CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA3CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_REG (0x00000654) #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA3CH0_CR_DLLPITESTANDADC_REG (0x00000658) #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA3CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA3CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA3CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA3CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA3CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA3CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA3CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA3CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA3CH0_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA3CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA3CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA3CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000065C) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_REG (0x00000660) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_REG (0x00000664) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000066C) #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA3CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000670) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_REG (0x00000674) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_REG (0x00000678) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA3CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA3CH1_CR_RXTRAINRANK0_REG (0x00000700) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA3CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA3CH1_CR_RXTRAINRANK1_REG (0x00000704) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA3CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA3CH1_CR_RXTRAINRANK2_REG (0x00000708) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA3CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA3CH1_CR_RXTRAINRANK3_REG (0x0000070C) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA3CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA3CH1_CR_RXPERBITRANK0_REG (0x00000710) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA3CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK1_REG (0x00000714) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA3CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK2_REG (0x00000718) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA3CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK3_REG (0x0000071C) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA3CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXTRAINRANK0_REG (0x00000720) #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA3CH1_CR_TXTRAINRANK1_REG (0x00000724) #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA3CH1_CR_TXTRAINRANK2_REG (0x00000728) #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA3CH1_CR_TXTRAINRANK3_REG (0x0000072C) #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA3CH1_CR_TXPERBITRANK0_REG (0x00000730) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA3CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK1_REG (0x00000734) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA3CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK2_REG (0x00000738) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA3CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK3_REG (0x0000073C) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA3CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA3CH1_CR_RCOMPDATA0_REG (0x00000740) #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA3CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA3CH1_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA3CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA3CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA3CH1_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA3CH1_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA3CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA3CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA3CH1_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA3CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA3CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA3CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA3CH1_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA3CH1_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA3CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA3CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA3CH1_CR_RCOMPDATA1_REG (0x00000744) #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA3CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA3CH1_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA3CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA3CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA3CH1_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA3CH1_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA3CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA3CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA3CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA3CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA3CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA3CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA3CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA3CH1_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA3CH1_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA3CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA3CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA3CH1_CR_TXXTALK_REG (0x00000748) #define DDRDATA3CH1_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA3CH1_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA3CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA3CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA3CH1_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA3CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA3CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA3CH1_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA3CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA3CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA3CH1_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA3CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA3CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA3CH1_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA3CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA3CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA3CH1_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA3CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA3CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA3CH1_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA3CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA3CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA3CH1_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA3CH1_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA3CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA3CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXOFFSETVDQ_REG (0x0000074C) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA3CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA3CH1_CR_DDRDATARESERVED_REG (0x00000750) #define DDRDATA3CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA3CH1_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA3CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA3CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_REG (0x00000754) #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA3CH1_CR_DLLPITESTANDADC_REG (0x00000758) #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA3CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA3CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA3CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA3CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA3CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA3CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA3CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA3CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA3CH1_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA3CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA3CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA3CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000075C) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_REG (0x00000760) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_REG (0x00000764) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000076C) #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA3CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000770) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_REG (0x00000774) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_REG (0x00000778) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA3CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA4CH0_CR_RXTRAINRANK0_REG (0x00000800) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA4CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA4CH0_CR_RXTRAINRANK1_REG (0x00000804) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA4CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA4CH0_CR_RXTRAINRANK2_REG (0x00000808) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA4CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA4CH0_CR_RXTRAINRANK3_REG (0x0000080C) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA4CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA4CH0_CR_RXPERBITRANK0_REG (0x00000810) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA4CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK1_REG (0x00000814) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA4CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK2_REG (0x00000818) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA4CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK3_REG (0x0000081C) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA4CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXTRAINRANK0_REG (0x00000820) #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA4CH0_CR_TXTRAINRANK1_REG (0x00000824) #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA4CH0_CR_TXTRAINRANK2_REG (0x00000828) #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA4CH0_CR_TXTRAINRANK3_REG (0x0000082C) #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA4CH0_CR_TXPERBITRANK0_REG (0x00000830) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA4CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK1_REG (0x00000834) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA4CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK2_REG (0x00000838) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA4CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK3_REG (0x0000083C) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA4CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA4CH0_CR_RCOMPDATA0_REG (0x00000840) #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA4CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA4CH0_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA4CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA4CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA4CH0_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA4CH0_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA4CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA4CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA4CH0_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA4CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA4CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA4CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA4CH0_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA4CH0_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA4CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA4CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA4CH0_CR_RCOMPDATA1_REG (0x00000844) #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA4CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA4CH0_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA4CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA4CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA4CH0_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA4CH0_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA4CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA4CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA4CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA4CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA4CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA4CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA4CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA4CH0_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA4CH0_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA4CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA4CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA4CH0_CR_TXXTALK_REG (0x00000848) #define DDRDATA4CH0_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA4CH0_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA4CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA4CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA4CH0_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA4CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA4CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA4CH0_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA4CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA4CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA4CH0_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA4CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA4CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA4CH0_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA4CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA4CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA4CH0_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA4CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA4CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA4CH0_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA4CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA4CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA4CH0_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA4CH0_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA4CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA4CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXOFFSETVDQ_REG (0x0000084C) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA4CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA4CH0_CR_DDRDATARESERVED_REG (0x00000850) #define DDRDATA4CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA4CH0_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA4CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA4CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_REG (0x00000854) #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA4CH0_CR_DLLPITESTANDADC_REG (0x00000858) #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA4CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA4CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA4CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA4CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA4CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA4CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA4CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA4CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA4CH0_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA4CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA4CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA4CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000085C) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_REG (0x00000860) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_REG (0x00000864) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000086C) #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA4CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000870) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_REG (0x00000874) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_REG (0x00000878) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA4CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA4CH1_CR_RXTRAINRANK0_REG (0x00000900) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA4CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA4CH1_CR_RXTRAINRANK1_REG (0x00000904) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA4CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA4CH1_CR_RXTRAINRANK2_REG (0x00000908) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA4CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA4CH1_CR_RXTRAINRANK3_REG (0x0000090C) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA4CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA4CH1_CR_RXPERBITRANK0_REG (0x00000910) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA4CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK1_REG (0x00000914) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA4CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK2_REG (0x00000918) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA4CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK3_REG (0x0000091C) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA4CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXTRAINRANK0_REG (0x00000920) #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA4CH1_CR_TXTRAINRANK1_REG (0x00000924) #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA4CH1_CR_TXTRAINRANK2_REG (0x00000928) #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA4CH1_CR_TXTRAINRANK3_REG (0x0000092C) #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA4CH1_CR_TXPERBITRANK0_REG (0x00000930) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA4CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK1_REG (0x00000934) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA4CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK2_REG (0x00000938) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA4CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK3_REG (0x0000093C) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA4CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA4CH1_CR_RCOMPDATA0_REG (0x00000940) #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA4CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA4CH1_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA4CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA4CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA4CH1_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA4CH1_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA4CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA4CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA4CH1_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA4CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA4CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA4CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA4CH1_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA4CH1_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA4CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA4CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA4CH1_CR_RCOMPDATA1_REG (0x00000944) #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA4CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA4CH1_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA4CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA4CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA4CH1_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA4CH1_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA4CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA4CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA4CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA4CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA4CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA4CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA4CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA4CH1_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA4CH1_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA4CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA4CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA4CH1_CR_TXXTALK_REG (0x00000948) #define DDRDATA4CH1_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA4CH1_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA4CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA4CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA4CH1_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA4CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA4CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA4CH1_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA4CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA4CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA4CH1_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA4CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA4CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA4CH1_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA4CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA4CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA4CH1_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA4CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA4CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA4CH1_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA4CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA4CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA4CH1_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA4CH1_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA4CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA4CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXOFFSETVDQ_REG (0x0000094C) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA4CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA4CH1_CR_DDRDATARESERVED_REG (0x00000950) #define DDRDATA4CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA4CH1_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA4CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA4CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_REG (0x00000954) #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA4CH1_CR_DLLPITESTANDADC_REG (0x00000958) #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA4CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA4CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA4CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA4CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA4CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA4CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA4CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA4CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA4CH1_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA4CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA4CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA4CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000095C) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_REG (0x00000960) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_REG (0x00000964) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000096C) #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA4CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000970) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_REG (0x00000974) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_REG (0x00000978) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA4CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA5CH0_CR_RXTRAINRANK0_REG (0x00000A00) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA5CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA5CH0_CR_RXTRAINRANK1_REG (0x00000A04) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA5CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA5CH0_CR_RXTRAINRANK2_REG (0x00000A08) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA5CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA5CH0_CR_RXTRAINRANK3_REG (0x00000A0C) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA5CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA5CH0_CR_RXPERBITRANK0_REG (0x00000A10) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA5CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK1_REG (0x00000A14) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA5CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK2_REG (0x00000A18) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA5CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK3_REG (0x00000A1C) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA5CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXTRAINRANK0_REG (0x00000A20) #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA5CH0_CR_TXTRAINRANK1_REG (0x00000A24) #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA5CH0_CR_TXTRAINRANK2_REG (0x00000A28) #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA5CH0_CR_TXTRAINRANK3_REG (0x00000A2C) #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA5CH0_CR_TXPERBITRANK0_REG (0x00000A30) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA5CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK1_REG (0x00000A34) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA5CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK2_REG (0x00000A38) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA5CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK3_REG (0x00000A3C) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA5CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA5CH0_CR_RCOMPDATA0_REG (0x00000A40) #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA5CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA5CH0_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA5CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA5CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA5CH0_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA5CH0_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA5CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA5CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA5CH0_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA5CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA5CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA5CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA5CH0_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA5CH0_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA5CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA5CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA5CH0_CR_RCOMPDATA1_REG (0x00000A44) #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA5CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA5CH0_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA5CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA5CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA5CH0_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA5CH0_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA5CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA5CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA5CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA5CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA5CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA5CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA5CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA5CH0_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA5CH0_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA5CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA5CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA5CH0_CR_TXXTALK_REG (0x00000A48) #define DDRDATA5CH0_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA5CH0_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA5CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA5CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA5CH0_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA5CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA5CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA5CH0_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA5CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA5CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA5CH0_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA5CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA5CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA5CH0_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA5CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA5CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA5CH0_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA5CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA5CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA5CH0_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA5CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA5CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA5CH0_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA5CH0_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA5CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA5CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXOFFSETVDQ_REG (0x00000A4C) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA5CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA5CH0_CR_DDRDATARESERVED_REG (0x00000A50) #define DDRDATA5CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA5CH0_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA5CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA5CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_REG (0x00000A54) #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA5CH0_CR_DLLPITESTANDADC_REG (0x00000A58) #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA5CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA5CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA5CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA5CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA5CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA5CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA5CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA5CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA5CH0_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA5CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA5CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA5CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x00000A5C) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_REG (0x00000A60) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_REG (0x00000A64) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x00000A6C) #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA5CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000A70) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_REG (0x00000A74) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_REG (0x00000A78) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA5CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA5CH1_CR_RXTRAINRANK0_REG (0x00000B00) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA5CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA5CH1_CR_RXTRAINRANK1_REG (0x00000B04) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA5CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA5CH1_CR_RXTRAINRANK2_REG (0x00000B08) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA5CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA5CH1_CR_RXTRAINRANK3_REG (0x00000B0C) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA5CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA5CH1_CR_RXPERBITRANK0_REG (0x00000B10) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA5CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK1_REG (0x00000B14) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA5CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK2_REG (0x00000B18) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA5CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK3_REG (0x00000B1C) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA5CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXTRAINRANK0_REG (0x00000B20) #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA5CH1_CR_TXTRAINRANK1_REG (0x00000B24) #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA5CH1_CR_TXTRAINRANK2_REG (0x00000B28) #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA5CH1_CR_TXTRAINRANK3_REG (0x00000B2C) #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA5CH1_CR_TXPERBITRANK0_REG (0x00000B30) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA5CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK1_REG (0x00000B34) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA5CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK2_REG (0x00000B38) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA5CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK3_REG (0x00000B3C) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA5CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA5CH1_CR_RCOMPDATA0_REG (0x00000B40) #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA5CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA5CH1_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA5CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA5CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA5CH1_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA5CH1_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA5CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA5CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA5CH1_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA5CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA5CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA5CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA5CH1_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA5CH1_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA5CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA5CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA5CH1_CR_RCOMPDATA1_REG (0x00000B44) #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA5CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA5CH1_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA5CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA5CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA5CH1_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA5CH1_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA5CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA5CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA5CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA5CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA5CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA5CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA5CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA5CH1_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA5CH1_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA5CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA5CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA5CH1_CR_TXXTALK_REG (0x00000B48) #define DDRDATA5CH1_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA5CH1_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA5CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA5CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA5CH1_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA5CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA5CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA5CH1_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA5CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA5CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA5CH1_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA5CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA5CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA5CH1_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA5CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA5CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA5CH1_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA5CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA5CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA5CH1_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA5CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA5CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA5CH1_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA5CH1_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA5CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA5CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXOFFSETVDQ_REG (0x00000B4C) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA5CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA5CH1_CR_DDRDATARESERVED_REG (0x00000B50) #define DDRDATA5CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA5CH1_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA5CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA5CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_REG (0x00000B54) #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA5CH1_CR_DLLPITESTANDADC_REG (0x00000B58) #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA5CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA5CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA5CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA5CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA5CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA5CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA5CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA5CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA5CH1_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA5CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA5CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA5CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x00000B5C) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_REG (0x00000B60) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_REG (0x00000B64) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x00000B6C) #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA5CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000B70) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_REG (0x00000B74) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_REG (0x00000B78) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA5CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA6CH0_CR_RXTRAINRANK0_REG (0x00000C00) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA6CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA6CH0_CR_RXTRAINRANK1_REG (0x00000C04) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA6CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA6CH0_CR_RXTRAINRANK2_REG (0x00000C08) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA6CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA6CH0_CR_RXTRAINRANK3_REG (0x00000C0C) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA6CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA6CH0_CR_RXPERBITRANK0_REG (0x00000C10) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA6CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK1_REG (0x00000C14) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA6CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK2_REG (0x00000C18) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA6CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK3_REG (0x00000C1C) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA6CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXTRAINRANK0_REG (0x00000C20) #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA6CH0_CR_TXTRAINRANK1_REG (0x00000C24) #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA6CH0_CR_TXTRAINRANK2_REG (0x00000C28) #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA6CH0_CR_TXTRAINRANK3_REG (0x00000C2C) #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA6CH0_CR_TXPERBITRANK0_REG (0x00000C30) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA6CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK1_REG (0x00000C34) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA6CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK2_REG (0x00000C38) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA6CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK3_REG (0x00000C3C) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA6CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA6CH0_CR_RCOMPDATA0_REG (0x00000C40) #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA6CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA6CH0_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA6CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA6CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA6CH0_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA6CH0_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA6CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA6CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA6CH0_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA6CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA6CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA6CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA6CH0_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA6CH0_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA6CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA6CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA6CH0_CR_RCOMPDATA1_REG (0x00000C44) #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA6CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA6CH0_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA6CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA6CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA6CH0_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA6CH0_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA6CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA6CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA6CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA6CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA6CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA6CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA6CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA6CH0_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA6CH0_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA6CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA6CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA6CH0_CR_TXXTALK_REG (0x00000C48) #define DDRDATA6CH0_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA6CH0_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA6CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA6CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA6CH0_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA6CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA6CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA6CH0_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA6CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA6CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA6CH0_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA6CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA6CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA6CH0_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA6CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA6CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA6CH0_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA6CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA6CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA6CH0_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA6CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA6CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA6CH0_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA6CH0_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA6CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA6CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXOFFSETVDQ_REG (0x00000C4C) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA6CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA6CH0_CR_DDRDATARESERVED_REG (0x00000C50) #define DDRDATA6CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA6CH0_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA6CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA6CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_REG (0x00000C54) #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA6CH0_CR_DLLPITESTANDADC_REG (0x00000C58) #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA6CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA6CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA6CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA6CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA6CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA6CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA6CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA6CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA6CH0_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA6CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA6CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA6CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x00000C5C) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_REG (0x00000C60) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_REG (0x00000C64) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x00000C6C) #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA6CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000C70) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_REG (0x00000C74) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_REG (0x00000C78) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA6CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA6CH1_CR_RXTRAINRANK0_REG (0x00000D00) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA6CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA6CH1_CR_RXTRAINRANK1_REG (0x00000D04) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA6CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA6CH1_CR_RXTRAINRANK2_REG (0x00000D08) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA6CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA6CH1_CR_RXTRAINRANK3_REG (0x00000D0C) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA6CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA6CH1_CR_RXPERBITRANK0_REG (0x00000D10) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA6CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK1_REG (0x00000D14) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA6CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK2_REG (0x00000D18) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA6CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK3_REG (0x00000D1C) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA6CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXTRAINRANK0_REG (0x00000D20) #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA6CH1_CR_TXTRAINRANK1_REG (0x00000D24) #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA6CH1_CR_TXTRAINRANK2_REG (0x00000D28) #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA6CH1_CR_TXTRAINRANK3_REG (0x00000D2C) #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA6CH1_CR_TXPERBITRANK0_REG (0x00000D30) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA6CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK1_REG (0x00000D34) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA6CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK2_REG (0x00000D38) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA6CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK3_REG (0x00000D3C) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA6CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA6CH1_CR_RCOMPDATA0_REG (0x00000D40) #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA6CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA6CH1_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA6CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA6CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA6CH1_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA6CH1_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA6CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA6CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA6CH1_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA6CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA6CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA6CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA6CH1_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA6CH1_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA6CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA6CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA6CH1_CR_RCOMPDATA1_REG (0x00000D44) #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA6CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA6CH1_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA6CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA6CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA6CH1_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA6CH1_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA6CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA6CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA6CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA6CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA6CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA6CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA6CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA6CH1_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA6CH1_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA6CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA6CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA6CH1_CR_TXXTALK_REG (0x00000D48) #define DDRDATA6CH1_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA6CH1_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA6CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA6CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA6CH1_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA6CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA6CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA6CH1_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA6CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA6CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA6CH1_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA6CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA6CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA6CH1_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA6CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA6CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA6CH1_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA6CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA6CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA6CH1_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA6CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA6CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA6CH1_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA6CH1_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA6CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA6CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXOFFSETVDQ_REG (0x00000D4C) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA6CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA6CH1_CR_DDRDATARESERVED_REG (0x00000D50) #define DDRDATA6CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA6CH1_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA6CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA6CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_REG (0x00000D54) #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA6CH1_CR_DLLPITESTANDADC_REG (0x00000D58) #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA6CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA6CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA6CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA6CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA6CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA6CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA6CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA6CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA6CH1_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA6CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA6CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA6CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x00000D5C) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_REG (0x00000D60) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_REG (0x00000D64) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x00000D6C) #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA6CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000D70) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_REG (0x00000D74) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_REG (0x00000D78) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA6CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA7CH0_CR_RXTRAINRANK0_REG (0x00000E00) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA7CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA7CH0_CR_RXTRAINRANK1_REG (0x00000E04) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA7CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA7CH0_CR_RXTRAINRANK2_REG (0x00000E08) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA7CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA7CH0_CR_RXTRAINRANK3_REG (0x00000E0C) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA7CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA7CH0_CR_RXPERBITRANK0_REG (0x00000E10) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA7CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK1_REG (0x00000E14) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA7CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK2_REG (0x00000E18) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA7CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK3_REG (0x00000E1C) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA7CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXTRAINRANK0_REG (0x00000E20) #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA7CH0_CR_TXTRAINRANK1_REG (0x00000E24) #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA7CH0_CR_TXTRAINRANK2_REG (0x00000E28) #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA7CH0_CR_TXTRAINRANK3_REG (0x00000E2C) #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA7CH0_CR_TXPERBITRANK0_REG (0x00000E30) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA7CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK1_REG (0x00000E34) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA7CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK2_REG (0x00000E38) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA7CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK3_REG (0x00000E3C) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA7CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA7CH0_CR_RCOMPDATA0_REG (0x00000E40) #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA7CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA7CH0_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA7CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA7CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA7CH0_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA7CH0_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA7CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA7CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA7CH0_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA7CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA7CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA7CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA7CH0_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA7CH0_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA7CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA7CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA7CH0_CR_RCOMPDATA1_REG (0x00000E44) #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA7CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA7CH0_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA7CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA7CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA7CH0_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA7CH0_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA7CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA7CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA7CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA7CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA7CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA7CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA7CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA7CH0_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA7CH0_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA7CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA7CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA7CH0_CR_TXXTALK_REG (0x00000E48) #define DDRDATA7CH0_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA7CH0_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA7CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA7CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA7CH0_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA7CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA7CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA7CH0_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA7CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA7CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA7CH0_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA7CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA7CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA7CH0_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA7CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA7CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA7CH0_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA7CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA7CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA7CH0_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA7CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA7CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA7CH0_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA7CH0_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA7CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA7CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXOFFSETVDQ_REG (0x00000E4C) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA7CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA7CH0_CR_DDRDATARESERVED_REG (0x00000E50) #define DDRDATA7CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA7CH0_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA7CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA7CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_REG (0x00000E54) #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA7CH0_CR_DLLPITESTANDADC_REG (0x00000E58) #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA7CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA7CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA7CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA7CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA7CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA7CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA7CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA7CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA7CH0_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA7CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA7CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA7CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x00000E5C) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_REG (0x00000E60) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_REG (0x00000E64) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x00000E6C) #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA7CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000E70) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_REG (0x00000E74) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_REG (0x00000E78) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA7CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA7CH1_CR_RXTRAINRANK0_REG (0x00000F00) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA7CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA7CH1_CR_RXTRAINRANK1_REG (0x00000F04) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA7CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA7CH1_CR_RXTRAINRANK2_REG (0x00000F08) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA7CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA7CH1_CR_RXTRAINRANK3_REG (0x00000F0C) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA7CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA7CH1_CR_RXPERBITRANK0_REG (0x00000F10) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA7CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK1_REG (0x00000F14) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA7CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK2_REG (0x00000F18) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA7CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK3_REG (0x00000F1C) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA7CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXTRAINRANK0_REG (0x00000F20) #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA7CH1_CR_TXTRAINRANK1_REG (0x00000F24) #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA7CH1_CR_TXTRAINRANK2_REG (0x00000F28) #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA7CH1_CR_TXTRAINRANK3_REG (0x00000F2C) #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA7CH1_CR_TXPERBITRANK0_REG (0x00000F30) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA7CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK1_REG (0x00000F34) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA7CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK2_REG (0x00000F38) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA7CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK3_REG (0x00000F3C) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA7CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA7CH1_CR_RCOMPDATA0_REG (0x00000F40) #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA7CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA7CH1_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA7CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA7CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA7CH1_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA7CH1_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA7CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA7CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA7CH1_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA7CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA7CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA7CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA7CH1_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA7CH1_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA7CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA7CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA7CH1_CR_RCOMPDATA1_REG (0x00000F44) #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA7CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA7CH1_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA7CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA7CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA7CH1_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA7CH1_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA7CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA7CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA7CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA7CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA7CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA7CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA7CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA7CH1_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA7CH1_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA7CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA7CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA7CH1_CR_TXXTALK_REG (0x00000F48) #define DDRDATA7CH1_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA7CH1_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA7CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA7CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA7CH1_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA7CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA7CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA7CH1_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA7CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA7CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA7CH1_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA7CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA7CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA7CH1_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA7CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA7CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA7CH1_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA7CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA7CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA7CH1_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA7CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA7CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA7CH1_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA7CH1_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA7CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA7CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXOFFSETVDQ_REG (0x00000F4C) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA7CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA7CH1_CR_DDRDATARESERVED_REG (0x00000F50) #define DDRDATA7CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA7CH1_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA7CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA7CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_REG (0x00000F54) #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA7CH1_CR_DLLPITESTANDADC_REG (0x00000F58) #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA7CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA7CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA7CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA7CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA7CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA7CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA7CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA7CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA7CH1_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA7CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA7CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA7CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x00000F5C) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_REG (0x00000F60) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_REG (0x00000F64) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_REG (0x00000F68) #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_OFF ( 0) #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_WID (24) #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_MSK (0x00FFFFFF) #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_MAX (0x00FFFFFF) #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_VrefCtl_DEF (0x000E453A) #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_OFF (24) #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA7CH1_CR_DDRCRVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_REG (0x00000F6C) #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_OFF ( 0) #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_WID (24) #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_MSK (0x00FFFFFF) #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_MAX (0x00FFFFFF) #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_VssHiCtl_DEF (0x004D8238) #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_OFF (24) #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_WID ( 8) #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA7CH1_CR_DDRCRVSSHICONTROL_OutputCode_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x00000F6C) #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA7CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00000F70) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_REG (0x00000F74) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_REG (0x00000F78) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA7CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA8CH0_CR_RXTRAINRANK0_REG (0x00001000) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA8CH0_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA8CH0_CR_RXTRAINRANK1_REG (0x00001004) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA8CH0_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA8CH0_CR_RXTRAINRANK2_REG (0x00001008) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA8CH0_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA8CH0_CR_RXTRAINRANK3_REG (0x0000100C) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA8CH0_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA8CH0_CR_RXPERBITRANK0_REG (0x00001010) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA8CH0_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK1_REG (0x00001014) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA8CH0_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK2_REG (0x00001018) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA8CH0_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK3_REG (0x0000101C) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA8CH0_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXTRAINRANK0_REG (0x00001020) #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA8CH0_CR_TXTRAINRANK1_REG (0x00001024) #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA8CH0_CR_TXTRAINRANK2_REG (0x00001028) #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA8CH0_CR_TXTRAINRANK3_REG (0x0000102C) #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA8CH0_CR_TXPERBITRANK0_REG (0x00001030) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA8CH0_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK1_REG (0x00001034) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA8CH0_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK2_REG (0x00001038) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA8CH0_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK3_REG (0x0000103C) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA8CH0_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA8CH0_CR_RCOMPDATA0_REG (0x00001040) #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA8CH0_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA8CH0_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA8CH0_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA8CH0_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA8CH0_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA8CH0_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA8CH0_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA8CH0_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA8CH0_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA8CH0_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA8CH0_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA8CH0_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA8CH0_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA8CH0_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA8CH0_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA8CH0_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA8CH0_CR_RCOMPDATA1_REG (0x00001044) #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA8CH0_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA8CH0_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA8CH0_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA8CH0_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA8CH0_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA8CH0_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA8CH0_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA8CH0_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA8CH0_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA8CH0_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA8CH0_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA8CH0_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA8CH0_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA8CH0_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA8CH0_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA8CH0_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA8CH0_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA8CH0_CR_TXXTALK_REG (0x00001048) #define DDRDATA8CH0_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA8CH0_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA8CH0_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA8CH0_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA8CH0_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA8CH0_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA8CH0_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA8CH0_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA8CH0_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA8CH0_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA8CH0_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA8CH0_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA8CH0_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA8CH0_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA8CH0_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA8CH0_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA8CH0_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA8CH0_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA8CH0_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA8CH0_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA8CH0_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA8CH0_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA8CH0_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA8CH0_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA8CH0_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA8CH0_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXOFFSETVDQ_REG (0x0000104C) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA8CH0_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA8CH0_CR_DDRDATARESERVED_REG (0x00001050) #define DDRDATA8CH0_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA8CH0_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA8CH0_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA8CH0_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_REG (0x00001054) #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA8CH0_CR_DLLPITESTANDADC_REG (0x00001058) #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA8CH0_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA8CH0_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA8CH0_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA8CH0_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA8CH0_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA8CH0_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA8CH0_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA8CH0_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA8CH0_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA8CH0_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA8CH0_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA8CH0_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_REG (0x0000105C) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_REG (0x00001060) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_REG (0x00001064) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000106C) #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA8CH0_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_REG (0x00001070) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_REG (0x00001074) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_REG (0x00001078) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA8CH0_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #define DDRDATA8CH1_CR_RXTRAINRANK0_REG (0x00001100) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxRcvEnPi_OFF ( 0) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxRcvEnPi_WID ( 9) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsPPi_OFF ( 9) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsPPi_WID ( 6) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsPPi_MSK (0x00007E00) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsPPi_MAX (0x0000003F) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxEq_OFF (15) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxEq_WID ( 5) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxEq_MSK (0x000F8000) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxEq_MAX (0x0000001F) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsNPi_OFF (20) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsNPi_WID ( 6) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsNPi_MSK (0x03F00000) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxDqsNPi_MAX (0x0000003F) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxVref_OFF (26) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxVref_WID ( 6) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxVref_MSK (0xFC000000) #define DDRDATA8CH1_CR_RXTRAINRANK0_RxVref_MAX (0x0000003F) #define DDRDATA8CH1_CR_RXTRAINRANK1_REG (0x00001104) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxRcvEnPi_OFF ( 0) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxRcvEnPi_WID ( 9) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsPPi_OFF ( 9) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsPPi_WID ( 6) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsPPi_MSK (0x00007E00) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsPPi_MAX (0x0000003F) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxEq_OFF (15) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxEq_WID ( 5) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxEq_MSK (0x000F8000) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxEq_MAX (0x0000001F) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsNPi_OFF (20) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsNPi_WID ( 6) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsNPi_MSK (0x03F00000) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxDqsNPi_MAX (0x0000003F) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxVref_OFF (26) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxVref_WID ( 6) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxVref_MSK (0xFC000000) #define DDRDATA8CH1_CR_RXTRAINRANK1_RxVref_MAX (0x0000003F) #define DDRDATA8CH1_CR_RXTRAINRANK2_REG (0x00001108) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxRcvEnPi_OFF ( 0) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxRcvEnPi_WID ( 9) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsPPi_OFF ( 9) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsPPi_WID ( 6) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsPPi_MSK (0x00007E00) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsPPi_MAX (0x0000003F) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxEq_OFF (15) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxEq_WID ( 5) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxEq_MSK (0x000F8000) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxEq_MAX (0x0000001F) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsNPi_OFF (20) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsNPi_WID ( 6) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsNPi_MSK (0x03F00000) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxDqsNPi_MAX (0x0000003F) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxVref_OFF (26) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxVref_WID ( 6) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxVref_MSK (0xFC000000) #define DDRDATA8CH1_CR_RXTRAINRANK2_RxVref_MAX (0x0000003F) #define DDRDATA8CH1_CR_RXTRAINRANK3_REG (0x0000110C) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxRcvEnPi_OFF ( 0) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxRcvEnPi_WID ( 9) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxRcvEnPi_MSK (0x000001FF) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxRcvEnPi_MAX (0x000001FF) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsPPi_OFF ( 9) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsPPi_WID ( 6) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsPPi_MSK (0x00007E00) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsPPi_MAX (0x0000003F) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxEq_OFF (15) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxEq_WID ( 5) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxEq_MSK (0x000F8000) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxEq_MAX (0x0000001F) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsNPi_OFF (20) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsNPi_WID ( 6) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsNPi_MSK (0x03F00000) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxDqsNPi_MAX (0x0000003F) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxVref_OFF (26) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxVref_WID ( 6) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxVref_MSK (0xFC000000) #define DDRDATA8CH1_CR_RXTRAINRANK3_RxVref_MAX (0x0000003F) #define DDRDATA8CH1_CR_RXPERBITRANK0_REG (0x00001110) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane3_OFF (12) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane4_OFF (16) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane5_OFF (20) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane6_OFF (24) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane7_OFF (28) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA8CH1_CR_RXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK1_REG (0x00001114) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane3_OFF (12) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane4_OFF (16) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane5_OFF (20) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane6_OFF (24) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane7_OFF (28) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA8CH1_CR_RXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK2_REG (0x00001118) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane3_OFF (12) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane4_OFF (16) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane5_OFF (20) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane6_OFF (24) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane7_OFF (28) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA8CH1_CR_RXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK3_REG (0x0000111C) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane3_OFF (12) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane4_OFF (16) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane5_OFF (20) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane6_OFF (24) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane7_OFF (28) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA8CH1_CR_RXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXTRAINRANK0_REG (0x00001120) #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_OFF ( 0) #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_WID ( 9) #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_MSK (0x000001FF) #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_MAX (0x000001FF) #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF ( 9) #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_WID ( 9) #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX (0x000001FF) #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare0_OFF (18) #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare0_WID ( 2) #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare0_MSK (0x000C0000) #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare0_MAX (0x00000003) #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_OFF (20) #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_WID ( 6) #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_MSK (0x03F00000) #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_MAX (0x0000003F) #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_OFF (26) #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_WID ( 6) #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_MSK (0xFC000000) #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_MAX (0x0000003F) #define DDRDATA8CH1_CR_TXTRAINRANK1_REG (0x00001124) #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_OFF ( 0) #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_WID ( 9) #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_MSK (0x000001FF) #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_MAX (0x000001FF) #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF ( 9) #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_WID ( 9) #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX (0x000001FF) #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare0_OFF (18) #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare0_WID ( 2) #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare0_MSK (0x000C0000) #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare0_MAX (0x00000003) #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_OFF (20) #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_WID ( 6) #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_MSK (0x03F00000) #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_MAX (0x0000003F) #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_OFF (26) #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_WID ( 6) #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_MSK (0xFC000000) #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_MAX (0x0000003F) #define DDRDATA8CH1_CR_TXTRAINRANK2_REG (0x00001128) #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_OFF ( 0) #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_WID ( 9) #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_MSK (0x000001FF) #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_MAX (0x000001FF) #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF ( 9) #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_WID ( 9) #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX (0x000001FF) #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare0_OFF (18) #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare0_WID ( 2) #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare0_MSK (0x000C0000) #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare0_MAX (0x00000003) #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_OFF (20) #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_WID ( 6) #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_MSK (0x03F00000) #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_MAX (0x0000003F) #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_OFF (26) #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_WID ( 6) #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_MSK (0xFC000000) #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_MAX (0x0000003F) #define DDRDATA8CH1_CR_TXTRAINRANK3_REG (0x0000112C) #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_OFF ( 0) #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_WID ( 9) #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_MSK (0x000001FF) #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_MAX (0x000001FF) #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF ( 9) #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_WID ( 9) #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK (0x0003FE00) #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX (0x000001FF) #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare0_OFF (18) #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare0_WID ( 2) #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare0_MSK (0x000C0000) #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare0_MAX (0x00000003) #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_OFF (20) #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_WID ( 6) #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_MSK (0x03F00000) #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_MAX (0x0000003F) #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_OFF (26) #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_WID ( 6) #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_MSK (0xFC000000) #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_MAX (0x0000003F) #define DDRDATA8CH1_CR_TXPERBITRANK0_REG (0x00001130) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane0_OFF ( 0) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane0_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane0_MSK (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane0_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane1_OFF ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane1_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane1_MSK (0x000000F0) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane1_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane2_OFF ( 8) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane2_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane2_MSK (0x00000F00) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane2_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane3_OFF (12) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane3_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane3_MSK (0x0000F000) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane3_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane4_OFF (16) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane4_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane4_MSK (0x000F0000) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane4_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane5_OFF (20) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane5_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane5_MSK (0x00F00000) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane5_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane6_OFF (24) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane6_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane6_MSK (0x0F000000) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane6_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane7_OFF (28) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane7_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane7_MSK (0xF0000000) #define DDRDATA8CH1_CR_TXPERBITRANK0_Lane7_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK1_REG (0x00001134) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane0_OFF ( 0) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane0_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane0_MSK (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane0_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane1_OFF ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane1_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane1_MSK (0x000000F0) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane1_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane2_OFF ( 8) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane2_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane2_MSK (0x00000F00) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane2_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane3_OFF (12) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane3_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane3_MSK (0x0000F000) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane3_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane4_OFF (16) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane4_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane4_MSK (0x000F0000) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane4_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane5_OFF (20) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane5_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane5_MSK (0x00F00000) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane5_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane6_OFF (24) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane6_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane6_MSK (0x0F000000) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane6_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane7_OFF (28) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane7_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane7_MSK (0xF0000000) #define DDRDATA8CH1_CR_TXPERBITRANK1_Lane7_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK2_REG (0x00001138) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane0_OFF ( 0) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane0_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane0_MSK (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane0_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane1_OFF ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane1_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane1_MSK (0x000000F0) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane1_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane2_OFF ( 8) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane2_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane2_MSK (0x00000F00) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane2_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane3_OFF (12) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane3_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane3_MSK (0x0000F000) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane3_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane4_OFF (16) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane4_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane4_MSK (0x000F0000) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane4_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane5_OFF (20) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane5_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane5_MSK (0x00F00000) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane5_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane6_OFF (24) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane6_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane6_MSK (0x0F000000) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane6_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane7_OFF (28) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane7_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane7_MSK (0xF0000000) #define DDRDATA8CH1_CR_TXPERBITRANK2_Lane7_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK3_REG (0x0000113C) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane0_OFF ( 0) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane0_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane0_MSK (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane0_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane1_OFF ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane1_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane1_MSK (0x000000F0) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane1_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane2_OFF ( 8) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane2_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane2_MSK (0x00000F00) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane2_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane3_OFF (12) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane3_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane3_MSK (0x0000F000) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane3_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane4_OFF (16) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane4_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane4_MSK (0x000F0000) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane4_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane5_OFF (20) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane5_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane5_MSK (0x00F00000) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane5_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane6_OFF (24) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane6_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane6_MSK (0x0F000000) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane6_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane7_OFF (28) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane7_WID ( 4) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane7_MSK (0xF0000000) #define DDRDATA8CH1_CR_TXPERBITRANK3_Lane7_MAX (0x0000000F) #define DDRDATA8CH1_CR_RCOMPDATA0_REG (0x00001140) #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_OFF ( 0) #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_WID ( 6) #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_MSK (0x0000003F) #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_MAX (0x0000003F) #define DDRDATA8CH1_CR_RCOMPDATA0_Spare0_OFF ( 6) #define DDRDATA8CH1_CR_RCOMPDATA0_Spare0_WID ( 3) #define DDRDATA8CH1_CR_RCOMPDATA0_Spare0_MSK (0x000001C0) #define DDRDATA8CH1_CR_RCOMPDATA0_Spare0_MAX (0x00000007) #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_OFF ( 9) #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_WID ( 6) #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_MSK (0x00007E00) #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_MAX (0x0000003F) #define DDRDATA8CH1_CR_RCOMPDATA0_VTComp_OFF (15) #define DDRDATA8CH1_CR_RCOMPDATA0_VTComp_WID ( 5) #define DDRDATA8CH1_CR_RCOMPDATA0_VTComp_MSK (0x000F8000) #define DDRDATA8CH1_CR_RCOMPDATA0_VTComp_MAX (0x0000001F) #define DDRDATA8CH1_CR_RCOMPDATA0_TcoComp_OFF (20) #define DDRDATA8CH1_CR_RCOMPDATA0_TcoComp_WID ( 6) #define DDRDATA8CH1_CR_RCOMPDATA0_TcoComp_MSK (0x03F00000) #define DDRDATA8CH1_CR_RCOMPDATA0_TcoComp_MAX (0x0000003F) #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_OFF (26) #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_WID ( 5) #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_MSK (0x7C000000) #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_MAX (0x0000001F) #define DDRDATA8CH1_CR_RCOMPDATA0_Spare2_OFF (31) #define DDRDATA8CH1_CR_RCOMPDATA0_Spare2_WID ( 1) #define DDRDATA8CH1_CR_RCOMPDATA0_Spare2_MSK (0x80000000) #define DDRDATA8CH1_CR_RCOMPDATA0_Spare2_MAX (0x00000001) #define DDRDATA8CH1_CR_RCOMPDATA1_REG (0x00001144) #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_OFF ( 0) #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_WID ( 6) #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_MSK (0x0000003F) #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_MAX (0x0000003F) #define DDRDATA8CH1_CR_RCOMPDATA1_Spare0_OFF ( 6) #define DDRDATA8CH1_CR_RCOMPDATA1_Spare0_WID ( 3) #define DDRDATA8CH1_CR_RCOMPDATA1_Spare0_MSK (0x000001C0) #define DDRDATA8CH1_CR_RCOMPDATA1_Spare0_MAX (0x00000007) #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_OFF ( 9) #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_WID ( 6) #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_MSK (0x00007E00) #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_MAX (0x0000003F) #define DDRDATA8CH1_CR_RCOMPDATA1_Spare1_OFF (15) #define DDRDATA8CH1_CR_RCOMPDATA1_Spare1_WID ( 1) #define DDRDATA8CH1_CR_RCOMPDATA1_Spare1_MSK (0x00008000) #define DDRDATA8CH1_CR_RCOMPDATA1_Spare1_MAX (0x00000001) #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvDn_OFF (16) #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvDn_WID ( 6) #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvDn_MSK (0x003F0000) #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvDn_MAX (0x0000003F) #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvUp_OFF (22) #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvUp_WID ( 6) #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvUp_MSK (0x0FC00000) #define DDRDATA8CH1_CR_RCOMPDATA1_PanicDrvUp_MAX (0x0000003F) #define DDRDATA8CH1_CR_RCOMPDATA1_LevelShifterComp_OFF (28) #define DDRDATA8CH1_CR_RCOMPDATA1_LevelShifterComp_WID ( 3) #define DDRDATA8CH1_CR_RCOMPDATA1_LevelShifterComp_MSK (0x70000000) #define DDRDATA8CH1_CR_RCOMPDATA1_LevelShifterComp_MAX (0x00000007) #define DDRDATA8CH1_CR_RCOMPDATA1_Spare2_OFF (31) #define DDRDATA8CH1_CR_RCOMPDATA1_Spare2_WID ( 1) #define DDRDATA8CH1_CR_RCOMPDATA1_Spare2_MSK (0x80000000) #define DDRDATA8CH1_CR_RCOMPDATA1_Spare2_MAX (0x00000001) #define DDRDATA8CH1_CR_TXXTALK_REG (0x00001148) #define DDRDATA8CH1_CR_TXXTALK_Lane0_OFF ( 0) #define DDRDATA8CH1_CR_TXXTALK_Lane0_WID ( 4) #define DDRDATA8CH1_CR_TXXTALK_Lane0_MSK (0x0000000F) #define DDRDATA8CH1_CR_TXXTALK_Lane0_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXXTALK_Lane1_OFF ( 4) #define DDRDATA8CH1_CR_TXXTALK_Lane1_WID ( 4) #define DDRDATA8CH1_CR_TXXTALK_Lane1_MSK (0x000000F0) #define DDRDATA8CH1_CR_TXXTALK_Lane1_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXXTALK_Lane2_OFF ( 8) #define DDRDATA8CH1_CR_TXXTALK_Lane2_WID ( 4) #define DDRDATA8CH1_CR_TXXTALK_Lane2_MSK (0x00000F00) #define DDRDATA8CH1_CR_TXXTALK_Lane2_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXXTALK_Lane3_OFF (12) #define DDRDATA8CH1_CR_TXXTALK_Lane3_WID ( 4) #define DDRDATA8CH1_CR_TXXTALK_Lane3_MSK (0x0000F000) #define DDRDATA8CH1_CR_TXXTALK_Lane3_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXXTALK_Lane4_OFF (16) #define DDRDATA8CH1_CR_TXXTALK_Lane4_WID ( 4) #define DDRDATA8CH1_CR_TXXTALK_Lane4_MSK (0x000F0000) #define DDRDATA8CH1_CR_TXXTALK_Lane4_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXXTALK_Lane5_OFF (20) #define DDRDATA8CH1_CR_TXXTALK_Lane5_WID ( 4) #define DDRDATA8CH1_CR_TXXTALK_Lane5_MSK (0x00F00000) #define DDRDATA8CH1_CR_TXXTALK_Lane5_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXXTALK_Lane6_OFF (24) #define DDRDATA8CH1_CR_TXXTALK_Lane6_WID ( 4) #define DDRDATA8CH1_CR_TXXTALK_Lane6_MSK (0x0F000000) #define DDRDATA8CH1_CR_TXXTALK_Lane6_MAX (0x0000000F) #define DDRDATA8CH1_CR_TXXTALK_Lane7_OFF (28) #define DDRDATA8CH1_CR_TXXTALK_Lane7_WID ( 4) #define DDRDATA8CH1_CR_TXXTALK_Lane7_MSK (0xF0000000) #define DDRDATA8CH1_CR_TXXTALK_Lane7_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXOFFSETVDQ_REG (0x0000114C) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane0_OFF ( 0) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane0_WID ( 4) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane0_MSK (0x0000000F) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane0_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane1_OFF ( 4) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane1_WID ( 4) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane1_MSK (0x000000F0) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane1_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane2_OFF ( 8) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane2_WID ( 4) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane2_MSK (0x00000F00) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane2_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane3_OFF (12) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane3_WID ( 4) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane3_MSK (0x0000F000) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane3_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane4_OFF (16) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane4_WID ( 4) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane4_MSK (0x000F0000) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane4_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane5_OFF (20) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane5_WID ( 4) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane5_MSK (0x00F00000) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane5_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane6_OFF (24) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane6_WID ( 4) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane6_MSK (0x0F000000) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane6_MAX (0x0000000F) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane7_OFF (28) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane7_WID ( 4) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane7_MSK (0xF0000000) #define DDRDATA8CH1_CR_RXOFFSETVDQ_Lane7_MAX (0x0000000F) #define DDRDATA8CH1_CR_DDRDATARESERVED_REG (0x00001150) #define DDRDATA8CH1_CR_DDRDATARESERVED_Spare_OFF ( 0) #define DDRDATA8CH1_CR_DDRDATARESERVED_Spare_WID (32) #define DDRDATA8CH1_CR_DDRDATARESERVED_Spare_MSK (0xFFFFFFFF) #define DDRDATA8CH1_CR_DDRDATARESERVED_Spare_MAX (0xFFFFFFFF) #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_REG (0x00001154) #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF ( 0) #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID ( 9) #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK (0x000001FF) #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX (0x000001FF) #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_OFF ( 9) #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_WID (23) #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_MSK (0xFFFFFE00) #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_MAX (0x007FFFFF) #define DDRDATA8CH1_CR_DLLPITESTANDADC_REG (0x00001158) #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_OFF ( 0) #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_WID ( 1) #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_MSK (0x00000001) #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_MAX (0x00000001) #define DDRDATA8CH1_CR_DLLPITESTANDADC_RunTest_DEF (0x00000000) #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_OFF ( 1) #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_WID ( 1) #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_MSK (0x00000002) #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_MAX (0x00000001) #define DDRDATA8CH1_CR_DLLPITESTANDADC_Load_DEF (0x00000000) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_OFF ( 2) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_WID ( 1) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_MSK (0x00000004) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_MAX (0x00000001) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeHVM_DEF (0x00000000) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_OFF ( 3) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_WID ( 1) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_MSK (0x00000008) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_MAX (0x00000001) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeDV_DEF (0x00000000) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_OFF ( 4) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_WID ( 1) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_MSK (0x00000010) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_MAX (0x00000001) #define DDRDATA8CH1_CR_DLLPITESTANDADC_ModeADC_DEF (0x00000000) #define DDRDATA8CH1_CR_DLLPITESTANDADC_LoadCount_OFF ( 5) #define DDRDATA8CH1_CR_DLLPITESTANDADC_LoadCount_WID (10) #define DDRDATA8CH1_CR_DLLPITESTANDADC_LoadCount_MSK (0x00007FE0) #define DDRDATA8CH1_CR_DLLPITESTANDADC_LoadCount_MAX (0x000003FF) #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_OFF (15) #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_WID (10) #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_MSK (0x01FF8000) #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_MAX (0x000003FF) #define DDRDATA8CH1_CR_DLLPITESTANDADC_CountStatus_DEF (0x00000000) #define DDRDATA8CH1_CR_DLLPITESTANDADC_Spare_OFF (25) #define DDRDATA8CH1_CR_DLLPITESTANDADC_Spare_WID ( 7) #define DDRDATA8CH1_CR_DLLPITESTANDADC_Spare_MSK (0xFE000000) #define DDRDATA8CH1_CR_DLLPITESTANDADC_Spare_MAX (0x0000007F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_REG (0x0000115C) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF ( 0) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID ( 6) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK (0x0000003F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX (0x0000003F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF ( 6) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID ( 6) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK (0x00000FC0) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX (0x0000003F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF (12) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID ( 5) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK (0x0001F000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX (0x0000001F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF (17) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID ( 5) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK (0x003E0000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX (0x0000001F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_OFF (22) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_WID ( 5) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MSK (0x07C00000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_MAX (0x0000001F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqTcoCompOffset_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF (27) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID ( 5) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK (0xF8000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX (0x0000001F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_REG (0x00001160) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_OFF ( 0) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_WID ( 4) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_MSK (0x0000000F) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_MAX (0x0000000F) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_OFF ( 4) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_WID ( 2) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_MSK (0x00000030) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_MAX (0x00000003) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF ( 6) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK (0x00000040) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF ( 7) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID ( 3) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK (0x00000380) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX (0x00000007) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF (10) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID ( 3) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK (0x00001C00) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX (0x00000007) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF (13) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID ( 4) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK (0x0001E000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX (0x0000000F) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF (17) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID ( 3) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK (0x000E0000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX (0x00000007) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF (20) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID ( 4) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK (0x00F00000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX (0x0000000F) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF (24) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID ( 3) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK (0x07000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX (0x00000007) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_OFF (27) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_WID ( 3) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MSK (0x38000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_MAX (0x00000007) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_BurstEndODTDelay_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_OFF (30) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MSK (0x40000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_LpDdrLongOdtEn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_OFF (31) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_MSK (0x80000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_Rsvd1_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_REG (0x00001164) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF ( 0) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID ( 5) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK (0x0000001F) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX (0x0000001F) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF ( 5) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK (0x00000020) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF ( 6) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK (0x00000040) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_OFF ( 7) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_WID ( 2) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_MSK (0x00000180) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_MAX (0x00000003) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LeakerComp_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_OFF ( 9) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_WID ( 4) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MSK (0x00001E00) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_MAX (0x0000000F) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDqsAmpOffset_DEF (0x00000008) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF (13) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID ( 5) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK (0x0003E000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX (0x0000001F) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF (0x00000011) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF (18) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK (0x00040000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_OFF (19) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_WID (13) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_MSK (0xFFF80000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_MAX (0x00001FFF) #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Spare_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_REG (0x0000116C) #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_OFF ( 0) #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_WID (24) #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MSK (0x00FFFFFF) #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_MAX (0x00FFFFFF) #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_VssHiOrVrefCtl_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_OFF (24) #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_WID ( 8) #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MSK (0xFF000000) #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_MAX (0x000000FF) #define DDRDATA8CH1_CR_DDRCRVSSHIORVREFCONTROL_OutputCode_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_REG (0x00001170) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF ( 0) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID ( 6) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK (0x0000003F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX (0x0000003F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF ( 6) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID ( 6) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK (0x00000FC0) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX (0x0000003F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF (12) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID ( 6) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK (0x0003F000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX (0x0000003F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF (18) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID ( 6) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK (0x00FC0000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX (0x0000003F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF (24) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID ( 7) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK (0x7F000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX (0x0000007F) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_OFF (31) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MSK (0x80000000) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_Spare_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_REG (0x00001174) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF ( 0) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK (0x00000002) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF ( 2) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK (0x00000004) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF ( 3) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK (0x00000008) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_OFF ( 4) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_MSK (0x00000010) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_OFF ( 5) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_MSK (0x00000020) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RfOn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF ( 6) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK (0x00000040) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF ( 7) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK (0x00000080) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF ( 8) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK (0x00000100) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF ( 9) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK (0x00000200) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF (10) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK (0x00000400) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF (11) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK (0x00000800) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_OFF (12) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_MSK (0x00001000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxLong_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF (13) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID ( 2) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK (0x00006000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX (0x00000003) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF (15) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID ( 3) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK (0x00038000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX (0x00000007) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_OFF (18) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MSK (0x00040000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DriverSegmentEnable_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_OFF (19) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MSK (0x00080000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DataVccddqHi_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_OFF (20) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MSK (0x00100000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRd_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_OFF (21) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MSK (0x00200000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFWr_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_OFF (22) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_WID ( 2) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MSK (0x00C00000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_MAX (0x00000003) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ReadRFRank_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF (24) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK (0x01000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF (25) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK (0x02000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF (26) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK (0x04000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF (27) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK (0x08000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF (28) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK (0x10000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_OFF (29) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MSK (0x20000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EnReadPreamble_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF (30) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK (0x40000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF (31) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID ( 1) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK (0x80000000) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_REG (0x00001178) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_OFF ( 0) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_WID ( 7) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MSK (0x0000007F) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_MAX (0x0000007F) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_CAVrefCtl_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_OFF ( 7) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_WID ( 7) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MSK (0x00003F80) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_MAX (0x0000007F) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch1VrefCtl_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_OFF (14) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_WID ( 7) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MSK (0x001FC000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_MAX (0x0000007F) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Ch0VrefCtl_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_OFF (21) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_WID ( 1) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MSK (0x00200000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCA_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_OFF (22) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_WID ( 1) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MSK (0x00400000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh1_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_OFF (23) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_WID ( 1) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MSK (0x00800000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_EnDimmVrefCh0_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_OFF (24) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_WID ( 2) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MSK (0x03000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_MAX (0x00000003) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_HiZTimerCtrl_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_OFF (26) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_WID ( 1) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MSK (0x04000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_VccddqHiQnnnH_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_OFF (27) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_WID ( 2) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_MSK (0x18000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_MAX (0x00000003) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_Rsvd_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_OFF (29) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_WID ( 1) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_MSK (0x20000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_caSlowBW_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_OFF (30) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_WID ( 1) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MSK (0x40000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch0SlowBW_DEF (0x00000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_OFF (31) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_WID ( 1) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MSK (0x80000000) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_MAX (0x00000001) #define DDRDATA8CH1_CR_DDRCRVREFADJUST1_ch1SlowBW_DEF (0x00000000) #pragma pack(pop) #endif // __McIoData_h__