2013 SharkBay Processor Reference Code API: Todo List

2013 SharkBay Processor Reference Code API
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Todo List
File PpmGlobalNvsArea.h
The format is derived from the ACPI reference code, version 0.95.
Generated on Thu Jun 20 2013 01:47:38 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: Deprecated List

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Deprecated List
Member _PPM_TURBO_SETTINGS::DdrPowerLimit1
in Powermgmt policy
Member _PPM_TURBO_SETTINGS::DdrPowerLimit1Time
in Powermgmt policy
Member _PPM_TURBO_SETTINGS::DdrPowerLimit2
in Powermgmt policy
Member _PPM_TURBO_SETTINGS::DdrPowerLimitLock
in Powermgmt policy
Member CPU_CONFIG::DcaPrefetchDelayValue
Deprecated for Client (Server specific)
Member CPU_CONFIG::DcaState
Deprecated for Client (Server specific)
Member CPU_CONFIG::FastString
Member CPU_CONFIG::MachineCheckStatusClean
Member CPU_CONFIG::VirtualWireMode
Member PPM_FUNCTION_ENABLES::AutoThermalReporting
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
Member PPM_FUNCTION_ENABLES::BiProcHot
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
Member PPM_FUNCTION_ENABLES::DisableProcHotOut
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
Member PPM_FUNCTION_ENABLES::DisableVRThermalAlert
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
Member PPM_FUNCTION_ENABLES::ProcHotResponce
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
Member PPM_FUNCTION_ENABLES::ThermalMonitor
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
Member PPM_FUNCTION_ENABLES::TStates
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.


2013 SharkBay Processor Reference Code API: Class List

  • Class List
  • Class Index
  • Class Members
Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
_DXE_CPU_INFO_PROTOCOL | Interface structure for the CPU Info Protocol
_DXE_CPU_PLATFORM_POLICY_PROTOCOL | The CPU platform policy protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure the processor
_EFI_MP_SERVICES_PROTOCOL | This information is basically from Intel Platform Innovation Framework for EFI Multiprocessor Services Protocol Specification
_EFI_PI_MP_SERVICES_PROTOCOL | When installed, the MP Services Protocol produces a collection of services that are needed for MP management
_EFI_SMM_THUNK_PROTOCOL |
_OC_MAILBOX_COMMAND |
_OC_MAILBOX_FULL |
_OC_MAILBOX_INTERFACE |
_OC_MAILBOX_ITEM |
_PCODE_MAILBOX_FULL |
_PCODE_MAILBOX_INTERFACE |
_PEI_CACHE_PPI | Platform code can use this interface to arrange MTRR configuration in PEI phase
_PEI_CPU_PLATFORM_POLICY_PPI | CPU Platform Policy PPI definition, this PPI provides interface to configure the processor
_PFAT_PROTOCOL | This protocol provides all the services required for flash writes/erases via PFAT PFAT Module can only be launched from SMM, this means that all flash writes & erases that BIOS needs to do must flow thru SMI Handler and so dependency on SMM_BASE_PROTOCOL for installing PFAT Protocol
_PPM_CUSTOM_CTDP | This structure is used to configure custom ConfigTdp level settings
_PPM_CUSTOM_CTDP_TABLE | PPM Custom ConfigTdp Settings
_PPM_GLOBAL_NVS_AREA_PROTOCOL | PPM Global NVS Area Protocol
_PPM_LOCK_ENABLES | This structure is used to control enabled / disabled various PPM MSR lock settings
_PPM_TURBO_SETTINGS | This structure is used to describe various PPM turbo settings
ACPI_CPU_DATA |
BIOS_OS_DATA_REGION |
BOOT_GUARD_CONFIG |
CORE_RATIO_LIMITS_ITEM |
CPU_CONFIG | General CPU feature Configuration for all processor features enabling bit definitions are in this field
CPU_CONFIG_PPI | General CPU features configration for all processor features enabling / configuration bit definitions are in this field
CPU_PHYSICAL_LOCATION |
EFI_CPU_MICROCODE_EXTENDED_TABLE |
EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER |
EFI_CPU_MICROCODE_HEADER |
EFI_CPU_PHYSICAL_LOCATION | Structure that describes the pyhiscal location of a logical CPU
EFI_CPU_VERSION |
EFI_CPUID_REGISTER |
EFI_DETAILED_CPU_INFO |
EFI_MP_HEALTH |
EFI_MP_HEALTH_FLAGS |
EFI_MP_PROC_CONTEXT |
EFI_PROCESSOR_INFORMATION | Structure that describes information about a logical CPU
GLOBAL_CONFIG_ITEM |
HEAP_BIOS_SPEC_VER_ELEMENT |
HEAP_BIOSACM_ELEMENT |
HEAP_EXT_DATA_ELEMENT |
OC_CAPABILITIES_ITEM |
OC_LIBRARY_COMMAND | OC Library structures
OVERCLOCKING_CONFIG_PPI | Overclocking Configuration controls which use the CPU overclocking mailbox interface are defined in this structure
PFAT_CONFIG | PFAT Configuration for all processor security features configuration structures are in this field
PFAT_HOB | HOB used to pass data through every phase of PFAT Bios PFAT Bios code is executed in PEI, DXE and SMM and HOB is the only method to properly pass data between every phase
PFAT_LOG | PFAT Log The logging facility is used to communicate detailed information regarding the execution of a PFAT script from the SMI handler which invoked the PFAT module itself
PHYSICAL_LOCATION |
PL1_THERMAL_CONTROL_FLOOR |
PLATFORM_CPU_INFORMATION | Platform Specific Processor Information
POWER_MGMT_CONFIG | Power management Configuration for all processor Power Management features enabling definitions are in this field
POWER_MGMT_CONFIG_PPI | Power management Configuration for all Processor Power Management Features Configs are in this field
PPDT | PFAT Platform Data Table (PPDT) Provides platform specific data required by PFAT Module
PPM_CTDP_LEVEL_SETTINGS |
PPM_CUSTOM_RATIO_TABLE | This structure is used to describe the custom processor ratio table desired by the platform
PPM_FUNCTION_ENABLES | This structure is used to describe which of the PPM functions will be enabled by PPM implementation
PPM_GLOBAL_NVS_AREA | Global NVS Area definition
PSEUDO_DESCRIPTOR |
PUP |
PUP_HEADER | PFAT Update Package Header
SECURITY_CONFIG | All processor security features enabling definitions are in this field
SECURITY_CONFIG_PPI | Security Configuration
SFAM_DATA |
SMRAM_CPU_DATA |
SMRAM_CPU_DATA_ADDRESS |
SVID_CONFIG_ITEM |
THERM_FUNCTION_ENABLES | This structure is used to describe which of the Thermal functions will be enabled by Thermal implementation
THUNK16_CONTEXT | Byte packed structure for an 16-bit real mode thunks
TXT_CONFIG |
TXT_FUNCTION_CONFIG | TxT Platform Configuration
TXT_INFO_DATA |
TXT_INFO_HOB |
VF_MAILBOX_COMMAND_DATA |
VOLTAGE_FREQUENCY_ITEM |
VOLTAGE_FREQUENCY_SETTINGS |


2013 SharkBay Processor Reference Code API: _DXE_CPU_INFO_PROTOCOL Struct Reference

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  • Class Members
Public Attributes
_DXE_CPU_INFO_PROTOCOL Struct Reference

Interface structure for the CPU Info Protocol. More...

#include <CpuInfo.h>

List of all members.

Public Attributes

UINT8 | Revision
Revision for the protocol structure.
UINT32 | RcVersion
Processor Features information.
UINT64 | CpuCommonFeatures
CPU Supported Feature. Output from CPU code.

Detailed Description

Interface structure for the CPU Info Protocol.

Definition at line 70 of file CpuInfo.h.

The documentation for this struct was generated from the following file:
  • CpuInfo.h


2013 SharkBay Processor Reference Code API: Member List

_DXE_CPU_INFO_PROTOCOL Member List
This is the complete list of members for _DXE_CPU_INFO_PROTOCOL, including all inherited members.
CpuCommonFeatures | _DXE_CPU_INFO_PROTOCOL
RcVersion | _DXE_CPU_INFO_PROTOCOL
Revision | _DXE_CPU_INFO_PROTOCOL


2013 SharkBay Processor Reference Code API: _DXE_CPU_PLATFORM_POLICY_PROTOCOL Struct Reference

Public Attributes
_DXE_CPU_PLATFORM_POLICY_PROTOCOL Struct Reference

The CPU platform policy protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure the processor. More...

#include <CpuPlatformPolicy.h>

Collaboration diagram for _DXE_CPU_PLATFORM_POLICY_PROTOCOL:
[legend]

List of all members.

Public Attributes

UINT8 Revision
This member specifies the revision of the CPU Policy protocol.
CPU_CONFIG * CpuConfig
Processor standard features configuration.
POWER_MGMT_CONFIG * PowerMgmtConfig
Processor power management features configuration.
SECURITY_CONFIG * SecurityConfig
Processor security features configuration.

Detailed Description

The CPU platform policy protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure the processor.

Platform code needs to provide the information for processor drivers to finish the initialization.

Definition at line 315 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

Member Data Documentation

UINT8 _DXE_CPU_PLATFORM_POLICY_PROTOCOL::Revision

This member specifies the revision of the CPU Policy protocol.

This field is used to indicate backwards compatible changes to the protocol. Platform code that produces this protocol must fill with the correct revision value for the PCH reference code to correctly interpret the content of the protocol fields.

Definition at line 321 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

_DXE_CPU_PLATFORM_POLICY_PROTOCOL Member List
This is the complete list of members for _DXE_CPU_PLATFORM_POLICY_PROTOCOL, including all inherited members.
CpuConfig | _DXE_CPU_PLATFORM_POLICY_PROTOCOL
PowerMgmtConfig | _DXE_CPU_PLATFORM_POLICY_PROTOCOL
Revision | _DXE_CPU_PLATFORM_POLICY_PROTOCOL
SecurityConfig | _DXE_CPU_PLATFORM_POLICY_PROTOCOL


2013 SharkBay Processor Reference Code API: _EFI_MP_SERVICES_PROTOCOL Struct Reference

Public Attributes
_EFI_MP_SERVICES_PROTOCOL Struct Reference

This information is basically from Intel Platform Innovation Framework for EFI Multiprocessor Services Protocol Specification. More...

#include <MpService.h>

Collaboration diagram for _EFI_MP_SERVICES_PROTOCOL:
[legend]

List of all members.

Public Attributes

EFI_MP_SERVICES_GET_GENERAL_MP_INFO | GetGeneralMPInfo
This service retrieves general information of multiprocessors in the system.
EFI_MP_SERVICES_GET_PROCESSOR_CONTEXT | GetProcessorContext
This service gets detailed MP-related information of the requested processor.
EFI_MP_SERVICES_STARTUP_ALL_APS | StartupAllAPs
This function is used to dispatch all enabled APs to the function specified by Procedure.
EFI_MP_SERVICES_STARTUP_THIS_AP | StartupThisAP
This function is used to dispatch one enabled AP to the function provided by the caller.
EFI_MP_SERVICES_SWITCH_BSP | SwitchBSP
This service switches the requested AP to be the BSP from that point onward.
EFI_MP_SERVICES_SEND_IPI | SendIPI
This service sends an IPI to a specified AP.
EFI_MP_SERVICES_ENABLEDISABLEAP | EnableDisableAP
This service lets the caller enable or disable an AP.
EFI_MP_SERVICES_WHOAMI | WhoAmI
This service lets the caller processor get its handle number, with which any processor in the system can be uniquely identified.

Detailed Description

This information is basically from Intel Platform Innovation Framework for EFI Multiprocessor Services Protocol Specification.

When installed, the MP Services Protocol produces a collection of services that are needed for MP management, such as initialization and management of application processors.

Definition at line 178 of file MpService.h.

The documentation for this struct was generated from the following file:
  • MpService.h


2013 SharkBay Processor Reference Code API: Member List

_EFI_MP_SERVICES_PROTOCOL Member List
This is the complete list of members for _EFI_MP_SERVICES_PROTOCOL, including all inherited members.
EnableDisableAP | _EFI_MP_SERVICES_PROTOCOL
GetGeneralMPInfo | _EFI_MP_SERVICES_PROTOCOL
GetProcessorContext | _EFI_MP_SERVICES_PROTOCOL
SendIPI | _EFI_MP_SERVICES_PROTOCOL
StartupAllAPs | _EFI_MP_SERVICES_PROTOCOL
StartupThisAP | _EFI_MP_SERVICES_PROTOCOL
SwitchBSP | _EFI_MP_SERVICES_PROTOCOL
WhoAmI | _EFI_MP_SERVICES_PROTOCOL


2013 SharkBay Processor Reference Code API: _EFI_PI_MP_SERVICES_PROTOCOL Struct Reference

Public Attributes
_EFI_PI_MP_SERVICES_PROTOCOL Struct Reference

When installed, the MP Services Protocol produces a collection of services that are needed for MP management. More...

#include <PiMpService.h>

Collaboration diagram for _EFI_PI_MP_SERVICES_PROTOCOL:
[legend]

List of all members.

Public Attributes

EFI_PI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors
This service retrieves the number of logical processor in the platform and the number of those logical processors that are enabled on this boot.
EFI_PI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo
This service retrieves detailed MP-related information about any processor on the platform.
EFI_PI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs
This service executes a caller provided function on all enabled APs.
EFI_PI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP
This service lets the caller get one enabled AP to execute a caller-provided function.
EFI_PI_MP_SERVICES_SWITCH_BSP SwitchBSP
This service switches the requested AP to be the BSP from that point onward.
EFI_PI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP
This service lets the caller enable or disable an AP from this point onward.
EFI_PI_MP_SERVICES_WHOAMI WhoAmI
This return the handle number for the calling processor.

Detailed Description

When installed, the MP Services Protocol produces a collection of services that are needed for MP management.

Before the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, the module that produces this protocol is required to place all APs into an idle state whenever the APs are disabled or the APs are not executing code as requested through the StartupAllAPs() or StartupThisAP() services. The idle state of an AP before the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled is implementation dependent.

After the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, all the APs must be placed in the OS compatible CPU state as defined by the UEFI Specification. Implementations of this protocol may use the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT to force APs into the OS compatible state as defined by the UEFI Specification. Modules that use this protocol must guarantee that all non-blocking mode requests on all APs have been completed before the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled. Since the order that event notification functions in the same event group are executed is not deterministic, an event of type EFI_EVENT_GROUP_READY_TO_BOOT cannot be used to guarantee that APs have completed their non-blocking mode requests.

When the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, the StartAllAPs() and StartupThisAp() services must no longer support non-blocking mode requests. The support for SwitchBSP() and EnableDisableAP() may no longer be supported after this event is signaled. Since UEFI Applications and UEFI OS Loaders execute after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, these UEFI images must be aware that the functionality of this protocol may be reduced.

Definition at line 465 of file PiMpService.h.

Member Data Documentation

EFI_PI_MP_SERVICES_ENABLEDISABLEAP _EFI_PI_MP_SERVICES_PROTOCOL::EnableDisableAP

This service lets the caller enable or disable an AP from this point onward.

This service may only be called from the BSP.

Definition at line 491 of file PiMpService.h.

EFI_PI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS _EFI_PI_MP_SERVICES_PROTOCOL::GetNumberOfProcessors

This service retrieves the number of logical processor in the platform and the number of those logical processors that are enabled on this boot.

This service may only be called from the BSP.

Definition at line 470 of file PiMpService.h.

EFI_PI_MP_SERVICES_WHOAMI _EFI_PI_MP_SERVICES_PROTOCOL::WhoAmI

This return the handle number for the calling processor.

This service may be called from the BSP and APs.

Definition at line 495 of file PiMpService.h.

The documentation for this struct was generated from the following file:
  • PiMpService.h


2013 SharkBay Processor Reference Code API: Member List

_EFI_PI_MP_SERVICES_PROTOCOL Member List
This is the complete list of members for _EFI_PI_MP_SERVICES_PROTOCOL, including all inherited members.
EnableDisableAP | _EFI_PI_MP_SERVICES_PROTOCOL
GetNumberOfProcessors | _EFI_PI_MP_SERVICES_PROTOCOL
GetProcessorInfo | _EFI_PI_MP_SERVICES_PROTOCOL
StartupAllAPs | _EFI_PI_MP_SERVICES_PROTOCOL
StartupThisAP | _EFI_PI_MP_SERVICES_PROTOCOL
SwitchBSP | _EFI_PI_MP_SERVICES_PROTOCOL
WhoAmI | _EFI_PI_MP_SERVICES_PROTOCOL


2013 SharkBay Processor Reference Code API: _EFI_SMM_THUNK_PROTOCOL Struct Reference

Public Attributes
_EFI_SMM_THUNK_PROTOCOL Struct Reference

List of all members.

Public Attributes

EFI_SMM_FARCALL86 | FarCall86
EFI_SMM_INTCALL86 | IntCall86

Detailed Description

Definition at line 57 of file SmmThunk.h.

The documentation for this struct was generated from the following file:
  • SmmThunk.h


2013 SharkBay Processor Reference Code API: Member List

_EFI_SMM_THUNK_PROTOCOL Member List
This is the complete list of members for _EFI_SMM_THUNK_PROTOCOL, including all inherited members.
FarCall86 (defined in _EFI_SMM_THUNK_PROTOCOL) | _EFI_SMM_THUNK_PROTOCOL
IntCall86 (defined in _EFI_SMM_THUNK_PROTOCOL) | _EFI_SMM_THUNK_PROTOCOL


2013 SharkBay Processor Reference Code API: _OC_MAILBOX_COMMAND Union Reference

Public Attributes
_OC_MAILBOX_COMMAND Union Reference

List of all members.

Public Attributes

UINT32 InterfaceData
struct {
UINT8 CommandCompletion: 8
UINT8 Param1: 8
UINT8 Param2: 8
UINT8 Reserved: 7
UINT8 RunBusy: 1
} Fields

Detailed Description

Definition at line 129 of file OverclockingLibrary.h.

The documentation for this union was generated from the following file:
  • OverclockingLibrary.h


2013 SharkBay Processor Reference Code API: Member List

_OC_MAILBOX_COMMAND Member List
This is the complete list of members for _OC_MAILBOX_COMMAND, including all inherited members.
CommandCompletion (defined in _OC_MAILBOX_COMMAND) | _OC_MAILBOX_COMMAND
Fields (defined in _OC_MAILBOX_COMMAND) | _OC_MAILBOX_COMMAND
InterfaceData (defined in _OC_MAILBOX_COMMAND) | _OC_MAILBOX_COMMAND
Param1 (defined in _OC_MAILBOX_COMMAND) | _OC_MAILBOX_COMMAND
Param2 (defined in _OC_MAILBOX_COMMAND) | _OC_MAILBOX_COMMAND
Reserved (defined in _OC_MAILBOX_COMMAND) | _OC_MAILBOX_COMMAND
RunBusy (defined in _OC_MAILBOX_COMMAND) | _OC_MAILBOX_COMMAND


2013 SharkBay Processor Reference Code API: _OC_MAILBOX_FULL Struct Reference

Public Attributes
_OC_MAILBOX_FULL Struct Reference
Collaboration diagram for _OC_MAILBOX_FULL:
[legend]

List of all members.

Public Attributes

UINT32 | Data
OC_MAILBOX_INTERFACE | Interface

Detailed Description

Definition at line 120 of file CpuPlatformLib.h.

The documentation for this struct was generated from the following file:
  • CpuPlatformLib.h


2013 SharkBay Processor Reference Code API: Member List

_OC_MAILBOX_FULL Member List
This is the complete list of members for _OC_MAILBOX_FULL, including all inherited members.
Data (defined in _OC_MAILBOX_FULL) | _OC_MAILBOX_FULL
Interface (defined in _OC_MAILBOX_FULL) | _OC_MAILBOX_FULL


2013 SharkBay Processor Reference Code API: _OC_MAILBOX_INTERFACE Union Reference

Public Attributes
_OC_MAILBOX_INTERFACE Union Reference

List of all members.

Public Attributes

UINT32 InterfaceData
struct {
UINT8 CommandCompletion: 8
UINT8 Param1: 8
UINT8 Param2: 8
UINT8 Reserved: 7
UINT8 RunBusy: 1
} Fields

Detailed Description

Definition at line 109 of file CpuPlatformLib.h.

The documentation for this union was generated from the following file:
  • CpuPlatformLib.h


2013 SharkBay Processor Reference Code API: Member List

_OC_MAILBOX_INTERFACE Member List
This is the complete list of members for _OC_MAILBOX_INTERFACE, including all inherited members.
CommandCompletion (defined in _OC_MAILBOX_INTERFACE) | _OC_MAILBOX_INTERFACE
Fields (defined in _OC_MAILBOX_INTERFACE) | _OC_MAILBOX_INTERFACE
InterfaceData (defined in _OC_MAILBOX_INTERFACE) | _OC_MAILBOX_INTERFACE
Param1 (defined in _OC_MAILBOX_INTERFACE) | _OC_MAILBOX_INTERFACE
Param2 (defined in _OC_MAILBOX_INTERFACE) | _OC_MAILBOX_INTERFACE
Reserved (defined in _OC_MAILBOX_INTERFACE) | _OC_MAILBOX_INTERFACE
RunBusy (defined in _OC_MAILBOX_INTERFACE) | _OC_MAILBOX_INTERFACE


2013 SharkBay Processor Reference Code API: _OC_MAILBOX_ITEM Struct Reference

Public Attributes
_OC_MAILBOX_ITEM Struct Reference
Collaboration diagram for _OC_MAILBOX_ITEM:
[legend]

List of all members.

Public Attributes

UINT32 | Data
OC_MAILBOX_COMMAND | Interface

Detailed Description

Definition at line 140 of file OverclockingLibrary.h.

The documentation for this struct was generated from the following file:
  • OverclockingLibrary.h


2013 SharkBay Processor Reference Code API: Member List

_OC_MAILBOX_ITEM Member List
This is the complete list of members for _OC_MAILBOX_ITEM, including all inherited members.
Data (defined in _OC_MAILBOX_ITEM) | _OC_MAILBOX_ITEM
Interface (defined in _OC_MAILBOX_ITEM) | _OC_MAILBOX_ITEM


2013 SharkBay Processor Reference Code API: _PCODE_MAILBOX_FULL Struct Reference

Public Attributes
_PCODE_MAILBOX_FULL Struct Reference
Collaboration diagram for _PCODE_MAILBOX_FULL:
[legend]

List of all members.

Public Attributes

PCODE_MAILBOX_INTERFACE | Interface
UINT32 | Data

Detailed Description

Definition at line 148 of file CpuPlatformLib.h.

The documentation for this struct was generated from the following file:
  • CpuPlatformLib.h


2013 SharkBay Processor Reference Code API: Member List

_PCODE_MAILBOX_FULL Member List
This is the complete list of members for _PCODE_MAILBOX_FULL, including all inherited members.
Data (defined in _PCODE_MAILBOX_FULL) | _PCODE_MAILBOX_FULL
Interface (defined in _PCODE_MAILBOX_FULL) | _PCODE_MAILBOX_FULL


2013 SharkBay Processor Reference Code API: _PCODE_MAILBOX_INTERFACE Union Reference

Public Attributes
_PCODE_MAILBOX_INTERFACE Union Reference

List of all members.

Public Attributes

UINT32 InterfaceData
struct {
UINT32 Command: 8
UINT32 Address: 21
UINT32 Reserved: 2
UINT32 RunBusy: 1
} Fields

Detailed Description

Definition at line 138 of file CpuPlatformLib.h.

The documentation for this union was generated from the following file:
  • CpuPlatformLib.h


2013 SharkBay Processor Reference Code API: Member List

_PCODE_MAILBOX_INTERFACE Member List
This is the complete list of members for _PCODE_MAILBOX_INTERFACE, including all inherited members.
Address (defined in _PCODE_MAILBOX_INTERFACE) | _PCODE_MAILBOX_INTERFACE
Command (defined in _PCODE_MAILBOX_INTERFACE) | _PCODE_MAILBOX_INTERFACE
Fields (defined in _PCODE_MAILBOX_INTERFACE) | _PCODE_MAILBOX_INTERFACE
InterfaceData (defined in _PCODE_MAILBOX_INTERFACE) | _PCODE_MAILBOX_INTERFACE
Reserved (defined in _PCODE_MAILBOX_INTERFACE) | _PCODE_MAILBOX_INTERFACE
RunBusy (defined in _PCODE_MAILBOX_INTERFACE) | _PCODE_MAILBOX_INTERFACE


2013 SharkBay Processor Reference Code API: _PEI_CACHE_PPI Struct Reference

Public Attributes
_PEI_CACHE_PPI Struct Reference

Platform code can use this interface to arrange MTRR configuration in PEI phase. More...

#include <Cache.h>

List of all members.

Public Attributes

PEI_SET_CACHE_PPI | SetCache
Set MTRR configuration for a memory region.
PEI_RESET_CACHE_PPI | ResetCache
Clean up MTRR in MTRR buffer.
PEI_ACTIVATE_CACHE_PPI | ActivateCache
Disable NEM if in NEM mode, and sync MTRR configuration from buffer to MSR.

Detailed Description

Platform code can use this interface to arrange MTRR configuration in PEI phase.

Definition at line 69 of file Cache.h.

The documentation for this struct was generated from the following file:
  • Cache.h


2013 SharkBay Processor Reference Code API: Member List

_PEI_CACHE_PPI Member List
This is the complete list of members for _PEI_CACHE_PPI, including all inherited members.
ActivateCache | _PEI_CACHE_PPI
ResetCache | _PEI_CACHE_PPI
SetCache | _PEI_CACHE_PPI


2013 SharkBay Processor Reference Code API: _PEI_CPU_PLATFORM_POLICY_PPI Struct Reference

Public Attributes
_PEI_CPU_PLATFORM_POLICY_PPI Struct Reference

CPU Platform Policy PPI definition, this PPI provides interface to configure the processor. More...

#include <CpuPlatformPolicy.h>

Collaboration diagram for _PEI_CPU_PLATFORM_POLICY_PPI:
[legend]

List of all members.

Public Attributes

UINT8 | Revision
Revision for the PPI structure.
CPU_CONFIG_PPI * CpuConfig
Processor Features Configuration.
POWER_MGMT_CONFIG_PPI * PowerMgmtConfig
Processor Power ManagementFeatures Configuration.
SECURITY_CONFIG_PPI * SecurityConfig
Processor Security features Configuration.
OVERCLOCKING_CONFIG_PPI * OverclockingConfig
Processor OverClocking features Configuration.
UINTN | CpuPlatformPpiPtr
PEI_CPU_PLATFORM_POLICY_PPI Ptr.

Detailed Description

CPU Platform Policy PPI definition, this PPI provides interface to configure the processor.

Platform code needs to configure the policies for processor ref code to finish the initialization.

Definition at line 331 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

_PEI_CPU_PLATFORM_POLICY_PPI Member List
This is the complete list of members for _PEI_CPU_PLATFORM_POLICY_PPI, including all inherited members.
CpuConfig | _PEI_CPU_PLATFORM_POLICY_PPI
CpuPlatformPpiPtr | _PEI_CPU_PLATFORM_POLICY_PPI
OverclockingConfig | _PEI_CPU_PLATFORM_POLICY_PPI
PowerMgmtConfig | _PEI_CPU_PLATFORM_POLICY_PPI
Revision | _PEI_CPU_PLATFORM_POLICY_PPI
SecurityConfig | _PEI_CPU_PLATFORM_POLICY_PPI


2013 SharkBay Processor Reference Code API: _PFAT_PROTOCOL Struct Reference

Public Attributes
_PFAT_PROTOCOL Struct Reference

This protocol provides all the services required for flash writes/erases via PFAT PFAT Module can only be launched from SMM, this means that all flash writes & erases that BIOS needs to do must flow thru SMI Handler and so dependency on SMM_BASE_PROTOCOL for installing PFAT Protocol. More...

#include <Pfat.h>

Collaboration diagram for _PFAT_PROTOCOL:
[legend]

List of all members.

Public Attributes

PFAT_WRITE Write
Invoked to fill up PFAT script buffer for flash writes.
PFAT_ERASE Erase
Invoked to fill up PFAT script buffer for flash erases.
PFAT_EXECUTE Execute
Will trigger invocation of PFAT module.

Detailed Description

This protocol provides all the services required for flash writes/erases via PFAT PFAT Module can only be launched from SMM, this means that all flash writes & erases that BIOS needs to do must flow thru SMI Handler and so dependency on SMM_BASE_PROTOCOL for installing PFAT Protocol.

Prior to PFAT SMM Protocol being installed there should be no writes/erases to flash.

Definition at line 123 of file Pfat.h.

The documentation for this struct was generated from the following file:
  • Pfat.h


2013 SharkBay Processor Reference Code API: Member List

_PFAT_PROTOCOL Member List
This is the complete list of members for _PFAT_PROTOCOL, including all inherited members.
Erase | _PFAT_PROTOCOL
Execute | _PFAT_PROTOCOL
Write | _PFAT_PROTOCOL


2013 SharkBay Processor Reference Code API: _PPM_CUSTOM_CTDP Struct Reference

Public Attributes
_PPM_CUSTOM_CTDP Struct Reference

This structure is used to configure custom ConfigTdp level settings. More...

#include <CpuPmConfig.h>

Collaboration diagram for _PPM_CUSTOM_CTDP:
[legend]

List of all members.

Public Attributes

UINT8 | ConfigTdpCustom
Describes whether or not Custom Config Tdp should be enabled.
UINT8 | CustomTdpCount
Describes the number of Custom Config Tdp levels required (1/2/3).
UINT8 | CustomBootModeIndex
Describes the Boot mode index selection from Custom Tdp levels.Index to CustomConfigTdpTable.
PPM_CUSTOM_CTDP_TABLE CustomConfigTdpTable [MAX_CUSTOM_CTDP_ENTRIES]
Describes the details of each Custom Config Tdp levels.

Detailed Description

This structure is used to configure custom ConfigTdp level settings.

Definition at line 136 of file CpuPmConfig.h.

Member Data Documentation

UINT8 _PPM_CUSTOM_CTDP::CustomBootModeIndex

Describes the Boot mode index selection from Custom Tdp levels.Index to CustomConfigTdpTable.

valid values are 0,1,2.

Definition at line 139 of file CpuPmConfig.h.

PPM_CUSTOM_CTDP_TABLE _PPM_CUSTOM_CTDP::CustomConfigTdpTable[MAX_CUSTOM_CTDP_ENTRIES]

Describes the details of each Custom Config Tdp levels.

This supports up to MAX_CUSTOM_CTDP_ENTRIES number of Custom ConfigTdp levels.

Definition at line 144 of file CpuPmConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPmConfig.h


2013 SharkBay Processor Reference Code API: Member List

_PPM_CUSTOM_CTDP Member List
This is the complete list of members for _PPM_CUSTOM_CTDP, including all inherited members.
ConfigTdpCustom | _PPM_CUSTOM_CTDP
CustomBootModeIndex | _PPM_CUSTOM_CTDP
CustomConfigTdpTable | _PPM_CUSTOM_CTDP
CustomTdpCount | _PPM_CUSTOM_CTDP


2013 SharkBay Processor Reference Code API: _PPM_CUSTOM_CTDP_TABLE Struct Reference

Public Attributes
_PPM_CUSTOM_CTDP_TABLE Struct Reference

PPM Custom ConfigTdp Settings. More...

#include <CpuPmConfig.h>

List of all members.

Public Attributes

UINT16 | CustomPowerLimit1
Short term Power Limit value for custom cTDP level in 125mw or watts.
UINT16 | CustomPowerLimit2
Long term Power Limit value for custom cTDP level in 125mw or watts.
UINT8 | CustomPowerLimit1Time
Short term Power Limit time window value for custom cTDP level.
UINT8 | CustomTurboActivationRatio
Turbo Activation Ratio for custom cTDP level.
UINT8 | CustomConfigTdpControl
Config Tdp Control (0/1/2) value for custom cTDP level.

Detailed Description

PPM Custom ConfigTdp Settings.

Definition at line 125 of file CpuPmConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPmConfig.h


2013 SharkBay Processor Reference Code API: Member List

_PPM_CUSTOM_CTDP_TABLE Member List
This is the complete list of members for _PPM_CUSTOM_CTDP_TABLE, including all inherited members.
CustomConfigTdpControl | _PPM_CUSTOM_CTDP_TABLE
CustomPowerLimit1 | _PPM_CUSTOM_CTDP_TABLE
CustomPowerLimit1Time | _PPM_CUSTOM_CTDP_TABLE
CustomPowerLimit2 | _PPM_CUSTOM_CTDP_TABLE
CustomTurboActivationRatio | _PPM_CUSTOM_CTDP_TABLE


2013 SharkBay Processor Reference Code API: _PPM_GLOBAL_NVS_AREA_PROTOCOL Struct Reference

Public Attributes
_PPM_GLOBAL_NVS_AREA_PROTOCOL Struct Reference

PPM Global NVS Area Protocol. More...

#include <PpmGlobalNvsArea.h>

Collaboration diagram for _PPM_GLOBAL_NVS_AREA_PROTOCOL:
[legend]

List of all members.

Public Attributes

PPM_GLOBAL_NVS_AREA * Area

Detailed Description

PPM Global NVS Area Protocol.

Definition at line 125 of file PpmGlobalNvsArea.h.

The documentation for this struct was generated from the following file:
  • PpmGlobalNvsArea.h


2013 SharkBay Processor Reference Code API: Member List

_PPM_GLOBAL_NVS_AREA_PROTOCOL Member List
This is the complete list of members for _PPM_GLOBAL_NVS_AREA_PROTOCOL, including all inherited members.
Area (defined in _PPM_GLOBAL_NVS_AREA_PROTOCOL) _PPM_GLOBAL_NVS_AREA_PROTOCOL


2013 SharkBay Processor Reference Code API: _PPM_LOCK_ENABLES Struct Reference

Public Attributes
_PPM_LOCK_ENABLES Struct Reference

This structure is used to control enabled / disabled various PPM MSR lock settings. More...

#include <CpuPmConfig.h>

List of all members.

Public Attributes

UINT32 | PmgCstCfgCtrlLock: 1
Setting this to 1 will set MSR 0xE2[15].
UINT32 | OverclockingLock: 1
Setting this to 1 will set MSR 0x194[20].
UINT32 | ProcHotLock: 1
Setting this to 1 will set MSR 0x1FC[23].
UINT32 | Reserved: 29
Bits reserved for future use.

Detailed Description

This structure is used to control enabled / disabled various PPM MSR lock settings.

Definition at line 150 of file CpuPmConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPmConfig.h


2013 SharkBay Processor Reference Code API: Member List

_PPM_LOCK_ENABLES Member List
This is the complete list of members for _PPM_LOCK_ENABLES, including all inherited members.
OverclockingLock | _PPM_LOCK_ENABLES
PmgCstCfgCtrlLock | _PPM_LOCK_ENABLES
ProcHotLock | _PPM_LOCK_ENABLES
Reserved | _PPM_LOCK_ENABLES


2013 SharkBay Processor Reference Code API: _PPM_TURBO_SETTINGS Struct Reference

Public Attributes
_PPM_TURBO_SETTINGS Struct Reference

This structure is used to describe various PPM turbo settings. More...

#include <CpuPmConfig.h>

List of all members.

Public Attributes

UINT16 | PowerLimit1
Package Long duration turbo mode power limit in 125mw or watts.
UINT32 | PowerLimit1Time
Package Long duration turbo mode time window in seconds.
UINT16 | PowerLimit2
Package Short duration turbo mode power limit in 125mw or watts.
UINT8 | TurboPowerLimitLock
Describes whether TURBO_POWER_LIMIT[63] should be set.
UINT16 | DdrPowerLimit1
UINT32 | DdrPowerLimit1Time
UINT16 | DdrPowerLimit2
UINT8 | DdrPowerLimitLock
UINT8 | ConfigTdpLevel
Configuration for boot TDP selection, value 0 describes TDP Nominal, value 1 describes TDP Down and value 2 describes TDP Up.
UINT8 | ConfigTdpLock
Configurable TDP Mode Lock can be sets the to Lock ConfigTdp mode settings from runtime change.
UINT8 | ConfigTdpBios
Configuration whether load Configurable TDP SSDT.
UINT8 | EnergyPolicy
Describes the Energy efficiency policy to be set in MSR 0x1B0.
UINT16 | PowerLimit3
Package PL3 power limit in 125mw or watts.
UINT32 | PowerLimit3Time
Package PL3 time window in seconds.
UINT8 | PowerLimit3DutyCycle
Package PL3 Duty Cycle.
UINT8 | PowerLimit3Lock
Package PL3 MSR 615h lock.

Detailed Description

This structure is used to describe various PPM turbo settings.

Definition at line 88 of file CpuPmConfig.h.

Member Data Documentation

UINT16 _PPM_TURBO_SETTINGS::DdrPowerLimit1
Deprecated:
in Powermgmt policy

Definition at line 96 of file CpuPmConfig.h.

UINT32 _PPM_TURBO_SETTINGS::DdrPowerLimit1Time
Deprecated:
in Powermgmt policy

Definition at line 97 of file CpuPmConfig.h.

UINT16 _PPM_TURBO_SETTINGS::DdrPowerLimit2
Deprecated:
in Powermgmt policy

Definition at line 98 of file CpuPmConfig.h.

UINT8 _PPM_TURBO_SETTINGS::DdrPowerLimitLock
Deprecated:
in Powermgmt policy

Definition at line 99 of file CpuPmConfig.h.

UINT16 _PPM_TURBO_SETTINGS::PowerLimit2

Package Short duration turbo mode power limit in 125mw or watts.

Definition at line 91 of file CpuPmConfig.h.

UINT8 _PPM_TURBO_SETTINGS::TurboPowerLimitLock

Describes whether TURBO_POWER_LIMIT[63] should be set.

Setting this bit will lock all Turbo settings.

Definition at line 95 of file CpuPmConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPmConfig.h


2013 SharkBay Processor Reference Code API: Member List

_PPM_TURBO_SETTINGS Member List
This is the complete list of members for _PPM_TURBO_SETTINGS, including all inherited members.
ConfigTdpBios | _PPM_TURBO_SETTINGS
ConfigTdpLevel | _PPM_TURBO_SETTINGS
ConfigTdpLock | _PPM_TURBO_SETTINGS
DdrPowerLimit1 | _PPM_TURBO_SETTINGS
DdrPowerLimit1Time | _PPM_TURBO_SETTINGS
DdrPowerLimit2 | _PPM_TURBO_SETTINGS
DdrPowerLimitLock | _PPM_TURBO_SETTINGS
EnergyPolicy | _PPM_TURBO_SETTINGS
PowerLimit1 | _PPM_TURBO_SETTINGS
PowerLimit1Time | _PPM_TURBO_SETTINGS
PowerLimit2 | _PPM_TURBO_SETTINGS
PowerLimit3 | _PPM_TURBO_SETTINGS
PowerLimit3DutyCycle | _PPM_TURBO_SETTINGS
PowerLimit3Lock | _PPM_TURBO_SETTINGS
PowerLimit3Time | _PPM_TURBO_SETTINGS
TurboPowerLimitLock | _PPM_TURBO_SETTINGS


2013 SharkBay Processor Reference Code API: ACPI_CPU_DATA Struct Reference

Public Attributes
ACPI_CPU_DATA Struct Reference

List of all members.

Public Attributes

BOOLEAN | APState
BOOLEAN | S3BootPath
EFI_PHYSICAL_ADDRESS | WakeUpBuffer
EFI_PHYSICAL_ADDRESS | GdtrProfile
EFI_PHYSICAL_ADDRESS | IdtrProfile
EFI_PHYSICAL_ADDRESS | CpuPrivateData
EFI_PHYSICAL_ADDRESS | StackAddress
EFI_PHYSICAL_ADDRESS | MicrocodePointerBuffer
EFI_PHYSICAL_ADDRESS | SmramBase
EFI_PHYSICAL_ADDRESS | SmmStartImageBase
UINT32 | SmmStartImageSize
UINT32 | NumberOfCpus

Detailed Description

Definition at line 33 of file CpuDataStruct.h.

The documentation for this struct was generated from the following file:
  • CpuDataStruct.h


2013 SharkBay Processor Reference Code API: Member List

ACPI_CPU_DATA Member List
This is the complete list of members for ACPI_CPU_DATA, including all inherited members.
APState (defined in ACPI_CPU_DATA) | ACPI_CPU_DATA
CpuPrivateData (defined in ACPI_CPU_DATA) | ACPI_CPU_DATA
GdtrProfile (defined in ACPI_CPU_DATA) | ACPI_CPU_DATA
IdtrProfile (defined in ACPI_CPU_DATA) | ACPI_CPU_DATA
MicrocodePointerBuffer (defined in ACPI_CPU_DATA) | ACPI_CPU_DATA
NumberOfCpus (defined in ACPI_CPU_DATA) | ACPI_CPU_DATA
S3BootPath (defined in ACPI_CPU_DATA) | ACPI_CPU_DATA
SmmStartImageBase (defined in ACPI_CPU_DATA) | ACPI_CPU_DATA
SmmStartImageSize (defined in ACPI_CPU_DATA) | ACPI_CPU_DATA
SmramBase (defined in ACPI_CPU_DATA) | ACPI_CPU_DATA
StackAddress (defined in ACPI_CPU_DATA) | ACPI_CPU_DATA
WakeUpBuffer (defined in ACPI_CPU_DATA) | ACPI_CPU_DATA


2013 SharkBay Processor Reference Code API: BIOS_OS_DATA_REGION Struct Reference

Public Attributes
BIOS_OS_DATA_REGION Struct Reference
Collaboration diagram for BIOS_OS_DATA_REGION:
[legend]

List of all members.

Public Attributes

UINT32 | Version
UINT32 | BiosSinitSize
EFI_PHYSICAL_ADDRESS | LcpPdBase
UINT64 | LcpPdSize
UINT32 | NumOfLogicalProcessors
UINT64 | Flags
HEAP_EXT_DATA_ELEMENT | ExtData

Detailed Description

Definition at line 142 of file Txt.h.

The documentation for this struct was generated from the following file:
  • Txt.h


2013 SharkBay Processor Reference Code API: Member List

BIOS_OS_DATA_REGION Member List
This is the complete list of members for BIOS_OS_DATA_REGION, including all inherited members.
BiosSinitSize (defined in BIOS_OS_DATA_REGION) | BIOS_OS_DATA_REGION
ExtData (defined in BIOS_OS_DATA_REGION) | BIOS_OS_DATA_REGION
Flags (defined in BIOS_OS_DATA_REGION) | BIOS_OS_DATA_REGION
LcpPdBase (defined in BIOS_OS_DATA_REGION) | BIOS_OS_DATA_REGION
LcpPdSize (defined in BIOS_OS_DATA_REGION) | BIOS_OS_DATA_REGION
NumOfLogicalProcessors (defined in BIOS_OS_DATA_REGION) | BIOS_OS_DATA_REGION
Version (defined in BIOS_OS_DATA_REGION) | BIOS_OS_DATA_REGION


2013 SharkBay Processor Reference Code API: BOOT_GUARD_CONFIG Struct Reference

Public Attributes
BOOT_GUARD_CONFIG Struct Reference

List of all members.

Public Attributes

BOOLEAN | MeasuredBoot
BOOLEAN | BypassTpmInit
TPM_TYPE | TpmType
BOOLEAN | BootGuardSupport
BOOLEAN | DisconnectAllTpms
BOOLEAN | ByPassTpmEventLog

Detailed Description

Definition at line 273 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

BOOT_GUARD_CONFIG Member List
This is the complete list of members for BOOT_GUARD_CONFIG, including all inherited members.
BootGuardSupport (defined in BOOT_GUARD_CONFIG) | BOOT_GUARD_CONFIG
ByPassTpmEventLog (defined in BOOT_GUARD_CONFIG) | BOOT_GUARD_CONFIG
BypassTpmInit (defined in BOOT_GUARD_CONFIG) | BOOT_GUARD_CONFIG
DisconnectAllTpms (defined in BOOT_GUARD_CONFIG) | BOOT_GUARD_CONFIG
MeasuredBoot (defined in BOOT_GUARD_CONFIG) | BOOT_GUARD_CONFIG
TpmType (defined in BOOT_GUARD_CONFIG) | BOOT_GUARD_CONFIG


2013 SharkBay Processor Reference Code API: CORE_RATIO_LIMITS_ITEM Struct Reference

Public Attributes
CORE_RATIO_LIMITS_ITEM Struct Reference

List of all members.

Public Attributes

UINT8 | MaxOcRatioLimit1C
UINT8 | MaxOcRatioLimit2C
UINT8 | MaxOcRatioLimit3C
UINT8 | MaxOcRatioLimit4C
UINT8 | Index

Detailed Description

Definition at line 177 of file OverclockingLibrary.h.

The documentation for this struct was generated from the following file:
  • OverclockingLibrary.h


2013 SharkBay Processor Reference Code API: Member List

CORE_RATIO_LIMITS_ITEM Member List
This is the complete list of members for CORE_RATIO_LIMITS_ITEM, including all inherited members.
Index (defined in CORE_RATIO_LIMITS_ITEM) | CORE_RATIO_LIMITS_ITEM
MaxOcRatioLimit1C (defined in CORE_RATIO_LIMITS_ITEM) | CORE_RATIO_LIMITS_ITEM
MaxOcRatioLimit2C (defined in CORE_RATIO_LIMITS_ITEM) | CORE_RATIO_LIMITS_ITEM
MaxOcRatioLimit3C (defined in CORE_RATIO_LIMITS_ITEM) | CORE_RATIO_LIMITS_ITEM
MaxOcRatioLimit4C (defined in CORE_RATIO_LIMITS_ITEM) | CORE_RATIO_LIMITS_ITEM


2013 SharkBay Processor Reference Code API: CPU_CONFIG Struct Reference

Public Attributes
CPU_CONFIG Struct Reference

General CPU feature Configuration for all processor features enabling bit definitions are in this field. More...

#include <CpuPlatformPolicy.h>

Collaboration diagram for CPU_CONFIG:
[legend]

List of all members.

Public Attributes

UINT8 | HtState: 1
Enable or Disable Hyper Threading State; 0: Disable; 1: Enable.
UINT8 | LimitCpuidMaximumValue: 1
Enable or Disable Limit Cpuid Maximum Value; 0: Disable; 1: Enable.
UINT8 | DcaState: 1
UINT8 | ExecuteDisableBit: 1
Enable or Disable Execute Disable Bit; 0: Disable; 1: Enable.
UINT8 | VmxEnable: 1
Enable or Disable VMX; 0: Disable; 1: Enable.
UINT8 | SmxEnable: 1
Enable or Disable SMX; 0: Disable; 1: Enable.
UINT8 | FastString: 1
UINT8 | MachineCheckEnable: 1
Enable or Disable Machine Check; 0: Disable; 1: Enable.
UINT8 | MonitorMwaitEnable: 1
Enable or Disable Monitor Mwait mode; 0: Disable; 1: Enable.
UINT8 | XapicEnable: 1
Enable or Disable Xapic mode; 0: Disable; 1: Enable.
UINT8 | MachineCheckStatusClean: 1
UINT8 | IsColdReset: 1
Check if is Cold Reset; 0: Not Cold Reset; 1: Cold Reset.
UINT8 | MlcStreamerPrefetcher: 1
Enable or Disable MlcStreamerPrefetcher; 0: Disable; 1: Enable.
UINT8 | MlcSpatialPrefetcher: 1
Enable or Disable MlcSpatialPrefetcher; 0: Disable; 1: Enable.
UINT8 | EnableDts: 2
Enable or Disable DTS feature; 0=Disable; 1=Enable; 2=OUT_OF_SPEC;.
UINT8 | FviReport: 1
Enable or Disable FVI report; 0: Disable; 1: Enable.
UINT8 | AesEnable: 1
Enable or Disable AES feature; 0: Disable; 1: Enable.
UINT8 | DebugInterfaceEnable: 1
Enable or Disable Debug Interface; 0: Disable; 1: Enable.
UINT8 | DebugInterfaceLockEnable: 1
Enable or Disable Debug Interface Lock; 0: Disable; 1: Enable.
UINT8 | ApIdleManner: 2
Settings for AP Threads Idle; 1: HALT 2:MWAIT 3:RUN.
UINT8 | ApHandoffManner: 2
Settings for AP Handoff to OS; 1: HALT 2:MWAIT32.
UINT8 | BspSelection
Select BSP.
UINT32 | DcaPrefetchDelayValue
UINT8 | VirtualWireMode
UINT8 | SmmbaseSwSmiNumber
SW SMI Number from Smbase.
UINT8 | FviSmbiosType
Create SMBIOS Table Type for FVI.
PLATFORM_CPU_RETRIEVE_MICROCODE RetrieveMicrocode
Platform code can provide microcode location thru this function.
PLATFORM_CPU_GET_MAX_COUNT GetMaxCount
Platform to provide the processor detail about Max Thread per Core, Max Cores per Die, Max Dies per Package and Max packages.
PLATFORM_CPU_GET_CPU_INFO GetCpuInfo
Platform code to provide platform specific processor information.

Detailed Description

General CPU feature Configuration for all processor features enabling bit definitions are in this field.

Platform code can enable/disable features thru this field.

Definition at line 232 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

Member Data Documentation

UINT32 CPU_CONFIG::DcaPrefetchDelayValue
Deprecated:
Deprecated for Client (Server specific)

Definition at line 267 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

UINT8 CPU_CONFIG::DcaState
Deprecated:
Deprecated for Client (Server specific)

Definition at line 238 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

UINT8 CPU_CONFIG::FastString
Deprecated:

Definition at line 242 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

UINT8 CPU_CONFIG::MachineCheckStatusClean
Deprecated:

Definition at line 249 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

UINT8 CPU_CONFIG::VirtualWireMode
Deprecated:

Definition at line 268 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

CPU_CONFIG Member List
This is the complete list of members for CPU_CONFIG, including all inherited members.
AesEnable | CPU_CONFIG
ApHandoffManner | CPU_CONFIG
ApIdleManner | CPU_CONFIG
BspSelection | CPU_CONFIG
DcaPrefetchDelayValue | CPU_CONFIG
DcaState | CPU_CONFIG
DebugInterfaceEnable | CPU_CONFIG
DebugInterfaceLockEnable | CPU_CONFIG
EnableDts | CPU_CONFIG
ExecuteDisableBit | CPU_CONFIG
FastString | CPU_CONFIG
FviReport | CPU_CONFIG
FviSmbiosType | CPU_CONFIG
GetCpuInfo | CPU_CONFIG
GetMaxCount | CPU_CONFIG
HtState | CPU_CONFIG
IsColdReset | CPU_CONFIG
LimitCpuidMaximumValue | CPU_CONFIG
MachineCheckEnable | CPU_CONFIG
MachineCheckStatusClean | CPU_CONFIG
MlcSpatialPrefetcher | CPU_CONFIG
MlcStreamerPrefetcher | CPU_CONFIG
MonitorMwaitEnable | CPU_CONFIG
RetrieveMicrocode | CPU_CONFIG
SmmbaseSwSmiNumber | CPU_CONFIG
SmxEnable | CPU_CONFIG
VirtualWireMode | CPU_CONFIG
VmxEnable | CPU_CONFIG
XapicEnable | CPU_CONFIG


2013 SharkBay Processor Reference Code API: CPU_CONFIG_PPI Struct Reference

Public Attributes
CPU_CONFIG_PPI Struct Reference

General CPU features configration for all processor features enabling / configuration bit definitions are in this field. More...

#include <CpuPlatformPolicy.h>

List of all members.

Public Attributes

UINT8 | BistOnReset: 1
Enable or Disable BIST on Reset.
UINT8 | HyperThreading: 1
Enable or Disable Hyper Threading.
UINT8 | CpuRatioOverride: 1
Enable or Disable CPU Radio Override.
UINT8 | VmxEnable: 1
Enable or Disable VMX.
UINT8 | Pfat: 1
Enable or Disable PFAT.
UINT8 | MlcStreamerPrefetcher: 1
Enable or Disable MLC Streamer Prefetcher.
UINT8 | MlcSpatialPrefetcher: 1
Enable or Disable MLC Spatial Prefetcher.
UINT8 | Txt: 1
Enable or Disable TXT.
UINT8 | Rsvdbyte: 8
A place holder for additonal functionalites expected in futture platforms.
UINT8 | ActiveCoreCount
Number of active cores.
UINT8 | CpuRatio
CPU ratio value.
UINT8 | CpuMaxNonTurboRatio
CPU Maximum Non-Turbo ratio value.

Detailed Description

General CPU features configration for all processor features enabling / configuration bit definitions are in this field.

Platform code can enable/disable/configure features thru this field.

Definition at line 120 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

CPU_CONFIG_PPI Member List
This is the complete list of members for CPU_CONFIG_PPI, including all inherited members.
ActiveCoreCount | CPU_CONFIG_PPI
BistOnReset | CPU_CONFIG_PPI
CpuMaxNonTurboRatio | CPU_CONFIG_PPI
CpuRatio | CPU_CONFIG_PPI
CpuRatioOverride | CPU_CONFIG_PPI
HyperThreading | CPU_CONFIG_PPI
MlcSpatialPrefetcher | CPU_CONFIG_PPI
MlcStreamerPrefetcher | CPU_CONFIG_PPI
Pfat | CPU_CONFIG_PPI
Rsvdbyte | CPU_CONFIG_PPI
Txt | CPU_CONFIG_PPI
VmxEnable | CPU_CONFIG_PPI


2013 SharkBay Processor Reference Code API: CPU_PHYSICAL_LOCATION Struct Reference

Public Attributes
CPU_PHYSICAL_LOCATION Struct Reference

List of all members.

Public Attributes

UINT32 | Package
UINT32 | Die
UINT32 | Core
UINT32 | Thread

Detailed Description

Definition at line 126 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

CPU_PHYSICAL_LOCATION Member List
This is the complete list of members for CPU_PHYSICAL_LOCATION, including all inherited members.
Core (defined in CPU_PHYSICAL_LOCATION) | CPU_PHYSICAL_LOCATION
Die (defined in CPU_PHYSICAL_LOCATION) | CPU_PHYSICAL_LOCATION
Package (defined in CPU_PHYSICAL_LOCATION) | CPU_PHYSICAL_LOCATION
Thread (defined in CPU_PHYSICAL_LOCATION) | CPU_PHYSICAL_LOCATION


2013 SharkBay Processor Reference Code API: EFI_CPU_MICROCODE_EXTENDED_TABLE Struct Reference

Public Attributes
EFI_CPU_MICROCODE_EXTENDED_TABLE Struct Reference

List of all members.

Public Attributes

UINT32 | ProcessorSignature
UINT32 | ProcessorFlag
UINT32 | ProcessorChecksum

Detailed Description

Definition at line 125 of file CpuDataStruct.h.

The documentation for this struct was generated from the following file:
  • CpuDataStruct.h


2013 SharkBay Processor Reference Code API: Member List

EFI_CPU_MICROCODE_EXTENDED_TABLE Member List
This is the complete list of members for EFI_CPU_MICROCODE_EXTENDED_TABLE, including all inherited members.
ProcessorChecksum (defined in EFI_CPU_MICROCODE_EXTENDED_TABLE) | EFI_CPU_MICROCODE_EXTENDED_TABLE
ProcessorFlag (defined in EFI_CPU_MICROCODE_EXTENDED_TABLE) | EFI_CPU_MICROCODE_EXTENDED_TABLE
ProcessorSignature (defined in EFI_CPU_MICROCODE_EXTENDED_TABLE) | EFI_CPU_MICROCODE_EXTENDED_TABLE


2013 SharkBay Processor Reference Code API: EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER Struct Reference

Public Attributes
EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER Struct Reference

List of all members.

Public Attributes

UINT32 | ExtendedSignatureCount
UINT32 | ExtendedTableChecksum
UINT8 | Reserved [12]

Detailed Description

Definition at line 119 of file CpuDataStruct.h.

The documentation for this struct was generated from the following file:
  • CpuDataStruct.h


2013 SharkBay Processor Reference Code API: Member List

EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER Member List
This is the complete list of members for EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER, including all inherited members.
ExtendedSignatureCount (defined in EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER) | EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER
ExtendedTableChecksum (defined in EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER) | EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER
Reserved (defined in EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER) | EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER


2013 SharkBay Processor Reference Code API: EFI_CPU_MICROCODE_HEADER Struct Reference

Public Attributes
EFI_CPU_MICROCODE_HEADER Struct Reference

List of all members.

Public Attributes

UINT32 | HeaderVersion
UINT32 | UpdateRevision
UINT32 | Date
UINT32 | ProcessorId
UINT32 | Checksum
UINT32 | LoaderRevision
UINT32 | ProcessorFlags
UINT32 | DataSize
UINT32 | TotalSize
UINT8 | Reserved [12]

Detailed Description

Definition at line 106 of file CpuDataStruct.h.

The documentation for this struct was generated from the following file:
  • CpuDataStruct.h


2013 SharkBay Processor Reference Code API: Member List

EFI_CPU_MICROCODE_HEADER Member List
This is the complete list of members for EFI_CPU_MICROCODE_HEADER, including all inherited members.
Checksum (defined in EFI_CPU_MICROCODE_HEADER) | EFI_CPU_MICROCODE_HEADER
DataSize (defined in EFI_CPU_MICROCODE_HEADER) | EFI_CPU_MICROCODE_HEADER
Date (defined in EFI_CPU_MICROCODE_HEADER) | EFI_CPU_MICROCODE_HEADER
HeaderVersion (defined in EFI_CPU_MICROCODE_HEADER) | EFI_CPU_MICROCODE_HEADER
LoaderRevision (defined in EFI_CPU_MICROCODE_HEADER) | EFI_CPU_MICROCODE_HEADER
ProcessorFlags (defined in EFI_CPU_MICROCODE_HEADER) | EFI_CPU_MICROCODE_HEADER
ProcessorId (defined in EFI_CPU_MICROCODE_HEADER) | EFI_CPU_MICROCODE_HEADER
Reserved (defined in EFI_CPU_MICROCODE_HEADER) | EFI_CPU_MICROCODE_HEADER
TotalSize (defined in EFI_CPU_MICROCODE_HEADER) | EFI_CPU_MICROCODE_HEADER
UpdateRevision (defined in EFI_CPU_MICROCODE_HEADER) | EFI_CPU_MICROCODE_HEADER


2013 SharkBay Processor Reference Code API: EFI_CPU_PHYSICAL_LOCATION Struct Reference

Public Attributes
EFI_CPU_PHYSICAL_LOCATION Struct Reference

Structure that describes the pyhiscal location of a logical CPU. More...

#include <PiMpService.h>

List of all members.

Public Attributes

UINT32 | Package
Zero-based physical package number that identifies the cartridge of the processor.
UINT32 | Core
Zero-based physical core number within package of the processor.
UINT32 | Thread
Zero-based logical thread number within core of the processor.

Detailed Description

Structure that describes the pyhiscal location of a logical CPU.

Definition at line 73 of file PiMpService.h.

The documentation for this struct was generated from the following file:
  • PiMpService.h


2013 SharkBay Processor Reference Code API: Member List

EFI_CPU_PHYSICAL_LOCATION Member List
This is the complete list of members for EFI_CPU_PHYSICAL_LOCATION, including all inherited members.
Core | EFI_CPU_PHYSICAL_LOCATION
Package | EFI_CPU_PHYSICAL_LOCATION
Thread | EFI_CPU_PHYSICAL_LOCATION


2013 SharkBay Processor Reference Code API: EFI_CPU_VERSION Struct Reference

Public Attributes
EFI_CPU_VERSION Struct Reference

List of all members.

Public Attributes

UINT32 | Stepping: 4
UINT32 | Model: 4
UINT32 | Family: 4
UINT32 | Type: 2
UINT32 | Reserved1: 2
UINT32 | ExtendedModel: 4
UINT32 | ExtendedFamily: 8
UINT32 | Reserved2: 4

Detailed Description

Definition at line 131 of file CpuDataStruct.h.

The documentation for this struct was generated from the following file:
  • CpuDataStruct.h


2013 SharkBay Processor Reference Code API: Member List

EFI_CPU_VERSION Member List
This is the complete list of members for EFI_CPU_VERSION, including all inherited members.
ExtendedFamily (defined in EFI_CPU_VERSION) | EFI_CPU_VERSION
ExtendedModel (defined in EFI_CPU_VERSION) | EFI_CPU_VERSION
Family (defined in EFI_CPU_VERSION) | EFI_CPU_VERSION
Model (defined in EFI_CPU_VERSION) | EFI_CPU_VERSION
Reserved1 (defined in EFI_CPU_VERSION) | EFI_CPU_VERSION
Reserved2 (defined in EFI_CPU_VERSION) | EFI_CPU_VERSION
Stepping (defined in EFI_CPU_VERSION) | EFI_CPU_VERSION
Type (defined in EFI_CPU_VERSION) | EFI_CPU_VERSION


2013 SharkBay Processor Reference Code API: EFI_CPUID_REGISTER Struct Reference

Public Attributes
EFI_CPUID_REGISTER Struct Reference

List of all members.

Public Attributes

UINT32 | RegEax
UINT32 | RegEbx
UINT32 | RegEcx
UINT32 | RegEdx

Detailed Description

Definition at line 99 of file CpuDataStruct.h.

The documentation for this struct was generated from the following file:
  • CpuDataStruct.h


2013 SharkBay Processor Reference Code API: Member List

EFI_CPUID_REGISTER Member List
This is the complete list of members for EFI_CPUID_REGISTER, including all inherited members.
RegEax (defined in EFI_CPUID_REGISTER) | EFI_CPUID_REGISTER
RegEbx (defined in EFI_CPUID_REGISTER) | EFI_CPUID_REGISTER
RegEcx (defined in EFI_CPUID_REGISTER) | EFI_CPUID_REGISTER
RegEdx (defined in EFI_CPUID_REGISTER) | EFI_CPUID_REGISTER


2013 SharkBay Processor Reference Code API: EFI_DETAILED_CPU_INFO Struct Reference

Public Attributes
EFI_DETAILED_CPU_INFO Struct Reference
Collaboration diagram for EFI_DETAILED_CPU_INFO:
[legend]

List of all members.

Public Attributes

EFI_MP_PROC_CONTEXT * | Context
EFI_EXP_BASE10_DATA | CoreFreq
EFI_EXP_BASE10_DATA | BusFreq
EFI_EXP_BASE2_DATA | CacheSize [EFI_CACHE_LMAX]
EFI_PROCESSOR_ID_DATA | CpuId
EFI_PROCESSOR_MICROCODE_REVISION_DATA | MuData
EFI_PROCESSOR_STATUS_DATA | Status

Detailed Description

Definition at line 161 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

EFI_DETAILED_CPU_INFO Member List
This is the complete list of members for EFI_DETAILED_CPU_INFO, including all inherited members.
BusFreq (defined in EFI_DETAILED_CPU_INFO) | EFI_DETAILED_CPU_INFO
CacheSize (defined in EFI_DETAILED_CPU_INFO) | EFI_DETAILED_CPU_INFO
Context (defined in EFI_DETAILED_CPU_INFO) | EFI_DETAILED_CPU_INFO
CoreFreq (defined in EFI_DETAILED_CPU_INFO) | EFI_DETAILED_CPU_INFO
CpuId (defined in EFI_DETAILED_CPU_INFO) | EFI_DETAILED_CPU_INFO
MuData (defined in EFI_DETAILED_CPU_INFO) | EFI_DETAILED_CPU_INFO
Status (defined in EFI_DETAILED_CPU_INFO) | EFI_DETAILED_CPU_INFO


2013 SharkBay Processor Reference Code API: EFI_MP_HEALTH Struct Reference

Public Attributes
EFI_MP_HEALTH Struct Reference
Collaboration diagram for EFI_MP_HEALTH:
[legend]

List of all members.

Public Attributes

EFI_MP_HEALTH_FLAGS | Flags
UINT32 | TestStatus

Detailed Description

Definition at line 67 of file MpService.h.

The documentation for this struct was generated from the following file:
  • MpService.h


2013 SharkBay Processor Reference Code API: Member List

EFI_MP_HEALTH Member List
This is the complete list of members for EFI_MP_HEALTH, including all inherited members.
Flags (defined in EFI_MP_HEALTH) | EFI_MP_HEALTH
TestStatus (defined in EFI_MP_HEALTH) | EFI_MP_HEALTH


2013 SharkBay Processor Reference Code API: EFI_MP_HEALTH_FLAGS Union Reference

Public Attributes
EFI_MP_HEALTH_FLAGS Union Reference

List of all members.

Public Attributes

struct {
UINT32 Status: 2
UINT32 Tested: 1
UINT32 Reserved1: 13
UINT32 VirtualMemoryUnavailable: 1
UINT32 Ia32ExecutionUnavailable: 1
UINT32 FloatingPointUnavailable: 1
UINT32 MiscFeaturesUnavailable: 1
UINT32 Reserved2: 12
} Bits
UINT32 Uint32

Detailed Description

Definition at line 49 of file MpService.h.

The documentation for this union was generated from the following file:
  • MpService.h


2013 SharkBay Processor Reference Code API: Member List

EFI_MP_HEALTH_FLAGS Member List
This is the complete list of members for EFI_MP_HEALTH_FLAGS, including all inherited members.
Bits (defined in EFI_MP_HEALTH_FLAGS) | EFI_MP_HEALTH_FLAGS
FloatingPointUnavailable (defined in EFI_MP_HEALTH_FLAGS) | EFI_MP_HEALTH_FLAGS
Ia32ExecutionUnavailable (defined in EFI_MP_HEALTH_FLAGS) | EFI_MP_HEALTH_FLAGS
MiscFeaturesUnavailable (defined in EFI_MP_HEALTH_FLAGS) | EFI_MP_HEALTH_FLAGS
Reserved1 (defined in EFI_MP_HEALTH_FLAGS) | EFI_MP_HEALTH_FLAGS
Reserved2 (defined in EFI_MP_HEALTH_FLAGS) | EFI_MP_HEALTH_FLAGS
Status (defined in EFI_MP_HEALTH_FLAGS) | EFI_MP_HEALTH_FLAGS
Tested (defined in EFI_MP_HEALTH_FLAGS) | EFI_MP_HEALTH_FLAGS
Uint32 (defined in EFI_MP_HEALTH_FLAGS) | EFI_MP_HEALTH_FLAGS
VirtualMemoryUnavailable (defined in EFI_MP_HEALTH_FLAGS) | EFI_MP_HEALTH_FLAGS


2013 SharkBay Processor Reference Code API: EFI_MP_PROC_CONTEXT Struct Reference

Public Attributes
EFI_MP_PROC_CONTEXT Struct Reference
Collaboration diagram for EFI_MP_PROC_CONTEXT:
[legend]

List of all members.

Public Attributes

UINT32 | ApicID
BOOLEAN | Enabled
EFI_CPU_DESIGNATION | Designation
EFI_MP_HEALTH | Health
UINTN | PackageNumber
UINTN | NumberOfCores
UINTN | NumberOfThreads
UINT64 | ProcessorPALCompatibilityFlags
UINT64 | ProcessorTestMask

Detailed Description

Definition at line 85 of file MpService.h.

The documentation for this struct was generated from the following file:
  • MpService.h


2013 SharkBay Processor Reference Code API: Member List

EFI_MP_PROC_CONTEXT Member List
This is the complete list of members for EFI_MP_PROC_CONTEXT, including all inherited members.
ApicID (defined in EFI_MP_PROC_CONTEXT) | EFI_MP_PROC_CONTEXT
Designation (defined in EFI_MP_PROC_CONTEXT) | EFI_MP_PROC_CONTEXT
Enabled (defined in EFI_MP_PROC_CONTEXT) | EFI_MP_PROC_CONTEXT
Health (defined in EFI_MP_PROC_CONTEXT) | EFI_MP_PROC_CONTEXT
NumberOfCores (defined in EFI_MP_PROC_CONTEXT) | EFI_MP_PROC_CONTEXT
NumberOfThreads (defined in EFI_MP_PROC_CONTEXT) | EFI_MP_PROC_CONTEXT
PackageNumber (defined in EFI_MP_PROC_CONTEXT) | EFI_MP_PROC_CONTEXT
ProcessorPALCompatibilityFlags (defined in EFI_MP_PROC_CONTEXT) | EFI_MP_PROC_CONTEXT
ProcessorTestMask (defined in EFI_MP_PROC_CONTEXT) | EFI_MP_PROC_CONTEXT


2013 SharkBay Processor Reference Code API: EFI_PROCESSOR_INFORMATION Struct Reference

Public Attributes
EFI_PROCESSOR_INFORMATION Struct Reference

Structure that describes information about a logical CPU. More...

#include <PiMpService.h>

Collaboration diagram for EFI_PROCESSOR_INFORMATION:
[legend]

List of all members.

Public Attributes

UINT64 | ProcessorId
The unique processor ID determined by system hardware.
UINT32 | StatusFlag
Flags indicating if the processor is BSP or AP, if the processor is enabled or disabled, and if the processor is healthy.
EFI_CPU_PHYSICAL_LOCATION Location
The physical location of the processor, including the physical package number that identifies the cartridge, the physical core number within package, and logical thread number within core.

Detailed Description

Structure that describes information about a logical CPU.

Definition at line 91 of file PiMpService.h.

Member Data Documentation

UINT64 EFI_PROCESSOR_INFORMATION::ProcessorId

The unique processor ID determined by system hardware.

For IA32 and X64, the processor ID is the same as the Local APIC ID. Only the lower 8 bits are used, and higher bits are reserved. For IPF, the lower 16 bits contains id/eid, and higher bits are reserved.

Definition at line 98 of file PiMpService.h.

UINT32 EFI_PROCESSOR_INFORMATION::StatusFlag

Flags indicating if the processor is BSP or AP, if the processor is enabled or disabled, and if the processor is healthy.

Bits 3..31 are reserved and must be 0.

 BSP  ENABLED  HEALTH  Description
 ===  =======  ======  ===================================================
  0      0       0     Unhealthy Disabled AP.
  0      0       1     Healthy Disabled AP.
  0      1       0     Unhealthy Enabled AP.
  0      1       1     Healthy Enabled AP.
  1      0       0     Invalid. The BSP can never be in the disabled state.
  1      0       1     Invalid. The BSP can never be in the disabled state.
  1      1       0     Unhealthy Enabled BSP.
  1      1       1     Healthy Enabled BSP.

Definition at line 117 of file PiMpService.h.

The documentation for this struct was generated from the following file:
  • PiMpService.h


2013 SharkBay Processor Reference Code API: Member List

EFI_PROCESSOR_INFORMATION Member List
This is the complete list of members for EFI_PROCESSOR_INFORMATION, including all inherited members.
Location | EFI_PROCESSOR_INFORMATION
ProcessorId | EFI_PROCESSOR_INFORMATION
StatusFlag | EFI_PROCESSOR_INFORMATION


2013 SharkBay Processor Reference Code API: GLOBAL_CONFIG_ITEM Struct Reference

Public Attributes
GLOBAL_CONFIG_ITEM Struct Reference

List of all members.

Public Attributes

UINT8 | DisableFivrFaults
UINT8 | DisableFivrEfficiency

Detailed Description

Definition at line 185 of file OverclockingLibrary.h.

The documentation for this struct was generated from the following file:
  • OverclockingLibrary.h


2013 SharkBay Processor Reference Code API: Member List

GLOBAL_CONFIG_ITEM Member List
This is the complete list of members for GLOBAL_CONFIG_ITEM, including all inherited members.
DisableFivrEfficiency (defined in GLOBAL_CONFIG_ITEM) | GLOBAL_CONFIG_ITEM
DisableFivrFaults (defined in GLOBAL_CONFIG_ITEM) | GLOBAL_CONFIG_ITEM


2013 SharkBay Processor Reference Code API: HEAP_BIOS_SPEC_VER_ELEMENT Struct Reference

Public Attributes
HEAP_BIOS_SPEC_VER_ELEMENT Struct Reference
Collaboration diagram for HEAP_BIOS_SPEC_VER_ELEMENT:
[legend]

List of all members.

Public Attributes

HEAP_EXT_DATA_ELEMENT | Header
UINT16 | SpecVerMajor
UINT16 | SpecVerMinor
UINT16 | SpecVerRevision

Detailed Description

Definition at line 121 of file Txt.h.

The documentation for this struct was generated from the following file:
  • Txt.h


2013 SharkBay Processor Reference Code API: Member List

HEAP_BIOS_SPEC_VER_ELEMENT Member List
This is the complete list of members for HEAP_BIOS_SPEC_VER_ELEMENT, including all inherited members.
Header (defined in HEAP_BIOS_SPEC_VER_ELEMENT) | HEAP_BIOS_SPEC_VER_ELEMENT
SpecVerMajor (defined in HEAP_BIOS_SPEC_VER_ELEMENT) | HEAP_BIOS_SPEC_VER_ELEMENT
SpecVerMinor (defined in HEAP_BIOS_SPEC_VER_ELEMENT) | HEAP_BIOS_SPEC_VER_ELEMENT
SpecVerRevision (defined in HEAP_BIOS_SPEC_VER_ELEMENT) | HEAP_BIOS_SPEC_VER_ELEMENT


2013 SharkBay Processor Reference Code API: HEAP_BIOSACM_ELEMENT Struct Reference

Public Attributes
HEAP_BIOSACM_ELEMENT Struct Reference
Collaboration diagram for HEAP_BIOSACM_ELEMENT:
[legend]

List of all members.

Public Attributes

HEAP_EXT_DATA_ELEMENT | Header
UINT32 | NumAcms

Detailed Description

Definition at line 132 of file Txt.h.

The documentation for this struct was generated from the following file:
  • Txt.h


2013 SharkBay Processor Reference Code API: Member List

HEAP_BIOSACM_ELEMENT Member List
This is the complete list of members for HEAP_BIOSACM_ELEMENT, including all inherited members.
Header (defined in HEAP_BIOSACM_ELEMENT) | HEAP_BIOSACM_ELEMENT
NumAcms (defined in HEAP_BIOSACM_ELEMENT) | HEAP_BIOSACM_ELEMENT


2013 SharkBay Processor Reference Code API: HEAP_EXT_DATA_ELEMENT Struct Reference

Public Attributes
HEAP_EXT_DATA_ELEMENT Struct Reference

List of all members.

Public Attributes

UINT32 | Type
UINT32 | Size

Detailed Description

Definition at line 111 of file Txt.h.

The documentation for this struct was generated from the following file:
  • Txt.h


2013 SharkBay Processor Reference Code API: Member List

HEAP_EXT_DATA_ELEMENT Member List
This is the complete list of members for HEAP_EXT_DATA_ELEMENT, including all inherited members.
Size (defined in HEAP_EXT_DATA_ELEMENT) | HEAP_EXT_DATA_ELEMENT
Type (defined in HEAP_EXT_DATA_ELEMENT) | HEAP_EXT_DATA_ELEMENT


2013 SharkBay Processor Reference Code API: OC_CAPABILITIES_ITEM Struct Reference

Public Attributes
OC_CAPABILITIES_ITEM Struct Reference

List of all members.

Public Attributes

UINT8 | MaxOcRatioLimit
BOOLEAN | RatioOcSupported
BOOLEAN | VoltageOverridesSupported
BOOLEAN | VoltageOffsetSupported
UINT8 | DomainId

Detailed Description

Definition at line 169 of file OverclockingLibrary.h.

The documentation for this struct was generated from the following file:
  • OverclockingLibrary.h


2013 SharkBay Processor Reference Code API: Member List

OC_CAPABILITIES_ITEM Member List
This is the complete list of members for OC_CAPABILITIES_ITEM, including all inherited members.
DomainId (defined in OC_CAPABILITIES_ITEM) | OC_CAPABILITIES_ITEM
MaxOcRatioLimit (defined in OC_CAPABILITIES_ITEM) | OC_CAPABILITIES_ITEM
RatioOcSupported (defined in OC_CAPABILITIES_ITEM) | OC_CAPABILITIES_ITEM
VoltageOffsetSupported (defined in OC_CAPABILITIES_ITEM) | OC_CAPABILITIES_ITEM
VoltageOverridesSupported (defined in OC_CAPABILITIES_ITEM) | OC_CAPABILITIES_ITEM


2013 SharkBay Processor Reference Code API: OC_LIBRARY_COMMAND Struct Reference

Public Attributes
OC_LIBRARY_COMMAND Struct Reference

OC Library structures. More...

#include <OverclockingLibrary.h>

List of all members.

Public Attributes

UINT32 | CommandData
UINT8 | CommandCompletion: 8
UINT8 | Param1: 8
UINT8 | Param2: 8
UINT8 | Reserved: 7
UINT8 | RunBusy: 1

Detailed Description

OC Library structures.

Definition at line 120 of file OverclockingLibrary.h.

The documentation for this struct was generated from the following file:
  • OverclockingLibrary.h


2013 SharkBay Processor Reference Code API: Member List

OC_LIBRARY_COMMAND Member List
This is the complete list of members for OC_LIBRARY_COMMAND, including all inherited members.
CommandCompletion (defined in OC_LIBRARY_COMMAND) | OC_LIBRARY_COMMAND
CommandData (defined in OC_LIBRARY_COMMAND) | OC_LIBRARY_COMMAND
Param1 (defined in OC_LIBRARY_COMMAND) | OC_LIBRARY_COMMAND
Param2 (defined in OC_LIBRARY_COMMAND) | OC_LIBRARY_COMMAND
Reserved (defined in OC_LIBRARY_COMMAND) | OC_LIBRARY_COMMAND
RunBusy (defined in OC_LIBRARY_COMMAND) | OC_LIBRARY_COMMAND


2013 SharkBay Processor Reference Code API: OVERCLOCKING_CONFIG_PPI Struct Reference

Public Attributes
OVERCLOCKING_CONFIG_PPI Struct Reference

Overclocking Configuration controls which use the CPU overclocking mailbox interface are defined in this structure. More...

#include <CpuPlatformPolicy.h>

List of all members.

Public Attributes

INT16 | CoreVoltageOffset
The voltage offset applied to the core while operating in turbo mode.
UINT16 | CoreVoltageOverride
The core voltage override which is applied to the entire range of cpu core frequencies.
UINT16 | CoreExtraTurboVoltage
Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
UINT16 | CoreMaxOcTurboRatio
Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit.
INT16 | ClrVoltageOffset
The voltage offset applied to CLR while operating in turbo mode.
UINT16 | ClrVoltageOverride
The clr voltage override which is applied to the entire range of cpu frequencies.
UINT16 | ClrExtraTurboVoltage
Extra Turbo voltage applied to clr.
UINT16 | ClrMaxOcTurboRatio
Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit.
UINT16 | SvidVoltageOverride
Overrides the VR voltage through SVID bus to apply a new input voltage to the cpu.
UINT8 | SvidEnable: 1
Enable or Disable SVID communication from FIVR to the external VR.
UINT8 | FivrFaultsEnable: 1
Enable or Disable FIVR Fault management.
UINT8 | FivrEfficiencyEnable: 1
Enable or Disable FIVR efficiency.
UINT8 | CoreVoltageMode: 1
0: Adaptive, 1: Override
UINT8 | ClrVoltageMode: 1
0: Adaptive, 1:Override
UINT8 | OcSupport: 1
0: Disable, 1: Enable
UINT8 | BitReserved: 2
Bits reserved for future use.

Detailed Description

Overclocking Configuration controls which use the CPU overclocking mailbox interface are defined in this structure.

Platform code can pass in data to the mailbox through this structure.

Definition at line 295 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

Member Data Documentation

UINT16 OVERCLOCKING_CONFIG_PPI::ClrExtraTurboVoltage

Extra Turbo voltage applied to clr.

Definition at line 311 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

INT16 OVERCLOCKING_CONFIG_PPI::CoreVoltageOffset

The voltage offset applied to the core while operating in turbo mode.

Definition at line 296 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

OVERCLOCKING_CONFIG_PPI Member List
This is the complete list of members for OVERCLOCKING_CONFIG_PPI, including all inherited members.
BitReserved | OVERCLOCKING_CONFIG_PPI
ClrExtraTurboVoltage | OVERCLOCKING_CONFIG_PPI
ClrMaxOcTurboRatio | OVERCLOCKING_CONFIG_PPI
ClrVoltageMode | OVERCLOCKING_CONFIG_PPI
ClrVoltageOffset | OVERCLOCKING_CONFIG_PPI
ClrVoltageOverride | OVERCLOCKING_CONFIG_PPI
CoreExtraTurboVoltage | OVERCLOCKING_CONFIG_PPI
CoreMaxOcTurboRatio | OVERCLOCKING_CONFIG_PPI
CoreVoltageMode | OVERCLOCKING_CONFIG_PPI
CoreVoltageOffset | OVERCLOCKING_CONFIG_PPI
CoreVoltageOverride | OVERCLOCKING_CONFIG_PPI
FivrEfficiencyEnable | OVERCLOCKING_CONFIG_PPI
FivrFaultsEnable | OVERCLOCKING_CONFIG_PPI
OcSupport | OVERCLOCKING_CONFIG_PPI
SvidEnable | OVERCLOCKING_CONFIG_PPI
SvidVoltageOverride | OVERCLOCKING_CONFIG_PPI


2013 SharkBay Processor Reference Code API: PFAT_CONFIG Struct Reference

Public Attributes
PFAT_CONFIG Struct Reference

PFAT Configuration for all processor security features configuration structures are in this field. More...

#include <CpuPlatformPolicy.h>

Collaboration diagram for PFAT_CONFIG:
[legend]

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Public Attributes

PUP_HEADER PupHeader
PFAT update package header that will be packaged along with PFAT script and update data.
PPDT Ppdt
PFAT Platform Data Table contains all the platform data that will be parsed by PFAT module.
UINT64 | PpdtHash [4]
Hash of the PPDT that will be programmed to PLAT_FRMW_PROT_HASH_0/1/2/3 MSR.
UINT8 | NumSpiComponents
Number of SPI flash components on platform.
UINT8 | ComponentSize [MAX_SPI_COMPONENTS]
Size of each flash component on platform.
UINT8 | PfatMemSize
PFAT memory size.
UINT8 | EcCmdDiscovery
EC Command discovery.
UINT8 | EcCmdProvisionEav
EC Command Provision Eav.
UINT8 | EcCmdLock
EC Command Lock.
PFAT_LOG PfatLog
PFAT log.

Detailed Description

PFAT Configuration for all processor security features configuration structures are in this field.

Platform code can pass relevant configuration data thru this field.

Definition at line 198 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

PFAT_CONFIG Member List
This is the complete list of members for PFAT_CONFIG, including all inherited members.
ComponentSize | PFAT_CONFIG
EcCmdDiscovery | PFAT_CONFIG
EcCmdLock | PFAT_CONFIG
EcCmdProvisionEav | PFAT_CONFIG
NumSpiComponents | PFAT_CONFIG
PfatLog | PFAT_CONFIG
PfatMemSize | PFAT_CONFIG
Ppdt | PFAT_CONFIG
PpdtHash | PFAT_CONFIG
PupHeader | PFAT_CONFIG


2013 SharkBay Processor Reference Code API: PFAT_HOB Struct Reference

Public Attributes
PFAT_HOB Struct Reference

HOB used to pass data through every phase of PFAT Bios PFAT Bios code is executed in PEI, DXE and SMM and HOB is the only method to properly pass data between every phase. More...

#include <PfatDefinitions.h>

Collaboration diagram for PFAT_HOB:
[legend]

List of all members.

Public Attributes

EFI_HOB_GUID_TYPE | EfiHobGuidType
PPDT Ppdt
PFAT Platform Data Table.
PUP_HEADER PupHeader
PFAT update package header, this header will be appended to all flash updates along with PSL script.
UINT8 | NumSpiComponents
Number of physical SPI flash components on platform.
UINT8 | ComponentSize [MAX_SPI_COMPONENTS]
Array containing size of each flash component.
UINT64 | PfatToolsIntIoTrapAdd
IO Trap address required to Initialize PFAT Tools Interface.
PFAT_LOG PfatLog
Header for PFAT Log Buffer.

Detailed Description

HOB used to pass data through every phase of PFAT Bios PFAT Bios code is executed in PEI, DXE and SMM and HOB is the only method to properly pass data between every phase.

Definition at line 310 of file PfatDefinitions.h.

The documentation for this struct was generated from the following file:
  • PfatDefinitions.h


2013 SharkBay Processor Reference Code API: Member List

PFAT_HOB Member List
This is the complete list of members for PFAT_HOB, including all inherited members.
ComponentSize | PFAT_HOB
EfiHobGuidType (defined in PFAT_HOB) | PFAT_HOB
NumSpiComponents | PFAT_HOB
PfatLog | PFAT_HOB
PfatToolsIntIoTrapAdd | PFAT_HOB
Ppdt | PFAT_HOB
PupHeader | PFAT_HOB


2013 SharkBay Processor Reference Code API: PFAT_LOG Struct Reference

Public Attributes
PFAT_LOG Struct Reference

PFAT Log The logging facility is used to communicate detailed information regarding the execution of a PFAT script from the SMI handler which invoked the PFAT module itself. More...

#include <PfatDefinitions.h>

List of all members.

Public Attributes

UINT16 | Version
Indicates the version of the log. Must be 0x0001.
UINT16 | LastPage
Last valid page index for the log.
UINT32 | LoggingOptions
Bitmap indicating what events to log BIT[0] - Step trace - this indicates a full execution trace.
UINT8 | Reserved5 [8]
UINT32 | PfatModSvn
Indicates a version number of the PFAT module.
UINT32 | NumOfEntriesInLog
Total number of log entries that have been written to the log.

Detailed Description

PFAT Log The logging facility is used to communicate detailed information regarding the execution of a PFAT script from the SMI handler which invoked the PFAT module itself.

Definition at line 285 of file PfatDefinitions.h.

Member Data Documentation

UINT32 PFAT_LOG::LoggingOptions

Bitmap indicating what events to log BIT[0] - Step trace - this indicates a full execution trace.

Each line is entered into the log with an EXECUTION_TRACE entry BIT[1] - Branch trace - All taken jumps are logged with a BRANCH_TRACE entry BIT[2] - Flash write - All flash write operations are logged with a FLASH_WRITE entry BIT[3] - Flash erase - All flash erase operations are logged with a FLASH_ERASE entry BIT[4] - Flash error - All error conditions from flash operations are logged with FLASH_ERROR entry BIT[5] - Debug - Log Debug opcode execution BIT[6] - PFAT module debug message - Log implementation specific debug messages from debug module BIT[31:7] - Reserved. Must be 0. If any reserved bits are set in Header.LoggingOptions, the PFAT module must disable the logging feature

Definition at line 299 of file PfatDefinitions.h.

The documentation for this struct was generated from the following file:
  • PfatDefinitions.h


2013 SharkBay Processor Reference Code API: Member List

PFAT_LOG Member List
This is the complete list of members for PFAT_LOG, including all inherited members.
LastPage | PFAT_LOG
LoggingOptions | PFAT_LOG
NumOfEntriesInLog | PFAT_LOG
PfatModSvn | PFAT_LOG
Reserved5 (defined in PFAT_LOG) | PFAT_LOG
Version | PFAT_LOG


2013 SharkBay Processor Reference Code API: PHYSICAL_LOCATION Struct Reference

Public Attributes
PHYSICAL_LOCATION Struct Reference

List of all members.

Public Attributes

UINT32 | Package
UINT32 | Die
UINT32 | Core
UINT32 | Thread

Detailed Description

Definition at line 78 of file MpService.h.

The documentation for this struct was generated from the following file:
  • MpService.h


2013 SharkBay Processor Reference Code API: Member List

PHYSICAL_LOCATION Member List
This is the complete list of members for PHYSICAL_LOCATION, including all inherited members.
Core (defined in PHYSICAL_LOCATION) | PHYSICAL_LOCATION
Die (defined in PHYSICAL_LOCATION) | PHYSICAL_LOCATION
Package (defined in PHYSICAL_LOCATION) | PHYSICAL_LOCATION
Thread (defined in PHYSICAL_LOCATION) | PHYSICAL_LOCATION


2013 SharkBay Processor Reference Code API: PL1_THERMAL_CONTROL_FLOOR Struct Reference

Public Attributes
PL1_THERMAL_CONTROL_FLOOR Struct Reference

List of all members.

Public Attributes

PL1_THERMAL_THROTTLE_FLOOR_UNIT | FloorIA
PL1_THERMAL_THROTTLE_FLOOR_UNIT | FloorGT
< FLOOR_IA, Default: 0 (Percent100)
PL1_THERMAL_THROTTLE_FLOOR_UNIT | FloorPCH
< FLOOR_GT, Default: 0 (Percent100)

Detailed Description

Definition at line 224 of file CpuPmConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPmConfig.h


2013 SharkBay Processor Reference Code API: Member List

PL1_THERMAL_CONTROL_FLOOR Member List
This is the complete list of members for PL1_THERMAL_CONTROL_FLOOR, including all inherited members.
FloorGT | PL1_THERMAL_CONTROL_FLOOR
FloorIA (defined in PL1_THERMAL_CONTROL_FLOOR) | PL1_THERMAL_CONTROL_FLOOR
FloorPCH | PL1_THERMAL_CONTROL_FLOOR


2013 SharkBay Processor Reference Code API: PLATFORM_CPU_INFORMATION Struct Reference

Public Attributes
PLATFORM_CPU_INFORMATION Struct Reference

Platform Specific Processor Information. More...

#include <CpuPlatformPolicy.h>

List of all members.

Public Attributes

UINT64 | ApicID
APIC ID.
STRING_REF | ReferenceString
Reference String.
EFI_PROCESSOR_SOCKET_TYPE_DATA | SocketType
Socket Type.
EFI_PROCESSOR_SOCKET_NAME_DATA | SocketName
Socket Name.
EFI_PROCESSOR_MAX_CORE_FREQUENCY_DATA | MaxCoreFrequency
Maximum Core Frequency.
EFI_PROCESSOR_MAX_FSB_FREQUENCY_DATA | MaxFsbFrequency
Maximum FSB Frequency.
EFI_PROCESSOR_CORE_FREQUENCY_LIST_DATA | PlatformCoreFrequencyList
Platform Core Frequency List.
EFI_PROCESSOR_FSB_FREQUENCY_LIST_DATA | PlatformFsbFrequencyList
Platform FSB Frequency List.
STRING_REF | AssetTag
Asset Tag.
EFI_HII_HANDLE | StringHandle
String Handle.
STRING_REF | SerialNumber
Serial Number.
STRING_REF | PartNumber
Part Number.

Detailed Description

Platform Specific Processor Information.

Definition at line 174 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

PLATFORM_CPU_INFORMATION Member List
This is the complete list of members for PLATFORM_CPU_INFORMATION, including all inherited members.
ApicID | PLATFORM_CPU_INFORMATION
AssetTag | PLATFORM_CPU_INFORMATION
MaxCoreFrequency | PLATFORM_CPU_INFORMATION
MaxFsbFrequency | PLATFORM_CPU_INFORMATION
PartNumber | PLATFORM_CPU_INFORMATION
PlatformCoreFrequencyList | PLATFORM_CPU_INFORMATION
PlatformFsbFrequencyList | PLATFORM_CPU_INFORMATION
ReferenceString | PLATFORM_CPU_INFORMATION
SerialNumber | PLATFORM_CPU_INFORMATION
SocketName | PLATFORM_CPU_INFORMATION
SocketType | PLATFORM_CPU_INFORMATION
StringHandle | PLATFORM_CPU_INFORMATION


2013 SharkBay Processor Reference Code API: POWER_MGMT_CONFIG Struct Reference

Public Attributes
POWER_MGMT_CONFIG Struct Reference

Power management Configuration for all processor Power Management features enabling definitions are in this field. More...

#include <CpuPmConfig.h>

Collaboration diagram for POWER_MGMT_CONFIG:
[legend]

List of all members.

Public Attributes

PPM_FUNCTION_ENABLES * pFunctionEnables
This structure is used to describe which of the PPM functions should be enabled.
PPM_CUSTOM_RATIO_TABLE * pCustomRatioTable
This structure is used to describe the custom CPU Frequency Table that should be used.
PPM_TURBO_SETTINGS * pTurboSettings
This structure is used to describe long duration and short duration turbo settings.
UINT8 | S3RestoreMsrSwSmiNumber
SW SMI number to restore the power Mgmt MSRs during S3 resume.
UINT8 * | pRatioLimit
This field is a pointer to Ratio Limit.
PPM_LOCK_ENABLES * pPpmLockEnables
This field is a pointer to PPM_LOCK_ENABLES structure.
PPM_CUSTOM_CTDP * pCustomCtdpSettings
This structure is used to describe the custom config TDP settings.
MAX_PKG_C_STATE PkgCStateLimit
This field is used to set the Max Pkg Cstate.
C_STATE_TIME_UNIT CstateLatencyControl0TimeUnit
TimeUnit for Latency Control0 MSR 0x60A[12:10].
C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit
TimeUnit for Latency Control1 MSR 0x60B[12:10].
C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit
TimeUnit for Latency Control2 MSR 0x60C[12:10].
C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit
TimeUnit for Latency Control3 MSR 0x633[12:10].
C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit
TimeUnit for Latency Control4 MSR 0x634[12:10].
C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit
TimeUnit for Latency Control5 MSR 0x635[12:10].
UINT16 | CstateLatencyControl0Irtl
Interrupt Response Time Limit of LatencyContol0 MSR 0x60A[9:0].
UINT16 | CstateLatencyControl1Irtl
Interrupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0].
UINT16 | CstateLatencyControl2Irtl
Interrupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0].
UINT16 | CstateLatencyControl3Irtl
Interrupt Response Time Limit of LatencyContol3 MSR 0x633[9:0].
UINT16 | CstateLatencyControl4Irtl
Interrupt Response Time Limit of LatencyContol4 MSR 0x634[9:0].
UINT16 | CstateLatencyControl5Irtl
Interrupt Response Time Limit of LatencyContol5 MSR 0x635[9:0].
BOOLEAN | RfiFreqTunningOffsetIsNegative
Specify RfiFreqTunningOffset is Positive or Negative.
UINT8 | RfiFreqTunningOffset
specify the Target FIVR Frequency offset.
UINT8 | PcodeCalibration
Calibrate 24MHz BCLK support; 0: NO_CALIBRATE, 1: PCODE_CALIBRATE, 2: BIOS_CALIBRATE (Default :1)
BOOLEAN | EnableRerunPcodeCalibration
Calibrate C state 24MHz BCLK support.
THERM_FUNCTION_ENABLES * ThermalFuncEnables
This structure is used to describe which of the Thermal functions should be enabled.
CUSTOM_POWER_UNIT CustomPowerUnit
Power Management Custom Power Limit Unit.

Detailed Description

Power management Configuration for all processor Power Management features enabling definitions are in this field.

Platform code can enable/disable features thru this field.

Definition at line 250 of file CpuPmConfig.h.

Member Data Documentation

BOOLEAN POWER_MGMT_CONFIG::EnableRerunPcodeCalibration

Calibrate C state 24MHz BCLK support.

Definition at line 292 of file CpuPmConfig.h.

PPM_CUSTOM_CTDP* POWER_MGMT_CONFIG::pCustomCtdpSettings

This structure is used to describe the custom config TDP settings.

Definition at line 269 of file CpuPmConfig.h.

PPM_CUSTOM_RATIO_TABLE* POWER_MGMT_CONFIG::pCustomRatioTable

This structure is used to describe the custom CPU Frequency Table that should be used.

For details of this structure, please see Related Definitions.

Definition at line 260 of file CpuPmConfig.h.

PPM_FUNCTION_ENABLES* POWER_MGMT_CONFIG::pFunctionEnables

This structure is used to describe which of the PPM functions should be enabled.

For details of this structure, please see Related Definitions.

Definition at line 255 of file CpuPmConfig.h.

MAX_PKG_C_STATE POWER_MGMT_CONFIG::PkgCStateLimit

This field is used to set the Max Pkg Cstate.

Default set to Auto which limits the Max Pkg Cstate to deep C-state.

Definition at line 273 of file CpuPmConfig.h.

PPM_TURBO_SETTINGS* POWER_MGMT_CONFIG::pTurboSettings

This structure is used to describe long duration and short duration turbo settings.

For details of this structure, please see Related Definitions.

Definition at line 265 of file CpuPmConfig.h.

UINT8 POWER_MGMT_CONFIG::RfiFreqTunningOffset

specify the Target FIVR Frequency offset.

Definition at line 287 of file CpuPmConfig.h.

THERM_FUNCTION_ENABLES* POWER_MGMT_CONFIG::ThermalFuncEnables

This structure is used to describe which of the Thermal functions should be enabled.

For details of this structure, please see Related Definitions.

Definition at line 297 of file CpuPmConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPmConfig.h


2013 SharkBay Processor Reference Code API: Member List

POWER_MGMT_CONFIG Member List
This is the complete list of members for POWER_MGMT_CONFIG, including all inherited members.
CstateLatencyControl0Irtl | POWER_MGMT_CONFIG
CstateLatencyControl0TimeUnit | POWER_MGMT_CONFIG
CstateLatencyControl1Irtl | POWER_MGMT_CONFIG
CstateLatencyControl1TimeUnit | POWER_MGMT_CONFIG
CstateLatencyControl2Irtl | POWER_MGMT_CONFIG
CstateLatencyControl2TimeUnit | POWER_MGMT_CONFIG
CstateLatencyControl3Irtl | POWER_MGMT_CONFIG
CstateLatencyControl3TimeUnit | POWER_MGMT_CONFIG
CstateLatencyControl4Irtl | POWER_MGMT_CONFIG
CstateLatencyControl4TimeUnit | POWER_MGMT_CONFIG
CstateLatencyControl5Irtl | POWER_MGMT_CONFIG
CstateLatencyControl5TimeUnit | POWER_MGMT_CONFIG
CustomPowerUnit | POWER_MGMT_CONFIG
EnableRerunPcodeCalibration | POWER_MGMT_CONFIG
PcodeCalibration | POWER_MGMT_CONFIG
pCustomCtdpSettings | POWER_MGMT_CONFIG
pCustomRatioTable | POWER_MGMT_CONFIG
pFunctionEnables | POWER_MGMT_CONFIG
PkgCStateLimit | POWER_MGMT_CONFIG
pPpmLockEnables | POWER_MGMT_CONFIG
pRatioLimit | POWER_MGMT_CONFIG
pTurboSettings | POWER_MGMT_CONFIG
RfiFreqTunningOffset | POWER_MGMT_CONFIG
RfiFreqTunningOffsetIsNegative | POWER_MGMT_CONFIG
S3RestoreMsrSwSmiNumber | POWER_MGMT_CONFIG
ThermalFuncEnables | POWER_MGMT_CONFIG


2013 SharkBay Processor Reference Code API: POWER_MGMT_CONFIG_PPI Struct Reference

Public Attributes
POWER_MGMT_CONFIG_PPI Struct Reference

Power management Configuration for all Processor Power Management Features Configs are in this field. More...

#include <CpuPlatformPolicy.h>

List of all members.

Public Attributes

UINT8 | BootInLfm
Boot in Low-Frequency-Mode.
UINT8 | TccActivationOffset
TCC Activation Offset.
UINT16 | VrCurrentLimit
MSR 0x601[12:0], Primary (IA) Current Limit, in 1/8 A units, 0=Auto.
UINT8 | VrCurrentLimitLock
MSR 0x601[31]: when set, locks bits 31:0 of this MSR.
UINT8 | Xe
Enable or Disable Intel Extreme Edition support.
UINT8 | RatioLimit [4]
1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 1-Core Ratio Limit + OC Bins.
UINT8 | VrMiscMinVid
MSR 0x603[31:24]: Used to constrain the CPU's minimum voltage during package C-states.
UINT8 | VrMiscIdleExitRampRate
MSR 0x603[50]: Controls the VR ramp rate on package C-state wake events.
UINT8 | VrMiscIdleEntryRampRate
MSR 0x603[51]: Controls the VR ramp rate on package C-state entry events.
UINT8 | VrMiscIdleEntryDecayEnable
MSR 0x603[52]: Enables decay mode on package C-state entry.
UINT8 | VrMiscSlowSlewRateConfig
MSR 0x53[54:53]: Slow Slew rate configuration.
UINT8 | VrMisc2FastRampVoltage
MSR 0x636[7:0]: Update FAST_RAMP_VOLTAGE; must be 0 to 0xFF, resolution 10mV.
UINT8 | VrMisc2MinC8Voltage
MSR 0x636[15:8]: Update MIN_C8_VOLTAGE; must be 0 to 0xFF, resolution 10mV.
UINT16 | VrMiscIoutSlope
MSR 0x603[49-40]: IOUT SLOPE. Default is 200.
UINT8 | VrMiscIoutOffsetSign
IOUT OFFSET Sign. 0 = positive offset. 1= negative offset.
UINT16 | VrMiscIoutOffset
MSR 0x603[39-32]: IOUT_OFFSET. 0 = 0%, 625 = 6.25% (Range is +6.25% ~ -6.25%)
UINT8 | VrPSI4enable
MSR 0x601[62]: PSI4 Enabled/Disabled bit in VR_CURRENT_CONFIG, it¡¦s only applied to HSW ULT.
UINT8 | Psi1Threshold
MSR 0x601[41:32]: Current Threshold for PSI1_CODE specified in Amps.
UINT8 | Psi2Threshold
MSR 0x601[51:42]: Current Threshold for PSI2_CODE specified in Amps.
UINT8 | Psi3Threshold
MSR 0x601[61:52]: Current Threshold for PSI3_CODE specified in Amps.
UINT8 | FivrSscEnable
Enable/Disable FIVR Spread Spectrum support.
UINT8 | FivrSscPercent
PCODE MMIO Mailbox: FIVR spread spectrum percentage value.

Detailed Description

Power management Configuration for all Processor Power Management Features Configs are in this field.

Platform code can enable/disable features thru this field.

Definition at line 149 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

Member Data Documentation

UINT8 POWER_MGMT_CONFIG_PPI::BootInLfm

Boot in Low-Frequency-Mode.

Definition at line 150 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

UINT8 POWER_MGMT_CONFIG_PPI::RatioLimit[4]

1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 1-Core Ratio Limit + OC Bins.

This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 2-Core Ratio Limit + OC Bins. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit. 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 3-Core Ratio Limit + OC Bins. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit. 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 4-Core Ratio Limit + OC Bins. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.

Definition at line 175 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

UINT8 POWER_MGMT_CONFIG_PPI::TccActivationOffset

TCC Activation Offset.

Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temp ¡V TCC Activation Offset.

Definition at line 155 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

UINT16 POWER_MGMT_CONFIG_PPI::VrCurrentLimit

MSR 0x601[12:0], Primary (IA) Current Limit, in 1/8 A units, 0=Auto.

Maximum instantaneous current allowed at any given time. Setting a value too far below the Iccmax specification for this platform/CPU might result in System hang / CATERR / BSOD depending on the platform configuration.

Definition at line 161 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

UINT8 POWER_MGMT_CONFIG_PPI::Xe

Enable or Disable Intel Extreme Edition support.

Definition at line 163 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

POWER_MGMT_CONFIG_PPI Member List
This is the complete list of members for POWER_MGMT_CONFIG_PPI, including all inherited members.
BootInLfm | POWER_MGMT_CONFIG_PPI
FivrSscEnable | POWER_MGMT_CONFIG_PPI
FivrSscPercent | POWER_MGMT_CONFIG_PPI
Psi1Threshold | POWER_MGMT_CONFIG_PPI
Psi2Threshold | POWER_MGMT_CONFIG_PPI
Psi3Threshold | POWER_MGMT_CONFIG_PPI
RatioLimit | POWER_MGMT_CONFIG_PPI
TccActivationOffset | POWER_MGMT_CONFIG_PPI
VrCurrentLimit | POWER_MGMT_CONFIG_PPI
VrCurrentLimitLock | POWER_MGMT_CONFIG_PPI
VrMisc2FastRampVoltage | POWER_MGMT_CONFIG_PPI
VrMisc2MinC8Voltage | POWER_MGMT_CONFIG_PPI
VrMiscIdleEntryDecayEnable | POWER_MGMT_CONFIG_PPI
VrMiscIdleEntryRampRate | POWER_MGMT_CONFIG_PPI
VrMiscIdleExitRampRate | POWER_MGMT_CONFIG_PPI
VrMiscIoutOffset | POWER_MGMT_CONFIG_PPI
VrMiscIoutOffsetSign | POWER_MGMT_CONFIG_PPI
VrMiscIoutSlope | POWER_MGMT_CONFIG_PPI
VrMiscMinVid | POWER_MGMT_CONFIG_PPI
VrMiscSlowSlewRateConfig | POWER_MGMT_CONFIG_PPI
VrPSI4enable | POWER_MGMT_CONFIG_PPI
Xe | POWER_MGMT_CONFIG_PPI


2013 SharkBay Processor Reference Code API: PPDT Struct Reference

Public Attributes
PPDT Struct Reference

PFAT Platform Data Table (PPDT) Provides platform specific data required by PFAT Module. More...

#include <PfatDefinitions.h>

Collaboration diagram for PPDT:
[legend]

List of all members.

Public Attributes

UINT32 | PpdtSize
Size in bytes of PPDT including SFAM.
UINT16 | PpdtMajVer
Indicates major version of PPDT.
UINT16 | PpdtMinVer
Indicates minor version of PPDT.
UINT8 | PlatId [16]
PLAT_ID used to be compared against the one found in the PUP Header to prevent cross platform flashing.
UINT8 | PkeySlot0 [32]
SHA256 hash for PUP verification key 0.
UINT8 | PkeySlot1 [32]
SHA256 hash for PUP verification key 1.
UINT8 | PkeySlot2 [32]
SHA256 hash for PUP verification key 2.
UINT32 | PfatModSvn
PFAT Module SVN.
UINT32 | BiosSvn
BIOS_SVN to prevent back-flashing.
UINT32 | ExecLim
Limit the number of opcodes that can be executed on any invocation of PFAT.
UINT32 | PlatAttr
Bitmap of platform policy attributes BIT[0]: Reserved.
UINT32 | EcCmd
BIT[9:0] - 8 bit IO port used for sending EC commands (writes), and reading EC status (reads) This field must be populated if PLAT_ATTR.EC_PRESENT != 0 This field must be zero if PLAT_ATTR.EC_PRESENT == 0 BIT[31:10] - Reserved.
UINT32 | EcData
BIT[9:0] - 8 bit IO port used for reading and writing data to the EC based on a command issued to EC_CMD This field must be populated if PLAT_ATTR.EC_PRESENT != 0 This field must be zero if PLAT_ATTR.EC_PRESENT == 0 BIT[31:10] - Reserved.
UINT32 | EcCmdGetSvn
BIT[7:0] - EC command indicating a read of the current EC firmware SVN This field must be populated if PLAT_ATTR.EC_PRESENT != 0 This field must be zero if PLAT_ATTR.EC_PRESENT == 0 BIT[31:8] - Reserved.
UINT32 | EcCmdOpen
BIT[7:0] - EC command indicating flash begin of flash update session This field must be populated if PLAT_ATTR.EC_PRESENT != 0 This field must be zero if PLAT_ATTR.EC_PRESENT == 0 BIT[31:8] - Reserved.
UINT32 | EcCmdClose
BIT[7:0] - EC command indicating the termination of PFAT protected session This field must be populated if PLAT_ATTR.EC_PRESENT != 0 This field must be zero if PLAT_ATTR.EC_PRESENT == 0 BIT[31:8] - Reserved.
UINT32 | EcCmdPortTest
BIT[7:0] - EC command used to verify connectivity between PFAT and EC This field must be populated if PLAT_ATTR.EC_PRESENT != 0 This field must be zero if PLAT_ATTR.EC_PRESENT == 0 BIT[31:8] - Reserved.
UINT8 | Reserved1 [4]
UINT8 | LastSfam
Defines number of elements in SFAM array BIT[5..0]: Index of the last SFAM element BIT[7..6]: Reserved for future use.
UINT8 | Reserved2 [3]
SFAM_DATA | SfamData [MAX_SFAM_COUNT]
Array of flash address map descriptors. sizeof (SFAM_DESC) == 8.

Detailed Description

PFAT Platform Data Table (PPDT) Provides platform specific data required by PFAT Module.

Definition at line 163 of file PfatDefinitions.h.

Member Data Documentation

UINT32 PPDT::EcCmd

BIT[9:0] - 8 bit IO port used for sending EC commands (writes), and reading EC status (reads) This field must be populated if PLAT_ATTR.EC_PRESENT != 0 This field must be zero if PLAT_ATTR.EC_PRESENT == 0 BIT[31:10] - Reserved.

Must be 0

Definition at line 198 of file PfatDefinitions.h.

UINT32 PPDT::EcCmdClose

BIT[7:0] - EC command indicating the termination of PFAT protected session This field must be populated if PLAT_ATTR.EC_PRESENT != 0 This field must be zero if PLAT_ATTR.EC_PRESENT == 0 BIT[31:8] - Reserved.

Must be 0

Definition at line 226 of file PfatDefinitions.h.

UINT32 PPDT::EcCmdGetSvn

BIT[7:0] - EC command indicating a read of the current EC firmware SVN This field must be populated if PLAT_ATTR.EC_PRESENT != 0 This field must be zero if PLAT_ATTR.EC_PRESENT == 0 BIT[31:8] - Reserved.

Must be 0

Definition at line 212 of file PfatDefinitions.h.

UINT32 PPDT::EcCmdOpen

BIT[7:0] - EC command indicating flash begin of flash update session This field must be populated if PLAT_ATTR.EC_PRESENT != 0 This field must be zero if PLAT_ATTR.EC_PRESENT == 0 BIT[31:8] - Reserved.

Must be 0

Definition at line 219 of file PfatDefinitions.h.

UINT32 PPDT::EcCmdPortTest

BIT[7:0] - EC command used to verify connectivity between PFAT and EC This field must be populated if PLAT_ATTR.EC_PRESENT != 0 This field must be zero if PLAT_ATTR.EC_PRESENT == 0 BIT[31:8] - Reserved.

Must be 0

Definition at line 233 of file PfatDefinitions.h.

UINT32 PPDT::EcData

BIT[9:0] - 8 bit IO port used for reading and writing data to the EC based on a command issued to EC_CMD This field must be populated if PLAT_ATTR.EC_PRESENT != 0 This field must be zero if PLAT_ATTR.EC_PRESENT == 0 BIT[31:10] - Reserved.

Must be 0

Definition at line 205 of file PfatDefinitions.h.

UINT8 PPDT::LastSfam

Defines number of elements in SFAM array BIT[5..0]: Index of the last SFAM element BIT[7..6]: Reserved for future use.

Must be 0

Definition at line 240 of file PfatDefinitions.h.

UINT32 PPDT::PlatAttr

Bitmap of platform policy attributes BIT[0]: Reserved.

Must be 0 BIT[2:1] (EC_PRESENT) 00b = There is not an EC is the system 01b = There exists an EC in the system, PFAT does not extend any protection to the EC 11b = There exist an EC in the system, PFAT extends protection to the EC 10b = Reserved. Must not be used BIT[3]: (DESCRIPTOR_OVERRIDE_POLICY) 0b = Do not override PFAT security policy 1b = Override PFAT security policy BIT[23:4]: Reserved, must be 0 BIT[24]: 0b = indicates PFAT module will not take additional steps. 1b = indicates PFAT module should take additional steps to mitigate potential interference from installed PEG device. BIT[31:25] Reserved, must be 0

Definition at line 191 of file PfatDefinitions.h.

The documentation for this struct was generated from the following file:
  • PfatDefinitions.h


2013 SharkBay Processor Reference Code API: Member List

PPDT Member List
This is the complete list of members for PPDT, including all inherited members.
BiosSvn | PPDT
EcCmd | PPDT
EcCmdClose | PPDT
EcCmdGetSvn | PPDT
EcCmdOpen | PPDT
EcCmdPortTest | PPDT
EcData | PPDT
ExecLim | PPDT
LastSfam | PPDT
PfatModSvn | PPDT
PkeySlot0 | PPDT
PkeySlot1 | PPDT
PkeySlot2 | PPDT
PlatAttr | PPDT
PlatId | PPDT
PpdtMajVer | PPDT
PpdtMinVer | PPDT
PpdtSize | PPDT
Reserved1 (defined in PPDT) | PPDT
Reserved2 (defined in PPDT) | PPDT
SfamData | PPDT


2013 SharkBay Processor Reference Code API: PPM_CTDP_LEVEL_SETTINGS Struct Reference

Public Attributes
PPM_CTDP_LEVEL_SETTINGS Struct Reference

List of all members.

Public Attributes

UINT16 | CtdpPowerLimit1
CTDP Power Limit1.
UINT16 | CtdpPowerLimit2
CTDP Power Limit2.
UINT8 | CtdpPowerLimitWindow
CTDP Power Limit Time Window.
UINT8 | CtdpCtc
CTDP CTC.
UINT8 | CtdpTar
CTDP TAR.
UINT8 | CtdpPpc
CTDP PPC.

Detailed Description

Definition at line 52 of file PpmGlobalNvsArea.h.

The documentation for this struct was generated from the following file:
  • PpmGlobalNvsArea.h


2013 SharkBay Processor Reference Code API: Member List

PPM_CTDP_LEVEL_SETTINGS Member List
This is the complete list of members for PPM_CTDP_LEVEL_SETTINGS, including all inherited members.
CtdpCtc | PPM_CTDP_LEVEL_SETTINGS
CtdpPowerLimit1 | PPM_CTDP_LEVEL_SETTINGS
CtdpPowerLimit2 | PPM_CTDP_LEVEL_SETTINGS
CtdpPowerLimitWindow | PPM_CTDP_LEVEL_SETTINGS
CtdpPpc | PPM_CTDP_LEVEL_SETTINGS
CtdpTar | PPM_CTDP_LEVEL_SETTINGS


2013 SharkBay Processor Reference Code API: PPM_CUSTOM_RATIO_TABLE Struct Reference

Public Attributes
PPM_CUSTOM_RATIO_TABLE Struct Reference

This structure is used to describe the custom processor ratio table desired by the platform. More...

#include <CpuPmConfig.h>

List of all members.

Public Attributes

UINT8 | NumberOfEntries
The number of custom ratio state entries, it must be a value from 2 to 16 for a valid custom ratio table.
UINT32 | Cpuid
The CPU ID for which this custom ratio table applies.
UINT16 | MaxRatio
The maximum ratio of the custom ratio table.
UINT16 | StateRatio [MAX_CUSTOM_RATIO_TABLE_ENTRIES]
The processor ratios in the custom ratio table.

Detailed Description

This structure is used to describe the custom processor ratio table desired by the platform.

Definition at line 37 of file CpuPmConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPmConfig.h


2013 SharkBay Processor Reference Code API: Member List

PPM_CUSTOM_RATIO_TABLE Member List
This is the complete list of members for PPM_CUSTOM_RATIO_TABLE, including all inherited members.
Cpuid | PPM_CUSTOM_RATIO_TABLE
MaxRatio | PPM_CUSTOM_RATIO_TABLE
NumberOfEntries | PPM_CUSTOM_RATIO_TABLE
StateRatio | PPM_CUSTOM_RATIO_TABLE


2013 SharkBay Processor Reference Code API: PPM_FUNCTION_ENABLES Struct Reference

Public Attributes
PPM_FUNCTION_ENABLES Struct Reference

This structure is used to describe which of the PPM functions will be enabled by PPM implementation. More...

#include <CpuPmConfig.h>

List of all members.

Public Attributes

UINT32 | Eist: 1
Enable or Disable Intel SpeedStep Technology.
UINT32 | Cx: 1
Enable or Disable CPU power states (C-states).
UINT32 | C1e: 1
Enable or Disable Enhanced C-states.
UINT32 | C3: 1
Enable or Disable C3.
UINT32 | C6: 1
Enable or Disable C6.
UINT32 | DeepCState: 3
Enable or Disable C7/C7S.
UINT32 | LongLatencyC6: 1
Enable or Disable C6 Long Latency.
UINT32 | LongLatencyC7: 1
Enable or Disable C7 Long Latency.
UINT32 | C8: 1
Enable or Disable C8.
UINT32 | C9: 1
Enable or Disable C9.
UINT32 | C10: 1
Enable or Disable C10.
UINT32 | C1AutoDemotion: 1
Enable or Disable C1 Auto Demotion.
UINT32 | C3AutoDemotion: 1
Enable or Disable C3 Auto Demotion.
UINT32 | TurboMode: 1
Enable or Disable long duration Turbo Mode.
UINT32 | PowerLimit2: 1
Enable or Disable short duration Turbo Mode.
UINT32 | EnergyEfficientPState: 1
Enable or Disable Energy Efficient P-state will be applied in Turbo mode.
UINT32 | BiProcHot: 1
UINT32 | TStates: 1
UINT32 | Xe: 1
Enable or Disable Intel Extreme Edition support.
UINT32 | C1UnDemotion: 1
Enable or Disable C1UnDemotion.
UINT32 | C3UnDemotion: 1
Enable or Disable C3UnDemotion.
UINT32 | PkgCStateDemotion: 1
Enable or Disable Package Cstate Demotion.
UINT32 | PkgCStateUnDemotion: 1
Enable or Disable Package Cstate UnDemotion.
UINT32 | DisableProcHotOut: 1
UINT32 | DisableVRThermalAlert: 1
UINT32 | ProcHotResponce: 1
UINT32 | AutoThermalReporting: 1
UINT32 | CStatePreWake: 1
Enable or Disable CState-Pre wake.
UINT32 | ThermalMonitor: 1
UINT32 | LakeTiny: 1
Enable or Disable LakeTiny Support.
UINT32 | TimedMwait: 1
Enable or Disable TimedMwait Support.
UINT32 | Reserved: 2
Bits reserved for future use.

Detailed Description

This structure is used to describe which of the PPM functions will be enabled by PPM implementation.

Definition at line 50 of file CpuPmConfig.h.

Member Data Documentation

UINT32 PPM_FUNCTION_ENABLES::AutoThermalReporting
Deprecated:
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.

Definition at line 77 of file CpuPmConfig.h.

UINT32 PPM_FUNCTION_ENABLES::BiProcHot
Deprecated:
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.

Definition at line 67 of file CpuPmConfig.h.

UINT32 PPM_FUNCTION_ENABLES::DisableProcHotOut
Deprecated:
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.

Definition at line 74 of file CpuPmConfig.h.

UINT32 PPM_FUNCTION_ENABLES::DisableVRThermalAlert
Deprecated:
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.

Definition at line 75 of file CpuPmConfig.h.

UINT32 PPM_FUNCTION_ENABLES::ProcHotResponce
Deprecated:
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.

Definition at line 76 of file CpuPmConfig.h.

UINT32 PPM_FUNCTION_ENABLES::ThermalMonitor
Deprecated:
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.

Definition at line 79 of file CpuPmConfig.h.

UINT32 PPM_FUNCTION_ENABLES::TStates
Deprecated:
in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.

Definition at line 68 of file CpuPmConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPmConfig.h


2013 SharkBay Processor Reference Code API: Member List

PPM_FUNCTION_ENABLES Member List
This is the complete list of members for PPM_FUNCTION_ENABLES, including all inherited members.
AutoThermalReporting | PPM_FUNCTION_ENABLES
BiProcHot | PPM_FUNCTION_ENABLES
C10 | PPM_FUNCTION_ENABLES
C1AutoDemotion | PPM_FUNCTION_ENABLES
C1e | PPM_FUNCTION_ENABLES
C1UnDemotion | PPM_FUNCTION_ENABLES
C3 | PPM_FUNCTION_ENABLES
C3AutoDemotion | PPM_FUNCTION_ENABLES
C3UnDemotion | PPM_FUNCTION_ENABLES
C6 | PPM_FUNCTION_ENABLES
C8 | PPM_FUNCTION_ENABLES
C9 | PPM_FUNCTION_ENABLES
CStatePreWake | PPM_FUNCTION_ENABLES
Cx | PPM_FUNCTION_ENABLES
DeepCState | PPM_FUNCTION_ENABLES
DisableProcHotOut | PPM_FUNCTION_ENABLES
DisableVRThermalAlert | PPM_FUNCTION_ENABLES
Eist | PPM_FUNCTION_ENABLES
EnergyEfficientPState | PPM_FUNCTION_ENABLES
LakeTiny | PPM_FUNCTION_ENABLES
LongLatencyC6 | PPM_FUNCTION_ENABLES
LongLatencyC7 | PPM_FUNCTION_ENABLES
PkgCStateDemotion | PPM_FUNCTION_ENABLES
PkgCStateUnDemotion | PPM_FUNCTION_ENABLES
PowerLimit2 | PPM_FUNCTION_ENABLES
ProcHotResponce | PPM_FUNCTION_ENABLES
Reserved | PPM_FUNCTION_ENABLES
ThermalMonitor | PPM_FUNCTION_ENABLES
TimedMwait | PPM_FUNCTION_ENABLES
TStates | PPM_FUNCTION_ENABLES
TurboMode | PPM_FUNCTION_ENABLES
Xe | PPM_FUNCTION_ENABLES


2013 SharkBay Processor Reference Code API: PPM_GLOBAL_NVS_AREA Struct Reference

Public Attributes
PPM_GLOBAL_NVS_AREA Struct Reference

Global NVS Area definition. More...

#include <PpmGlobalNvsArea.h>

Collaboration diagram for PPM_GLOBAL_NVS_AREA:
[legend]

List of all members.

Public Attributes

UINT8 | Revision
(0) PPM GlobalNvs Revision
UINT32 | PpmFlags
(1-4) PPM Flags
UINT8 | Reserved
(5) Reserved
UINT8 | AutoCriticalTripPoint
(6) Auto Critical Trip Point
UINT8 | AutoPassiveTripPoint
(7) Auto Passive Trip Point
UINT8 | AutoActiveTripPoint
(8) Auto Active Trip Point
UINT32 | Cpuid
(9) CPUID
UINT8 | ConfigurablePpc
(13) Boot Mode vlues for _PPC
UINT8 | CustomConfigTdp
(14) ConfigTdp Enabled/Disabled
UINT8 | CtdpLevelsSupported
(15) ConfigTdp Number Of Levels
UINT8 | ConfigTdpBootModeIndex
(16) CTDP Boot Mode Index
PPM_CTDP_LEVEL_SETTINGS | CtdpLevelSettings [3]
(17) CTDP Level 0 Power Limit1 (19) CTDP Level 0 Power Limit2 (21) CTDP Level 0 Power Limit1 Time Window (22) CTDP Level 0 CTC (23) CTDP Level 0 TAR (24) CTDP Level 0 PPC (25) CTDP Level 1 Power Limit1 (27) CTDP Level 1 Power Limit2 (29) CTDP Level 1 Power Limit1 Time Window (30) CTDP Level 1 CTC (31) CTDP Level 1 TAR (32) CTDP Level 1 PPC (33) CTDP Level 2 Power Limit1 (35) CTDP Level 2 Power Limit2 (37) CTDP Level 2 Power Limit1 Time Window (38) CTDP Level 2 CTC (39) CTDP Level 2 TAR (40) CTDP Level 2 PPC
UINT8 | C3MwaitValue
(41) Mwait Hint value for C3
UINT8 | C6MwaitValue
(42) Mwait Hint value for C6
UINT8 | C7MwaitValue
(43) Mwait Hint value for C6
UINT8 | CDMwaitValue
(44) Mwait Hint value for C7/C8/C9/C10
UINT16 | C3Latency
(45-46) Latency value for C3
UINT16 | C6Latency
(47-48) Latency Value for C6
UINT16 | C7Latency
(49-50) Latency Value for C6
UINT16 | CDLatency
(51-52) Latency Value for C7/C8/C9/C10
UINT16 | CDIOLevel
(53-54) IO Level Value for C7/C8/C9/C10
UINT16 | CDPowerValue
(55-56) Power Value for C7/C8/C9/C10
UINT8 | MiscPowerManagementFlags
(57) MiscPowerManagementFlags

Detailed Description

Global NVS Area definition.

Definition at line 64 of file PpmGlobalNvsArea.h.

The documentation for this struct was generated from the following file:
  • PpmGlobalNvsArea.h


2013 SharkBay Processor Reference Code API: Member List

PPM_GLOBAL_NVS_AREA Member List
This is the complete list of members for PPM_GLOBAL_NVS_AREA, including all inherited members.
AutoActiveTripPoint | PPM_GLOBAL_NVS_AREA
AutoCriticalTripPoint | PPM_GLOBAL_NVS_AREA
AutoPassiveTripPoint | PPM_GLOBAL_NVS_AREA
C3Latency | PPM_GLOBAL_NVS_AREA
C3MwaitValue | PPM_GLOBAL_NVS_AREA
C6Latency | PPM_GLOBAL_NVS_AREA
C6MwaitValue | PPM_GLOBAL_NVS_AREA
C7Latency | PPM_GLOBAL_NVS_AREA
C7MwaitValue | PPM_GLOBAL_NVS_AREA
CDIOLevel | PPM_GLOBAL_NVS_AREA
CDLatency | PPM_GLOBAL_NVS_AREA
CDMwaitValue | PPM_GLOBAL_NVS_AREA
CDPowerValue | PPM_GLOBAL_NVS_AREA
ConfigTdpBootModeIndex | PPM_GLOBAL_NVS_AREA
ConfigurablePpc | PPM_GLOBAL_NVS_AREA
Cpuid | PPM_GLOBAL_NVS_AREA
CtdpLevelSettings | PPM_GLOBAL_NVS_AREA
CtdpLevelsSupported | PPM_GLOBAL_NVS_AREA
CustomConfigTdp | PPM_GLOBAL_NVS_AREA
MiscPowerManagementFlags | PPM_GLOBAL_NVS_AREA
PpmFlags | PPM_GLOBAL_NVS_AREA
Reserved | PPM_GLOBAL_NVS_AREA
Revision | PPM_GLOBAL_NVS_AREA


2013 SharkBay Processor Reference Code API: PSEUDO_DESCRIPTOR Struct Reference

Public Attributes
PSEUDO_DESCRIPTOR Struct Reference

List of all members.

Public Attributes

UINT16 | Limit
UINTN | Base

Detailed Description

Definition at line 27 of file CpuDataStruct.h.

The documentation for this struct was generated from the following file:
  • CpuDataStruct.h


2013 SharkBay Processor Reference Code API: Member List

PSEUDO_DESCRIPTOR Member List
This is the complete list of members for PSEUDO_DESCRIPTOR, including all inherited members.
Base (defined in PSEUDO_DESCRIPTOR) | PSEUDO_DESCRIPTOR
Limit (defined in PSEUDO_DESCRIPTOR) | PSEUDO_DESCRIPTOR


2013 SharkBay Processor Reference Code API: PUP Struct Reference

Public Attributes
PUP Struct Reference
Collaboration diagram for PUP:
[legend]

List of all members.

Public Attributes

PUP_HEADER | PupHeader
UINT64 | PupBuffer [PUP_BUFFER_SIZE/8]

Detailed Description

Definition at line 268 of file PfatDefinitions.h.

The documentation for this struct was generated from the following file:
  • PfatDefinitions.h


2013 SharkBay Processor Reference Code API: Member List

PUP Member List
This is the complete list of members for PUP, including all inherited members.
PupBuffer (defined in PUP) | PUP
PupHeader (defined in PUP) | PUP


2013 SharkBay Processor Reference Code API: PUP_HEADER Struct Reference

Public Attributes
PUP_HEADER Struct Reference

PFAT Update Package Header. More...

#include <PfatDefinitions.h>

List of all members.

Public Attributes

UINT16 | Version
Version of the update package header. Must be 0x0001.
UINT8 | Reserved3 [2]
UINT8 | PlatId [16]
PLAT_ID used to be compared against the one found in the PPDT to prevent cross platform flashing.
UINT16 | PkgAttributes
If any bit set in this field then PUP must be signed and valid PUPC must be provided for PUP to be processed BIT[0] - Indicates write/erase operations will be executed on protected flash area indicated in the PPDT SFAM BIT[1] - Indicates protected EC operations included.
UINT8 | Reserved4 [2]
UINT16 | PslMajorVer
Indicates the PSL major version. Must be 1.
UINT16 | PslMinorVer
Indicates the PSL minor version. Must be 0.
UINT32 | ScriptSectionSize
Size in bytes of the script.
UINT32 | DataSectionSize
Size of the data region in bytes.
UINT32 | BiosSvn
BIOS SVN.
UINT32 | EcSvn
EC SVN.
UINT32 | VendorSpecific

Detailed Description

PFAT Update Package Header.

Definition at line 248 of file PfatDefinitions.h.

The documentation for this struct was generated from the following file:
  • PfatDefinitions.h


2013 SharkBay Processor Reference Code API: Member List

PUP_HEADER Member List
This is the complete list of members for PUP_HEADER, including all inherited members.
BiosSvn | PUP_HEADER
DataSectionSize | PUP_HEADER
EcSvn | PUP_HEADER
PkgAttributes | PUP_HEADER
PlatId | PUP_HEADER
PslMajorVer | PUP_HEADER
PslMinorVer | PUP_HEADER
Reserved3 (defined in PUP_HEADER) | PUP_HEADER
Reserved4 (defined in PUP_HEADER) | PUP_HEADER
ScriptSectionSize | PUP_HEADER
VendorSpecific (defined in PUP_HEADER) | PUP_HEADER
Version | PUP_HEADER


2013 SharkBay Processor Reference Code API: SECURITY_CONFIG Struct Reference

Public Attributes
SECURITY_CONFIG Struct Reference

All processor security features enabling definitions are in this field. More...

#include <CpuPlatformPolicy.h>

Collaboration diagram for SECURITY_CONFIG:
[legend]

List of all members.

Public Attributes

TXT_FUNCTION_CONFIG * TxtFunctionConfig

Detailed Description

All processor security features enabling definitions are in this field.

Platform code can enable/disable features thru this field.

Definition at line 306 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

SECURITY_CONFIG Member List
This is the complete list of members for SECURITY_CONFIG, including all inherited members.
TxtFunctionConfig (defined in SECURITY_CONFIG) SECURITY_CONFIG


2013 SharkBay Processor Reference Code API: SECURITY_CONFIG_PPI Struct Reference

Public Attributes
SECURITY_CONFIG_PPI Struct Reference

Security Configuration. More...

#include <CpuPlatformPolicy.h>

Collaboration diagram for SECURITY_CONFIG_PPI:
[legend]

List of all members.

Public Attributes

PFAT_CONFIG * PfatConfig
PFAT Configuration settings.
TXT_CONFIG * TxtConfig
TxT Configuration settings.
BOOT_GUARD_CONFIG * BootGuardConfig
Boot Guard Configuration settings.

Detailed Description

Security Configuration.

Definition at line 285 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

SECURITY_CONFIG_PPI Member List
This is the complete list of members for SECURITY_CONFIG_PPI, including all inherited members.
BootGuardConfig | SECURITY_CONFIG_PPI
PfatConfig | SECURITY_CONFIG_PPI
TxtConfig | SECURITY_CONFIG_PPI


2013 SharkBay Processor Reference Code API: SFAM_DATA Struct Reference

Public Attributes
SFAM_DATA Struct Reference

List of all members.

Public Attributes

UINT32 | FirstByte
Linear flash address of the first byte of the signed range, must be aligned to be first byte in the block. Ordering is little-endian.
UINT32 | LastByte
Linear flash address of the last byte of the signed range, must be aligned to be last byte in the block. Ordering is little-endian.

Detailed Description

Definition at line 154 of file PfatDefinitions.h.

The documentation for this struct was generated from the following file:
  • PfatDefinitions.h


2013 SharkBay Processor Reference Code API: Member List

SFAM_DATA Member List
This is the complete list of members for SFAM_DATA, including all inherited members.
FirstByte | SFAM_DATA
LastByte | SFAM_DATA


2013 SharkBay Processor Reference Code API: SMRAM_CPU_DATA Struct Reference

Public Attributes
SMRAM_CPU_DATA Struct Reference
Collaboration diagram for SMRAM_CPU_DATA:
[legend]

List of all members.

Public Attributes

EFI_GUID | HeaderGuid
EFI_PHYSICAL_ADDRESS | AcpiCpuPointer
ACPI_CPU_DATA | AcpiCpuData
EFI_PHYSICAL_ADDRESS | GdtrProfileOffset
EFI_PHYSICAL_ADDRESS | GdtOffset
EFI_PHYSICAL_ADDRESS | IdtrProfileOffset
EFI_PHYSICAL_ADDRESS | IdtOffset
EFI_PHYSICAL_ADDRESS | CpuPrivateDataOffset
EFI_PHYSICAL_ADDRESS | S3BootScriptTableOffset
EFI_PHYSICAL_ADDRESS | S3BspMtrrTableOffset
EFI_PHYSICAL_ADDRESS | MicrocodePointerBufferOffset
It is pointer to pointer array.
EFI_PHYSICAL_ADDRESS | MicrocodeDataBufferOffset
It is pointer to the data.
UINT32 | GdtrProfileSize
We need put all the data buffer here as well.
UINT32 | GdtSize
UINT32 | IdtrProfileSize
UINT32 | IdtSize
UINT32 | CpuPrivateDataSize
UINT32 | S3BootScriptTableSize
UINT32 | S3BspMtrrTableSize
UINT32 | MicrocodePointerBufferSize
UINT32 | MicrocodeDataBufferSize

Detailed Description

Definition at line 48 of file CpuDataStruct.h.

Member Data Documentation

UINT32 SMRAM_CPU_DATA::GdtrProfileSize

We need put all the data buffer here as well.

These data will be copied to original location in S3.

Definition at line 75 of file CpuDataStruct.h.

EFI_PHYSICAL_ADDRESS SMRAM_CPU_DATA::MicrocodeDataBufferOffset

It is pointer to the data.

Definition at line 67 of file CpuDataStruct.h.

The documentation for this struct was generated from the following file:
  • CpuDataStruct.h


2013 SharkBay Processor Reference Code API: Member List

SMRAM_CPU_DATA Member List
This is the complete list of members for SMRAM_CPU_DATA, including all inherited members.
AcpiCpuData (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
AcpiCpuPointer (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
CpuPrivateDataOffset (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
CpuPrivateDataSize (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
GdtOffset (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
GdtrProfileOffset (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
GdtrProfileSize | SMRAM_CPU_DATA
GdtSize (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
HeaderGuid (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
IdtOffset (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
IdtrProfileOffset (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
IdtrProfileSize (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
IdtSize (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
MicrocodeDataBufferOffset | SMRAM_CPU_DATA
MicrocodeDataBufferSize (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
MicrocodePointerBufferOffset | SMRAM_CPU_DATA
MicrocodePointerBufferSize (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
S3BootScriptTableOffset (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
S3BootScriptTableSize (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
S3BspMtrrTableOffset (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA
S3BspMtrrTableSize (defined in SMRAM_CPU_DATA) | SMRAM_CPU_DATA


2013 SharkBay Processor Reference Code API: SMRAM_CPU_DATA_ADDRESS Struct Reference

Public Attributes
SMRAM_CPU_DATA_ADDRESS Struct Reference

List of all members.

Public Attributes

EFI_PHYSICAL_ADDRESS | LockBoxData
EFI_PHYSICAL_ADDRESS | SmramCpuData
UINT64 | LockBoxSize

Detailed Description

Definition at line 38 of file SmramCpuDataVariable.h.

The documentation for this struct was generated from the following file:
  • SmramCpuDataVariable.h


2013 SharkBay Processor Reference Code API: Member List

SMRAM_CPU_DATA_ADDRESS Member List
This is the complete list of members for SMRAM_CPU_DATA_ADDRESS, including all inherited members.
LockBoxData (defined in SMRAM_CPU_DATA_ADDRESS) | SMRAM_CPU_DATA_ADDRESS
LockBoxSize (defined in SMRAM_CPU_DATA_ADDRESS) | SMRAM_CPU_DATA_ADDRESS
SmramCpuData (defined in SMRAM_CPU_DATA_ADDRESS) | SMRAM_CPU_DATA_ADDRESS


2013 SharkBay Processor Reference Code API: SVID_CONFIG_ITEM Struct Reference

Public Attributes
SVID_CONFIG_ITEM Struct Reference

List of all members.

Public Attributes

UINT16 | VoltageTarget
BOOLEAN | SvidDisable

Detailed Description

Definition at line 164 of file OverclockingLibrary.h.

The documentation for this struct was generated from the following file:
  • OverclockingLibrary.h


2013 SharkBay Processor Reference Code API: Member List

SVID_CONFIG_ITEM Member List
This is the complete list of members for SVID_CONFIG_ITEM, including all inherited members.
SvidDisable (defined in SVID_CONFIG_ITEM) | SVID_CONFIG_ITEM
VoltageTarget (defined in SVID_CONFIG_ITEM) | SVID_CONFIG_ITEM


2013 SharkBay Processor Reference Code API: THERM_FUNCTION_ENABLES Struct Reference

Public Attributes
THERM_FUNCTION_ENABLES Struct Reference

This structure is used to describe which of the Thermal functions will be enabled by Thermal implementation. More...

#include <CpuPmConfig.h>

Collaboration diagram for THERM_FUNCTION_ENABLES:
[legend]

List of all members.

Public Attributes

UINT16 | BiProcHot: 1
Enable or Disable Bi-Directional PROCHOT#.
UINT16 | TStates: 1
Enable or Disable T states.
UINT16 | DisableProcHotOut: 1
Enable or Disable PROCHOT# signal being driven externally.
UINT16 | DisableVRThermalAlert: 1
Enable or Disable VR Thermal Alert.
UINT16 | ProcHotResponce: 1
Enable or Disable PROCHOT# Responce.
UINT16 | AutoThermalReporting: 1
Enable or Disable Thermal Reporting through ACPI tables.
UINT16 | ThermalMonitor: 1
Enable or Disable Thermal Monitor.
UINT16 | Pl1ThermalControl: 2
Disable(0), Enable/Manual(1), Auto(2) PL1 thermal throttling features.
UINT16 | ThermReserved: 7
Reserved.
PL1_THERMAL_CONTROL_FLOOR Pl1ThermalControlFloor
PL1 Floor Throttle Values.

Detailed Description

This structure is used to describe which of the Thermal functions will be enabled by Thermal implementation.

Definition at line 233 of file CpuPmConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPmConfig.h


2013 SharkBay Processor Reference Code API: Member List

THERM_FUNCTION_ENABLES Member List
This is the complete list of members for THERM_FUNCTION_ENABLES, including all inherited members.
AutoThermalReporting | THERM_FUNCTION_ENABLES
BiProcHot | THERM_FUNCTION_ENABLES
DisableProcHotOut | THERM_FUNCTION_ENABLES
DisableVRThermalAlert | THERM_FUNCTION_ENABLES
Pl1ThermalControl | THERM_FUNCTION_ENABLES
Pl1ThermalControlFloor | THERM_FUNCTION_ENABLES
ProcHotResponce | THERM_FUNCTION_ENABLES
ThermalMonitor | THERM_FUNCTION_ENABLES
ThermReserved | THERM_FUNCTION_ENABLES
TStates | THERM_FUNCTION_ENABLES


2013 SharkBay Processor Reference Code API: THUNK16_CONTEXT Struct Reference

Public Attributes
THUNK16_CONTEXT Struct Reference

Byte packed structure for an 16-bit real mode thunks. More...

#include <ThunkLib.h>

List of all members.

Public Attributes

UINT32 | RealModeBuffer
UINT32 | DefaultStack

Detailed Description

Byte packed structure for an 16-bit real mode thunks.

Definition at line 25 of file ThunkLib.h.

The documentation for this struct was generated from the following file:
  • ThunkLib.h


2013 SharkBay Processor Reference Code API: Member List

THUNK16_CONTEXT Member List
This is the complete list of members for THUNK16_CONTEXT, including all inherited members.
DefaultStack (defined in THUNK16_CONTEXT) | THUNK16_CONTEXT
RealModeBuffer (defined in THUNK16_CONTEXT) | THUNK16_CONTEXT


2013 SharkBay Processor Reference Code API: TXT_CONFIG Struct Reference

Public Attributes
TXT_CONFIG Struct Reference

List of all members.

Public Attributes

UINT64 | SinitMemorySize
Size of SINIT module if installed in flash part. Zero otherwise.
UINT64 | TxtHeapMemorySize
Size of memory reserved for TXT Heap. This memory is used by MLE.
EFI_PHYSICAL_ADDRESS | TxtDprMemoryBase
Base address of DPR protected memory reserved for Intel TXT component.
UINT64 | TxtDprMemorySize
Size of DPR protected memory reserved for Intel TXT component.
EFI_PHYSICAL_ADDRESS | BiosAcmBase
Base address of BIOS ACM in flash part.
UINT64 | BiosAcmSize
Size of ACM Binary.
EFI_PHYSICAL_ADDRESS | McuUpdateDataAddr
Base address of CPU micro code patch loaded into BSP.
UINT64 | TgaSize
Size of Trusted Graphics Aperture if supported by chipset.
EFI_PHYSICAL_ADDRESS | TxtLcpPdBase
Base address of Platform Default Launch Control Policy data if installed in flash part.
UINT64 | TxtLcpPdSize
Size of Platform Default Launch Control Policy data if installed in flash part.

Detailed Description

Definition at line 232 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

Member Data Documentation

EFI_PHYSICAL_ADDRESS TXT_CONFIG::BiosAcmBase

Base address of BIOS ACM in flash part.

It can be passed through platform code for customization; Intel TXT reference code would skip searching the BIOS ACM in PEI firmware volume if the field is not zero.

Definition at line 241 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

UINT64 TXT_CONFIG::BiosAcmSize

Size of ACM Binary.

Definition at line 242 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

EFI_PHYSICAL_ADDRESS TXT_CONFIG::McuUpdateDataAddr

Base address of CPU micro code patch loaded into BSP.

It can be passed through platform code for customization; Intel TXT reference code would skip searching the micro code path in PEI firmware volume if the field is not zero.

Definition at line 247 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

UINT64 TXT_CONFIG::TgaSize

Size of Trusted Graphics Aperture if supported by chipset.

For Cantiga must be 0.

Definition at line 251 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

UINT64 TXT_CONFIG::TxtDprMemorySize

Size of DPR protected memory reserved for Intel TXT component.

Definition at line 236 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

EFI_PHYSICAL_ADDRESS TXT_CONFIG::TxtLcpPdBase

Base address of Platform Default Launch Control Policy data if installed in flash part.

Zero otherwise.

Definition at line 255 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

UINT64 TXT_CONFIG::TxtLcpPdSize

Size of Platform Default Launch Control Policy data if installed in flash part.

Zero otherwise.

Definition at line 259 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

TXT_CONFIG Member List
This is the complete list of members for TXT_CONFIG, including all inherited members.
BiosAcmBase | TXT_CONFIG
BiosAcmSize | TXT_CONFIG
McuUpdateDataAddr | TXT_CONFIG
SinitMemorySize | TXT_CONFIG
TgaSize | TXT_CONFIG
TxtDprMemoryBase | TXT_CONFIG
TxtDprMemorySize | TXT_CONFIG
TxtHeapMemorySize | TXT_CONFIG
TxtLcpPdBase | TXT_CONFIG
TxtLcpPdSize | TXT_CONFIG


2013 SharkBay Processor Reference Code API: TXT_FUNCTION_CONFIG Struct Reference

Public Attributes
TXT_FUNCTION_CONFIG Struct Reference

TxT Platform Configuration. More...

#include <CpuPlatformPolicy.h>

List of all members.

Public Attributes

UINT8 | ResetAux: 1
Reset Auxiliary content when it is set "TRUE".
UINT8 | Reserved: 7
Reserved for future use.
UINT8 | ByetReserved [1]
Reserved for future use.

Detailed Description

TxT Platform Configuration.

Definition at line 295 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

The documentation for this struct was generated from the following file:
  • Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h


2013 SharkBay Processor Reference Code API: Member List

TXT_FUNCTION_CONFIG Member List
This is the complete list of members for TXT_FUNCTION_CONFIG, including all inherited members.
ByetReserved | TXT_FUNCTION_CONFIG
Reserved | TXT_FUNCTION_CONFIG
ResetAux | TXT_FUNCTION_CONFIG


2013 SharkBay Processor Reference Code API: TXT_INFO_DATA Struct Reference

Public Attributes
TXT_INFO_DATA Struct Reference

List of all members.

Public Attributes

BOOLEAN | ChipsetIsTxtCapable
UINT8 | TxtMode
UINT64 | PmBase
UINT64 | SinitMemorySize
UINT64 | TxtHeapMemorySize
EFI_PHYSICAL_ADDRESS | TxtDprMemoryBase
UINT64 | TxtDprMemorySize
EFI_PHYSICAL_ADDRESS | BiosAcmBase
UINT64 | BiosAcmSize
EFI_PHYSICAL_ADDRESS | McuUpdateDataAddr
EFI_PHYSICAL_ADDRESS | SinitAcmBase
UINT64 | SinitAcmSize
UINT64 | TgaSize
EFI_PHYSICAL_ADDRESS | TxtLcpPdBase
UINT64 | TxtLcpPdSize
UINT64 | Flags

Detailed Description

Definition at line 33 of file TxtInfoHob.h.

The documentation for this struct was generated from the following file:
  • TxtInfoHob.h


2013 SharkBay Processor Reference Code API: Member List

TXT_INFO_DATA Member List
This is the complete list of members for TXT_INFO_DATA, including all inherited members.
BiosAcmBase (defined in TXT_INFO_DATA) | TXT_INFO_DATA
BiosAcmSize (defined in TXT_INFO_DATA) | TXT_INFO_DATA
ChipsetIsTxtCapable (defined in TXT_INFO_DATA) | TXT_INFO_DATA
Flags (defined in TXT_INFO_DATA) | TXT_INFO_DATA
McuUpdateDataAddr (defined in TXT_INFO_DATA) | TXT_INFO_DATA
PmBase (defined in TXT_INFO_DATA) | TXT_INFO_DATA
SinitAcmBase (defined in TXT_INFO_DATA) | TXT_INFO_DATA
SinitAcmSize (defined in TXT_INFO_DATA) | TXT_INFO_DATA
SinitMemorySize (defined in TXT_INFO_DATA) | TXT_INFO_DATA
TgaSize (defined in TXT_INFO_DATA) | TXT_INFO_DATA
TxtDprMemoryBase (defined in TXT_INFO_DATA) | TXT_INFO_DATA
TxtDprMemorySize (defined in TXT_INFO_DATA) | TXT_INFO_DATA
TxtHeapMemorySize (defined in TXT_INFO_DATA) | TXT_INFO_DATA
TxtLcpPdBase (defined in TXT_INFO_DATA) | TXT_INFO_DATA
TxtLcpPdSize (defined in TXT_INFO_DATA) | TXT_INFO_DATA
TxtMode (defined in TXT_INFO_DATA) | TXT_INFO_DATA


2013 SharkBay Processor Reference Code API: TXT_INFO_HOB Struct Reference

Public Attributes
TXT_INFO_HOB Struct Reference
Collaboration diagram for TXT_INFO_HOB:
[legend]

List of all members.

Public Attributes

EFI_HOB_GUID_TYPE | EfiHobGuidType
TXT_INFO_DATA | Data

Detailed Description

Definition at line 59 of file TxtInfoHob.h.

The documentation for this struct was generated from the following file:
  • TxtInfoHob.h


2013 SharkBay Processor Reference Code API: Member List

TXT_INFO_HOB Member List
This is the complete list of members for TXT_INFO_HOB, including all inherited members.
Data (defined in TXT_INFO_HOB) | TXT_INFO_HOB
EfiHobGuidType (defined in TXT_INFO_HOB) | TXT_INFO_HOB


2013 SharkBay Processor Reference Code API: VF_MAILBOX_COMMAND_DATA Struct Reference

Public Attributes
VF_MAILBOX_COMMAND_DATA Struct Reference

List of all members.

Public Attributes

UINT32 | MaxOcRatio: 8
UINT32 | VoltageTargetU12: 12
UINT32 | TargetMode: 1
UINT32 | VoltageOffsetS11: 11

Detailed Description

Definition at line 190 of file OverclockingLibrary.h.

The documentation for this struct was generated from the following file:
  • OverclockingLibrary.h


2013 SharkBay Processor Reference Code API: Member List

VF_MAILBOX_COMMAND_DATA Member List
This is the complete list of members for VF_MAILBOX_COMMAND_DATA, including all inherited members.
MaxOcRatio (defined in VF_MAILBOX_COMMAND_DATA) | VF_MAILBOX_COMMAND_DATA
TargetMode (defined in VF_MAILBOX_COMMAND_DATA) | VF_MAILBOX_COMMAND_DATA
VoltageOffsetS11 (defined in VF_MAILBOX_COMMAND_DATA) | VF_MAILBOX_COMMAND_DATA
VoltageTargetU12 (defined in VF_MAILBOX_COMMAND_DATA) | VF_MAILBOX_COMMAND_DATA


2013 SharkBay Processor Reference Code API: VOLTAGE_FREQUENCY_ITEM Struct Reference

Public Attributes
VOLTAGE_FREQUENCY_ITEM Struct Reference
Collaboration diagram for VOLTAGE_FREQUENCY_ITEM:
[legend]

List of all members.

Public Attributes

VOLTAGE_FREQUENCY_SETTINGS | VfSettings
UINT8 | DomainId

Detailed Description

Definition at line 152 of file OverclockingLibrary.h.

The documentation for this struct was generated from the following file:
  • OverclockingLibrary.h


2013 SharkBay Processor Reference Code API: Member List

VOLTAGE_FREQUENCY_ITEM Member List
This is the complete list of members for VOLTAGE_FREQUENCY_ITEM, including all inherited members.
DomainId (defined in VOLTAGE_FREQUENCY_ITEM) | VOLTAGE_FREQUENCY_ITEM
VfSettings (defined in VOLTAGE_FREQUENCY_ITEM) | VOLTAGE_FREQUENCY_ITEM


2013 SharkBay Processor Reference Code API: VOLTAGE_FREQUENCY_SETTINGS Struct Reference

Public Attributes
VOLTAGE_FREQUENCY_SETTINGS Struct Reference

List of all members.

Public Attributes

UINT8 | MaxOcRatio
UINT8 | VoltageTargetMode
UINT16 | VoltageTarget
INT16 | VoltageOffset

Detailed Description

Definition at line 145 of file OverclockingLibrary.h.

The documentation for this struct was generated from the following file:
  • OverclockingLibrary.h


2013 SharkBay Processor Reference Code API: Member List

VOLTAGE_FREQUENCY_SETTINGS Member List
This is the complete list of members for VOLTAGE_FREQUENCY_SETTINGS, including all inherited members.
MaxOcRatio (defined in VOLTAGE_FREQUENCY_SETTINGS) | VOLTAGE_FREQUENCY_SETTINGS
VoltageOffset (defined in VOLTAGE_FREQUENCY_SETTINGS) | VOLTAGE_FREQUENCY_SETTINGS
VoltageTarget (defined in VOLTAGE_FREQUENCY_SETTINGS) | VOLTAGE_FREQUENCY_SETTINGS
VoltageTargetMode (defined in VOLTAGE_FREQUENCY_SETTINGS) | VOLTAGE_FREQUENCY_SETTINGS


2013 SharkBay Processor Reference Code API: Class Index

Class Index
A | B | C | E | G | H | O | P | S | T | V | _
A
EFI_CPUID_REGISTER PFAT_HOB SMRAM_CPU_DATA _EFI_MP_SERVICES_PROTOCOL
EFI_DETAILED_CPU_INFO PFAT_LOG SMRAM_CPU_DATA_ADDRESS _EFI_PI_MP_SERVICES_PROTOCOL
ACPI_CPU_DATA EFI_MP_HEALTH PHYSICAL_LOCATION SVID_CONFIG_ITEM _EFI_SMM_THUNK_PROTOCOL
B
EFI_MP_HEALTH_FLAGS PL1_THERMAL_CONTROL_FLOOR
T
_OC_MAILBOX_COMMAND
EFI_MP_PROC_CONTEXT PLATFORM_CPU_INFORMATION _OC_MAILBOX_FULL
BIOS_OS_DATA_REGION EFI_PROCESSOR_INFORMATION POWER_MGMT_CONFIG THERM_FUNCTION_ENABLES _OC_MAILBOX_INTERFACE
BOOT_GUARD_CONFIG
G
POWER_MGMT_CONFIG_PPI THUNK16_CONTEXT _OC_MAILBOX_ITEM
C
PPDT TXT_CONFIG _PCODE_MAILBOX_FULL
GLOBAL_CONFIG_ITEM PPM_CTDP_LEVEL_SETTINGS TXT_FUNCTION_CONFIG _PCODE_MAILBOX_INTERFACE
CORE_RATIO_LIMITS_ITEM
H
PPM_CUSTOM_RATIO_TABLE TXT_INFO_DATA _PEI_CACHE_PPI
CPU_CONFIG PPM_FUNCTION_ENABLES TXT_INFO_HOB _PEI_CPU_PLATFORM_POLICY_PPI
CPU_CONFIG_PPI HEAP_BIOS_SPEC_VER_ELEMENT PPM_GLOBAL_NVS_AREA
V
_PFAT_PROTOCOL
CPU_PHYSICAL_LOCATION HEAP_BIOSACM_ELEMENT PSEUDO_DESCRIPTOR _PPM_CUSTOM_CTDP
E
HEAP_EXT_DATA_ELEMENT PUP VF_MAILBOX_COMMAND_DATA _PPM_CUSTOM_CTDP_TABLE
O
PUP_HEADER VOLTAGE_FREQUENCY_ITEM _PPM_GLOBAL_NVS_AREA_PROTOCOL
EFI_CPU_MICROCODE_EXTENDED_TABLE
S
VOLTAGE_FREQUENCY_SETTINGS _PPM_LOCK_ENABLES
EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER OC_CAPABILITIES_ITEM
_
_PPM_TURBO_SETTINGS
EFI_CPU_MICROCODE_HEADER OC_LIBRARY_COMMAND SECURITY_CONFIG
EFI_CPU_PHYSICAL_LOCATION OVERCLOCKING_CONFIG_PPI SECURITY_CONFIG_PPI _DXE_CPU_INFO_PROTOCOL
EFI_CPU_VERSION
P
SFAM_DATA _DXE_CPU_PLATFORM_POLICY_PROTOCOL
PFAT_CONFIG
A | B | C | E | G | H | O | P | S | T | V | _


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- a -

  • ActivateCache : _PEI_CACHE_PPI
  • ActiveCoreCount : CPU_CONFIG_PPI
  • AesEnable : CPU_CONFIG
  • ApHandoffManner : CPU_CONFIG
  • ApicID : PLATFORM_CPU_INFORMATION
  • ApIdleManner : CPU_CONFIG
  • AssetTag : PLATFORM_CPU_INFORMATION
  • AutoActiveTripPoint : PPM_GLOBAL_NVS_AREA
  • AutoCriticalTripPoint : PPM_GLOBAL_NVS_AREA
  • AutoPassiveTripPoint : PPM_GLOBAL_NVS_AREA
  • AutoThermalReporting : THERM_FUNCTION_ENABLES , PPM_FUNCTION_ENABLES


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- b -

  • BiosAcmBase : TXT_CONFIG
  • BiosAcmSize : TXT_CONFIG
  • BiosSvn : PUP_HEADER , PPDT
  • BiProcHot : PPM_FUNCTION_ENABLES , THERM_FUNCTION_ENABLES
  • BistOnReset : CPU_CONFIG_PPI
  • BitReserved : OVERCLOCKING_CONFIG_PPI
  • BootGuardConfig : SECURITY_CONFIG_PPI
  • BootInLfm : POWER_MGMT_CONFIG_PPI
  • BspSelection : CPU_CONFIG
  • ByetReserved : TXT_FUNCTION_CONFIG


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- c -

  • C10 : PPM_FUNCTION_ENABLES
  • C1AutoDemotion : PPM_FUNCTION_ENABLES
  • C1e : PPM_FUNCTION_ENABLES
  • C1UnDemotion : PPM_FUNCTION_ENABLES
  • C3 : PPM_FUNCTION_ENABLES
  • C3AutoDemotion : PPM_FUNCTION_ENABLES
  • C3Latency : PPM_GLOBAL_NVS_AREA
  • C3MwaitValue : PPM_GLOBAL_NVS_AREA
  • C3UnDemotion : PPM_FUNCTION_ENABLES
  • C6 : PPM_FUNCTION_ENABLES
  • C6Latency : PPM_GLOBAL_NVS_AREA
  • C6MwaitValue : PPM_GLOBAL_NVS_AREA
  • C7Latency : PPM_GLOBAL_NVS_AREA
  • C7MwaitValue : PPM_GLOBAL_NVS_AREA
  • C8 : PPM_FUNCTION_ENABLES
  • C9 : PPM_FUNCTION_ENABLES
  • CDIOLevel : PPM_GLOBAL_NVS_AREA
  • CDLatency : PPM_GLOBAL_NVS_AREA
  • CDMwaitValue : PPM_GLOBAL_NVS_AREA
  • CDPowerValue : PPM_GLOBAL_NVS_AREA
  • ClrExtraTurboVoltage : OVERCLOCKING_CONFIG_PPI
  • ClrMaxOcTurboRatio : OVERCLOCKING_CONFIG_PPI
  • ClrVoltageMode : OVERCLOCKING_CONFIG_PPI
  • ClrVoltageOffset : OVERCLOCKING_CONFIG_PPI
  • ClrVoltageOverride : OVERCLOCKING_CONFIG_PPI
  • ComponentSize : PFAT_HOB , PFAT_CONFIG
  • ConfigTdpBios : _PPM_TURBO_SETTINGS
  • ConfigTdpBootModeIndex : PPM_GLOBAL_NVS_AREA
  • ConfigTdpCustom : _PPM_CUSTOM_CTDP
  • ConfigTdpLevel : _PPM_TURBO_SETTINGS
  • ConfigTdpLock : _PPM_TURBO_SETTINGS
  • ConfigurablePpc : PPM_GLOBAL_NVS_AREA
  • Core : EFI_CPU_PHYSICAL_LOCATION
  • CoreExtraTurboVoltage : OVERCLOCKING_CONFIG_PPI
  • CoreMaxOcTurboRatio : OVERCLOCKING_CONFIG_PPI
  • CoreVoltageMode : OVERCLOCKING_CONFIG_PPI
  • CoreVoltageOffset : OVERCLOCKING_CONFIG_PPI
  • CoreVoltageOverride : OVERCLOCKING_CONFIG_PPI
  • CpuCommonFeatures : _DXE_CPU_INFO_PROTOCOL
  • CpuConfig : _PEI_CPU_PLATFORM_POLICY_PPI , _DXE_CPU_PLATFORM_POLICY_PROTOCOL
  • Cpuid : PPM_CUSTOM_RATIO_TABLE , PPM_GLOBAL_NVS_AREA
  • CpuMaxNonTurboRatio : CPU_CONFIG_PPI
  • CpuPlatformPpiPtr : _PEI_CPU_PLATFORM_POLICY_PPI
  • CpuRatio : CPU_CONFIG_PPI
  • CpuRatioOverride : CPU_CONFIG_PPI
  • CstateLatencyControl0Irtl : POWER_MGMT_CONFIG
  • CstateLatencyControl0TimeUnit : POWER_MGMT_CONFIG
  • CstateLatencyControl1Irtl : POWER_MGMT_CONFIG
  • CstateLatencyControl1TimeUnit : POWER_MGMT_CONFIG
  • CstateLatencyControl2Irtl : POWER_MGMT_CONFIG
  • CstateLatencyControl2TimeUnit : POWER_MGMT_CONFIG
  • CstateLatencyControl3Irtl : POWER_MGMT_CONFIG
  • CstateLatencyControl3TimeUnit : POWER_MGMT_CONFIG
  • CstateLatencyControl4Irtl : POWER_MGMT_CONFIG
  • CstateLatencyControl4TimeUnit : POWER_MGMT_CONFIG
  • CstateLatencyControl5Irtl : POWER_MGMT_CONFIG
  • CstateLatencyControl5TimeUnit : POWER_MGMT_CONFIG
  • CStatePreWake : PPM_FUNCTION_ENABLES
  • CtdpCtc : PPM_CTDP_LEVEL_SETTINGS
  • CtdpLevelSettings : PPM_GLOBAL_NVS_AREA
  • CtdpLevelsSupported : PPM_GLOBAL_NVS_AREA
  • CtdpPowerLimit1 : PPM_CTDP_LEVEL_SETTINGS
  • CtdpPowerLimit2 : PPM_CTDP_LEVEL_SETTINGS
  • CtdpPowerLimitWindow : PPM_CTDP_LEVEL_SETTINGS
  • CtdpPpc : PPM_CTDP_LEVEL_SETTINGS
  • CtdpTar : PPM_CTDP_LEVEL_SETTINGS
  • CustomBootModeIndex : _PPM_CUSTOM_CTDP
  • CustomConfigTdp : PPM_GLOBAL_NVS_AREA
  • CustomConfigTdpControl : _PPM_CUSTOM_CTDP_TABLE
  • CustomConfigTdpTable : _PPM_CUSTOM_CTDP
  • CustomPowerLimit1 : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerLimit1Time : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerLimit2 : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerUnit : POWER_MGMT_CONFIG
  • CustomTdpCount : _PPM_CUSTOM_CTDP
  • CustomTurboActivationRatio : _PPM_CUSTOM_CTDP_TABLE
  • Cx : PPM_FUNCTION_ENABLES


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- d -

  • DataSectionSize : PUP_HEADER
  • DcaPrefetchDelayValue : CPU_CONFIG
  • DcaState : CPU_CONFIG
  • DdrPowerLimit1 : _PPM_TURBO_SETTINGS
  • DdrPowerLimit1Time : _PPM_TURBO_SETTINGS
  • DdrPowerLimit2 : _PPM_TURBO_SETTINGS
  • DdrPowerLimitLock : _PPM_TURBO_SETTINGS
  • DebugInterfaceEnable : CPU_CONFIG
  • DebugInterfaceLockEnable : CPU_CONFIG
  • DeepCState : PPM_FUNCTION_ENABLES
  • DisableProcHotOut : THERM_FUNCTION_ENABLES , PPM_FUNCTION_ENABLES
  • DisableVRThermalAlert : THERM_FUNCTION_ENABLES , PPM_FUNCTION_ENABLES


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- e -

  • EcCmd : PPDT
  • EcCmdClose : PPDT
  • EcCmdDiscovery : PFAT_CONFIG
  • EcCmdGetSvn : PPDT
  • EcCmdLock : PFAT_CONFIG
  • EcCmdOpen : PPDT
  • EcCmdPortTest : PPDT
  • EcCmdProvisionEav : PFAT_CONFIG
  • EcData : PPDT
  • EcSvn : PUP_HEADER
  • Eist : PPM_FUNCTION_ENABLES
  • EnableDisableAP : _EFI_MP_SERVICES_PROTOCOL , _EFI_PI_MP_SERVICES_PROTOCOL
  • EnableDts : CPU_CONFIG
  • EnableRerunPcodeCalibration : POWER_MGMT_CONFIG
  • EnergyEfficientPState : PPM_FUNCTION_ENABLES
  • EnergyPolicy : _PPM_TURBO_SETTINGS
  • Erase : _PFAT_PROTOCOL
  • ExecLim : PPDT
  • Execute : _PFAT_PROTOCOL
  • ExecuteDisableBit : CPU_CONFIG


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- f -

  • FastString : CPU_CONFIG
  • FirstByte : SFAM_DATA
  • FivrEfficiencyEnable : OVERCLOCKING_CONFIG_PPI
  • FivrFaultsEnable : OVERCLOCKING_CONFIG_PPI
  • FivrSscEnable : POWER_MGMT_CONFIG_PPI
  • FivrSscPercent : POWER_MGMT_CONFIG_PPI
  • FloorGT : PL1_THERMAL_CONTROL_FLOOR
  • FloorPCH : PL1_THERMAL_CONTROL_FLOOR
  • FviReport : CPU_CONFIG
  • FviSmbiosType : CPU_CONFIG
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- g -

  • GdtrProfileSize : SMRAM_CPU_DATA
  • GetCpuInfo : CPU_CONFIG
  • GetGeneralMPInfo : _EFI_MP_SERVICES_PROTOCOL
  • GetMaxCount : CPU_CONFIG
  • GetNumberOfProcessors : _EFI_PI_MP_SERVICES_PROTOCOL
  • GetProcessorContext : _EFI_MP_SERVICES_PROTOCOL
  • GetProcessorInfo : _EFI_PI_MP_SERVICES_PROTOCOL
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- h -

  • HtState : CPU_CONFIG
  • HyperThreading : CPU_CONFIG_PPI
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- i -

  • IsColdReset : CPU_CONFIG
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- l -

  • LakeTiny : PPM_FUNCTION_ENABLES
  • LastByte : SFAM_DATA
  • LastPage : PFAT_LOG
  • LastSfam : PPDT
  • LimitCpuidMaximumValue : CPU_CONFIG
  • Location : EFI_PROCESSOR_INFORMATION
  • LoggingOptions : PFAT_LOG
  • LongLatencyC6 : PPM_FUNCTION_ENABLES
  • LongLatencyC7 : PPM_FUNCTION_ENABLES
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- m -

  • MachineCheckEnable : CPU_CONFIG
  • MachineCheckStatusClean : CPU_CONFIG
  • MaxCoreFrequency : PLATFORM_CPU_INFORMATION
  • MaxFsbFrequency : PLATFORM_CPU_INFORMATION
  • MaxRatio : PPM_CUSTOM_RATIO_TABLE
  • McuUpdateDataAddr : TXT_CONFIG
  • MicrocodeDataBufferOffset : SMRAM_CPU_DATA
  • MicrocodePointerBufferOffset : SMRAM_CPU_DATA
  • MiscPowerManagementFlags : PPM_GLOBAL_NVS_AREA
  • MlcSpatialPrefetcher : CPU_CONFIG_PPI , CPU_CONFIG
  • MlcStreamerPrefetcher : CPU_CONFIG , CPU_CONFIG_PPI
  • MonitorMwaitEnable : CPU_CONFIG
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


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Here is a list of all documented class members with links to the class documentation for each member:

- n -

  • NumberOfEntries : PPM_CUSTOM_RATIO_TABLE
  • NumOfEntriesInLog : PFAT_LOG
  • NumSpiComponents : PFAT_HOB , PFAT_CONFIG
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Here is a list of all documented class members with links to the class documentation for each member:

- o -

  • OcSupport : OVERCLOCKING_CONFIG_PPI
  • OverclockingConfig : _PEI_CPU_PLATFORM_POLICY_PPI
  • OverclockingLock : _PPM_LOCK_ENABLES
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- p -

  • Package : EFI_CPU_PHYSICAL_LOCATION
  • PartNumber : PLATFORM_CPU_INFORMATION
  • PcodeCalibration : POWER_MGMT_CONFIG
  • pCustomCtdpSettings : POWER_MGMT_CONFIG
  • pCustomRatioTable : POWER_MGMT_CONFIG
  • Pfat : CPU_CONFIG_PPI
  • PfatConfig : SECURITY_CONFIG_PPI
  • PfatLog : PFAT_HOB , PFAT_CONFIG
  • PfatMemSize : PFAT_CONFIG
  • PfatModSvn : PPDT , PFAT_LOG
  • PfatToolsIntIoTrapAdd : PFAT_HOB
  • pFunctionEnables : POWER_MGMT_CONFIG
  • PkeySlot0 : PPDT
  • PkeySlot1 : PPDT
  • PkeySlot2 : PPDT
  • PkgAttributes : PUP_HEADER
  • PkgCStateDemotion : PPM_FUNCTION_ENABLES
  • PkgCStateLimit : POWER_MGMT_CONFIG
  • PkgCStateUnDemotion : PPM_FUNCTION_ENABLES
  • Pl1ThermalControl : THERM_FUNCTION_ENABLES
  • Pl1ThermalControlFloor : THERM_FUNCTION_ENABLES
  • PlatAttr : PPDT
  • PlatformCoreFrequencyList : PLATFORM_CPU_INFORMATION
  • PlatformFsbFrequencyList : PLATFORM_CPU_INFORMATION
  • PlatId : PPDT , PUP_HEADER
  • PmgCstCfgCtrlLock : _PPM_LOCK_ENABLES
  • PowerLimit1 : _PPM_TURBO_SETTINGS
  • PowerLimit1Time : _PPM_TURBO_SETTINGS
  • PowerLimit2 : PPM_FUNCTION_ENABLES , _PPM_TURBO_SETTINGS
  • PowerLimit3 : _PPM_TURBO_SETTINGS
  • PowerLimit3DutyCycle : _PPM_TURBO_SETTINGS
  • PowerLimit3Lock : _PPM_TURBO_SETTINGS
  • PowerLimit3Time : _PPM_TURBO_SETTINGS
  • PowerMgmtConfig : _PEI_CPU_PLATFORM_POLICY_PPI , _DXE_CPU_PLATFORM_POLICY_PROTOCOL
  • Ppdt : PFAT_HOB , PFAT_CONFIG
  • PpdtHash : PFAT_CONFIG
  • PpdtMajVer : PPDT
  • PpdtMinVer : PPDT
  • PpdtSize : PPDT
  • PpmFlags : PPM_GLOBAL_NVS_AREA
  • pPpmLockEnables : POWER_MGMT_CONFIG
  • pRatioLimit : POWER_MGMT_CONFIG
  • ProcessorId : EFI_PROCESSOR_INFORMATION
  • ProcHotLock : _PPM_LOCK_ENABLES
  • ProcHotResponce : PPM_FUNCTION_ENABLES , THERM_FUNCTION_ENABLES
  • Psi1Threshold : POWER_MGMT_CONFIG_PPI
  • Psi2Threshold : POWER_MGMT_CONFIG_PPI
  • Psi3Threshold : POWER_MGMT_CONFIG_PPI
  • PslMajorVer : PUP_HEADER
  • PslMinorVer : PUP_HEADER
  • pTurboSettings : POWER_MGMT_CONFIG
  • PupHeader : PFAT_CONFIG , PFAT_HOB
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


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Here is a list of all documented class members with links to the class documentation for each member:

- r -

  • RatioLimit : POWER_MGMT_CONFIG_PPI
  • RcVersion : _DXE_CPU_INFO_PROTOCOL
  • ReferenceString : PLATFORM_CPU_INFORMATION
  • Reserved : TXT_FUNCTION_CONFIG , PPM_FUNCTION_ENABLES , _PPM_LOCK_ENABLES , PPM_GLOBAL_NVS_AREA
  • ResetAux : TXT_FUNCTION_CONFIG
  • ResetCache : _PEI_CACHE_PPI
  • RetrieveMicrocode : CPU_CONFIG
  • Revision : PPM_GLOBAL_NVS_AREA , _DXE_CPU_PLATFORM_POLICY_PROTOCOL , _PEI_CPU_PLATFORM_POLICY_PPI , _DXE_CPU_INFO_PROTOCOL
  • RfiFreqTunningOffset : POWER_MGMT_CONFIG
  • RfiFreqTunningOffsetIsNegative : POWER_MGMT_CONFIG
  • Rsvdbyte : CPU_CONFIG_PPI
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Here is a list of all documented class members with links to the class documentation for each member:

- s -

  • S3RestoreMsrSwSmiNumber : POWER_MGMT_CONFIG
  • ScriptSectionSize : PUP_HEADER
  • SecurityConfig : _DXE_CPU_PLATFORM_POLICY_PROTOCOL , _PEI_CPU_PLATFORM_POLICY_PPI
  • SendIPI : _EFI_MP_SERVICES_PROTOCOL
  • SerialNumber : PLATFORM_CPU_INFORMATION
  • SetCache : _PEI_CACHE_PPI
  • SfamData : PPDT
  • SinitMemorySize : TXT_CONFIG
  • SmmbaseSwSmiNumber : CPU_CONFIG
  • SmxEnable : CPU_CONFIG
  • SocketName : PLATFORM_CPU_INFORMATION
  • SocketType : PLATFORM_CPU_INFORMATION
  • StartupAllAPs : _EFI_PI_MP_SERVICES_PROTOCOL , _EFI_MP_SERVICES_PROTOCOL
  • StartupThisAP : _EFI_MP_SERVICES_PROTOCOL , _EFI_PI_MP_SERVICES_PROTOCOL
  • StateRatio : PPM_CUSTOM_RATIO_TABLE
  • StatusFlag : EFI_PROCESSOR_INFORMATION
  • StringHandle : PLATFORM_CPU_INFORMATION
  • SvidEnable : OVERCLOCKING_CONFIG_PPI
  • SvidVoltageOverride : OVERCLOCKING_CONFIG_PPI
  • SwitchBSP : _EFI_PI_MP_SERVICES_PROTOCOL , _EFI_MP_SERVICES_PROTOCOL
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- t -

  • TccActivationOffset : POWER_MGMT_CONFIG_PPI
  • TgaSize : TXT_CONFIG
  • ThermalFuncEnables : POWER_MGMT_CONFIG
  • ThermalMonitor : PPM_FUNCTION_ENABLES , THERM_FUNCTION_ENABLES
  • ThermReserved : THERM_FUNCTION_ENABLES
  • Thread : EFI_CPU_PHYSICAL_LOCATION
  • TimedMwait : PPM_FUNCTION_ENABLES
  • TStates : PPM_FUNCTION_ENABLES , THERM_FUNCTION_ENABLES
  • TurboMode : PPM_FUNCTION_ENABLES
  • TurboPowerLimitLock : _PPM_TURBO_SETTINGS
  • Txt : CPU_CONFIG_PPI
  • TxtConfig : SECURITY_CONFIG_PPI
  • TxtDprMemoryBase : TXT_CONFIG
  • TxtDprMemorySize : TXT_CONFIG
  • TxtHeapMemorySize : TXT_CONFIG
  • TxtLcpPdBase : TXT_CONFIG
  • TxtLcpPdSize : TXT_CONFIG
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Here is a list of all documented class members with links to the class documentation for each member:

- v -

  • Version : PUP_HEADER , PFAT_LOG
  • VirtualWireMode : CPU_CONFIG
  • VmxEnable : CPU_CONFIG_PPI , CPU_CONFIG
  • VrCurrentLimit : POWER_MGMT_CONFIG_PPI
  • VrCurrentLimitLock : POWER_MGMT_CONFIG_PPI
  • VrMisc2FastRampVoltage : POWER_MGMT_CONFIG_PPI
  • VrMisc2MinC8Voltage : POWER_MGMT_CONFIG_PPI
  • VrMiscIdleEntryDecayEnable : POWER_MGMT_CONFIG_PPI
  • VrMiscIdleEntryRampRate : POWER_MGMT_CONFIG_PPI
  • VrMiscIdleExitRampRate : POWER_MGMT_CONFIG_PPI
  • VrMiscIoutOffset : POWER_MGMT_CONFIG_PPI
  • VrMiscIoutOffsetSign : POWER_MGMT_CONFIG_PPI
  • VrMiscIoutSlope : POWER_MGMT_CONFIG_PPI
  • VrMiscMinVid : POWER_MGMT_CONFIG_PPI
  • VrMiscSlowSlewRateConfig : POWER_MGMT_CONFIG_PPI
  • VrPSI4enable : POWER_MGMT_CONFIG_PPI
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: Class Members

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Here is a list of all documented class members with links to the class documentation for each member:

- w -

  • WhoAmI : _EFI_MP_SERVICES_PROTOCOL , _EFI_PI_MP_SERVICES_PROTOCOL
  • Write : _PFAT_PROTOCOL
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Here is a list of all documented class members with links to the class documentation for each member:

- x -

  • XapicEnable : CPU_CONFIG
  • Xe : PPM_FUNCTION_ENABLES , POWER_MGMT_CONFIG_PPI
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


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- a -

  • ActivateCache : _PEI_CACHE_PPI
  • ActiveCoreCount : CPU_CONFIG_PPI
  • AesEnable : CPU_CONFIG
  • ApHandoffManner : CPU_CONFIG
  • ApicID : PLATFORM_CPU_INFORMATION
  • ApIdleManner : CPU_CONFIG
  • AssetTag : PLATFORM_CPU_INFORMATION
  • AutoActiveTripPoint : PPM_GLOBAL_NVS_AREA
  • AutoCriticalTripPoint : PPM_GLOBAL_NVS_AREA
  • AutoPassiveTripPoint : PPM_GLOBAL_NVS_AREA
  • AutoThermalReporting : THERM_FUNCTION_ENABLES , PPM_FUNCTION_ENABLES
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


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- b -

  • BiosAcmBase : TXT_CONFIG
  • BiosAcmSize : TXT_CONFIG
  • BiosSvn : PUP_HEADER , PPDT
  • BiProcHot : PPM_FUNCTION_ENABLES , THERM_FUNCTION_ENABLES
  • BistOnReset : CPU_CONFIG_PPI
  • BitReserved : OVERCLOCKING_CONFIG_PPI
  • BootGuardConfig : SECURITY_CONFIG_PPI
  • BootInLfm : POWER_MGMT_CONFIG_PPI
  • BspSelection : CPU_CONFIG
  • ByetReserved : TXT_FUNCTION_CONFIG
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


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- c -

  • C10 : PPM_FUNCTION_ENABLES
  • C1AutoDemotion : PPM_FUNCTION_ENABLES
  • C1e : PPM_FUNCTION_ENABLES
  • C1UnDemotion : PPM_FUNCTION_ENABLES
  • C3 : PPM_FUNCTION_ENABLES
  • C3AutoDemotion : PPM_FUNCTION_ENABLES
  • C3Latency : PPM_GLOBAL_NVS_AREA
  • C3MwaitValue : PPM_GLOBAL_NVS_AREA
  • C3UnDemotion : PPM_FUNCTION_ENABLES
  • C6 : PPM_FUNCTION_ENABLES
  • C6Latency : PPM_GLOBAL_NVS_AREA
  • C6MwaitValue : PPM_GLOBAL_NVS_AREA
  • C7Latency : PPM_GLOBAL_NVS_AREA
  • C7MwaitValue : PPM_GLOBAL_NVS_AREA
  • C8 : PPM_FUNCTION_ENABLES
  • C9 : PPM_FUNCTION_ENABLES
  • CDIOLevel : PPM_GLOBAL_NVS_AREA
  • CDLatency : PPM_GLOBAL_NVS_AREA
  • CDMwaitValue : PPM_GLOBAL_NVS_AREA
  • CDPowerValue : PPM_GLOBAL_NVS_AREA
  • ClrExtraTurboVoltage : OVERCLOCKING_CONFIG_PPI
  • ClrMaxOcTurboRatio : OVERCLOCKING_CONFIG_PPI
  • ClrVoltageMode : OVERCLOCKING_CONFIG_PPI
  • ClrVoltageOffset : OVERCLOCKING_CONFIG_PPI
  • ClrVoltageOverride : OVERCLOCKING_CONFIG_PPI
  • ComponentSize : PFAT_HOB , PFAT_CONFIG
  • ConfigTdpBios : _PPM_TURBO_SETTINGS
  • ConfigTdpBootModeIndex : PPM_GLOBAL_NVS_AREA
  • ConfigTdpCustom : _PPM_CUSTOM_CTDP
  • ConfigTdpLevel : _PPM_TURBO_SETTINGS
  • ConfigTdpLock : _PPM_TURBO_SETTINGS
  • ConfigurablePpc : PPM_GLOBAL_NVS_AREA
  • Core : EFI_CPU_PHYSICAL_LOCATION
  • CoreExtraTurboVoltage : OVERCLOCKING_CONFIG_PPI
  • CoreMaxOcTurboRatio : OVERCLOCKING_CONFIG_PPI
  • CoreVoltageMode : OVERCLOCKING_CONFIG_PPI
  • CoreVoltageOffset : OVERCLOCKING_CONFIG_PPI
  • CoreVoltageOverride : OVERCLOCKING_CONFIG_PPI
  • CpuCommonFeatures : _DXE_CPU_INFO_PROTOCOL
  • CpuConfig : _PEI_CPU_PLATFORM_POLICY_PPI , _DXE_CPU_PLATFORM_POLICY_PROTOCOL
  • Cpuid : PPM_CUSTOM_RATIO_TABLE , PPM_GLOBAL_NVS_AREA
  • CpuMaxNonTurboRatio : CPU_CONFIG_PPI
  • CpuPlatformPpiPtr : _PEI_CPU_PLATFORM_POLICY_PPI
  • CpuRatio : CPU_CONFIG_PPI
  • CpuRatioOverride : CPU_CONFIG_PPI
  • CstateLatencyControl0Irtl : POWER_MGMT_CONFIG
  • CstateLatencyControl0TimeUnit : POWER_MGMT_CONFIG
  • CstateLatencyControl1Irtl : POWER_MGMT_CONFIG
  • CstateLatencyControl1TimeUnit : POWER_MGMT_CONFIG
  • CstateLatencyControl2Irtl : POWER_MGMT_CONFIG
  • CstateLatencyControl2TimeUnit : POWER_MGMT_CONFIG
  • CstateLatencyControl3Irtl : POWER_MGMT_CONFIG
  • CstateLatencyControl3TimeUnit : POWER_MGMT_CONFIG
  • CstateLatencyControl4Irtl : POWER_MGMT_CONFIG
  • CstateLatencyControl4TimeUnit : POWER_MGMT_CONFIG
  • CstateLatencyControl5Irtl : POWER_MGMT_CONFIG
  • CstateLatencyControl5TimeUnit : POWER_MGMT_CONFIG
  • CStatePreWake : PPM_FUNCTION_ENABLES
  • CtdpCtc : PPM_CTDP_LEVEL_SETTINGS
  • CtdpLevelSettings : PPM_GLOBAL_NVS_AREA
  • CtdpLevelsSupported : PPM_GLOBAL_NVS_AREA
  • CtdpPowerLimit1 : PPM_CTDP_LEVEL_SETTINGS
  • CtdpPowerLimit2 : PPM_CTDP_LEVEL_SETTINGS
  • CtdpPowerLimitWindow : PPM_CTDP_LEVEL_SETTINGS
  • CtdpPpc : PPM_CTDP_LEVEL_SETTINGS
  • CtdpTar : PPM_CTDP_LEVEL_SETTINGS
  • CustomBootModeIndex : _PPM_CUSTOM_CTDP
  • CustomConfigTdp : PPM_GLOBAL_NVS_AREA
  • CustomConfigTdpControl : _PPM_CUSTOM_CTDP_TABLE
  • CustomConfigTdpTable : _PPM_CUSTOM_CTDP
  • CustomPowerLimit1 : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerLimit1Time : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerLimit2 : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerUnit : POWER_MGMT_CONFIG
  • CustomTdpCount : _PPM_CUSTOM_CTDP
  • CustomTurboActivationRatio : _PPM_CUSTOM_CTDP_TABLE
  • Cx : PPM_FUNCTION_ENABLES
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- d -

  • DataSectionSize : PUP_HEADER
  • DcaPrefetchDelayValue : CPU_CONFIG
  • DcaState : CPU_CONFIG
  • DdrPowerLimit1 : _PPM_TURBO_SETTINGS
  • DdrPowerLimit1Time : _PPM_TURBO_SETTINGS
  • DdrPowerLimit2 : _PPM_TURBO_SETTINGS
  • DdrPowerLimitLock : _PPM_TURBO_SETTINGS
  • DebugInterfaceEnable : CPU_CONFIG
  • DebugInterfaceLockEnable : CPU_CONFIG
  • DeepCState : PPM_FUNCTION_ENABLES
  • DisableProcHotOut : THERM_FUNCTION_ENABLES , PPM_FUNCTION_ENABLES
  • DisableVRThermalAlert : THERM_FUNCTION_ENABLES , PPM_FUNCTION_ENABLES
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- e -

  • EcCmd : PPDT
  • EcCmdClose : PPDT
  • EcCmdDiscovery : PFAT_CONFIG
  • EcCmdGetSvn : PPDT
  • EcCmdLock : PFAT_CONFIG
  • EcCmdOpen : PPDT
  • EcCmdPortTest : PPDT
  • EcCmdProvisionEav : PFAT_CONFIG
  • EcData : PPDT
  • EcSvn : PUP_HEADER
  • Eist : PPM_FUNCTION_ENABLES
  • EnableDisableAP : _EFI_MP_SERVICES_PROTOCOL , _EFI_PI_MP_SERVICES_PROTOCOL
  • EnableDts : CPU_CONFIG
  • EnableRerunPcodeCalibration : POWER_MGMT_CONFIG
  • EnergyEfficientPState : PPM_FUNCTION_ENABLES
  • EnergyPolicy : _PPM_TURBO_SETTINGS
  • Erase : _PFAT_PROTOCOL
  • ExecLim : PPDT
  • Execute : _PFAT_PROTOCOL
  • ExecuteDisableBit : CPU_CONFIG
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- f -

  • FastString : CPU_CONFIG
  • FirstByte : SFAM_DATA
  • FivrEfficiencyEnable : OVERCLOCKING_CONFIG_PPI
  • FivrFaultsEnable : OVERCLOCKING_CONFIG_PPI
  • FivrSscEnable : POWER_MGMT_CONFIG_PPI
  • FivrSscPercent : POWER_MGMT_CONFIG_PPI
  • FloorGT : PL1_THERMAL_CONTROL_FLOOR
  • FloorPCH : PL1_THERMAL_CONTROL_FLOOR
  • FviReport : CPU_CONFIG
  • FviSmbiosType : CPU_CONFIG
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- g -

  • GdtrProfileSize : SMRAM_CPU_DATA
  • GetCpuInfo : CPU_CONFIG
  • GetGeneralMPInfo : _EFI_MP_SERVICES_PROTOCOL
  • GetMaxCount : CPU_CONFIG
  • GetNumberOfProcessors : _EFI_PI_MP_SERVICES_PROTOCOL
  • GetProcessorContext : _EFI_MP_SERVICES_PROTOCOL
  • GetProcessorInfo : _EFI_PI_MP_SERVICES_PROTOCOL
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


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- h -

  • HtState : CPU_CONFIG
  • HyperThreading : CPU_CONFIG_PPI
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  • IsColdReset : CPU_CONFIG
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- l -

  • LakeTiny : PPM_FUNCTION_ENABLES
  • LastByte : SFAM_DATA
  • LastPage : PFAT_LOG
  • LastSfam : PPDT
  • LimitCpuidMaximumValue : CPU_CONFIG
  • Location : EFI_PROCESSOR_INFORMATION
  • LoggingOptions : PFAT_LOG
  • LongLatencyC6 : PPM_FUNCTION_ENABLES
  • LongLatencyC7 : PPM_FUNCTION_ENABLES
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- m -

  • MachineCheckEnable : CPU_CONFIG
  • MachineCheckStatusClean : CPU_CONFIG
  • MaxCoreFrequency : PLATFORM_CPU_INFORMATION
  • MaxFsbFrequency : PLATFORM_CPU_INFORMATION
  • MaxRatio : PPM_CUSTOM_RATIO_TABLE
  • McuUpdateDataAddr : TXT_CONFIG
  • MicrocodeDataBufferOffset : SMRAM_CPU_DATA
  • MicrocodePointerBufferOffset : SMRAM_CPU_DATA
  • MiscPowerManagementFlags : PPM_GLOBAL_NVS_AREA
  • MlcSpatialPrefetcher : CPU_CONFIG_PPI , CPU_CONFIG
  • MlcStreamerPrefetcher : CPU_CONFIG , CPU_CONFIG_PPI
  • MonitorMwaitEnable : CPU_CONFIG
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  • NumberOfEntries : PPM_CUSTOM_RATIO_TABLE
  • NumOfEntriesInLog : PFAT_LOG
  • NumSpiComponents : PFAT_HOB , PFAT_CONFIG
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- o -

  • OcSupport : OVERCLOCKING_CONFIG_PPI
  • OverclockingConfig : _PEI_CPU_PLATFORM_POLICY_PPI
  • OverclockingLock : _PPM_LOCK_ENABLES
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- p -

  • Package : EFI_CPU_PHYSICAL_LOCATION
  • PartNumber : PLATFORM_CPU_INFORMATION
  • PcodeCalibration : POWER_MGMT_CONFIG
  • pCustomCtdpSettings : POWER_MGMT_CONFIG
  • pCustomRatioTable : POWER_MGMT_CONFIG
  • Pfat : CPU_CONFIG_PPI
  • PfatConfig : SECURITY_CONFIG_PPI
  • PfatLog : PFAT_HOB , PFAT_CONFIG
  • PfatMemSize : PFAT_CONFIG
  • PfatModSvn : PPDT , PFAT_LOG
  • PfatToolsIntIoTrapAdd : PFAT_HOB
  • pFunctionEnables : POWER_MGMT_CONFIG
  • PkeySlot0 : PPDT
  • PkeySlot1 : PPDT
  • PkeySlot2 : PPDT
  • PkgAttributes : PUP_HEADER
  • PkgCStateDemotion : PPM_FUNCTION_ENABLES
  • PkgCStateLimit : POWER_MGMT_CONFIG
  • PkgCStateUnDemotion : PPM_FUNCTION_ENABLES
  • Pl1ThermalControl : THERM_FUNCTION_ENABLES
  • Pl1ThermalControlFloor : THERM_FUNCTION_ENABLES
  • PlatAttr : PPDT
  • PlatformCoreFrequencyList : PLATFORM_CPU_INFORMATION
  • PlatformFsbFrequencyList : PLATFORM_CPU_INFORMATION
  • PlatId : PPDT , PUP_HEADER
  • PmgCstCfgCtrlLock : _PPM_LOCK_ENABLES
  • PowerLimit1 : _PPM_TURBO_SETTINGS
  • PowerLimit1Time : _PPM_TURBO_SETTINGS
  • PowerLimit2 : PPM_FUNCTION_ENABLES , _PPM_TURBO_SETTINGS
  • PowerLimit3 : _PPM_TURBO_SETTINGS
  • PowerLimit3DutyCycle : _PPM_TURBO_SETTINGS
  • PowerLimit3Lock : _PPM_TURBO_SETTINGS
  • PowerLimit3Time : _PPM_TURBO_SETTINGS
  • PowerMgmtConfig : _PEI_CPU_PLATFORM_POLICY_PPI , _DXE_CPU_PLATFORM_POLICY_PROTOCOL
  • Ppdt : PFAT_HOB , PFAT_CONFIG
  • PpdtHash : PFAT_CONFIG
  • PpdtMajVer : PPDT
  • PpdtMinVer : PPDT
  • PpdtSize : PPDT
  • PpmFlags : PPM_GLOBAL_NVS_AREA
  • pPpmLockEnables : POWER_MGMT_CONFIG
  • pRatioLimit : POWER_MGMT_CONFIG
  • ProcessorId : EFI_PROCESSOR_INFORMATION
  • ProcHotLock : _PPM_LOCK_ENABLES
  • ProcHotResponce : PPM_FUNCTION_ENABLES , THERM_FUNCTION_ENABLES
  • Psi1Threshold : POWER_MGMT_CONFIG_PPI
  • Psi2Threshold : POWER_MGMT_CONFIG_PPI
  • Psi3Threshold : POWER_MGMT_CONFIG_PPI
  • PslMajorVer : PUP_HEADER
  • PslMinorVer : PUP_HEADER
  • pTurboSettings : POWER_MGMT_CONFIG
  • PupHeader : PFAT_CONFIG , PFAT_HOB
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  • RatioLimit : POWER_MGMT_CONFIG_PPI
  • RcVersion : _DXE_CPU_INFO_PROTOCOL
  • ReferenceString : PLATFORM_CPU_INFORMATION
  • Reserved : TXT_FUNCTION_CONFIG , PPM_FUNCTION_ENABLES , _PPM_LOCK_ENABLES , PPM_GLOBAL_NVS_AREA
  • ResetAux : TXT_FUNCTION_CONFIG
  • ResetCache : _PEI_CACHE_PPI
  • RetrieveMicrocode : CPU_CONFIG
  • Revision : PPM_GLOBAL_NVS_AREA , _DXE_CPU_PLATFORM_POLICY_PROTOCOL , _PEI_CPU_PLATFORM_POLICY_PPI , _DXE_CPU_INFO_PROTOCOL
  • RfiFreqTunningOffset : POWER_MGMT_CONFIG
  • RfiFreqTunningOffsetIsNegative : POWER_MGMT_CONFIG
  • Rsvdbyte : CPU_CONFIG_PPI
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  • S3RestoreMsrSwSmiNumber : POWER_MGMT_CONFIG
  • ScriptSectionSize : PUP_HEADER
  • SecurityConfig : _DXE_CPU_PLATFORM_POLICY_PROTOCOL , _PEI_CPU_PLATFORM_POLICY_PPI
  • SendIPI : _EFI_MP_SERVICES_PROTOCOL
  • SerialNumber : PLATFORM_CPU_INFORMATION
  • SetCache : _PEI_CACHE_PPI
  • SfamData : PPDT
  • SinitMemorySize : TXT_CONFIG
  • SmmbaseSwSmiNumber : CPU_CONFIG
  • SmxEnable : CPU_CONFIG
  • SocketName : PLATFORM_CPU_INFORMATION
  • SocketType : PLATFORM_CPU_INFORMATION
  • StartupAllAPs : _EFI_PI_MP_SERVICES_PROTOCOL , _EFI_MP_SERVICES_PROTOCOL
  • StartupThisAP : _EFI_MP_SERVICES_PROTOCOL , _EFI_PI_MP_SERVICES_PROTOCOL
  • StateRatio : PPM_CUSTOM_RATIO_TABLE
  • StatusFlag : EFI_PROCESSOR_INFORMATION
  • StringHandle : PLATFORM_CPU_INFORMATION
  • SvidEnable : OVERCLOCKING_CONFIG_PPI
  • SvidVoltageOverride : OVERCLOCKING_CONFIG_PPI
  • SwitchBSP : _EFI_PI_MP_SERVICES_PROTOCOL , _EFI_MP_SERVICES_PROTOCOL
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- t -

  • TccActivationOffset : POWER_MGMT_CONFIG_PPI
  • TgaSize : TXT_CONFIG
  • ThermalFuncEnables : POWER_MGMT_CONFIG
  • ThermalMonitor : PPM_FUNCTION_ENABLES , THERM_FUNCTION_ENABLES
  • ThermReserved : THERM_FUNCTION_ENABLES
  • Thread : EFI_CPU_PHYSICAL_LOCATION
  • TimedMwait : PPM_FUNCTION_ENABLES
  • TStates : PPM_FUNCTION_ENABLES , THERM_FUNCTION_ENABLES
  • TurboMode : PPM_FUNCTION_ENABLES
  • TurboPowerLimitLock : _PPM_TURBO_SETTINGS
  • Txt : CPU_CONFIG_PPI
  • TxtConfig : SECURITY_CONFIG_PPI
  • TxtDprMemoryBase : TXT_CONFIG
  • TxtDprMemorySize : TXT_CONFIG
  • TxtHeapMemorySize : TXT_CONFIG
  • TxtLcpPdBase : TXT_CONFIG
  • TxtLcpPdSize : TXT_CONFIG
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- v -

  • Version : PUP_HEADER , PFAT_LOG
  • VirtualWireMode : CPU_CONFIG
  • VmxEnable : CPU_CONFIG_PPI , CPU_CONFIG
  • VrCurrentLimit : POWER_MGMT_CONFIG_PPI
  • VrCurrentLimitLock : POWER_MGMT_CONFIG_PPI
  • VrMisc2FastRampVoltage : POWER_MGMT_CONFIG_PPI
  • VrMisc2MinC8Voltage : POWER_MGMT_CONFIG_PPI
  • VrMiscIdleEntryDecayEnable : POWER_MGMT_CONFIG_PPI
  • VrMiscIdleEntryRampRate : POWER_MGMT_CONFIG_PPI
  • VrMiscIdleExitRampRate : POWER_MGMT_CONFIG_PPI
  • VrMiscIoutOffset : POWER_MGMT_CONFIG_PPI
  • VrMiscIoutOffsetSign : POWER_MGMT_CONFIG_PPI
  • VrMiscIoutSlope : POWER_MGMT_CONFIG_PPI
  • VrMiscMinVid : POWER_MGMT_CONFIG_PPI
  • VrMiscSlowSlewRateConfig : POWER_MGMT_CONFIG_PPI
  • VrPSI4enable : POWER_MGMT_CONFIG_PPI
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- w -

  • WhoAmI : _EFI_MP_SERVICES_PROTOCOL , _EFI_PI_MP_SERVICES_PROTOCOL
  • Write : _PFAT_PROTOCOL
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- x -

  • XapicEnable : CPU_CONFIG
  • Xe : PPM_FUNCTION_ENABLES , POWER_MGMT_CONFIG_PPI
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2013 SharkBay Processor Reference Code API: File List

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  • File Members
File List
Here is a list of all documented files with brief descriptions:
BootGuardLibrary.h [code] | Header file for Boot Guard Lib implementation
Cache.h [code] | Cache PPI defined in EFI 2.0 This code abstracts Cache Settings
CommonIncludes.h [code] | This file defines common equates
CpuAccess.h [code] | Macros to simplify and abstract the interface to CPU configuration
CpuBaseLib.h [code]
Copyright:
Copyright (c) 2004 - 2012 Intel Corporation
CpuDataStruct.h [code] | CPU data structure
CpuInfo.h [code] | Protocol used to report CPU information
CpuPlatformLib.h [code] | Header file for CpuPlatform Lib
CpuPlatformLibrary.h [code] | Header file for Cpu Platform Lib implementation
Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h [code] | CPU policy PPI produced by a platform driver specifying various expected CPU settings
Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h [code] | Protocol used for specifying platform related CPU information and policy setting
CpuPmConfig.h [code] | Describes the defintions / functions visible to the rest of the PPM
CpuRegs.h [code] | Conventions:
HtBistHob.h [code] | GUID used for HT BIST Status HOB entries in the HOB list
MpService.h [code] | This protocol produces MP Protocol
OverclockingLibrary.h [code] | Header file for Cpu Platform Lib implementation
Pfat.h [code] | This file defines the PFAT Protocol which implements the Intel(R) PFAT Host Controller Compatibility Interface
PfatDefinitions.h [code] | Describes the functions visible to the rest of the Pfat
PiMpService.h [code] | Definitions for the PI MP Services Protocol defined in the PI spec
PowerMgmtAcpiTableStorage.h [code] | GUID definition for the Power Management ACPI table storage file name
PowerMgmtDefinitions.h [code] | This file contains define definitions specific to Haswell processor
PowerMgmtInitDone.h [code] | This file defines the PowerMgmtInitDone Protocol
PoweronHob.h [code] | GUID for Power On boot mode
PpmGlobalNvsArea.h [code] | Definition of the CPU PM global NVS area protocol
SmmThunk.h [code] | This file defines SMM Thunk abstraction protocol
SmramCpuDataHeader.h [code] | GUIDs used for SMRAM CPU DATA Header signature
SmramCpuDataVariable.h [code] | GUIDs used for SMRAM CPU DATA Variable to keep 2 locations for copying data from regular memory to SMM memory
ThunkLib.h [code] | Real Mode Thunk Functions for IA32 and X64
TpmInitialized.h [code] | Tpm Initialized PPI definition, used to notify any code after TPM initialized
Txt.h [code] | This file contains definitions required to use the TXT BIOS Authenticated Code Module Library
TxtInfoHob.h [code] | This file contains definitions required for creation of TXT Info HOB
TxtLibrary.h [code] | This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor
TxtMemoryUnlocked.h [code] | This file contains PPI definition that is installed by TXT PEIM
TxtOneTouch.h [code] | This file contains definitions required for One-Touch function
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2013 SharkBay Processor Reference Code API: BootGuardLibrary.h File Reference

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Functions
BootGuardLibrary.h File Reference

Header file for Boot Guard Lib implementation. More...

Go to the source code of this file.

Functions

BOOLEAN | IsBootGuardSupported (VOID)
Determine if Boot Guard is supported.
EFI_STATUS | StopPbeTimer (VOID)
Stop PBE timer if system is in Boot Guard boot.

Detailed Description

Header file for Boot Guard Lib implementation.

Copyright:
Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file BootGuardLibrary.h.

Function Documentation

BOOLEAN IsBootGuardSupported ( VOID )

Determine if Boot Guard is supported.

Return values:
TRUE | - Processor is Boot Guard capable.
FALSE | - Processor is not Boot Guard capable.
EFI_STATUS StopPbeTimer ( VOID )

Stop PBE timer if system is in Boot Guard boot.

Return values:
EFI_SUCCESS | - Stop PBE timer
EFI_UNSUPPORTED | - Not in Boot GuardSupport mode.
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2013 SharkBay Processor Reference Code API: BootGuardLibrary.h Source File

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BootGuardLibrary.h
Go to the documentation of this file.
00001
00021 #ifndef _BOOT_GUARD_LIBRARY_H_
00022 #define _BOOT_GUARD_LIBRARY_H_
00023
00031 BOOLEAN
00032 IsBootGuardSupported (
00033   VOID
00034   );
00035
00042 EFI_STATUS
00043 StopPbeTimer (
00044   VOID
00045   );
00046 #endif
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2013 SharkBay Processor Reference Code API: Cache.h File Reference

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Classes | Defines | Typedefs | Enumerations | Functions | Variables
Cache.h File Reference

Cache PPI defined in EFI 2.0 This code abstracts Cache Settings. More...

Go to the source code of this file.

Classes

struct | _PEI_CACHE_PPI
Platform code can use this interface to arrange MTRR configuration in PEI phase. More...

Defines

#define | PEI_CACHE_PPI_GUID

Typedefs

typedef enum _EFI_MEMORY_CACHE_TYPE | EFI_MEMORY_CACHE_TYPE
typedef EFI_STATUS(* | PEI_SET_CACHE_PPI )(IN EFI_PEI_SERVICES **PeiServices, IN PEI_CACHE_PPI *This, IN EFI_PHYSICAL_ADDRESS MemoryAddress, IN UINT64 MemoryLength, IN EFI_MEMORY_CACHE_TYPE MemoryCacheType)
typedef EFI_STATUS(* | PEI_RESET_CACHE_PPI )(IN EFI_PEI_SERVICES **PeiServices, IN PEI_CACHE_PPI *This)
typedef EFI_STATUS(* | PEI_ACTIVATE_CACHE_PPI )(IN EFI_PEI_SERVICES **PeiServices, IN PEI_CACHE_PPI *This)

Enumerations

enum | _EFI_MEMORY_CACHE_TYPE

Functions

EFI_FORWARD_DECLARATION (PEI_CACHE_PPI)

Variables

EFI_GUID | gPeiCachePpiGuid

Detailed Description

Cache PPI defined in EFI 2.0 This code abstracts Cache Settings.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Definition in file Cache.h.

Define Documentation

#define PEI_CACHE_PPI_GUID
Value:
{ \
    0x9be4bc2, 0x790e, 0x4dea, 0x8b, 0xdc, 0x38, 0x5, 0x16, 0x98, 0x39, 0x44 \
  }

Definition at line 23 of file Cache.h.

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2013 SharkBay Processor Reference Code API: Cache.h Source File

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Cache.h
Go to the documentation of this file.
00001
00020 #ifndef _PEI_CACHE_PPI_H_
00021 #define _PEI_CACHE_PPI_H_
00022
00023 #define PEI_CACHE_PPI_GUID \
00024   { \
00025     0x9be4bc2, 0x790e, 0x4dea, 0x8b, 0xdc, 0x38, 0x5, 0x16, 0x98, 0x39, 0x44 \
00026   }
00027
00028 EFI_FORWARD_DECLARATION (PEI_CACHE_PPI);
00029
00030 typedef enum _EFI_MEMORY_CACHE_TYPE
00031 {
00032   EfiCacheTypeUncacheable   = 0,
00033   EfiCacheTypeWriteCombining= 1,
00034   EfiCacheTypeReserved2     = 2,
00035   EfiCacheTypeReserved3     = 3,
00036   EfiCacheTypeWriteThrough  = 4,
00037   EfiCacheTypeWriteProtected= 5,
00038   EfiCacheTypeWriteBack     = 6,
00039   EfiCacheTypeMaximumType   = 7
00040 } EFI_MEMORY_CACHE_TYPE;
00041
00042 typedef
00043 EFI_STATUS
00044 (EFIAPI *PEI_SET_CACHE_PPI)(
00045   IN EFI_PEI_SERVICES      **PeiServices,
00046   IN PEI_CACHE_PPI         *This,
00047   IN EFI_PHYSICAL_ADDRESS  MemoryAddress,
00048   IN UINT64                MemoryLength,
00049   IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
00050   );
00051
00052 typedef
00053 EFI_STATUS
00054 (EFIAPI *PEI_RESET_CACHE_PPI)(
00055   IN EFI_PEI_SERVICES **PeiServices,
00056   IN PEI_CACHE_PPI    *This
00057   );
00058
00059 typedef
00060 EFI_STATUS
00061 (EFIAPI *PEI_ACTIVATE_CACHE_PPI)(
00062   IN EFI_PEI_SERVICES **PeiServices,
00063   IN PEI_CACHE_PPI    *This
00064   );
00065
00069 struct _PEI_CACHE_PPI {
00073   PEI_SET_CACHE_PPI      SetCache;
00077   PEI_RESET_CACHE_PPI    ResetCache;
00081   PEI_ACTIVATE_CACHE_PPI ActivateCache;
00082 };
00083
00084 extern EFI_GUID gPeiCachePpiGuid;
00085
00086 #endif
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2013 SharkBay Processor Reference Code API: CommonIncludes.h File Reference

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Defines
CommonIncludes.h File Reference

This file defines common equates. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Defines

#define | V_INTEL_VID 0x8086
#define | STALL_ONE_MICRO_SECOND 1
#define | STALL_ONE_MILLI_SECOND 1000
#define | V_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | V_MAX(a, b) (((a) > (b)) ? (a) : (b))
#define | BIT63 0x8000000000000000ULL
Bit map macro.
#define | BIT62 0x4000000000000000ULL
#define | BIT61 0x2000000000000000ULL
#define | BIT60 0x1000000000000000ULL
#define | BIT59 0x0800000000000000ULL
#define | BIT58 0x0400000000000000ULL
#define | BIT57 0x0200000000000000ULL
#define | BIT56 0x0100000000000000ULL
#define | BIT55 0x0080000000000000ULL
#define | BIT54 0x0040000000000000ULL
#define | BIT53 0x0020000000000000ULL
#define | BIT52 0x0010000000000000ULL
#define | BIT51 0x0008000000000000ULL
#define | BIT50 0x0004000000000000ULL
#define | BIT49 0x0002000000000000ULL
#define | BIT48 0x0001000000000000ULL
#define | BIT47 0x0000800000000000ULL
#define | BIT46 0x0000400000000000ULL
#define | BIT45 0x0000200000000000ULL
#define | BIT44 0x0000100000000000ULL
#define | BIT43 0x0000080000000000ULL
#define | BIT42 0x0000040000000000ULL
#define | BIT41 0x0000020000000000ULL
#define | BIT40 0x0000010000000000ULL
#define | BIT39 0x0000008000000000ULL
#define | BIT38 0x0000004000000000ULL
#define | BIT37 0x0000002000000000ULL
#define | BIT36 0x0000001000000000ULL
#define | BIT35 0x0000000800000000ULL
#define | BIT34 0x0000000400000000ULL
#define | BIT33 0x0000000200000000ULL
#define | BIT32 0x0000000100000000ULL
#define | BIT31 0x80000000
#define | BIT30 0x40000000
#define | BIT29 0x20000000
#define | BIT28 0x10000000
#define | BIT27 0x08000000
#define | BIT26 0x04000000
#define | BIT25 0x02000000
#define | BIT24 0x01000000
#define | BIT23 0x00800000
#define | BIT22 0x00400000
#define | BIT21 0x00200000
#define | BIT20 0x00100000
#define | BIT19 0x00080000
#define | BIT18 0x00040000
#define | BIT17 0x00020000
#define | BIT16 0x00010000
#define | BIT15 0x00008000
#define | BIT14 0x00004000
#define | BIT13 0x00002000
#define | BIT12 0x00001000
#define | BIT11 0x00000800
#define | BIT10 0x00000400
#define | BIT9 0x00000200
#define | BIT8 0x00000100
#define | BIT7 0x00000080
#define | BIT6 0x00000040
#define | BIT5 0x00000020
#define | BIT4 0x00000010
#define | BIT3 0x00000008
#define | BIT2 0x00000004
#define | BIT1 0x00000002
#define | BIT0 0x00000001
#define | BITS(x) (1 << (x))
#define | BIT(Pos, Value) (1 << (Pos) & (Value))
#define | BITRANGE(From, Width, Value) (((Value) >> (From)) & ((1 << (Width)) - 1))

Detailed Description

This file defines common equates.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Mobile Silicon Support Module" and is licensed for Intel Mobile CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file CommonIncludes.h.

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2013 SharkBay Processor Reference Code API: CommonIncludes.h Source File

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CommonIncludes.h
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00001
00021 #ifndef _COMMON_INCLUDES_H_
00022 #define _COMMON_INCLUDES_H_
00023
00024 #define V_INTEL_VID 0x8086
00025
00026 #ifndef STALL_ONE_MICRO_SECOND
00027 #define STALL_ONE_MICRO_SECOND  1
00028 #endif
00029 #ifndef STALL_ONE_MILLI_SECOND
00030 #define STALL_ONE_MILLI_SECOND  1000
00031 #endif
00032 //
00033 // Min Max
00034 //
00035 #define V_MIN(a, b) (((a) < (b)) ? (a) : (b))
00036 #define V_MAX(a, b) (((a) > (b)) ? (a) : (b))
00037
00041 #ifndef BIT0
00042
00043 #define BIT63 0x8000000000000000ULL
00044 #define BIT62 0x4000000000000000ULL
00045 #define BIT61 0x2000000000000000ULL
00046 #define BIT60 0x1000000000000000ULL
00047 #define BIT59 0x0800000000000000ULL
00048 #define BIT58 0x0400000000000000ULL
00049 #define BIT57 0x0200000000000000ULL
00050 #define BIT56 0x0100000000000000ULL
00051 #define BIT55 0x0080000000000000ULL
00052 #define BIT54 0x0040000000000000ULL
00053 #define BIT53 0x0020000000000000ULL
00054 #define BIT52 0x0010000000000000ULL
00055 #define BIT51 0x0008000000000000ULL
00056 #define BIT50 0x0004000000000000ULL
00057 #define BIT49 0x0002000000000000ULL
00058 #define BIT48 0x0001000000000000ULL
00059 #define BIT47 0x0000800000000000ULL
00060 #define BIT46 0x0000400000000000ULL
00061 #define BIT45 0x0000200000000000ULL
00062 #define BIT44 0x0000100000000000ULL
00063 #define BIT43 0x0000080000000000ULL
00064 #define BIT42 0x0000040000000000ULL
00065 #define BIT41 0x0000020000000000ULL
00066 #define BIT40 0x0000010000000000ULL
00067 #define BIT39 0x0000008000000000ULL
00068 #define BIT38 0x0000004000000000ULL
00069 #define BIT37 0x0000002000000000ULL
00070 #define BIT36 0x0000001000000000ULL
00071 #define BIT35 0x0000000800000000ULL
00072 #define BIT34 0x0000000400000000ULL
00073 #define BIT33 0x0000000200000000ULL
00074 #define BIT32 0x0000000100000000ULL
00075
00076 #define BIT31 0x80000000
00077 #define BIT30 0x40000000
00078 #define BIT29 0x20000000
00079 #define BIT28 0x10000000
00080 #define BIT27 0x08000000
00081 #define BIT26 0x04000000
00082 #define BIT25 0x02000000
00083 #define BIT24 0x01000000
00084 #define BIT23 0x00800000
00085 #define BIT22 0x00400000
00086 #define BIT21 0x00200000
00087 #define BIT20 0x00100000
00088 #define BIT19 0x00080000
00089 #define BIT18 0x00040000
00090 #define BIT17 0x00020000
00091 #define BIT16 0x00010000
00092 #define BIT15 0x00008000
00093 #define BIT14 0x00004000
00094 #define BIT13 0x00002000
00095 #define BIT12 0x00001000
00096 #define BIT11 0x00000800
00097 #define BIT10 0x00000400
00098 #define BIT9  0x00000200
00099 #define BIT8  0x00000100
00100 #define BIT7  0x00000080
00101 #define BIT6  0x00000040
00102 #define BIT5  0x00000020
00103 #define BIT4  0x00000010
00104 #define BIT3  0x00000008
00105 #define BIT2  0x00000004
00106 #define BIT1  0x00000002
00107 #define BIT0  0x00000001
00108 #endif
00109
00110 #define BITS(x) (1 << (x))
00111
00112 /*
00113 Notes :
00114   1.  Bit position always starts at 0.
00115   2.  Following macros are applicable only for Word alligned integers.
00116 */
00117 #define BIT(Pos, Value)               (1 << (Pos) & (Value))
00118 #define BITRANGE(From, Width, Value)  (((Value) >> (From)) & ((1 << (Width)) - 1))
00119
00120 #endif
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2013 SharkBay Processor Reference Code API: CpuAccess.h File Reference

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CpuAccess.h File Reference

Macros to simplify and abstract the interface to CPU configuration. More...

#include "CpuRegs.h"
#include "CpuDataStruct.h"
#include "CpuBaseLib.h"
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Detailed Description

Macros to simplify and abstract the interface to CPU configuration.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file CpuAccess.h.

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2013 SharkBay Processor Reference Code API: CpuAccess.h Source File

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CpuAccess.h
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00001
00021 #ifndef _CPUACCESS_H_
00022 #define _CPUACCESS_H_
00023
00024 #include "CpuRegs.h"
00025 #include "CpuDataStruct.h"
00026 #include "CpuBaseLib.h"
00027
00028 #endif
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2013 SharkBay Processor Reference Code API: CpuBaseLib.h File Reference

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Defines | Functions
CpuBaseLib.h File Reference

Copyright:
Copyright (c) 2004 - 2012 Intel Corporation.
More...

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Defines

#define | EfiMakeCpuVersion(f, m, s) (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))
Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number.
#define | IA32API __cdecl

Functions

VOID IA32API | EfiHalt (VOID)
Halt the Cpu.
VOID IA32API | EfiWbinvd (VOID)
Write back and invalidate the Cpu cache.
VOID IA32API | EfiInvd (VOID)
Invalidate the Cpu cache.
VOID IA32API | EfiCpuid (IN UINT32 RegisterInEax, OUT EFI_CPUID_REGISTER *Regs)
Get the Cpu info by excute the CPUID instruction.
VOID IA32API | EfiCpuidExt (IN UINT32 RegisterInEax, IN UINT32 CacheLevel, OUT EFI_CPUID_REGISTER *Regs)
When RegisterInEax != 4, the functionality is the same as EfiCpuid.
UINT64 IA32API | EfiReadMsr (IN UINT32 Index)
Read Cpu MSR.
VOID IA32API | EfiWriteMsr (IN UINT32 Index, IN UINT64 Value)
Write Cpu MSR.
UINT64 IA32API | EfiReadTsc (VOID)
Read Time stamp.
VOID IA32API | EfiDisableCache (VOID)
Writing back and invalidate the cache,then diable it.
VOID IA32API | EfiEnableCache (VOID)
Invalidate the cache,then Enable it.
UINT32 IA32API | EfiGetEflags (VOID)
Get Eflags.
VOID IA32API | EfiDisableInterrupts (VOID)
Disable interrupt.
VOID IA32API | EfiEnableInterrupts (VOID)
Enable interrupt.
VOID IA32API | EfiCpuVersion (IN UINT16 *FamilyId, OPTIONAL IN UINT8 *Model, OPTIONAL IN UINT8 *SteppingId, OPTIONAL IN UINT8 *Processor OPTIONAL)
Extract CPU detail version infomation.

Detailed Description

Copyright:
Copyright (c) 2004 - 2012 Intel Corporation.

All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file CpuBaseLib.h.

Function Documentation

VOID IA32API EfiCpuid | ( | IN UINT32 | RegisterInEax,
 |  | OUT EFI_CPUID_REGISTER * | Regs
 | ) |  |

Get the Cpu info by excute the CPUID instruction.

Parameters:
[in] | RegisterInEax | -The input value to put into register EAX
[in] | Regs | -The Output value
VOID IA32API EfiCpuidExt | ( | IN UINT32 | RegisterInEax,
 |  | IN UINT32 | CacheLevel,
 |  | OUT EFI_CPUID_REGISTER * | Regs
 | ) |  |

When RegisterInEax != 4, the functionality is the same as EfiCpuid.

When RegisterInEax == 4, the function return the deterministic cache parameters by excuting the CPUID instruction

Parameters:
[in] | RegisterInEax | - The input value to put into register EAX
[in] | CacheLevel | - The deterministic cache level
[in] | Regs | - The Output value
VOID IA32API EfiCpuVersion | ( | IN UINT16 * | FamilyId,
 |  | OPTIONAL IN UINT8 * | Model,
 |  | OPTIONAL IN UINT8 * | SteppingId,
 |  | OPTIONAL IN UINT8 *Processor | OPTIONAL
 | ) |  |

Extract CPU detail version infomation.

Parameters:
[in] | FamilyId | - FamilyId, including ExtendedFamilyId
[in] | Model | - Model, including ExtendedModel
[in] | SteppingId | - SteppingId
[in] | Processor | - Processor
UINT32 IA32API EfiGetEflags ( VOID )

Get Eflags.

Return values:
Return the Eflags value
UINT64 IA32API EfiReadMsr ( IN UINT32 Index )

Read Cpu MSR.

Parameters:
[in] Index - The index value to select the register
Return values:
UINT64 - the read data
UINT64 IA32API EfiReadTsc ( VOID )

Read Time stamp.

Return values:
Return the read data
VOID IA32API EfiWriteMsr | ( | IN UINT32 | Index,
 |  | IN UINT64 | Value
 | ) |  |

Write Cpu MSR.

Parameters:
[in] | Index | - The index value to select the register
[in] | Value | - The value to write to the selected register
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2013 SharkBay Processor Reference Code API: CpuBaseLib.h Source File

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CpuBaseLib.h
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00001
00019 #ifndef _CPU_BASE_LIB_H
00020 #define _CPU_BASE_LIB_H
00021
00025 #define EfiMakeCpuVersion(f, m, s)  (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))
00026
00027 #if defined (__GNUC__)
00028 #define IA32API                     _EFIAPI
00029 #else
00030 #define IA32API                     __cdecl
00031 #endif
00032
00036 VOID
00037 IA32API
00038 EfiHalt (
00039   VOID
00040   );
00041
00045 VOID
00046 IA32API
00047 EfiWbinvd (
00048   VOID
00049   );
00050
00054 VOID
00055 IA32API
00056 EfiInvd (
00057   VOID
00058   );
00059
00066 VOID
00067 IA32API
00068 EfiCpuid (
00069   IN UINT32              RegisterInEax,
00070   OUT EFI_CPUID_REGISTER *Regs
00071   );
00072
00082 VOID
00083 IA32API
00084 EfiCpuidExt (
00085   IN UINT32              RegisterInEax,
00086   IN UINT32              CacheLevel,
00087   OUT EFI_CPUID_REGISTER *Regs
00088   );
00089
00097 UINT64
00098 IA32API
00099 EfiReadMsr (
00100   IN UINT32 Index
00101   );
00102
00109 VOID
00110 IA32API
00111 EfiWriteMsr (
00112   IN UINT32 Index,
00113   IN UINT64 Value
00114   );
00115
00121 UINT64
00122 IA32API
00123 EfiReadTsc (
00124   VOID
00125   );
00126
00130 VOID
00131 IA32API
00132 EfiDisableCache (
00133   VOID
00134   );
00135
00139 VOID
00140 IA32API
00141 EfiEnableCache (
00142   VOID
00143   );
00144
00150 UINT32
00151 IA32API
00152 EfiGetEflags (
00153   VOID
00154   );
00155
00159 VOID
00160 IA32API
00161 EfiDisableInterrupts (
00162   VOID
00163   );
00167 VOID
00168 IA32API
00169 EfiEnableInterrupts (
00170   VOID
00171   );
00172
00181 VOID
00182 IA32API
00183 EfiCpuVersion (
00184   IN UINT16           *FamilyId,
00185   OPTIONAL
00186   IN UINT8            *Model,
00187   OPTIONAL
00188   IN UINT8            *SteppingId,
00189   OPTIONAL
00190   IN UINT8 *Processor OPTIONAL
00191   );
00192
00193 #endif
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2013 SharkBay Processor Reference Code API: CpuDataStruct.h File Reference

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Classes
CpuDataStruct.h File Reference

CPU data structure. More...

#include <EFI_GUID_DEFINITION (SmramCpuDataVariable)>
#include <EFI_GUID_DEFINITION (SmramCpuDataHeader)>
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Classes

struct | PSEUDO_DESCRIPTOR
struct | ACPI_CPU_DATA
struct | SMRAM_CPU_DATA
struct | EFI_CPUID_REGISTER
struct | EFI_CPU_MICROCODE_HEADER
struct | EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER
struct | EFI_CPU_MICROCODE_EXTENDED_TABLE
struct | EFI_CPU_VERSION

Detailed Description

CPU data structure.

Copyright:
Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file CpuDataStruct.h.

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2013 SharkBay Processor Reference Code API: CpuDataStruct.h Source File

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CpuDataStruct.h
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00001
00020 #ifndef _CPU_DATA_STRUCT_H
00021 #define _CPU_DATA_STRUCT_H
00022
00023 #include EFI_GUID_DEFINITION (SmramCpuDataVariable)
00024 #include EFI_GUID_DEFINITION (SmramCpuDataHeader)
00025
00026 #pragma pack(1)
00027 typedef struct {
00028   UINT16 Limit;
00029   UINTN  Base;
00030 } PSEUDO_DESCRIPTOR;
00031 #pragma pack()
00032
00033 typedef struct {
00034   BOOLEAN              APState;
00035   BOOLEAN              S3BootPath;
00036   EFI_PHYSICAL_ADDRESS WakeUpBuffer;
00037   EFI_PHYSICAL_ADDRESS GdtrProfile;
00038   EFI_PHYSICAL_ADDRESS IdtrProfile;
00039   EFI_PHYSICAL_ADDRESS CpuPrivateData;
00040   EFI_PHYSICAL_ADDRESS StackAddress;
00041   EFI_PHYSICAL_ADDRESS MicrocodePointerBuffer;
00042   EFI_PHYSICAL_ADDRESS SmramBase;
00043   EFI_PHYSICAL_ADDRESS SmmStartImageBase;
00044   UINT32               SmmStartImageSize;
00045   UINT32               NumberOfCpus;
00046 } ACPI_CPU_DATA;
00047
00048 typedef struct {
00049   //
00050   // Guid as Signature.
00051   //
00052   EFI_GUID             HeaderGuid;
00053   EFI_PHYSICAL_ADDRESS AcpiCpuPointer;
00054   ACPI_CPU_DATA        AcpiCpuData;
00055
00056   //
00057   // It points the data defined below.
00058   //
00059   EFI_PHYSICAL_ADDRESS GdtrProfileOffset;
00060   EFI_PHYSICAL_ADDRESS GdtOffset;
00061   EFI_PHYSICAL_ADDRESS IdtrProfileOffset;
00062   EFI_PHYSICAL_ADDRESS IdtOffset;
00063   EFI_PHYSICAL_ADDRESS CpuPrivateDataOffset;
00064   EFI_PHYSICAL_ADDRESS S3BootScriptTableOffset;
00065   EFI_PHYSICAL_ADDRESS S3BspMtrrTableOffset;
00066   EFI_PHYSICAL_ADDRESS MicrocodePointerBufferOffset;
00067   EFI_PHYSICAL_ADDRESS MicrocodeDataBufferOffset;
00068
00069
00070
00071
00072   //
00073   // DataBuffer size
00074   //
00075   UINT32 GdtrProfileSize;
00076   UINT32 GdtSize;
00077   UINT32 IdtrProfileSize;
00078   UINT32 IdtSize;
00079   UINT32 CpuPrivateDataSize;
00080   UINT32 S3BootScriptTableSize;
00081   UINT32 S3BspMtrrTableSize;
00082   UINT32 MicrocodePointerBufferSize;
00083   UINT32 MicrocodeDataBufferSize;
00084
00085   //
00086   //  UINT8                 WakeUpBufferData[WakeUpBufferSize];
00087   //  UINT8                 GdtrProfileData[GdtrProfileSize];
00088   //  UINT8                 GdtData[GdtSize];
00089   //  UINT8                 IdtrProfileData[IdtrProfileSize];
00090   //  UINT8                 IdtData[IdtSize];
00091   //  UINT8                 CpuPrivateData[CpuPrivateDataSize];
00092   //  UINT8                 S3BootScriptTable[S3BootScriptTableSize];
00093   //  UINT8                 S3BspMtrrTable[S3BspMtrrTableSize];
00094   //  UINT32                MicrocodePointerBufferData[NumberOfCpus + 1];
00095   //  UINT8                 MicrocodeDataBufferData[MicrocodeDataBufferSize * NumberOfCpus];
00096   //
00097 } SMRAM_CPU_DATA;
00098
00099 typedef struct {
00100   UINT32 RegEax;
00101   UINT32 RegEbx;
00102   UINT32 RegEcx;
00103   UINT32 RegEdx;
00104 } EFI_CPUID_REGISTER;
00105
00106 typedef struct {
00107   UINT32 HeaderVersion;
00108   UINT32 UpdateRevision;
00109   UINT32 Date;
00110   UINT32 ProcessorId;
00111   UINT32 Checksum;
00112   UINT32 LoaderRevision;
00113   UINT32 ProcessorFlags;
00114   UINT32 DataSize;
00115   UINT32 TotalSize;
00116   UINT8  Reserved[12];
00117 } EFI_CPU_MICROCODE_HEADER;
00118
00119 typedef struct {
00120   UINT32 ExtendedSignatureCount;
00121   UINT32 ExtendedTableChecksum;
00122   UINT8  Reserved[12];
00123 } EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;
00124
00125 typedef struct {
00126   UINT32 ProcessorSignature;
00127   UINT32 ProcessorFlag;
00128   UINT32 ProcessorChecksum;
00129 } EFI_CPU_MICROCODE_EXTENDED_TABLE;
00130
00131 typedef struct {
00132   UINT32 Stepping       : 4;
00133   UINT32 Model          : 4;
00134   UINT32 Family         : 4;
00135   UINT32 Type           : 2;
00136   UINT32 Reserved1      : 2;
00137   UINT32 ExtendedModel  : 4;
00138   UINT32 ExtendedFamily : 8;
00139   UINT32 Reserved2      : 4;
00140 } EFI_CPU_VERSION;
00141
00142 #endif
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2013 SharkBay Processor Reference Code API: CpuInfo.h File Reference

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CpuInfo.h File Reference

Protocol used to report CPU information. More...

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Classes

struct | _DXE_CPU_INFO_PROTOCOL
Interface structure for the CPU Info Protocol. More...

Defines

#define | DXE_CPU_INFO_PROTOCOL_GUID
#define | DXE_CPU_INFO_REVISION_1 1
Protocol revision number Any backwards compatible changes to this protocol will result in an update in the revision number Major changes will require publication of a new protocol.
#define | CPU_RC_VERSION 0x01060100
RCVersion[7:0] is the release number.
#define | TXT_SUPPORT 1
The processor Command Feature Definition is a super set and abstracts from hardware.
#define | VMX_SUPPORT (1 << 1)
#define | XD_SUPPORT (1 << 2)
#define | DCA_SUPPORT (1 << 3)
#define | XAPIC_SUPPORT (1 << 4)
#define | AES_SUPPORT (1 << 5)
#define | HT_SUPPORT (1 << 6)
#define | DEBUG_SUPPORT (1 << 7)
#define | DEBUG_LOCK_SUPPORT (1 << 8)

Typedefs

typedef struct
_DXE_CPU_INFO_PROTOCOL 		DXE_CPU_INFO_PROTOCOL

Functions

EFI_FORWARD_DECLARATION (DXE_CPU_INFO_PROTOCOL_GUID)

Variables

EFI_GUID | gDxeCpuInfoProtocolGuid

Detailed Description

Protocol used to report CPU information.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file CpuInfo.h.

Define Documentation

#define CPU_RC_VERSION 0x01060100

RCVersion[7:0] is the release number.

For example: Version 0.7.1 should be 00 07 01 00 (0x00070100)

Definition at line 41 of file CpuInfo.h.

#define DXE_CPU_INFO_PROTOCOL_GUID
Value:
{ \
    0xe223cf65, 0xf6ce, 0x4122, 0xb3, 0xaf, 0x4b, 0xd1, 0x8a, 0xff, 0x40, 0xa1 \
  }

Definition at line 24 of file CpuInfo.h.

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2013 SharkBay Processor Reference Code API: CpuInfo.h Source File

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CpuInfo.h
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00001
00020 #ifndef _CPU_INFO_H_
00021 #define _CPU_INFO_H_
00022
00023 EFI_FORWARD_DECLARATION (DXE_CPU_INFO_PROTOCOL_GUID);
00024 #define DXE_CPU_INFO_PROTOCOL_GUID \
00025   { \
00026     0xe223cf65, 0xf6ce, 0x4122, 0xb3, 0xaf, 0x4b, 0xd1, 0x8a, 0xff, 0x40, 0xa1 \
00027   }
00028
00034 #define DXE_CPU_INFO_REVISION_1 1
00035
00041 #define CPU_RC_VERSION  0x01060100
00042
00043 extern EFI_GUID gDxeCpuInfoProtocolGuid;
00044
00045 //
00046 // Forward reference for ANSI C compatibility
00047 //
00048 typedef struct _DXE_CPU_INFO_PROTOCOL DXE_CPU_INFO_PROTOCOL;
00049
00050 //
00051 // CPU Common Feature Definition
00052 //
00053
00057 #define TXT_SUPPORT   1
00058 #define VMX_SUPPORT   (1 << 1)
00059 #define XD_SUPPORT    (1 << 2)
00060 #define DCA_SUPPORT   (1 << 3)
00061 #define XAPIC_SUPPORT (1 << 4)
00062 #define AES_SUPPORT   (1 << 5)
00063 #define HT_SUPPORT    (1 << 6)
00064 #define DEBUG_SUPPORT (1 << 7)
00065 #define DEBUG_LOCK_SUPPORT (1 << 8)
00066
00070 struct _DXE_CPU_INFO_PROTOCOL {
00071   UINT8  Revision;
00072   UINT32 RcVersion;
00073   //
00074   // Bit definition for functionality enable/disable
00075   //
00076   UINT64 CpuCommonFeatures;
00077 };
00078
00079 #endif
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2013 SharkBay Processor Reference Code API: CpuPlatformLib.h File Reference

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Classes | Defines | Typedefs | Functions
CpuPlatformLib.h File Reference

Header file for CpuPlatform Lib. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

union | _OC_MAILBOX_INTERFACE
struct | _OC_MAILBOX_FULL
union | _PCODE_MAILBOX_INTERFACE
struct | _PCODE_MAILBOX_FULL

Defines

#define | MAILBOX_TYPE_PCODE 0x00000001
#define | MAILBOX_TYPE_OC 0x00000002
#define | PCODE_MAILBOX_INTERFACE_OFFSET 0x5DA4
#define | PCODE_MAILBOX_DATA_OFFSET 0x5DA0
#define | OC_MAILBOX_MSR 0x00000150
#define | MCHBAR_OFFSET 0x48
#define | READ_ICC_MAX_CMD 0x80002A03
#define | SAMPLE_TSC_24AND100_CMD 0x80000009
#define | READ_TSC24_LOWER_CMD 0x80000109
#define | READ_TSC24_UPPER_CMD 0x80000209
#define | READ_TSC100_LOWER_CMD 0x80000309
#define | READ_TSC100_UPPER_CMD 0x80000409
#define | READ_PCODE_CALIBRATED_CMD 0x80000509
#define | WRITE_CONVERTION_RATIO_CMD 0x80000609
#define | WRITE_PREVENT_BCLKOFF_CMD 0x80000709
#define | WRITE_MEASURE_INTERVAL_CMD 0x80000809
#define | WRITE_FSM_MEASURE_INTVL_CMD 0x80000909
#define | START_CAL_VALUE 0x85000000
#define | READ_PL1_DUTY_CYCLE_CLAMP_ENABLE 0x00000015
#define | WRITE_PL1_DUTY_CYCLE_CLAMP_ENABLE 0x00000016
#define | READ_DDR_FORCE_2X_REFRESH 0x00000017
#define | WRITE_DDR_FORCE_2X_REFRESH 0x00000018
#define | MAILBOX_WAIT_TIMEOUT 1000
1 millisecond
#define | MAILBOX_WAIT_STALL 1
1 microsecond
#define | MAILBOX_READ_TIMEOUT 10
10 microseconds
#define | OC_MAILBOX_CC_SUCCESS 0
#define | OC_MAILBOX_CC_OC_LOCKED 1
#define | OC_MAILBOX_CC_INVALID_DOMAIN 2
#define | OC_MAILBOX_CC_MAX_RATIO_EXCEEDED 3
#define | OC_MAILBOX_CC_MAX_VOLTAGE_EXCEEDED 4
#define | OC_MAILBOX_CC_OC_NOT_SUPPORTED 5
#define | PCODE_MAILBOX_CC_SUCCESS 0
#define | PCODE_MAILBOX_CC_ILLEGAL_CMD 1
#define | PCODE_MAILBOX_CC_TIMEOUT 2
#define | PCODE_MAILBOX_CC_ILLEGAL_DATA 3
#define | PCODE_MAILBOX_CC_RESERVED 4
#define | PCODE_MAILBOX_CC_ILLEGAL_VR_ID 5
#define | PCODE_MAILBOX_CC_VR_INTERFACE_LOCKED 6
#define | PCODE_MAILBOX_CC_VR_ERROR 7
#define | READ_PCH_POWER_LEVELS_CMD 0x8000000A
#define | READ_EXT_PCH_POWER_LEVELS_CMD 0x8000000B

Typedefs

typedef union _OC_MAILBOX_INTERFACE | OC_MAILBOX_INTERFACE
typedef struct _OC_MAILBOX_FULL | OC_MAILBOX_FULL
typedef union
_PCODE_MAILBOX_INTERFACE 		PCODE_MAILBOX_INTERFACE
typedef struct _PCODE_MAILBOX_FULL | PCODE_MAILBOX_FULL

Functions

CPU_FAMILY | GetCpuFamily (VOID)
Check CPU Type of the platform.
CPU_STEPPING | GetCpuStepping (VOID)
Return Cpu stepping type.
BOOLEAN | IsCpuSupported (VOID)
Determine if CPU is supported.
UINT8 | GetCpuSku (VOID)
Return CPU Sku.
EFI_STATUS | MailboxWrite (IN UINT32 MailboxType, IN UINT32 MailboxCommand, IN UINT32 MailboxData, OUT UINT32 *MailboxStatus)
Generic Mailbox function for mailbox write commands.
EFI_STATUS | MailboxRead (IN UINT32 MailboxType, IN UINT32 MailboxCommand, OUT UINT32 *MailboxDataPtr, OUT UINT32 *MailboxStatus)
Generic Mailbox function for mailbox read commands.
EFI_STATUS | PollMailboxReady (IN UINT32 MailboxType)
Poll the run/busy bit of the mailbox until available or timeout expires.

Detailed Description

Header file for CpuPlatform Lib.

Copyright:
Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement

Definition in file CpuPlatformLib.h.

Function Documentation

CPU_FAMILY GetCpuFamily ( VOID )

Check CPU Type of the platform.

Return values:
CPU_FAMILY CPU type
UINT8 GetCpuSku ( VOID )

Return CPU Sku.

Return values:
UINT8 CPU Sku
CPU_STEPPING GetCpuStepping ( VOID )

Return Cpu stepping type.

Return values:
CPU_STEPPING Cpu stepping type
BOOLEAN IsCpuSupported ( VOID )

Determine if CPU is supported.

Return values:
TRUE | CPU is supported
FALSE | CPU is not supported
EFI_STATUS MailboxRead | ( | IN UINT32 | MailboxType,
 |  | IN UINT32 | MailboxCommand,
 |  | OUT UINT32 * | MailboxDataPtr,
 |  | OUT UINT32 * | MailboxStatus
 | ) |  |

Generic Mailbox function for mailbox read commands.

This function will write the read request, and populate the read results in the output data.

Parameters:
IN] | MailboxType,
IN] | MailboxCommand,
OUT] | *MailboxDataPtr,
OUT] | *MailboxStatus
Return values:
EFI_STATUS
EFI_STATUS MailboxWrite | ( | IN UINT32 | MailboxType,
 |  | IN UINT32 | MailboxCommand,
 |  | IN UINT32 | MailboxData,
 |  | OUT UINT32 * | MailboxStatus
 | ) |  |

Generic Mailbox function for mailbox write commands.

This function will poll the mailbox interface for control, issue the write request, poll for completion, and verify the write was succussful.

Parameters:
IN] | MailboxType,
IN] | MailboxCommand,
IN] | MailboxData,
OUT] | *MailboxStatus
Return values:
EFI_STATUS
EFI_STATUS PollMailboxReady ( IN UINT32 MailboxType )

Poll the run/busy bit of the mailbox until available or timeout expires.

Parameters:
IN] MailboxType,
Return values:
EFI_STATUS
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2013 SharkBay Processor Reference Code API: CpuPlatformLib.h Source File

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CpuPlatformLib.h
Go to the documentation of this file.
00001
00019 #ifndef _CPU_PLATFORM_LIB_H_
00020 #define _CPU_PLATFORM_LIB_H_
00021
00027 CPU_FAMILY
00028 EFIAPI
00029 GetCpuFamily (
00030   VOID
00031   );
00032
00038 CPU_STEPPING
00039 EFIAPI
00040 GetCpuStepping (
00041   VOID
00042   );
00043
00050 BOOLEAN
00051 IsCpuSupported (
00052   VOID
00053   );
00054
00060 UINT8
00061 EFIAPI
00062 GetCpuSku (
00063   VOID
00064   );
00065
00066 //
00067 //  Mailbox Related Definitions
00068 //
00069 #define MAILBOX_TYPE_PCODE              0x00000001
00070 #define MAILBOX_TYPE_OC                 0x00000002
00071 #define PCODE_MAILBOX_INTERFACE_OFFSET  0x5DA4
00072 #define PCODE_MAILBOX_DATA_OFFSET       0x5DA0
00073 #define OC_MAILBOX_MSR                  0x00000150
00074 #define MCHBAR_OFFSET                   0x48
00075
00076 //
00077 // Mailbox commands
00078 //
00079 #define READ_ICC_MAX_CMD                  0x80002A03
00080 #define SAMPLE_TSC_24AND100_CMD           0x80000009
00081 #define READ_TSC24_LOWER_CMD              0x80000109
00082 #define READ_TSC24_UPPER_CMD              0x80000209
00083 #define READ_TSC100_LOWER_CMD             0x80000309
00084 #define READ_TSC100_UPPER_CMD             0x80000409
00085 #define READ_PCODE_CALIBRATED_CMD         0x80000509
00086 #define WRITE_CONVERTION_RATIO_CMD        0x80000609
00087 #define WRITE_PREVENT_BCLKOFF_CMD         0x80000709
00088 #define WRITE_MEASURE_INTERVAL_CMD        0x80000809
00089 #define WRITE_FSM_MEASURE_INTVL_CMD       0x80000909
00090 #define START_CAL_VALUE                   0x85000000
00091 #define READ_PL1_DUTY_CYCLE_CLAMP_ENABLE  0x00000015
00092 #define WRITE_PL1_DUTY_CYCLE_CLAMP_ENABLE 0x00000016
00093 #define READ_DDR_FORCE_2X_REFRESH         0x00000017
00094 #define WRITE_DDR_FORCE_2X_REFRESH        0x00000018
00095
00096 #ifndef MAILBOX_WAIT_TIMEOUT
00097 #define MAILBOX_WAIT_TIMEOUT  1000  ///< 1 millisecond
00098 #endif
00099 #ifndef MAILBOX_WAIT_STALL
00100 #define MAILBOX_WAIT_STALL    1     ///< 1 microsecond
00101 #endif
00102 #ifndef MAILBOX_READ_TIMEOUT
00103 #define MAILBOX_READ_TIMEOUT  10    ///< 10 microseconds
00104 #endif
00105
00106 //
00107 //  OC Mailbox Structures
00108 //
00109 typedef union _OC_MAILBOX_INTERFACE {
00110   UINT32 InterfaceData;
00111   struct {
00112     UINT8 CommandCompletion : 8;
00113     UINT8 Param1            : 8;
00114     UINT8 Param2            : 8;
00115     UINT8 Reserved          : 7;
00116     UINT8 RunBusy           : 1;
00117   } Fields;
00118 } OC_MAILBOX_INTERFACE;
00119
00120 typedef struct _OC_MAILBOX_FULL {
00121   UINT32               Data;
00122   OC_MAILBOX_INTERFACE Interface;
00123 } OC_MAILBOX_FULL;
00124
00125 //
00126 //  OC Mailbox completion codes
00127 //
00128 #define OC_MAILBOX_CC_SUCCESS              0
00129 #define OC_MAILBOX_CC_OC_LOCKED            1
00130 #define OC_MAILBOX_CC_INVALID_DOMAIN       2
00131 #define OC_MAILBOX_CC_MAX_RATIO_EXCEEDED   3
00132 #define OC_MAILBOX_CC_MAX_VOLTAGE_EXCEEDED 4
00133 #define OC_MAILBOX_CC_OC_NOT_SUPPORTED     5
00134
00135 //
00136 //  PCODE Mailbox Structures
00137 //
00138 typedef union _PCODE_MAILBOX_INTERFACE {
00139   UINT32 InterfaceData;
00140   struct {
00141     UINT32 Command  : 8;
00142     UINT32 Address  : 21;
00143     UINT32 Reserved : 2;
00144     UINT32 RunBusy  : 1;
00145   } Fields;
00146 } PCODE_MAILBOX_INTERFACE;
00147
00148 typedef struct _PCODE_MAILBOX_FULL {
00149   PCODE_MAILBOX_INTERFACE Interface;
00150   UINT32                  Data;
00151 } PCODE_MAILBOX_FULL;
00152
00153 //
00154 //  Pcode Mailbox completion codes
00155 //
00156 #define PCODE_MAILBOX_CC_SUCCESS              0
00157 #define PCODE_MAILBOX_CC_ILLEGAL_CMD          1
00158 #define PCODE_MAILBOX_CC_TIMEOUT              2
00159 #define PCODE_MAILBOX_CC_ILLEGAL_DATA         3
00160 #define PCODE_MAILBOX_CC_RESERVED             4
00161 #define PCODE_MAILBOX_CC_ILLEGAL_VR_ID        5
00162 #define PCODE_MAILBOX_CC_VR_INTERFACE_LOCKED  6
00163 #define PCODE_MAILBOX_CC_VR_ERROR             7
00164
00165 #define READ_PCH_POWER_LEVELS_CMD             0x8000000A
00166 #define READ_EXT_PCH_POWER_LEVELS_CMD         0x8000000B
00167
00168 EFI_STATUS
00169 EFIAPI MailboxWrite (
00170   IN UINT32  MailboxType,
00171   IN UINT32  MailboxCommand,
00172   IN UINT32  MailboxData,
00173   OUT UINT32 *MailboxStatus
00174   )
00187 ;
00188
00189 EFI_STATUS
00190 EFIAPI MailboxRead (
00191   IN UINT32  MailboxType,
00192   IN UINT32  MailboxCommand,
00193   OUT UINT32 *MailboxDataPtr,
00194   OUT UINT32 *MailboxStatus
00195   )
00207 ;
00208
00209 EFI_STATUS
00210 EFIAPI PollMailboxReady (
00211   IN UINT32 MailboxType
00212   )
00220 ;
00221 #endif
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2013 SharkBay Processor Reference Code API: CpuPlatformLibrary.h File Reference

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CpuPlatformLibrary.h File Reference

Header file for Cpu Platform Lib implementation. More...

#include "EdkIIGlueBase.h"
#include "EdkIIGluePeim.h"
#include "CpuAccess.h"
#include "CpuPlatformLib.h"
#include "PchAccess.h"
#include "PchPlatformLib.h"
Include dependency graph for CpuPlatformLibrary.h:

Go to the source code of this file.

Detailed Description

Header file for Cpu Platform Lib implementation.

Copyright:
Copyright (c) 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement

Definition in file CpuPlatformLibrary.h.

Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: CpuPlatformLibrary.h Source File

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CpuPlatformLibrary.h
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00001
00019 #ifndef _CPU_PLATFORM_LIBRARY_IMPLEMENTATION_H_
00020 #define _CPU_PLATFORM_LIBRARY_IMPLEMENTATION_H_
00021
00022 #if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
00023 #include "EdkIIGlueBase.h"
00024 #include "EdkIIGluePeim.h"
00025 #include "CpuAccess.h"
00026 #include "CpuPlatformLib.h"
00027 #include "PchAccess.h"
00028 #include "PchPlatformLib.h"
00029 #endif
00030
00031 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: CpuPlatformPolicy.h File Reference

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CpuPlatformPolicy.h File Reference

CPU policy PPI produced by a platform driver specifying various expected CPU settings. More...

#include "PfatDefinitions.h"
Include dependency graph for Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h:

Go to the source code of this file.

Classes

struct | CPU_CONFIG_PPI
General CPU features configration for all processor features enabling / configuration bit definitions are in this field. More...
struct | POWER_MGMT_CONFIG_PPI
Power management Configuration for all Processor Power Management Features Configs are in this field. More...
struct | PFAT_CONFIG
PFAT Configuration for all processor security features configuration structures are in this field. More...
struct | TXT_CONFIG
struct | BOOT_GUARD_CONFIG
struct | SECURITY_CONFIG_PPI
Security Configuration. More...
struct | OVERCLOCKING_CONFIG_PPI
Overclocking Configuration controls which use the CPU overclocking mailbox interface are defined in this structure. More...
struct | _PEI_CPU_PLATFORM_POLICY_PPI
CPU Platform Policy PPI definition, this PPI provides interface to configure the processor. More...

Defines

#define | PEI_CPU_PLATFORM_POLICY_PPI_GUID
#define | CPU_FEATURE_ENABLE 1
#define | CPU_FEATURE_DISABLE 0
#define | PEI_CPU_PLATFORM_POLICY_PPI_REVISION_1 1
PPI revision number Any backwards compatible changes to this PPI will result in an update in the revision number Major changes will require publication of a new PPI.
#define | PEI_CPU_PLATFORM_POLICY_PPI_REVISION_2 2
*Revision 2: Added policies for PFAT-BIOS-EC Interface to PFAT_CONFIG Added PfatLog to PFAT_CONFIG
#define | PEI_CPU_PLATFORM_POLICY_PPI_REVISION_3 3
*Revision 3: Added VR_MISC MSR configuration policies POWER_MGMT_CONFIG.VrMiscMinVid; POWER_MGMT_CONFIG.VrMiscIdleExitRampRate; POWER_MGMT_CONFIG.VrMiscIdleEntryRampRate; POWER_MGMT_CONFIG.VrMiscIdleEntryDecayEnable; POWER_MGMT_CONFIG.VrMiscSlowSlewRateConfig; Added VR_MISC2 MSR configuration policies POWER_MGMT_CONFIG.VrMisc2FastRampVoltage; POWER_MGMT_CONFIG.VrMisc2MinC8Voltage; Extended POWER_MGMT_CONFIG.BootInLfm settings from 0(HFM)/ 1(LFM) to 0(HFM)/ 1(LFM)/ 2(TURBO)
#define | PEI_CPU_PLATFORM_POLICY_PPI_REVISION_4 4
*Revision 4: Added VR_MISC MSR configuration policies POWER_MGMT_CONFIG.VrMiscIoutSlope; POWER_MGMT_CONFIG.VrMiscIoutOffsetSign; POWER_MGMT_CONFIG.VrMiscIoutOffset;
#define | PEI_CPU_PLATFORM_POLICY_PPI_REVISION_5 5
*Revision 5: Added POWER_MGMT_CONFIG_PPI policies POWER_MGMT_CONFIG_PPI.VrPSI4enable; POWER_MGMT_CONFIG_PPI.Psi1Threshold; POWER_MGMT_CONFIG_PPI.Psi2Threshold; POWER_MGMT_CONFIG_PPI.Psi3Threshold;
#define | PEI_CPU_PLATFORM_POLICY_PPI_REVISION_6 6
*Revision 6: Added POWER_MGMT_CONFIG_PPI Fivr polcies POWER_MGMT_CONFIG_PPI.FivrSscEnable POWER_MGMT_CONFIG_PPI.FivrSscPercent
#define | PEI_CPU_PLATFORM_POLICY_PPI_REVISION_7 7
*Revision 7: Added CpuPlatformPpiPtr BOOT_GUARD_CONFIG.BootGuardSupport BOOT_GUARD_CONFIG.DisconnectAllTpms
#define | PEI_CPU_PLATFORM_POLICY_PPI_REVISION_8 8
*Revision 8: Added BOOT_GUARD_CONFIG configuration policies BOOT_GUARD_CONFIG.ByPassTpmEventLog
#define | TXT_SINIT_MEMORY_SIZE 0x20000
#define | TXT_HEAP_MEMORY_SIZE 0xE0000
#define | TXT_DPR_MEMORY_SIZE 0x400000
#define | TXT_DEVICE_MEMORY_SIZE (TXT_SINIT_MEMORY_SIZE + TXT_HEAP_MEMORY_SIZE)
#define | TXT_LCP_PD_BASE 0x0
Platform default LCP.
#define | TXT_LCP_PD_SIZE 0x0
Platform default LCP.
#define | TXT_TGA_MEMORY_SIZE 0x0
Maximum 512K of TGA memory (aperture)
#define | TXT_TGTT_MEMORY_SIZE 0x80000
512K of TGTT memory
#define | TXT_TGR_MEMORY_SIZE 0x80000
512K of TGR memory (Registers)
#define | TXT_TOTAL_STOLEN_MEMORY_SIZE (TXT_DPR_MEMORY_SIZE)

Typedefs

typedef struct
_PEI_CPU_PLATFORM_POLICY_PPI 		PEI_CPU_PLATFORM_POLICY_PPI

Enumerations

enum | TPM_TYPE

Variables

EFI_GUID | gPeiCpuPlatformPolicyPpiGuid

Detailed Description

CPU policy PPI produced by a platform driver specifying various expected CPU settings.

This PPI is consumed by CPU PEI modules.

Copyright:
Copyright (c) 2009 - 2013 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement

Definition in file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

Define Documentation

#define PEI_CPU_PLATFORM_POLICY_PPI_GUID
Value:
{ \
    0xf8d5438e, 0x26e1, 0x481d, 0xb6, 0x3c, 0x30, 0xd6, 0xef, 0xf4, 0xa4, 0x20 \
  }

Definition at line 32 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

#define PEI_CPU_PLATFORM_POLICY_PPI_REVISION_1 1

PPI revision number Any backwards compatible changes to this PPI will result in an update in the revision number Major changes will require publication of a new PPI.

*Revision 1: Original version

Definition at line 65 of file Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h.

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2013 SharkBay Processor Reference Code API: CpuPlatformPolicy.h Source File

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00001
00020 #ifndef CPU_PLATFORM_POLICY_H_
00021 #define CPU_PLATFORM_POLICY_H_
00022
00023 #include "PfatDefinitions.h"
00024
00025 //
00026 // CPU policy provided by platform for PEI phase
00027 //
00028 //
00029 // EDK and EDKII have different GUID formats
00030 //
00031 #if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
00032 #define PEI_CPU_PLATFORM_POLICY_PPI_GUID \
00033   { \
00034     0xf8d5438e, 0x26e1, 0x481d, 0xb6, 0x3c, 0x30, 0xd6, 0xef, 0xf4, 0xa4, 0x20 \
00035   }
00036 #else
00037 #define PEI_CPU_PLATFORM_POLICY_PPI_GUID \
00038   { \
00039     0xf8d5438e, 0x26e1, 0x481d, \
00040     { \
00041       0xb6, 0x3c, 0x30, 0xd6, 0xef, 0xf4, 0xa4, 0x20 \
00042     } \
00043   }
00044 #endif
00045
00046 extern EFI_GUID gPeiCpuPlatformPolicyPpiGuid;
00047
00048 //
00049 // Forward reference for ANSI C compatibility
00050 //
00051 typedef struct _PEI_CPU_PLATFORM_POLICY_PPI PEI_CPU_PLATFORM_POLICY_PPI;
00052
00053 #define CPU_FEATURE_ENABLE  1
00054 #define CPU_FEATURE_DISABLE 0
00055
00061
00065 #define PEI_CPU_PLATFORM_POLICY_PPI_REVISION_1  1
00066
00067
00068
00069 #define PEI_CPU_PLATFORM_POLICY_PPI_REVISION_2  2
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082 #define PEI_CPU_PLATFORM_POLICY_PPI_REVISION_3  3
00083
00084
00085
00086
00087
00088
00089 #define PEI_CPU_PLATFORM_POLICY_PPI_REVISION_4  4
00090
00091
00092
00093
00094
00095
00096
00097 #define PEI_CPU_PLATFORM_POLICY_PPI_REVISION_5  5
00098
00099
00100
00101
00102
00103 #define PEI_CPU_PLATFORM_POLICY_PPI_REVISION_6  6
00104
00105
00106
00107
00108
00109 #define PEI_CPU_PLATFORM_POLICY_PPI_REVISION_7  7
00110
00111
00112
00113
00114 #define PEI_CPU_PLATFORM_POLICY_PPI_REVISION_8  8
00115
00120 typedef struct {
00121   //
00122   // Byte 0, bit definition for functionality enable/disable
00123   //
00124   UINT8 BistOnReset           : 1;
00125   UINT8 HyperThreading        : 1;
00126   UINT8 CpuRatioOverride      : 1;
00127   UINT8 VmxEnable             : 1;
00128   UINT8 Pfat                  : 1;
00129   UINT8 MlcStreamerPrefetcher : 1;
00130   UINT8 MlcSpatialPrefetcher  : 1;
00131   UINT8 Txt                   : 1;
00132
00133   //
00134   // Byte 1, bit definition for functionality enable/disable
00135   //
00136   UINT8 Rsvdbyte : 8;
00137   //
00138   // Generic CPU feature configuration
00139   //
00140   UINT8 ActiveCoreCount;
00141   UINT8 CpuRatio;
00142   UINT8 CpuMaxNonTurboRatio;
00143 } CPU_CONFIG_PPI;
00144
00149 typedef struct {
00150   UINT8  BootInLfm;
00151
00152
00153
00154
00155   UINT8  TccActivationOffset;
00161   UINT16 VrCurrentLimit;
00162   UINT8  VrCurrentLimitLock;
00163   UINT8  Xe;
00164
00165
00166
00167
00168
00169
00170
00171
00172
00173
00174
00175   UINT8  RatioLimit[4];
00176   UINT8  VrMiscMinVid;
00177   UINT8  VrMiscIdleExitRampRate;
00178   UINT8  VrMiscIdleEntryRampRate;
00179   UINT8  VrMiscIdleEntryDecayEnable;
00180   UINT8  VrMiscSlowSlewRateConfig;
00181   UINT8  VrMisc2FastRampVoltage;
00182   UINT8  VrMisc2MinC8Voltage;
00183   UINT16 VrMiscIoutSlope;
00184   UINT8  VrMiscIoutOffsetSign;
00185   UINT16 VrMiscIoutOffset;
00186   UINT8  VrPSI4enable;
00187   UINT8  Psi1Threshold;
00188   UINT8  Psi2Threshold;
00189   UINT8  Psi3Threshold;
00190   UINT8  FivrSscEnable;
00191   UINT8  FivrSscPercent;
00192 } POWER_MGMT_CONFIG_PPI;
00193
00198 typedef struct {
00202   PUP_HEADER PupHeader;
00206   PPDT       Ppdt;
00207   UINT64     PpdtHash[4];
00208   UINT8      NumSpiComponents;
00209   UINT8      ComponentSize[MAX_SPI_COMPONENTS];
00210   UINT8      PfatMemSize;
00211   UINT8      EcCmdDiscovery;
00212   UINT8      EcCmdProvisionEav;
00213   UINT8      EcCmdLock;
00214   PFAT_LOG   PfatLog;
00215 } PFAT_CONFIG;
00216
00217 //
00218 // TxT Configuraion Policy
00219 //
00220 #define TXT_SINIT_MEMORY_SIZE         0x20000
00221 #define TXT_HEAP_MEMORY_SIZE          0xE0000
00222 #define TXT_DPR_MEMORY_SIZE           0x400000
00223 #define TXT_DEVICE_MEMORY_SIZE        (TXT_SINIT_MEMORY_SIZE + TXT_HEAP_MEMORY_SIZE)
00224
00225 #define TXT_LCP_PD_BASE               0x0     ///< Platform default LCP
00226 #define TXT_LCP_PD_SIZE               0x0     ///< Platform default LCP
00227 #define TXT_TGA_MEMORY_SIZE           0x0     ///< Maximum 512K of TGA memory (aperture)
00228 #define TXT_TGTT_MEMORY_SIZE          0x80000 ///< 512K of TGTT memory
00229 #define TXT_TGR_MEMORY_SIZE           0x80000 ///< 512K of TGR memory (Registers)
00230 #define TXT_TOTAL_STOLEN_MEMORY_SIZE  (TXT_DPR_MEMORY_SIZE)
00231
00232 typedef struct {
00233   UINT64               SinitMemorySize;
00234   UINT64               TxtHeapMemorySize;
00235   EFI_PHYSICAL_ADDRESS TxtDprMemoryBase;
00236   UINT64               TxtDprMemorySize;
00237
00238
00239
00240
00241   EFI_PHYSICAL_ADDRESS BiosAcmBase;
00242   UINT64               BiosAcmSize;
00243
00244
00245
00246
00247   EFI_PHYSICAL_ADDRESS McuUpdateDataAddr;
00251   UINT64               TgaSize;
00255   EFI_PHYSICAL_ADDRESS TxtLcpPdBase;
00259   UINT64               TxtLcpPdSize;
00260 } TXT_CONFIG;
00261
00262 //
00263 // Boot Guard Configuration
00264 //
00265 typedef enum {
00266   TpmNone = 0,
00267   dTpm12,
00268   dTpm20,
00269   Ptt,
00270   TpmTypeMax
00271 } TPM_TYPE;
00272
00273 typedef struct {
00274   BOOLEAN               MeasuredBoot;
00275   BOOLEAN               BypassTpmInit;
00276   TPM_TYPE              TpmType;
00277   BOOLEAN               BootGuardSupport;
00278   BOOLEAN               DisconnectAllTpms;
00279   BOOLEAN               ByPassTpmEventLog;
00280 } BOOT_GUARD_CONFIG;
00281
00285 typedef struct {
00286   PFAT_CONFIG        *PfatConfig;
00287   TXT_CONFIG         *TxtConfig;
00288   BOOT_GUARD_CONFIG  *BootGuardConfig;
00289 } SECURITY_CONFIG_PPI;
00290
00295 typedef struct {
00296   INT16  CoreVoltageOffset;
00297
00298
00299
00300   UINT16 CoreVoltageOverride;
00304   UINT16 CoreExtraTurboVoltage;
00308   UINT16 CoreMaxOcTurboRatio;
00309   INT16  ClrVoltageOffset;
00310   UINT16 ClrVoltageOverride;
00311   UINT16 ClrExtraTurboVoltage;
00312
00313
00314
00315   UINT16 ClrMaxOcTurboRatio;
00316   UINT16 SvidVoltageOverride;
00317   UINT8  SvidEnable           : 1;
00318   UINT8  FivrFaultsEnable     : 1;
00319   UINT8  FivrEfficiencyEnable : 1;
00320   UINT8  CoreVoltageMode      : 1;
00321   UINT8  ClrVoltageMode       : 1;
00322   UINT8  OcSupport            : 1;
00323   UINT8  BitReserved          : 2;
00324 } OVERCLOCKING_CONFIG_PPI;
00325
00331 struct _PEI_CPU_PLATFORM_POLICY_PPI {
00335   UINT8                   Revision;
00339   CPU_CONFIG_PPI          *CpuConfig;
00343   POWER_MGMT_CONFIG_PPI   *PowerMgmtConfig;
00347   SECURITY_CONFIG_PPI     *SecurityConfig;
00351   OVERCLOCKING_CONFIG_PPI *OverclockingConfig;
00355   UINTN                  CpuPlatformPpiPtr;
00356 };
00357
00358 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: CpuPlatformPolicy.h File Reference

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CpuPlatformPolicy.h File Reference

Protocol used for specifying platform related CPU information and policy setting. More...

#include "CpuPmConfig.h"
#include <EFI_PROTOCOL_DEFINITION (MpService)>
#include <EFI_GUID_DEFINITION (DataHubRecords)>
#include <EFI_PROTOCOL_DEFINITION (Hii)>
Include dependency graph for Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h:

Go to the source code of this file.

Classes

struct | CPU_PHYSICAL_LOCATION
struct | EFI_DETAILED_CPU_INFO
struct | PLATFORM_CPU_INFORMATION
Platform Specific Processor Information. More...
struct | CPU_CONFIG
General CPU feature Configuration for all processor features enabling bit definitions are in this field. More...
struct | TXT_FUNCTION_CONFIG
TxT Platform Configuration. More...
struct | SECURITY_CONFIG
All processor security features enabling definitions are in this field. More...
struct | _DXE_CPU_PLATFORM_POLICY_PROTOCOL
The CPU platform policy protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure the processor. More...

Defines

#define | DXE_CPU_PLATFORM_POLICY_PROTOCOL_GUID
#define | DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_1 1
Protocol revision number Any backwards compatible changes to this protocol will result in an update in the revision number Major changes will require publication of a new protocol.
#define | DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_2 2
Revision 2: Added CPU_CONFIG.DebugInterfaceEnable Added CPU_CONFIG.DebugInterfaceLockEnable.
#define | DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_3 3
Revision 3: Added CPU_CONFIG.ApIdleManner Added CPU_CONFIG.ApHandoffManner.
#define | DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_4 4
Revision 4: Added POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControl.
#define | DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_5 5
Revision 5: Added POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3 POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3Time POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3DutyCycle POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3Lock.
#define | DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_6 6
Revision 6: Added POWER_MGMT_CONFIG.CustomPowerUnit .Support for user to configuration custom Power Limts in milli watts Default Power Unit for follwing Items changes to MilliWatts POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS PowerLimit1 PowerLimit2 PowerLimit3 POWER_MGMT_CONFIG.PPM_CUSTOM_CTDP CustomPowerLimit1 CustomPowerLimit2.
#define | DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_7 7
Revision 7: Added POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControlFloor.
#define | CPU_CAUSE_NOT_DISABLED 0x0000
The reason for changing the state of the processor Only applies to Disabling processors.
#define | CPU_CAUSE_INTERNAL_ERROR 0x0001
#define | CPU_CAUSE_THERMAL_ERROR 0x0002
#define | CPU_CAUSE_SELFTEST_FAILURE 0x0004
#define | CPU_CAUSE_PREBOOT_TIMEOUT 0x0008
#define | CPU_CAUSE_FAILED_TO_START 0x0010
#define | CPU_CAUSE_CONFIG_ERROR 0x0020
#define | CPU_CAUSE_USER_SELECTION 0x0080
#define | CPU_CAUSE_BY_ASSOCIATION 0x0100
#define | CPU_CAUSE_UNSPECIFIED 0x8000
#define | CPU_FEATURE_ENABLE 1
#define | CPU_FEATURE_DISABLE 0
#define | DTS_OUT_OF_SPEC_ONLY 2
#define | DTS_OUT_OF_SPEC_OCCURRED 3

Typedefs

typedef struct
_DXE_CPU_PLATFORM_POLICY_PROTOCOL 		DXE_CPU_PLATFORM_POLICY_PROTOCOL
The CPU platform policy protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure the processor.
typedef EFI_STATUS(* | PLATFORM_CPU_RETRIEVE_MICROCODE )(IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This, OUT UINT8 **MicrocodeData)
This function is for platform code to provide Microcode location since different BIOS has different flash layout.
typedef UINT32 | CPU_STATE_CHANGE_CAUSE
typedef EFI_STATUS(* | PLATFORM_CPU_GET_MAX_COUNT )(IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This, OUT UINT32 *MaxThreadsPerCore, OUT UINT32 *MaxCoresPerDie, OUT UINT32 *MaxDiesPerPackage, OUT UINT32 *MaxPackages)
This interface is for platform to provide processor support layout, such as how many packages we want processor code to support.
typedef EFI_STATUS(* | PLATFORM_CPU_GET_CPU_INFO )(IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This, IN CPU_PHYSICAL_LOCATION *Location, IN OUT PLATFORM_CPU_INFORMATION *PlatformCpuInfo)
Platform code can provide platform specific processor information, such as processor socket Name on board, processor Socket Type, and so on for SMBIOS table creation.

Enumerations

enum | CPU_PLATFORM_CATEGORY
The platform category, Server, Desktop and Mobile are defined.

Functions

EFI_FORWARD_DECLARATION (DXE_CPU_PLATFORM_POLICY_PROTOCOL_GUID)

Variables

EFI_GUID | gDxeCpuPlatformPolicyProtocolGuid

Detailed Description

Protocol used for specifying platform related CPU information and policy setting.

Copyright:
Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

Define Documentation

#define CPU_CAUSE_NOT_DISABLED 0x0000

The reason for changing the state of the processor Only applies to Disabling processors.

In future, we can add add/remove support

Definition at line 148 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

#define DXE_CPU_PLATFORM_POLICY_PROTOCOL_GUID
Value:
{ \
    0x1279e288, 0x24cd, 0x47e9, 0x96, 0xba, 0xd7, 0xa3, 0x8c, 0x17, 0xbd, 0x64 \
  }

Definition at line 35 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_1 1

Protocol revision number Any backwards compatible changes to this protocol will result in an update in the revision number Major changes will require publication of a new protocol.

Revision 1: Initial version

Definition at line 49 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_5 5

Revision 5: Added POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3 POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3Time POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3DutyCycle POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3Lock.

SECURITY_CONFIG.BOOT_GUARD_FUNCTION_CONFIG.SkipStopPbet

Definition at line 78 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_6 6

Revision 6: Added POWER_MGMT_CONFIG.CustomPowerUnit .Support for user to configuration custom Power Limts in milli watts Default Power Unit for follwing Items changes to MilliWatts POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS PowerLimit1 PowerLimit2 PowerLimit3 POWER_MGMT_CONFIG.PPM_CUSTOM_CTDP CustomPowerLimit1 CustomPowerLimit2.

Definition at line 93 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_7 7

Revision 7: Added POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControlFloor.

Changed definition of POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControl from 1 (enable) to 1 (enable/manual) POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControlFloor

Definition at line 101 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

Typedef Documentation

typedef struct _DXE_CPU_PLATFORM_POLICY_PROTOCOL DXE_CPU_PLATFORM_POLICY_PROTOCOL

The CPU platform policy protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure the processor.

Platform code needs to provide the information for processor drivers to finish the initialization.

Definition at line 109 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

typedef EFI_STATUS( * PLATFORM_CPU_GET_MAX_COUNT)(IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This, OUT UINT32 *MaxThreadsPerCore, OUT UINT32 *MaxCoresPerDie, OUT UINT32 *MaxDiesPerPackage, OUT UINT32 *MaxPackages)

This interface is for platform to provide processor support layout, such as how many packages we want processor code to support.

If return EFI_UNSUPPORTED, processor code will assume MAXIMUM_CPU_NUMBER and allocate MAX memory for all APs.

Definition at line 196 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

typedef EFI_STATUS( * PLATFORM_CPU_RETRIEVE_MICROCODE)(IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This, OUT UINT8 **MicrocodeData)

This function is for platform code to provide Microcode location since different BIOS has different flash layout.

Platform code need to provide a function for CPU code to call to get the Microcode location in flash or memory.

Definition at line 121 of file Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h.

Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: CpuPlatformPolicy.h Source File

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CpuPlatformPolicy.h
Go to the documentation of this file.
00001
00020 #ifndef _CPU_PLATFORM_POLICY_H_
00021 #define _CPU_PLATFORM_POLICY_H_
00022
00023 #include "CpuPmConfig.h"
00024
00025 #include EFI_PROTOCOL_DEFINITION (MpService)
00026 #include EFI_GUID_DEFINITION (DataHubRecords)
00027
00028 #if (EFI_SPECIFICATION_VERSION >= 0x2000A)
00029 #include EFI_PROTOCOL_DEFINITION (HiiDatabase)
00030 #else
00031 #include EFI_PROTOCOL_DEFINITION (Hii)
00032 #endif
00033
00034 EFI_FORWARD_DECLARATION (DXE_CPU_PLATFORM_POLICY_PROTOCOL_GUID);
00035 #define DXE_CPU_PLATFORM_POLICY_PROTOCOL_GUID \
00036   { \
00037     0x1279e288, 0x24cd, 0x47e9, 0x96, 0xba, 0xd7, 0xa3, 0x8c, 0x17, 0xbd, 0x64 \
00038   }
00039
00045
00049 #define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_1 1
00050
00051
00052
00053
00054 #define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_2 2
00055
00056
00057
00058
00059 #define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_3 3
00060
00064 #define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_4 4
00065
00066
00067
00068
00069
00070 //
00071 // BootGuard:InternalOnlyBegin
00072 //
00074 //
00075 // BootGuard:InternalOnlyEnd
00076 //
00078 #define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_5 5
00079
00092
00093 #define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_6 6
00094
00100
00101 #define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_7 7
00102
00103
00104 extern EFI_GUID gDxeCpuPlatformPolicyProtocolGuid;
00105
00106 //
00107 // Forward reference for ANSI C compatibility
00108 //
00109 typedef struct _DXE_CPU_PLATFORM_POLICY_PROTOCOL DXE_CPU_PLATFORM_POLICY_PROTOCOL;
00110
00111 //
00112 // Prototypes for the Platform CPU Protocol
00113 //
00114
00119 typedef
00120 EFI_STATUS
00121 (EFIAPI *PLATFORM_CPU_RETRIEVE_MICROCODE)(
00122   IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This,
00123   OUT UINT8                           **MicrocodeData
00124   );
00125
00126 typedef struct {
00127   UINT32 Package;
00128   UINT32 Die;
00129   UINT32 Core;
00130   UINT32 Thread;
00131 } CPU_PHYSICAL_LOCATION;
00132
00136 typedef enum {
00137   CpuPlatformUnknown= 0,
00138   CpuPlatformDesktop,
00139   CpuPlatformMobile,
00140   CpuPlatformServer,
00141   CpuPlatformMax
00142 } CPU_PLATFORM_CATEGORY;
00143
00148 #define CPU_CAUSE_NOT_DISABLED      0x0000
00149 #define CPU_CAUSE_INTERNAL_ERROR    0x0001
00150 #define CPU_CAUSE_THERMAL_ERROR     0x0002
00151 #define CPU_CAUSE_SELFTEST_FAILURE  0x0004
00152 #define CPU_CAUSE_PREBOOT_TIMEOUT   0x0008
00153 #define CPU_CAUSE_FAILED_TO_START   0x0010
00154 #define CPU_CAUSE_CONFIG_ERROR      0x0020
00155 #define CPU_CAUSE_USER_SELECTION    0x0080
00156 #define CPU_CAUSE_BY_ASSOCIATION    0x0100
00157 #define CPU_CAUSE_UNSPECIFIED       0x8000
00158
00159 typedef UINT32 CPU_STATE_CHANGE_CAUSE;
00160
00161 typedef struct {
00162   EFI_MP_PROC_CONTEXT                   *Context;
00163   EFI_EXP_BASE10_DATA                   CoreFreq;
00164   EFI_EXP_BASE10_DATA                   BusFreq;
00165   EFI_EXP_BASE2_DATA                    CacheSize[EFI_CACHE_LMAX];
00166   EFI_PROCESSOR_ID_DATA                 CpuId;
00167   EFI_PROCESSOR_MICROCODE_REVISION_DATA MuData;
00168   EFI_PROCESSOR_STATUS_DATA             Status;
00169 } EFI_DETAILED_CPU_INFO;
00170
00174 typedef struct {
00175   UINT64                                 ApicID;
00176   STRING_REF                             ReferenceString;
00177   EFI_PROCESSOR_SOCKET_TYPE_DATA         SocketType;
00178   EFI_PROCESSOR_SOCKET_NAME_DATA         SocketName;
00179   EFI_PROCESSOR_MAX_CORE_FREQUENCY_DATA  MaxCoreFrequency;
00180   EFI_PROCESSOR_MAX_FSB_FREQUENCY_DATA   MaxFsbFrequency;
00181   EFI_PROCESSOR_CORE_FREQUENCY_LIST_DATA PlatformCoreFrequencyList;
00182   EFI_PROCESSOR_FSB_FREQUENCY_LIST_DATA  PlatformFsbFrequencyList;
00183   STRING_REF                             AssetTag;
00184   EFI_HII_HANDLE                         StringHandle;
00185   STRING_REF                             SerialNumber;
00186   STRING_REF                             PartNumber;
00187 } PLATFORM_CPU_INFORMATION;
00188
00194 typedef
00195 EFI_STATUS
00196 (EFIAPI *PLATFORM_CPU_GET_MAX_COUNT)(
00197   IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This,
00198   OUT UINT32                          *MaxThreadsPerCore,
00199   OUT UINT32                          *MaxCoresPerDie,
00200   OUT UINT32                          *MaxDiesPerPackage,
00201   OUT UINT32                          *MaxPackages
00202   );
00203
00208 typedef
00209 EFI_STATUS
00210 (EFIAPI *PLATFORM_CPU_GET_CPU_INFO)(
00211   IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This,
00212   IN CPU_PHYSICAL_LOCATION            *Location,
00213   IN OUT PLATFORM_CPU_INFORMATION     *PlatformCpuInfo
00214   );
00215
00216 //
00217 // Generic definitions for device enabling/disabling used by CPU code
00218 //
00219 #define CPU_FEATURE_ENABLE  1
00220 #define CPU_FEATURE_DISABLE 0
00221
00222 //
00223 // Generic definitions for DTS
00224 //
00225 #define DTS_OUT_OF_SPEC_ONLY      2
00226 #define DTS_OUT_OF_SPEC_OCCURRED  3
00227
00232 typedef struct {
00233   //
00234   // Byte 0, bit definition for functionality enable/disable
00235   //
00236   UINT8 HtState                : 1;
00237   UINT8 LimitCpuidMaximumValue : 1;
00238   UINT8 DcaState               : 1;
00239   UINT8 ExecuteDisableBit      : 1;
00240   UINT8 VmxEnable              : 1;
00241   UINT8 SmxEnable              : 1;
00242   UINT8 FastString             : 1;
00243   UINT8 MachineCheckEnable     : 1;
00244   //
00245   // Byte 1, bit definition for functionality enable/disable
00246   //
00247   UINT8 MonitorMwaitEnable      : 1;
00248   UINT8 XapicEnable             : 1;
00249   UINT8 MachineCheckStatusClean : 1;
00250   UINT8 IsColdReset             : 1;
00251   UINT8 MlcStreamerPrefetcher   : 1;
00252   UINT8 MlcSpatialPrefetcher    : 1;
00253   UINT8 EnableDts               : 2;
00254   //
00255   // Byte 2, byte definition for addiional functionalities expected later
00256   //
00257   UINT8 FviReport                : 1;
00258   UINT8 AesEnable                : 1;
00259   UINT8 DebugInterfaceEnable     : 1;
00260   UINT8 DebugInterfaceLockEnable : 1;
00261   UINT8 ApIdleManner             : 2;
00262   UINT8 ApHandoffManner          : 2;
00263   //
00264   // CPU feature configuration
00265   //
00266   UINT8  BspSelection;
00267   UINT32 DcaPrefetchDelayValue;
00268   UINT8  VirtualWireMode;
00269   UINT8  SmmbaseSwSmiNumber;
00270   //
00271   // CPU Misc Config
00272   //
00273   UINT8 FviSmbiosType;
00274   //
00275   // Functions provided by platform code
00276   //
00280   PLATFORM_CPU_RETRIEVE_MICROCODE RetrieveMicrocode;
00285   PLATFORM_CPU_GET_MAX_COUNT      GetMaxCount;
00289   PLATFORM_CPU_GET_CPU_INFO       GetCpuInfo;
00290 } CPU_CONFIG;
00291
00295 typedef struct {
00296   UINT8 ResetAux : 1;
00297   UINT8 Reserved : 7;
00298   UINT8 ByetReserved[1];
00299 } TXT_FUNCTION_CONFIG;
00300
00301
00306 typedef struct {
00307   TXT_FUNCTION_CONFIG *TxtFunctionConfig;
00308 } SECURITY_CONFIG;
00309
00315 typedef struct _DXE_CPU_PLATFORM_POLICY_PROTOCOL {
00321   UINT8             Revision;
00325   CPU_CONFIG        *CpuConfig;
00329   POWER_MGMT_CONFIG *PowerMgmtConfig;
00333   SECURITY_CONFIG   *SecurityConfig;
00334 } DXE_CPU_PLATFORM_POLICY_PROTOCOL;
00335
00336 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: CpuPmConfig.h File Reference

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Classes | Defines | Typedefs | Enumerations
CpuPmConfig.h File Reference

Describes the defintions / functions visible to the rest of the PPM. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PPM_CUSTOM_RATIO_TABLE
This structure is used to describe the custom processor ratio table desired by the platform. More...
struct | PPM_FUNCTION_ENABLES
This structure is used to describe which of the PPM functions will be enabled by PPM implementation. More...
struct | _PPM_TURBO_SETTINGS
This structure is used to describe various PPM turbo settings. More...
struct | _PPM_CUSTOM_CTDP_TABLE
PPM Custom ConfigTdp Settings. More...
struct | _PPM_CUSTOM_CTDP
This structure is used to configure custom ConfigTdp level settings. More...
struct | _PPM_LOCK_ENABLES
This structure is used to control enabled / disabled various PPM MSR lock settings. More...
struct | PL1_THERMAL_CONTROL_FLOOR
struct | THERM_FUNCTION_ENABLES
This structure is used to describe which of the Thermal functions will be enabled by Thermal implementation. More...
struct | POWER_MGMT_CONFIG
Power management Configuration for all processor Power Management features enabling definitions are in this field. More...

Defines

#define | MAX_CUSTOM_RATIO_TABLE_ENTRIES 16
Define maximum number of custom ratio states supported.
#define | MAX_CUSTOM_CTDP_ENTRIES 3
Define maximum number of custom ConfigTdp entries supported.

Typedefs

typedef struct _PPM_TURBO_SETTINGS | PPM_TURBO_SETTINGS
This structure is used to describe various PPM turbo settings.
typedef struct
_PPM_CUSTOM_CTDP_TABLE 		PPM_CUSTOM_CTDP_TABLE
PPM Custom ConfigTdp Settings.
typedef struct _PPM_CUSTOM_CTDP | PPM_CUSTOM_CTDP
This structure is used to configure custom ConfigTdp level settings.
typedef struct _PPM_LOCK_ENABLES | PPM_LOCK_ENABLES
This structure is used to control enabled / disabled various PPM MSR lock settings.

Enumerations

enum | DEEP_C_STATE
PM Deep C State Limit.
enum | MAX_PKG_C_STATE
PPM Package C State Limit.
enum | C_STATE_TIME_UNIT
PPM Package C State Time Limit.
enum | CUSTOM_POWER_UNIT
Custom Power Uints.User can choose to enter in MilliWatts or Watts. More...
enum | PL1_THERMAL_THROTTLE_FLOOR_UNIT

Detailed Description

Describes the defintions / functions visible to the rest of the PPM.

Copyright:
Copyright (c) 2011 - 2013 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file CpuPmConfig.h.

Enumeration Type Documentation

enum CUSTOM_POWER_UNIT

Custom Power Uints.User can choose to enter in MilliWatts or Watts.

Enumerator:
PowerUnitWatts

in Watts

PowerUnit125MilliWatts

in 125 Milli Watts. Example 11.250 W Value to use for Power limts 90

Definition at line 195 of file CpuPmConfig.h.

Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: CpuPmConfig.h Source File

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CpuPmConfig.h
Go to the documentation of this file.
00001
00021 #ifndef _CPU_PM_CONFIG_H_
00022 #define _CPU_PM_CONFIG_H_
00023
00027 #define MAX_CUSTOM_RATIO_TABLE_ENTRIES  16
00028
00032 #define MAX_CUSTOM_CTDP_ENTRIES 3
00033
00037 typedef struct {
00041   UINT8  NumberOfEntries;
00042   UINT32 Cpuid;
00043   UINT16 MaxRatio;
00044   UINT16 StateRatio[MAX_CUSTOM_RATIO_TABLE_ENTRIES];
00045 } PPM_CUSTOM_RATIO_TABLE;
00046
00050 typedef struct {
00051   UINT32 Eist                  : 1;
00052   UINT32 Cx                    : 1;
00053   UINT32 C1e                   : 1;
00054   UINT32 C3                    : 1;
00055   UINT32 C6                    : 1;
00056   UINT32 DeepCState            : 3;
00057   UINT32 LongLatencyC6         : 1;
00058   UINT32 LongLatencyC7         : 1;
00059   UINT32 C8                    : 1;
00060   UINT32 C9                    : 1;
00061   UINT32 C10                   : 1;
00062   UINT32 C1AutoDemotion        : 1;
00063   UINT32 C3AutoDemotion        : 1;
00064   UINT32 TurboMode             : 1;
00065   UINT32 PowerLimit2           : 1;
00066   UINT32 EnergyEfficientPState : 1;
00067   UINT32 BiProcHot             : 1;
00068   UINT32 TStates               : 1;
00069   UINT32 Xe                    : 1;
00070   UINT32 C1UnDemotion          : 1;
00071   UINT32 C3UnDemotion          : 1;
00072   UINT32 PkgCStateDemotion     : 1;
00073   UINT32 PkgCStateUnDemotion   : 1;
00074   UINT32 DisableProcHotOut     : 1;
00075   UINT32 DisableVRThermalAlert : 1;
00076   UINT32 ProcHotResponce       : 1;
00077   UINT32 AutoThermalReporting  : 1;
00078   UINT32 CStatePreWake         : 1;
00079   UINT32 ThermalMonitor        : 1;
00080   UINT32 LakeTiny              : 1;
00081   UINT32 TimedMwait            : 1;
00082   UINT32 Reserved              : 2;
00083 } PPM_FUNCTION_ENABLES;
00084
00088 typedef struct _PPM_TURBO_SETTINGS {
00089   UINT16 PowerLimit1;
00090   UINT32 PowerLimit1Time;
00091   UINT16 PowerLimit2;
00092
00093
00094
00095   UINT8  TurboPowerLimitLock;
00096   UINT16 DdrPowerLimit1;
00097   UINT32 DdrPowerLimit1Time;
00098   UINT16 DdrPowerLimit2;
00099   UINT8  DdrPowerLimitLock;
00100
00101
00102
00103
00104   UINT8  ConfigTdpLevel;
00108   UINT8  ConfigTdpLock;
00109   UINT8  ConfigTdpBios;
00110   UINT8  EnergyPolicy;
00111
00112   //
00113   // PL3 configuration
00114   //
00115   UINT16 PowerLimit3;
00116   UINT32 PowerLimit3Time;
00117   UINT8  PowerLimit3DutyCycle;
00118   UINT8  PowerLimit3Lock;
00119
00120 } PPM_TURBO_SETTINGS;
00121
00125 typedef struct _PPM_CUSTOM_CTDP_TABLE {
00126   UINT16 CustomPowerLimit1;
00127   UINT16 CustomPowerLimit2;
00128   UINT8  CustomPowerLimit1Time;
00129   UINT8  CustomTurboActivationRatio;
00130   UINT8  CustomConfigTdpControl;
00131 } PPM_CUSTOM_CTDP_TABLE;
00132
00136 typedef struct _PPM_CUSTOM_CTDP {
00137   UINT8                 ConfigTdpCustom;
00138   UINT8                 CustomTdpCount;
00139   UINT8                 CustomBootModeIndex;
00140
00141
00142
00143
00144   PPM_CUSTOM_CTDP_TABLE CustomConfigTdpTable[MAX_CUSTOM_CTDP_ENTRIES];
00145 } PPM_CUSTOM_CTDP;
00146
00150 typedef struct _PPM_LOCK_ENABLES {
00151   UINT32 PmgCstCfgCtrlLock : 1;
00152   UINT32 OverclockingLock  : 1;
00153   UINT32 ProcHotLock       : 1;
00154   UINT32 Reserved          : 29;
00155 } PPM_LOCK_ENABLES;
00159 typedef enum {
00160   Disabled                = 0,
00161   DeepC7,
00162   DeepC7S
00163 } DEEP_C_STATE;
00167 typedef enum {
00168   PkgC0C1                 = 0,
00169   PkgC2,
00170   PkgC3,
00171   PkgC6,
00172   PkgC7,
00173   PkgC7s,
00174   PkgC8,
00175   PkgC9,
00176   PkgC10,
00177   PkgCMax,
00178   PkgCpuDefault = 254,
00179   PkgAuto = 255
00180 } MAX_PKG_C_STATE;
00184 typedef enum {
00185   TimeUnit1ns             = 0,
00186   TimeUnit32ns,
00187   TimeUnit1024ns,
00188   TimeUnit32768ns,
00189   TimeUnit1048576ns,
00190   TimeUnit33554432ns
00191 } C_STATE_TIME_UNIT;
00195 typedef enum {
00196   PowerUnitWatts = 0,
00197   PowerUnit125MilliWatts,
00198   PowerUnitMax
00199 } CUSTOM_POWER_UNIT;
00200
00201 typedef enum {
00202   Percent5  = 242,
00203   Percent10 = 229,
00204   Percent15 = 217,
00205   Percent20 = 204,
00206   Percent25 = 191,
00207   Percent30 = 178,
00208   Percent35 = 166,
00209   Percent40 = 153,
00210   Percent45 = 140,
00211   Percent50 = 127,
00212   Percent55 = 115,
00213   Percent60 = 102,
00214   Percent65 = 89,
00215   Percent70 = 76,
00216   Percent75 = 64,
00217   Percent80 = 51,
00218   Percent85 = 38,
00219   Percent90 = 25,
00220   Percent95 = 13,
00221   Percent100 = 0
00222 } PL1_THERMAL_THROTTLE_FLOOR_UNIT;
00223
00224 typedef struct {
00225     PL1_THERMAL_THROTTLE_FLOOR_UNIT FloorIA;
00226     PL1_THERMAL_THROTTLE_FLOOR_UNIT FloorGT;
00227     PL1_THERMAL_THROTTLE_FLOOR_UNIT FloorPCH;
00228 } PL1_THERMAL_CONTROL_FLOOR;
00229
00233 typedef struct {
00234   UINT16 BiProcHot             : 1;
00235   UINT16 TStates               : 1;
00236   UINT16 DisableProcHotOut     : 1;
00237   UINT16 DisableVRThermalAlert : 1;
00238   UINT16 ProcHotResponce       : 1;
00239   UINT16 AutoThermalReporting  : 1;
00240   UINT16 ThermalMonitor        : 1;
00241   UINT16 Pl1ThermalControl     : 2;
00242   UINT16 ThermReserved         : 7;
00243   PL1_THERMAL_CONTROL_FLOOR Pl1ThermalControlFloor;
00244 } THERM_FUNCTION_ENABLES;
00245
00250 typedef struct {
00255   PPM_FUNCTION_ENABLES   *pFunctionEnables;
00260   PPM_CUSTOM_RATIO_TABLE *pCustomRatioTable;
00265   PPM_TURBO_SETTINGS     *pTurboSettings;
00266   UINT8                  S3RestoreMsrSwSmiNumber;
00267   UINT8                  *pRatioLimit;
00268   PPM_LOCK_ENABLES       *pPpmLockEnables;
00269   PPM_CUSTOM_CTDP        *pCustomCtdpSettings;
00270
00271
00272
00273   MAX_PKG_C_STATE        PkgCStateLimit;
00274   C_STATE_TIME_UNIT      CstateLatencyControl0TimeUnit;
00275   C_STATE_TIME_UNIT      CstateLatencyControl1TimeUnit;
00276   C_STATE_TIME_UNIT      CstateLatencyControl2TimeUnit;
00277   C_STATE_TIME_UNIT      CstateLatencyControl3TimeUnit;
00278   C_STATE_TIME_UNIT      CstateLatencyControl4TimeUnit;
00279   C_STATE_TIME_UNIT      CstateLatencyControl5TimeUnit;
00280   UINT16                 CstateLatencyControl0Irtl;
00281   UINT16                 CstateLatencyControl1Irtl;
00282   UINT16                 CstateLatencyControl2Irtl;
00283   UINT16                 CstateLatencyControl3Irtl;
00284   UINT16                 CstateLatencyControl4Irtl;
00285   UINT16                 CstateLatencyControl5Irtl;
00286   BOOLEAN                RfiFreqTunningOffsetIsNegative;
00287   UINT8                  RfiFreqTunningOffset;
00288
00289
00290
00291   UINT8                  PcodeCalibration;
00292   BOOLEAN                EnableRerunPcodeCalibration;
00293
00294
00295
00296
00297   THERM_FUNCTION_ENABLES *ThermalFuncEnables;
00298   CUSTOM_POWER_UNIT   CustomPowerUnit;
00299
00300 } POWER_MGMT_CONFIG;
00301
00302 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: CpuRegs.h File Reference

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Defines | Enumerations
CpuRegs.h File Reference

Conventions: More...

#include "CommonIncludes.h"
Include dependency graph for CpuRegs.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Defines

#define | APIC_REGISTER_LOCAL_ID_OFFSET 0x00000020
#define | APIC_REGISTER_APIC_VERSION_OFFSET 0x00000030
#define | APIC_REGISTER_SPURIOUS_VECTOR_OFFSET 0x000000F0
#define | APIC_REGISTER_ICR_LOW_OFFSET 0x00000300
#define | APIC_REGISTER_ICR_HIGH_OFFSET 0x00000310
#define | APIC_REGISTER_LINT0_VECTOR_OFFSET 0x00000350
#define | APIC_REGISTER_LINT1_VECTOR_OFFSET 0x00000360
#define | BROADCAST_MODE_SPECIFY_CPU 0x00
#define | BROADCAST_MODE_ALL_INCLUDING_SELF 0x01
#define | BROADCAST_MODE_ALL_EXCLUDING_SELF 0x02
#define | DELIVERY_MODE_FIXED 0x00
#define | DELIVERY_MODE_LOWEST_PRIORITY 0x01
#define | DELIVERY_MODE_SMI 0x02
#define | DELIVERY_MODE_REMOTE_READ 0x03
#define | DELIVERY_MODE_NMI 0x04
#define | DELIVERY_MODE_INIT 0x05
#define | DELIVERY_MODE_SIPI 0x06
#define | DELIVERY_MODE_MAX 0x07
#define | TRIGGER_MODE_EDGE 0x00
#define | TRIGGER_MODE_LEVEL 0x01
#define | CACHE_UNCACHEABLE 0
#define | CACHE_WRITECOMBINING 1
#define | CACHE_WRITETHROUGH 4
#define | CACHE_WRITEPROTECTED 5
#define | CACHE_WRITEBACK 6
#define | CPUID_SIGNATURE 0x0
#define | CPUID_VERSION_INFO 0x1
#define | CPUID_FUNCTION_4 0x4
#define | CPU_CACHE_TYPE_MASK 0x1F
#define | CPU_CACHE_LEVEL_MASK 0x07
#define | CPU_CACHE_ASSOCIATIVITY_MASK 0x03FF
#define | CPU_CACHE_PARTITION_MASK 0x03FF
#define | CPU_CACHE_LINE_SIZE_MASK 0x0FFF
#define | B_CPUID_VERSION_INFO_ECX_MWAIT BIT3
#define | B_CPUID_VERSION_INFO_ECX_VME BIT5
#define | B_CPUID_VERSION_INFO_ECX_SME BIT6
#define | B_CPUID_VERSION_INFO_ECX_EIST BIT7
#define | B_CPUID_VERSION_INFO_ECX_TM2 BIT8
#define | B_CPUID_VERSION_INFO_ECX_DCA BIT18
#define | B_CPUID_VERSION_INFO_ECX_AES BIT25
#define | B_CPUID_VERSION_INFO_ECX_XAPIC BIT21
#define | B_CPUID_VERSION_INFO_EDX_XD BIT20
#define | B_CPUID_VERSION_INFO_EDX_HT BIT28
#define | B_CPUID_VERSION_INFO_EDX_TM1 BIT29
#define | CPUID_CACHE_INFO 0x2
#define | CPUID_SERIAL_NUMBER 0x3
#define | CPUID_CACHE_PARAMS 0x4
#define | V_CPUID_CACHE_TYPE_MASK 0x1F
#define | B_CPUID_CACHE_TYPE_DATA 0x1
#define | B_CPUID_CACHE_TYPE_INSTRUCTION 0x2
#define | B_CPUID_CACHE_TYPE_UNIFIED 0x3
#define | V_CPUID_CACHE_LEVEL_MASK 0xE0
#define | B_CPUID_CACHE_LEVEL_SHIFT 5
#define | B_CPUID_CACHE_PARAMS_WAYS_SHIFT 22
#define | B_CPUID_CACHE_PARAMS_PARTITIONS_SHIFT 12
#define | CPUID_MONITOR_MWAIT_PARAMS 0x5
#define | B_CPUID_MONITOR_MWAIT_ECX_EXTENSIONS BIT0
#define | B_CPUID_MONITOR_MWAIT_EDX_CSTATE BIT0
#define | V_CPUID_MONITOR_MWAIT_EDX_ENHANCED_CSTATE 0x2
#define | CPUID_POWER_MANAGEMENT_PARAMS 0x6
#define | B_CPUID_POWER_MANAGEMENT_EAX_TURBO BIT1
#define | B_CPUID_POWER_MANAGEMENT_EAX_FINE_GRAINED_CLOCK_MODULATION BIT5
#define | B_CPUID_POWER_MANAGEMENT_ECX_ENERGY_EFFICIENT_POLICY_SUPPORT BIT3
#define | CPUID_REV7 0x7
#define | CPUID_REV8 0x8
#define | CPUID_DCA_PARAMS 0x9
#define | CPUID_REVA 0xA
#define | CPUID_CORE_TOPOLOGY 0xB
#define | CPUID_EXTENDED_FUNCTION 0x80000000
#define | CPUID_EXTENDED_CPU_SIG 0x80000001
#define | CPUID_BRAND_STRING1 0x80000002
#define | CPUID_BRAND_STRING2 0x80000003
#define | CPUID_BRAND_STRING3 0x80000004
#define | CPUID_L2_CACHE_FEATURE 0x80000006
#define | CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
#define | MSR_IA32_PLATFORM_ID 0x00000017
#define | MSR_IA32_APIC_BASE 0x0000001B
#define | B_MSR_IA32_APIC_BASE_G_XAPIC BIT11
#define | B_MSR_IA32_APIC_BASE_M_XAPIC BIT10
#define | B_MSR_IA32_APIC_BASE_BSP BIT8
#define | PIC_THREAD_CONTROL 0x0000002E
#define | B_PIC_THREAD_CONTROL_TPR_DIS BIT10
#define | MSR_CORE_THREAD_COUNT 0x00000035
#define | N_CORE_COUNT_OFFSET 16
#define | B_THREAD_COUNT_MASK 0xFFFF
#define | MSR_SOCKET_ID_MSR 0x00000039
#define | MSR_IA32_FEATURE_CONTROL 0x0000003A
#define | B_MSR_IA32_FEATURE_CONTROL_LOCK BIT0
#define | B_MSR_IA32_FEATURE_CONTROL_ELT BIT1
#define | B_MSR_IA32_FEATURE_CONTROL_EVT BIT2
#define | B_MSR_IA32_FEATURE_CONTROL_SLFE (BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT14)
#define | B_MSR_IA32_FEATURE_CONTROL_SGE BIT15
#define | MSR_IA32_SMM_SAVE_CONTROL 0x0000003E
#define | B_MSR_IA32_SMM_SAVE_CONTROL_SFPPE BIT0
#define | MSR_IA32_BIOS_UPDT_TRIG 0x00000079
#define | MSR_IA32_BIOS_SIGN_ID 0x0000008B
#define | MSR_IA32_SMM_MONITOR_CONTROL 0x0000009B
#define | MSR_IA32_PMC0_MSR 0x000000C1
#define | MSR_IA32_PMC1_MSR 0x000000C2
#define | MSR_IA32_PMC2_MSR 0x000000C3
#define | MSR_IA32_PMC3_MSR 0x000000C4
#define | MSR_IA32_PMC4_MSR 0x000000C5
#define | MSR_IA32_PMC5_MSR 0x000000C6
#define | MSR_IA32_PMC6_MSR 0x000000C7
#define | MSR_IA32_PMC7_MSR 0x000000C8
#define | MSR_PLATFORM_INFO 0x000000CE
#define | N_PLATFORM_INFO_MIN_RATIO 40
#define | B_PLATFORM_INFO_RATIO_MASK 0xFF
#define | N_PLATFORM_INFO_MAX_RATIO 8
#define | B_MSR_PLATFORM_INFO_PFAT_AVAIL BIT35
#define | N_MSR_PLATFORM_INFO_CONFIG_TDP_NUM_LEVELS_OFFSET 33
#define | V_CONFIG_TDP_NUM_LEVELS_MASK (BIT34 | BIT33)
#define | B_PLATFORM_INFO_TDC_TDP_LIMIT BIT29
#define | N_PLATFORM_INFO_RATIO_LIMIT 28
#define | B_PLATFORM_INFO_RATIO_LIMIT BIT28
#define | B_FIVR_RFI_TUNING_AVAIL BIT25
#define | B_PLATFORM_INFO_SMM_SAVE_CONTROL BIT16
#define | N_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET 30
#define | B_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET BIT30
#define | B_PLATFORM_INFO_TIMED_MWAIT_SUPPORTED BIT37
#define | MSR_PMG_CST_CONFIG 0x000000E2
#define | B_CST_CONTROL_LOCK BIT15
#define | B_IO_MWAIT_REDIRECTION_ENABLE BIT10
#define | B_TIMED_MWAIT_ENABLE BIT31
#define | B_PACKAGE_C_STATE_LIMIT (BIT3 | BIT2 | BIT1 | BIT0)
#define | V_CSTATE_LIMIT_C1 0x01
#define | V_CSTATE_LIMIT_C3 0x02
#define | V_CSTATE_LIMIT_C6 0x03
#define | V_CSTATE_LIMIT_C7 0x04
#define | V_CSTATE_LIMIT_C7S 0x05
#define | V_CSTATE_LIMIT_C8 0x06
#define | V_CSTATE_LIMIT_C9 0x07
#define | V_CSTATE_LIMIT_C10 0x08
#define | B_C3_AUTO_DEMOTION_ENABLE BIT25
#define | B_C1_AUTO_DEMOTION_ENABLE BIT26
#define | B_C3_AUTO_UNDEMOTION_ENABLE BIT27
#define | B_C1_AUTO_UNDEMOTION_ENABLE BIT28
#define | B_PKG_CSTATE_DEMOTION_ENABLE BIT29
#define | B_PKG_CSTATE_UNDEMOTION_ENABLE BIT30
#define | MSR_RFI_TUNNING 0x000000E3
#define | V_FREQ_TUNNING_MASK 0xFFFF
#define | MSR_PMG_IO_CAPTURE_BASE 0x000000E4
#define | B_MSR_PMG_CST_RANGE (BIT18 | BIT17 | BIT16)
#define | V_IO_CAPT_LVL2 (0x0 << 16)
C3.
#define | V_IO_CAPT_LVL3 (0x1 << 16)
C6.
#define | V_IO_CAPT_LVL4 (0x2 << 16)
C7.
#define | V_IO_CAPT_LVL5 (0x3 << 16)
C8.
#define | V_IO_CAPT_LVL6 (0x4 << 16)
C9.
#define | V_IO_CAPT_LVL7 (0x5 << 16)
C10.
#define | V_IO_CAPT_LVL2_BASE_ADDR_MASK 0xFFFF
#define | IA32_MTRR_CAP 0x000000FE
#define | B_IA32_MTRR_VARIABLE_SUPPORT 0xFF
#define | B_IA32_MTRR_CAP_FIXED_SUPPORT BIT8
#define | B_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
#define | B_IA32_MTRR_CAP_EMRR_SUPPORT BIT12
#define | MSR_PLAT_FRMW_PROT_CTRL 0x00000110
#define | B_MSR_PLAT_FRMW_PROT_CTRL_LK BIT0
#define | B_MSR_PLAT_FRMW_PROT_CTRL_EN BIT1
#define | B_MSR_PLAT_FRMW_PROT_CTRL_S1 BIT2
#define | MSR_PLAT_FRMW_PROT_HASH_0 0x00000111
#define | MSR_PLAT_FRMW_PROT_HASH_1 0x00000112
#define | MSR_PLAT_FRMW_PROT_HASH_2 0x00000113
#define | MSR_PLAT_FRMW_PROT_HASH_3 0x00000114
#define | MSR_PLAT_FRMW_PROT_TRIG_PARAM 0x00000115
#define | N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_STATUS_OFFSET 0
#define | V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_STATUS_MASK 0x000000000000FFFF
#define | N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_DATA_OFFSET 16
#define | V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_DATA_MASK 0x000000000000FFFF
#define | N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_TERMINAL_OFFSET 32
#define | V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_TERMINAL_MASK 0x000000000000FFFF
#define | B_MSR_PLAT_FRMW_PROT_TRIG_PARAM_SE BIT62
#define | N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_SE_OFFSET 62
#define | MSR_PLAT_FRMW_PROT_TRIGGER 0x00000116
#define | MSR_PLAT_FRMW_PROT_PASSWD 0x00000117
#define | MSR_SPCL_CHIPSET_USAGE_ADDR 0x000001FE
#define | MSR_IA32_FEATURE_CONFIG 0x0000013C
#define | B_IA32_FEATURE_CONFIG_AES_DIS BIT1
#define | B_IA32_FEATURE_CONFIG_LOCK BIT0
#define | IA32_MCG_CAP 0x00000179
#define | IA32_MCG_STATUS 0x0000017A
#define | MSR_FLEX_RATIO 0x00000194
#define | N_FLEX_RATIO 8
#define | B_FLEX_RATIO (0xFF << 8)
#define | B_FLEX_EN BIT16
#define | B_MAX_EXTRA_VOLTAGE 0xFF
#define | N_OVERCLOCKING_BINS 17
#define | B_OVERCLOCKING_BINS (0x7 << 17)
#define | B_OVERCLOCKING_LOCK BIT20
#define | RATIO_FLEX_CLEAR_MASK 0xFFFFFFFFFFFF00FFULL
#define | MSR_IA32_PERF_STS 0x00000198
#define | N_IA32_PERF_STSP_STATE_TARGET 8
#define | B_IA32_PERF_STSP_STATE_MASK 0xFF
#define | MSR_IA32_PERF_CTRL 0x00000199
#define | N_IA32_PERF_CTRLP_STATE_TARGET 8
#define | B_IA32_PERF_CTRLP_STATE_TARGET (0x7F << 8)
#define | B_IA32_PERF_CTRL_TURBO_DIS BIT32
#define | MSR_IA32_CLOCK_MODULATION 0x0000019A
#define | IA32_THERM_INTERRUPT 0x0000019B
#define | B_IA32_THERM_INTERRUPT_VIE BIT4
#define | MSR_IA32_THERM_STATUS 0x0000019C
#define | MSR_IA32_MISC_ENABLE 0x000001A0
#define | B_MSR_IA32_MISC_ENABLE_FSE BIT0
#define | B_MSR_IA32_MISC_ENABLE_TME BIT3
#define | N_MSR_IA32_MISC_ENABLE_EIST_OFFSET 16
#define | B_MSR_IA32_MISC_ENABLE_EIST BIT16
#define | B_MSR_IA32_MISC_ENABLE_MONITOR BIT18
#define | B_MSR_IA32_MISC_ENABLE_CPUID_MAX BIT22
#define | B_MSR_IA32_MISC_ENABLE_TPR_DIS BIT23
#define | B_MSR_IA32_MISC_ENABLE_XD BIT34
#define | B_MSR_IA32_MISC_DISABLE_TURBO BIT38
#define | MSR_TEMPERATURE_TARGET 0x000001A2
#define | N_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LIMIT 24
#define | N_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_OFFSET (16)
#define | B_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_MASK (0xFF << 16)
#define | N_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET 8
#define | B_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET (0xFF << 8)
#define | MISC_FEATURE_CONTROL 0x000001A4
#define | B_MISC_FEATURE_CONTROL_MLC_STRP BIT0
#define | B_MISC_FEATURE_CONTROL_MLC_SPAP BIT1
#define | B_MISC_FEATURE_CONTROL_DCU_STRP BIT2
#define | B_MISC_FEATURE_CONTROL_DCU_IPP BIT3
#define | MSR_MISC_PWR_MGMT 0x000001AA
#define | B_MSR_MISC_PWR_MGMT_EIST_HW BIT0
#define | B_MSR_MISC_PWR_MGMT_LTMI BIT22
#define | MSR_TURBO_POWER_CURRENT_LIMIT 0x000001AC
#define | B_MSR_TURBO_POWER_CURRENT_LIMIT_TDC_EN BIT31
#define | N_MSR_TURBO_POWER_CURRENT_LIMIT_TDC_LIMIT 16
#define | B_MSR_TURBO_POWER_CURRENT_LIMIT_TDC_LIMIT (0x7F << 16)
#define | B_MSR_TURBO_POWER_CURRENT_LIMIT_TDP_EN BIT15
#define | N_MSR_TURBO_POWER_CURRENT_LIMIT_TDP_LIMIT 0
#define | B_MSR_TURBO_POWER_CURRENT_LIMIT_TDP_LIMIT (0x7F << 0)
#define | MSR_TURBO_RATIO_LIMIT 0x000001AD
#define | N_MSR_TURBO_RATIO_LIMIT_1C 0
#define | B_MSR_TURBO_RATIO_LIMIT_1C (0xFF << 0)
#define | N_MSR_TURBO_RATIO_LIMIT_2C 8
#define | B_MSR_TURBO_RATIO_LIMIT_2C (0xFF << 8)
#define | N_MSR_TURBO_RATIO_LIMIT_3C 16
#define | B_MSR_TURBO_RATIO_LIMIT_3C (0xFF << 16)
#define | N_MSR_TURBO_RATIO_LIMIT_4C 24
#define | B_MSR_TURBO_RATIO_LIMIT_4C (0xFF << 24)
#define | MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1B0
#define | B_ENERGY_POLICY_MASK 0xF
#define | MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
#define | B_MSR_IA32_PLATFORM_DCA_CAP_TYPE0_EN BIT0
#define | MSR_IA32_CPU_DCA_CAP 0x000001F9
#define | B_MSR_IA32_CPU_DCA_CAP_TYPE0_SUP BIT0
#define | MSR_IA32_DCA_0_CAP 0x000001FA
#define | B_MSR_IA32_CPU_DCA_CAP_ENDID BIT11
#define | N_MSR_IA32_CPU_DCA_CAP_DELAY 13
#define | B_MSR_IA32_CPU_DCA_CAP_DELAY (BIT13 | BIT14 | BIT15 | BIT16)
#define | B_MSR_IA32_CPU_DCA_CAP_SW_LOCK BIT24
#define | B_MSR_IA32_CPU_DCA_CAP_SW_FLUSH BIT25
#define | B_MSR_IA32_CPU_DCA_CAP_HW_LOCK BIT26
#define | MSR_POWER_CTL 0x000001FC
#define | B_MSR_POWER_CTL_BROCHOT BIT0
#define | B_MSR_POWER_CTL_C1E BIT1
#define | B_ENERGY_EFFICIENT_P_STATE_FEATURE_ENABLE BIT18
#define | B_MSR_POWER_CTL_DISABLE_PHOT_OUT BIT21
#define | B_MSR_POWER_CTL_PROC_HOT_RESPONSE BIT22
#define | B_MSR_POWER_CTL_PROC_HOT_LOCK BIT23
#define | B_MSR_POWER_CTL_DISABLE_VR_THERMAL_ALERT BIT24
#define | B_MSR_POWER_CTL_CSTATE_PRE_WAKE_DISABLE BIT30
#define | MSR_FERR_CAPABILITIES 0x000001F1
#define | B_MSR_FERR_ENABLE BIT0
#define | MSR_VR_CURRENT_CONFIG 0x00000601
#define | B_CURRENT_LIMIT_LOCK BIT31
#define | B_CURRENT_LIMIT_MASK 0x1FFF
#define | MSR_VR_MISC_CONFIG 0x603
#define | N_MSR_VR_MISC_CONFIG_MIN_VID_OFFSET 24
#define | B_MSR_VR_MISC_CONFIG_MIN_VID_MASK 0xFF
#define | V_MSR_VR_MISC_CONFIG_MIN_VID_DEFAULT 0
#define | N_MSR_VR_MISC_CONFIG_IDLE_EXIT_RAMP_RATE_OFFSET 50
#define | B_MSR_VR_MISC_CONFIG_IDLE_EXIT_RAMP_RATE BIT50
#define | N_MSR_VR_MISC_CONFIG_IDLE_ENTRY_RAMP_RATE_OFFSET 51
#define | B_MSR_VR_MISC_CONFIG_IDLE_ENTRY_RAMP_RATE BIT51
#define | N_MSR_VR_MISC_CONFIG_IDLE_ENTRY_DECAY_ENABLE_OFFSET 52
#define | B_MSR_VR_MISC_CONFIG_IDLE_ENTRY_DECAY_ENABLE BIT52
#define | N_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_OFFSET 53
#define | B_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_MASK (BIT54 | BIT53)
#define | V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_DEFAULT 1
#define | V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_2 0
#define | V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_4 BIT53
#define | V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_8 BIT54
#define | V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_16 (BIT54 | BIT53)
#define | MSR_VR_MISC_CONFIG2 0x636
#define | N_MSR_VR_MISC_CONFIG2_FAST_RAMP_VOLTAGE_OFFSET 0
#define | B_MSR_VR_MISC_CONFIG2_FAST_RAMP_VOLTAGE_MASK 0xFF
#define | V_MSR_VR_MISC_CONFIG2_FAST_RAMP_VOLTAGE_DEFAULT 0x6F
#define | N_MSR_VR_MISC_CONFIG2_MIN_C8_VOLTAGE_OFFSET 8
#define | B_MSR_VR_MISC_CONFIG2_MIN_C8_VOLTAGE_MASK 0xFF
#define | V_MSR_VR_MISC_CONFIG2_MIN_C8_VOLTAGE_DEFAULT 0
#define | MSR_PACKAGE_POWER_SKU_UNIT 0x606
#define | PACKAGE_POWER_UNIT_MASK 0xF
#define | PACKAGE_TIME_UNIT_MASK 0xF0000
#define | MSR_C_STATE_LATENCY_CONTROL_0 0x60A
#define | MSR_C_STATE_LATENCY_CONTROL_1 0x60B
#define | MSR_C_STATE_LATENCY_CONTROL_2 0x60C
#define | MSR_C_STATE_LATENCY_CONTROL_3 0x633
#define | MSR_C_STATE_LATENCY_CONTROL_4 0x634
#define | MSR_C_STATE_LATENCY_CONTROL_5 0x635
#define | B_PKG_IRTL_VALID BIT15
#define | B_INTERRUPT_RESPONSE_TIME_LIMIT_MASK 0x3FF
#define | B_TIME_UNIT_MASK (0x7 << 10)
#define | N_TIME_UNIT_OFFSET 10
#define | MSR_PACKAGE_POWER_LIMIT 0x610
#define | MSR_PACKAGE_POWER_SKU 0x614
#define | B_POWER_LIMIT_ENABLE BIT15
#define | B_CRITICAL_POWER_CLAMP_ENABLE BIT16
#define | B_POWER_LIMIT_LOCK BIT31
#define | POWER_LIMIT_MASK (0x7FFF)
#define | POWER_LIMIT_1_TIME_MASK (0xFE0000)
#define | PACKAGE_TDP_POWER_MASK (0x7FFF)
#define | PACKAGE_MIN_POWER_MASK (0x7FFF0000)
#define | PACKAGE_MAX_POWER_MASK (0x7FFF)
#define | MSR_PLATFORM_POWER_LIMIT 0x615
#define | POWER_LIMIT_3_TIME_MASK (0xFE0000)
#define | POWER_LIMIT_3_DUTY_CYCLE_MASK (0x7F000000)
#define | MSR_DDR_RAPL_LIMIT 0x618
#define | MSR_RING_RATIO_LIMIT 0x620
#define | MSR_MAX_RING_RATIO_LIMIT_MASK 0x7F
#define | MSR_CONFIG_TDP_NOMINAL 0x648
#define | CONFIG_TDP_NOMINAL_RATIO_MASK 0xFF
#define | MSR_CONFIG_TDP_LVL1 0x649
#define | CONFIG_TDP_LVL1_RATIO_OFFSET 16
#define | CONFIG_TDP_LVL1_RATIO_MASK (0xFF << 16)
#define | CONFIG_TDP_LVL1_PKG_TDP_MASK (0x7FFF)
#define | MSR_CONFIG_TDP_LVL2 0x64A
#define | CONFIG_TDP_LVL2_RATIO_OFFSET 16
#define | CONFIG_TDP_LVL2_RATIO_MASK (0xFF << 16)
#define | CONFIG_TDP_LVL2_PKG_TDP_MASK (0x7FFF)
#define | MSR_CONFIG_TDP_CONTROL 0x64B
#define | CONFIG_TDP_CONTROL_LOCK (1 << 31)
#define | CONFIG_TDP_CONTROL_LVL_MASK 0x3
#define | CONFIG_TDP_NOMINAL 0
#define | CONFIG_TDP_LEVEL1 1
#define | CONFIG_TDP_LEVEL2 2
#define | MSR_TURBO_ACTIVATION_RATIO 0x64C
#define | MSR_TURBO_ACTIVATION_RATIO_LOCK (1 << 31)
#define | MSR_TURBO_ACTIVATION_RATIO_MASK 0xFF
#define | SMRR_PHYS_BASE 0x000001F2
#define | SMRR_PHYS_MASK 0x000001F3
#define | EMRR_PHYS_BASE 0x000001F4
#define | EMRR_PHYS_MASK 0x000001F5
#define | B_MSR_EMRR_PHYS_MASK_EN BIT11
#define | B_MSR_EMRR_PHYS_MASK_LOCK BIT10
#define | V_MAXIMUM_VARIABLE_MTRR_NUMBER 10
#define | CACHE_VARIABLE_MTRR_BASE 0x00000200
#define | V_FIXED_MTRR_NUMBER 11
#define | IA32_MTRR_FIX64K_00000 0x00000250
#define | IA32_MTRR_FIX16K_80000 0x00000258
#define | IA32_MTRR_FIX16K_A0000 0x00000259
#define | IA32_MTRR_FIX4K_C0000 0x00000268
#define | IA32_MTRR_FIX4K_C8000 0x00000269
#define | IA32_MTRR_FIX4K_D0000 0x0000026A
#define | IA32_MTRR_FIX4K_D8000 0x0000026B
#define | IA32_MTRR_FIX4K_E0000 0x0000026C
#define | IA32_MTRR_FIX4K_E8000 0x0000026D
#define | IA32_MTRR_FIX4K_F0000 0x0000026E
#define | IA32_MTRR_FIX4K_F8000 0x0000026F
#define | MSR_IA32_CR_PAT 0x00000277
#define | CACHE_IA32_MTRR_DEF_TYPE 0x000002FF
#define | B_CACHE_MTRR_VALID BIT11
#define | B_CACHE_FIXED_MTRR_VALID BIT10
#define | NO_EVICT_MODE 0x000002E0
#define | B_NO_EVICT_MODE_SETUP BIT0
#define | B_NO_EVICT_MODE_RUN BIT1
#define | UNCORE_CR_MEMLOCK_COMMANDS 0x000002E2
#define | B_LOCK_MEM_CFG BIT1
#define | EFI_PCIEXBAR 0x00000300
#define | B_PCIEXBAR_EN BIT0
#define | B_PCIEXBAR_SIZE (BIT1 | BIT2 | BIT3)
#define | N_PCIEXBAR_SIZE 1
#define | IA32_MC0_CTL 0x00000400
#define | IA32_MC0_STATUS 0x00000401
#define | IA32_MC0_ADDR 0x00000402
#define | IA32_MC0_MISC 0x00000403
#define | IA32_MC8_CTL (IA32_MC0_CTL + (8 * 4))
#define | IA32_MC5_STATUS (IA32_MC0_STATUS + (5 * 4))
#define | IA32_MC6_STATUS (IA32_MC0_STATUS + (6 * 4))
#define | IA32_MC7_STATUS (IA32_MC0_STATUS + (7 * 4))
#define | IA32_MC8_STATUS (IA32_MC0_STATUS + (8 * 4))
#define | MSR_IA32_VMX_BASIC 0x00000480
#define | MSR_IA32_VMX_MISC 0x00000485
#define | APIC_GLOBAL_ENABLE 0x00000800
#define | EXT_XAPIC_LOGICAL_APIC_ID 0x00000802
#define | EXT_XAPIC_VERSION 0x00000803
#define | EXT_XAPIC_SVR 0x0000080F
#define | EXT_XAPIC_ICR 0x00000830
#define | MSR_EXT_XAPIC_LVT_THERM 0x00000833
#define | EXT_XAPIC_LVT_LINT0 0x00000835
#define | EXT_XAPIC_LVT_LINT1 0x00000836
#define | MSR_IA32_DEBUG_INTERFACE 0x00000C80
#define | B_DEBUG_INTERFACE_ENABLE BIT0
#define | B_DEBUG_INTERFACE_LOCK BIT30
#define | B_DEBUG_INTERFACE_DEBUG_STATUS BIT31
#define | NUM_TENTHS_TO_PERCENTAGE 1000
#define | FIVR_SSC_LOCK_BIT BIT31
#define | MAX_FIVR_SSC_PERCENT 60
#define | MSR_SMM_MCA_CAP 0x17D
#define | B_TARGETED_SMI BIT56
#define | N_TARGETED_SMI 56
#define | B_SMM_CPU_SVRSTR BIT57
#define | N_SMM_CPU_SVRSTR 57
#define | B_SMM_CODE_ACCESS_CHK BIT58
#define | N_SMM_CODE_ACCESS_CHK 58
#define | B_LONG_FLOW_INDICATION BIT59
#define | N_LONG_FLOW_INDICATION 59
#define | MSR_SMM_FEATURE_CONTROL 0x4E0
#define | B_SMM_FEATURE_CONTROL_LOCK BIT0
#define | B_SMM_CPU_SAVE_EN BIT1
#define | B_SMM_CODE_CHK_EN BIT2
#define | MSR_SMM_ENABLE 0x4E1
#define | MSR_SMM_DELAYED 0x4E2
#define | MSR_SMM_BLOCKED 0x4E3
#define | MSR_CR0 0xC00
#define | MSR_CR3 0xC01
#define | MSR_EFLAGS 0xC02
#define | MSR_RIP 0xC04
#define | MSR_DR6 0xC05
#define | MSR_DR7 0xC06
#define | MSR_TR_LDTR 0xC07
#define | MSR_GS_FS 0xC08
#define | MSR_DS_SS 0xC09
#define | MSR_CS_ES 0xC0A
#define | MSR_IO_MISC_INFO 0xC0B
#define | MSR_IO_MEM_ADDR 0xC0C
#define | MSR_RDI 0xC0D
#define | MSR_RSI 0xC0E
#define | MSR_RBP 0xC0F
#define | MSR_RSP 0xC10
#define | MSR_RBX 0xC11
#define | MSR_RDX 0xC12
#define | MSR_RCX 0xC13
#define | MSR_RAX 0xC14
#define | MSR_R8 0xC15
#define | MSR_R9 0xC16
#define | MSR_R10 0xC17
#define | MSR_R11 0xC18
#define | MSR_R12 0xC19
#define | MSR_R13 0xC1A
#define | MSR_R14 0xC1B
#define | MSR_R15 0xC1C
#define | MSR_EVENT_CTL_HLT_IO 0xC1F
#define | MSR_SMBASE 0xC20
#define | MSR_SMM_REVID 0xC21
#define | MSR_IEDBASE 0xC22
#define | MSR_EPTP_ENABLE 0xC23
#define | MSR_EPTP 0xC24
#define | MSR_LDTR_BASE 0xC2C
#define | MSR_IDTR_BASE 0xC2D
#define | MSR_GDTR_BASE 0xC2E
#define | MSR_CR4 0xC37
#define | MSR_IO_RSI 0xC40
#define | MSR_IO_RCX 0xC41
#define | MSR_IO_RIP 0xC42
#define | MSR_IO_RDI 0xC43
#define | MSR_BC_PBEC 0x139
#define | B_STOP_PBET BIT0
#define | MSR_BOOT_GUARD_SACM_INFO 0x13A
#define | B_NEM_INIT BIT0
#define | V_TPM_PRESENT_MASK 0x06
#define | V_TPM_PRESENT_NO_TPM 0
#define | V_TPM_PRESENT_DTPM_12 1
#define | V_TPM_PRESENT_DTPM_20 2
#define | V_TPM_PRESENT_PTT 3
#define | B_TPM_SUCCESS BIT3
#define | B_MEASURED BIT5
#define | B_VERIFIED BIT6
#define | TXT_PUBLIC_BASE 0xFED30000
#define | R_CPU_BOOT_GUARD_ERRORCODE 0x30
#define | R_CPU_BOOT_GUARD_BOOTSTATUS 0xA0
#define | R_CPU_BOOT_GUARD_ACM_STATUS 0x328
#define | V_CPU_BOOT_GUARD_LOAD_ACM_SUCCESS 0x8000000000000000
#define | B_BOOT_GUARD_ACM_ERRORCODE_MASK 0x00007FF0
#define | CPUID_FULL_STEPPING 0x0000000F
#define | CPUID_FULL_FAMILY_MODEL 0x0FFF0FF0
#define | CPUID_FULL_FAMILY_MODEL_STEPPING 0x0FFF0FFF
#define | CPUID_FULL_FAMILY_MODEL_HASWELL 0x000306C0
#define | CPUID_FULL_FAMILY_MODEL_HASWELL_ULT 0x00040650
#define | CPUID_FULL_FAMILY_MODEL_CRYSTALWELL 0x00040660
#define | CPUID_PROCESSOR_TOPOLOGY 0xB

Enumerations

enum | CPU_FAMILY
enum | CPU_STEPPING
enum | CPU_SKU

Detailed Description

Conventions:

  • Prefixes: Definitions beginning with "MSR_" are MSRs Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values of bits within the registers Definitions beginning with "S_" are register sizes Definitions beginning with "N_" are the bit position
Copyright:
Copyright (c) 2004 - 2013 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file CpuRegs.h.

Enumeration Type Documentation

enum CPU_STEPPING
Enumerator:
EnumHswA0

Haswell Family Stepping.

EnumHswUltB0

Haswell ULT Family Stepping.

EnumCrwB0

Crystalwell Family Stepping.

EnumCpuSteppingMax

Max Stepping.

Definition at line 551 of file CpuRegs.h.


2013 SharkBay Processor Reference Code API: CpuRegs.h Source File

  • File List
  • File Members
CpuRegs.h
Go to the documentation of this file.
00001
00027 #ifndef _CPU_REGS_H_
00028 #define _CPU_REGS_H_
00029
00030 #include "CommonIncludes.h"
00031
00032 //
00033 // Local APIC defines
00034 //
00035 #define APIC_REGISTER_LOCAL_ID_OFFSET         0x00000020
00036 #define APIC_REGISTER_APIC_VERSION_OFFSET     0x00000030
00037 #define APIC_REGISTER_SPURIOUS_VECTOR_OFFSET  0x000000F0
00038 #define APIC_REGISTER_ICR_LOW_OFFSET          0x00000300
00039 #define APIC_REGISTER_ICR_HIGH_OFFSET         0x00000310
00040 #define APIC_REGISTER_LINT0_VECTOR_OFFSET     0x00000350
00041 #define APIC_REGISTER_LINT1_VECTOR_OFFSET     0x00000360
00042
00043 #define BROADCAST_MODE_SPECIFY_CPU            0x00
00044 #define BROADCAST_MODE_ALL_INCLUDING_SELF     0x01
00045 #define BROADCAST_MODE_ALL_EXCLUDING_SELF     0x02
00046
00047 #ifndef DELIVERY_MODE_REMOTE_READ
00048
00049 #define DELIVERY_MODE_FIXED           0x00
00050 #define DELIVERY_MODE_LOWEST_PRIORITY 0x01
00051 #define DELIVERY_MODE_SMI             0x02
00052 #define DELIVERY_MODE_REMOTE_READ     0x03
00053 #define DELIVERY_MODE_NMI             0x04
00054 #define DELIVERY_MODE_INIT            0x05
00055 #define DELIVERY_MODE_SIPI            0x06
00056 #define DELIVERY_MODE_MAX             0x07
00057
00058 #define TRIGGER_MODE_EDGE             0x00
00059 #define TRIGGER_MODE_LEVEL            0x01
00060
00061 #endif
00062
00063 #define CACHE_UNCACHEABLE               0
00064 #define CACHE_WRITECOMBINING            1
00065 #define CACHE_WRITETHROUGH              4
00066 #define CACHE_WRITEPROTECTED            5
00067 #define CACHE_WRITEBACK                 6
00068
00069 #define CPUID_SIGNATURE                 0x0
00070 #define CPUID_VERSION_INFO              0x1
00071 #define CPUID_FUNCTION_4                0x4
00072 #define CPU_CACHE_TYPE_MASK             0x1F
00073 #define CPU_CACHE_LEVEL_MASK            0x07
00074 #define CPU_CACHE_ASSOCIATIVITY_MASK    0x03FF
00075 #define CPU_CACHE_PARTITION_MASK        0x03FF
00076 #define CPU_CACHE_LINE_SIZE_MASK        0x0FFF
00077 #define B_CPUID_VERSION_INFO_ECX_MWAIT  BIT3
00078 #define B_CPUID_VERSION_INFO_ECX_VME    BIT5
00079 #define B_CPUID_VERSION_INFO_ECX_SME    BIT6
00080 #define B_CPUID_VERSION_INFO_ECX_EIST   BIT7
00081 #define B_CPUID_VERSION_INFO_ECX_TM2    BIT8
00082 #define B_CPUID_VERSION_INFO_ECX_DCA    BIT18
00083 #define B_CPUID_VERSION_INFO_ECX_AES    BIT25
00084 #define B_CPUID_VERSION_INFO_ECX_XAPIC  BIT21
00085 #define B_CPUID_VERSION_INFO_EDX_XD     BIT20
00086 #define B_CPUID_VERSION_INFO_EDX_HT     BIT28
00087 #define B_CPUID_VERSION_INFO_EDX_TM1    BIT29
00088
00089 #define CPUID_CACHE_INFO                0x2
00090 #define CPUID_SERIAL_NUMBER             0x3
00091 #define CPUID_CACHE_PARAMS              0x4
00092
00093 //
00094 // CPU ID Instruction defines
00095 //
00096 #define V_CPUID_CACHE_TYPE_MASK         0x1F
00097 #define B_CPUID_CACHE_TYPE_DATA         0x1
00098 #define B_CPUID_CACHE_TYPE_INSTRUCTION  0x2
00099 #define B_CPUID_CACHE_TYPE_UNIFIED      0x3
00100 #define V_CPUID_CACHE_LEVEL_MASK        0xE0
00101 #define B_CPUID_CACHE_LEVEL_SHIFT       5
00102 #define B_CPUID_CACHE_PARAMS_WAYS_SHIFT                               22
00103 #define B_CPUID_CACHE_PARAMS_PARTITIONS_SHIFT                         12
00104 #define CPUID_MONITOR_MWAIT_PARAMS                                    0x5
00105 #define B_CPUID_MONITOR_MWAIT_ECX_EXTENSIONS                          BIT0
00106 #define B_CPUID_MONITOR_MWAIT_EDX_CSTATE                              BIT0
00107 #define V_CPUID_MONITOR_MWAIT_EDX_ENHANCED_CSTATE                     0x2
00108 #define CPUID_POWER_MANAGEMENT_PARAMS                                 0x6
00109 #define B_CPUID_POWER_MANAGEMENT_EAX_TURBO                            BIT1
00110 #define B_CPUID_POWER_MANAGEMENT_EAX_FINE_GRAINED_CLOCK_MODULATION    BIT5
00111 #define B_CPUID_POWER_MANAGEMENT_ECX_ENERGY_EFFICIENT_POLICY_SUPPORT  BIT3
00112 #define CPUID_REV7                                                    0x7
00113 #define CPUID_REV8                                                    0x8
00114 #define CPUID_DCA_PARAMS                                              0x9
00115 #define CPUID_REVA                                                    0xA
00116 #define CPUID_CORE_TOPOLOGY                                           0xB
00117 #define CPUID_EXTENDED_FUNCTION                                       0x80000000
00118 #define CPUID_EXTENDED_CPU_SIG                                        0x80000001
00119 #define CPUID_BRAND_STRING1                                           0x80000002
00120 #define CPUID_BRAND_STRING2                                           0x80000003
00121 #define CPUID_BRAND_STRING3                                           0x80000004
00122 #define CPUID_L2_CACHE_FEATURE                                        0x80000006
00123 #define CPUID_VIR_PHY_ADDRESS_SIZE                                    0x80000008
00124
00125 //
00126 // MSR defines
00127 //
00128 #define MSR_IA32_PLATFORM_ID                                          0x00000017
00129 #define MSR_IA32_APIC_BASE                                            0x0000001B
00130 #define B_MSR_IA32_APIC_BASE_G_XAPIC                                  BIT11
00131 #define B_MSR_IA32_APIC_BASE_M_XAPIC                                  BIT10
00132 #define B_MSR_IA32_APIC_BASE_BSP                                      BIT8
00133 #define PIC_THREAD_CONTROL                                            0x0000002E
00134 #define B_PIC_THREAD_CONTROL_TPR_DIS                                  BIT10
00135 #define MSR_CORE_THREAD_COUNT                                         0x00000035
00136 #define N_CORE_COUNT_OFFSET                                           16
00137 #define B_THREAD_COUNT_MASK                                           0xFFFF
00138 #define MSR_SOCKET_ID_MSR                                             0x00000039
00139 #define MSR_IA32_FEATURE_CONTROL                                      0x0000003A
00140 #define B_MSR_IA32_FEATURE_CONTROL_LOCK                               BIT0
00141 #define B_MSR_IA32_FEATURE_CONTROL_ELT                                BIT1
00142 #define B_MSR_IA32_FEATURE_CONTROL_EVT                                BIT2
00143 #define B_MSR_IA32_FEATURE_CONTROL_SLFE                               (BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT14)
00144 #define B_MSR_IA32_FEATURE_CONTROL_SGE                                BIT15
00145 #define MSR_IA32_SMM_SAVE_CONTROL                                     0x0000003E
00146 #define B_MSR_IA32_SMM_SAVE_CONTROL_SFPPE                             BIT0
00147 #define MSR_IA32_BIOS_UPDT_TRIG                                       0x00000079
00148 #define MSR_IA32_BIOS_SIGN_ID                                         0x0000008B
00149 #define MSR_IA32_SMM_MONITOR_CONTROL                                  0x0000009B
00150 #define MSR_IA32_PMC0_MSR                                             0x000000C1
00151 #define MSR_IA32_PMC1_MSR                                             0x000000C2
00152 #define MSR_IA32_PMC2_MSR                                             0x000000C3
00153 #define MSR_IA32_PMC3_MSR                                             0x000000C4
00154 #define MSR_IA32_PMC4_MSR                                             0x000000C5
00155 #define MSR_IA32_PMC5_MSR                                             0x000000C6
00156 #define MSR_IA32_PMC6_MSR                                             0x000000C7
00157 #define MSR_IA32_PMC7_MSR                                             0x000000C8
00158 #define MSR_PLATFORM_INFO                                             0x000000CE
00159 #define N_PLATFORM_INFO_MIN_RATIO                                     40
00160 #define B_PLATFORM_INFO_RATIO_MASK                                    0xFF
00161 #define N_PLATFORM_INFO_MAX_RATIO                                     8
00162 #define B_MSR_PLATFORM_INFO_PFAT_AVAIL                                BIT35
00163 #define N_MSR_PLATFORM_INFO_CONFIG_TDP_NUM_LEVELS_OFFSET              33
00164 #define V_CONFIG_TDP_NUM_LEVELS_MASK                                  (BIT34 | BIT33)
00165 #define B_PLATFORM_INFO_TDC_TDP_LIMIT                                 BIT29
00166 #define N_PLATFORM_INFO_RATIO_LIMIT                                   28
00167 #define B_PLATFORM_INFO_RATIO_LIMIT                                   BIT28
00168 #define B_FIVR_RFI_TUNING_AVAIL                                       BIT25
00169 #define B_PLATFORM_INFO_SMM_SAVE_CONTROL                              BIT16
00170 #define N_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET                    30
00171 #define B_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET                    BIT30
00172 #define B_PLATFORM_INFO_TIMED_MWAIT_SUPPORTED                         BIT37
00173 #define MSR_PMG_CST_CONFIG                                            0x000000E2
00174 #define B_CST_CONTROL_LOCK                                            BIT15
00175 #define B_IO_MWAIT_REDIRECTION_ENABLE                                 BIT10
00176 #define B_TIMED_MWAIT_ENABLE                                          BIT31
00177 #define B_PACKAGE_C_STATE_LIMIT                                       (BIT3 | BIT2 | BIT1 | BIT0)
00178 #define V_CSTATE_LIMIT_C1                                             0x01
00179 #define V_CSTATE_LIMIT_C3                                             0x02
00180 #define V_CSTATE_LIMIT_C6                                             0x03
00181 #define V_CSTATE_LIMIT_C7                                             0x04
00182 #define V_CSTATE_LIMIT_C7S                                            0x05
00183 #define V_CSTATE_LIMIT_C8                                             0x06
00184 #define V_CSTATE_LIMIT_C9                                             0x07
00185 #define V_CSTATE_LIMIT_C10                                            0x08
00186 #define B_C3_AUTO_DEMOTION_ENABLE                                     BIT25
00187 #define B_C1_AUTO_DEMOTION_ENABLE                                     BIT26
00188 #define B_C3_AUTO_UNDEMOTION_ENABLE                                   BIT27
00189 #define B_C1_AUTO_UNDEMOTION_ENABLE                                   BIT28
00190 #define B_PKG_CSTATE_DEMOTION_ENABLE                                  BIT29
00191 #define B_PKG_CSTATE_UNDEMOTION_ENABLE                                BIT30
00192 #define MSR_RFI_TUNNING                                               0x000000E3
00193 #define V_FREQ_TUNNING_MASK                                           0xFFFF
00194 #define MSR_PMG_IO_CAPTURE_BASE                                       0x000000E4
00195 #define B_MSR_PMG_CST_RANGE                                           (BIT18 | BIT17 | BIT16)
00196 #define V_IO_CAPT_LVL2                                                (0x0 << 16)   ///< C3
00197 #define V_IO_CAPT_LVL3                                                (0x1 << 16)   ///< C6
00198 #define V_IO_CAPT_LVL4                                                (0x2 << 16)   ///< C7
00199 #define V_IO_CAPT_LVL5                                                (0x3 << 16)   ///< C8
00200 #define V_IO_CAPT_LVL6                                                (0x4 << 16)   ///< C9
00201 #define V_IO_CAPT_LVL7                                                (0x5 << 16)   ///< C10
00202 #define V_IO_CAPT_LVL2_BASE_ADDR_MASK                                 0xFFFF
00203 #define IA32_MTRR_CAP                                                 0x000000FE
00204 #define B_IA32_MTRR_VARIABLE_SUPPORT                                  0xFF
00205 #define B_IA32_MTRR_CAP_FIXED_SUPPORT                                 BIT8
00206 #define B_IA32_MTRR_CAP_SMRR_SUPPORT                                  BIT11
00207 #define B_IA32_MTRR_CAP_EMRR_SUPPORT                                  BIT12
00208 #define MSR_PLAT_FRMW_PROT_CTRL                                       0x00000110
00209 #define B_MSR_PLAT_FRMW_PROT_CTRL_LK                                  BIT0
00210 #define B_MSR_PLAT_FRMW_PROT_CTRL_EN                                  BIT1
00211 #define B_MSR_PLAT_FRMW_PROT_CTRL_S1                                  BIT2
00212 #define MSR_PLAT_FRMW_PROT_HASH_0                                     0x00000111
00213 #define MSR_PLAT_FRMW_PROT_HASH_1                                     0x00000112
00214 #define MSR_PLAT_FRMW_PROT_HASH_2                                     0x00000113
00215 #define MSR_PLAT_FRMW_PROT_HASH_3                                     0x00000114
00216 #define MSR_PLAT_FRMW_PROT_TRIG_PARAM                                 0x00000115
00217 #define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_STATUS_OFFSET                 0
00218 #define V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_STATUS_MASK                   0x000000000000FFFF
00219 #define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_DATA_OFFSET                   16
00220 #define V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_DATA_MASK                     0x000000000000FFFF
00221 #define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_TERMINAL_OFFSET               32
00222 #define V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_TERMINAL_MASK                 0x000000000000FFFF
00223 #define B_MSR_PLAT_FRMW_PROT_TRIG_PARAM_SE                            BIT62
00224 #define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_SE_OFFSET                     62
00225 #define MSR_PLAT_FRMW_PROT_TRIGGER                                    0x00000116
00226 #define MSR_PLAT_FRMW_PROT_PASSWD                                     0x00000117
00227 #define MSR_SPCL_CHIPSET_USAGE_ADDR                                   0x000001FE
00228 #define MSR_IA32_FEATURE_CONFIG                                       0x0000013C
00229 #define B_IA32_FEATURE_CONFIG_AES_DIS                                 BIT1
00230 #define B_IA32_FEATURE_CONFIG_LOCK                                    BIT0
00231 #define IA32_MCG_CAP                                                  0x00000179
00232 #define IA32_MCG_STATUS                                               0x0000017A
00233 #define MSR_FLEX_RATIO                                                0x00000194
00234 #define N_FLEX_RATIO                                                  8
00235 #define B_FLEX_RATIO                                                  (0xFF << 8)
00236 #define B_FLEX_EN                                                     BIT16
00237 #define B_MAX_EXTRA_VOLTAGE                                           0xFF
00238 #define N_OVERCLOCKING_BINS                                           17
00239 #define B_OVERCLOCKING_BINS                                           (0x7 << 17)
00240 #define B_OVERCLOCKING_LOCK                                           BIT20
00241 #define RATIO_FLEX_CLEAR_MASK                                         0xFFFFFFFFFFFF00FFULL
00242 #define MSR_IA32_PERF_STS                                             0x00000198
00243 #define N_IA32_PERF_STSP_STATE_TARGET                                 8
00244 #define B_IA32_PERF_STSP_STATE_MASK                                   0xFF
00245 #define MSR_IA32_PERF_CTRL                                            0x00000199
00246 #define N_IA32_PERF_CTRLP_STATE_TARGET                                8
00247 #define B_IA32_PERF_CTRLP_STATE_TARGET                                (0x7F << 8)
00248 #define B_IA32_PERF_CTRL_TURBO_DIS                                    BIT32
00249 #define MSR_IA32_CLOCK_MODULATION                                     0x0000019A
00250 #define IA32_THERM_INTERRUPT                                          0x0000019B
00251 #define B_IA32_THERM_INTERRUPT_VIE                                    BIT4
00252 #define MSR_IA32_THERM_STATUS                                         0x0000019C
00253 #define MSR_IA32_MISC_ENABLE                                          0x000001A0
00254 #define B_MSR_IA32_MISC_ENABLE_FSE                                    BIT0
00255 #define B_MSR_IA32_MISC_ENABLE_TME                                    BIT3
00256 #define N_MSR_IA32_MISC_ENABLE_EIST_OFFSET                            16
00257 #define B_MSR_IA32_MISC_ENABLE_EIST                                   BIT16
00258 #define B_MSR_IA32_MISC_ENABLE_MONITOR                                BIT18
00259 #define B_MSR_IA32_MISC_ENABLE_CPUID_MAX                              BIT22
00260 #define B_MSR_IA32_MISC_ENABLE_TPR_DIS                                BIT23
00261 #define B_MSR_IA32_MISC_ENABLE_XD                                     BIT34
00262 #define B_MSR_IA32_MISC_DISABLE_TURBO                                 BIT38
00263 #define MSR_TEMPERATURE_TARGET                                        0x000001A2
00264 #define N_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LIMIT                     24
00265 #define N_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_OFFSET    (16)
00266 #define B_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_MASK      (0xFF << 16)
00267 #define N_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET               8
00268 #define B_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET               (0xFF << 8)
00269 #define MISC_FEATURE_CONTROL                                          0x000001A4
00270 #define B_MISC_FEATURE_CONTROL_MLC_STRP                               BIT0
00271 #define B_MISC_FEATURE_CONTROL_MLC_SPAP                               BIT1
00272 #define B_MISC_FEATURE_CONTROL_DCU_STRP                               BIT2
00273 #define B_MISC_FEATURE_CONTROL_DCU_IPP                                BIT3
00274 #define MSR_MISC_PWR_MGMT                                             0x000001AA
00275 #define B_MSR_MISC_PWR_MGMT_EIST_HW                                   BIT0
00276 #define B_MSR_MISC_PWR_MGMT_LTMI                                      BIT22
00277 #define MSR_TURBO_POWER_CURRENT_LIMIT                                 0x000001AC
00278 #define B_MSR_TURBO_POWER_CURRENT_LIMIT_TDC_EN                        BIT31
00279 #define N_MSR_TURBO_POWER_CURRENT_LIMIT_TDC_LIMIT                     16
00280 #define B_MSR_TURBO_POWER_CURRENT_LIMIT_TDC_LIMIT                     (0x7F << 16)
00281 #define B_MSR_TURBO_POWER_CURRENT_LIMIT_TDP_EN                        BIT15
00282 #define N_MSR_TURBO_POWER_CURRENT_LIMIT_TDP_LIMIT                     0
00283 #define B_MSR_TURBO_POWER_CURRENT_LIMIT_TDP_LIMIT                     (0x7F << 0)
00284 #define MSR_TURBO_RATIO_LIMIT                                         0x000001AD
00285 #define N_MSR_TURBO_RATIO_LIMIT_1C                                    0
00286 #define B_MSR_TURBO_RATIO_LIMIT_1C                                    (0xFF << 0)
00287 #define N_MSR_TURBO_RATIO_LIMIT_2C                                    8
00288 #define B_MSR_TURBO_RATIO_LIMIT_2C                                    (0xFF << 8)
00289 #define N_MSR_TURBO_RATIO_LIMIT_3C                                    16
00290 #define B_MSR_TURBO_RATIO_LIMIT_3C                                    (0xFF << 16)
00291 #define N_MSR_TURBO_RATIO_LIMIT_4C                                    24
00292 #define B_MSR_TURBO_RATIO_LIMIT_4C                                    (0xFF << 24)
00293 #define MSR_IA32_ENERGY_PERFORMANCE_BIAS                              0x1B0
00294 #define B_ENERGY_POLICY_MASK                                          0xF
00295 #define MSR_IA32_PLATFORM_DCA_CAP                                     0x000001F8
00296 #define B_MSR_IA32_PLATFORM_DCA_CAP_TYPE0_EN                          BIT0
00297 #define MSR_IA32_CPU_DCA_CAP                                          0x000001F9
00298 #define B_MSR_IA32_CPU_DCA_CAP_TYPE0_SUP                              BIT0
00299 #define MSR_IA32_DCA_0_CAP                                            0x000001FA
00300 #define B_MSR_IA32_CPU_DCA_CAP_ENDID                                  BIT11
00301 #define N_MSR_IA32_CPU_DCA_CAP_DELAY                                  13
00302 #define B_MSR_IA32_CPU_DCA_CAP_DELAY                                  (BIT13 | BIT14 | BIT15 | BIT16)
00303 #define B_MSR_IA32_CPU_DCA_CAP_SW_LOCK                                BIT24
00304 #define B_MSR_IA32_CPU_DCA_CAP_SW_FLUSH                               BIT25
00305 #define B_MSR_IA32_CPU_DCA_CAP_HW_LOCK                                BIT26
00306 #define MSR_POWER_CTL                                                 0x000001FC
00307 #define B_MSR_POWER_CTL_BROCHOT                                       BIT0
00308 #define B_MSR_POWER_CTL_C1E                                           BIT1
00309 #define B_ENERGY_EFFICIENT_P_STATE_FEATURE_ENABLE                     BIT18
00310 #define B_MSR_POWER_CTL_DISABLE_PHOT_OUT                              BIT21
00311 #define B_MSR_POWER_CTL_PROC_HOT_RESPONSE                             BIT22
00312 #define B_MSR_POWER_CTL_PROC_HOT_LOCK                                 BIT23
00313 #define B_MSR_POWER_CTL_DISABLE_VR_THERMAL_ALERT                      BIT24
00314 #define B_MSR_POWER_CTL_CSTATE_PRE_WAKE_DISABLE                       BIT30
00315 #define MSR_FERR_CAPABILITIES                                         0x000001F1
00316 #define B_MSR_FERR_ENABLE                                             BIT0
00317 #define MSR_VR_CURRENT_CONFIG                                         0x00000601
00318 #define B_CURRENT_LIMIT_LOCK                                          BIT31
00319 #define B_CURRENT_LIMIT_MASK                                          0x1FFF
00320 #define MSR_VR_MISC_CONFIG                                            0x603
00321 #define N_MSR_VR_MISC_CONFIG_MIN_VID_OFFSET                           24
00322 #define B_MSR_VR_MISC_CONFIG_MIN_VID_MASK                             0xFF
00323 #define V_MSR_VR_MISC_CONFIG_MIN_VID_DEFAULT                          0
00324 #define N_MSR_VR_MISC_CONFIG_IDLE_EXIT_RAMP_RATE_OFFSET               50
00325 #define B_MSR_VR_MISC_CONFIG_IDLE_EXIT_RAMP_RATE                      BIT50
00326 #define N_MSR_VR_MISC_CONFIG_IDLE_ENTRY_RAMP_RATE_OFFSET              51
00327 #define B_MSR_VR_MISC_CONFIG_IDLE_ENTRY_RAMP_RATE                     BIT51
00328 #define N_MSR_VR_MISC_CONFIG_IDLE_ENTRY_DECAY_ENABLE_OFFSET           52
00329 #define B_MSR_VR_MISC_CONFIG_IDLE_ENTRY_DECAY_ENABLE                  BIT52
00330 #define N_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_OFFSET             53
00331 #define B_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_MASK               (BIT54 | BIT53)
00332 #define V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_DEFAULT            1
00333 #define V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_2             0
00334 #define V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_4             BIT53
00335 #define V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_8             BIT54
00336 #define V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_16            (BIT54 | BIT53)
00337 #define MSR_VR_MISC_CONFIG2                                           0x636
00338 #define N_MSR_VR_MISC_CONFIG2_FAST_RAMP_VOLTAGE_OFFSET                0
00339 #define B_MSR_VR_MISC_CONFIG2_FAST_RAMP_VOLTAGE_MASK                  0xFF
00340 #define V_MSR_VR_MISC_CONFIG2_FAST_RAMP_VOLTAGE_DEFAULT               0x6F
00341 #define N_MSR_VR_MISC_CONFIG2_MIN_C8_VOLTAGE_OFFSET                   8
00342 #define B_MSR_VR_MISC_CONFIG2_MIN_C8_VOLTAGE_MASK                     0xFF
00343 #define V_MSR_VR_MISC_CONFIG2_MIN_C8_VOLTAGE_DEFAULT                  0
00344 #define MSR_PACKAGE_POWER_SKU_UNIT                                    0x606
00345 #define PACKAGE_POWER_UNIT_MASK                                       0xF
00346 #define PACKAGE_TIME_UNIT_MASK                                        0xF0000
00347 #define MSR_C_STATE_LATENCY_CONTROL_0                                 0x60A
00348 #define MSR_C_STATE_LATENCY_CONTROL_1                                 0x60B
00349 #define MSR_C_STATE_LATENCY_CONTROL_2                                 0x60C
00350 #define MSR_C_STATE_LATENCY_CONTROL_3                                 0x633
00351 #define MSR_C_STATE_LATENCY_CONTROL_4                                 0x634
00352 #define MSR_C_STATE_LATENCY_CONTROL_5                                 0x635
00353 #define B_PKG_IRTL_VALID                                              BIT15
00354 #define B_INTERRUPT_RESPONSE_TIME_LIMIT_MASK                          0x3FF
00355 #define B_TIME_UNIT_MASK                                              (0x7 << 10)
00356 #define N_TIME_UNIT_OFFSET                                            10
00357 #define MSR_PACKAGE_POWER_LIMIT                                       0x610
00358 #define MSR_PACKAGE_POWER_SKU                                         0x614
00359 #define B_POWER_LIMIT_ENABLE                                          BIT15
00360 #define B_CRITICAL_POWER_CLAMP_ENABLE                                 BIT16
00361 #define B_POWER_LIMIT_LOCK                                            BIT31
00362 #define POWER_LIMIT_MASK                                              (0x7FFF)
00363 #define POWER_LIMIT_1_TIME_MASK                                       (0xFE0000)
00364 #define PACKAGE_TDP_POWER_MASK                                        (0x7FFF)
00365 #define PACKAGE_MIN_POWER_MASK                                        (0x7FFF0000)
00366 #define PACKAGE_MAX_POWER_MASK                                        (0x7FFF)
00367 #define MSR_PLATFORM_POWER_LIMIT                                      0x615
00368 #define POWER_LIMIT_3_TIME_MASK                                       (0xFE0000)
00369 #define POWER_LIMIT_3_DUTY_CYCLE_MASK                                 (0x7F000000)
00370 #define MSR_DDR_RAPL_LIMIT                                            0x618
00371 #define MSR_RING_RATIO_LIMIT                                          0x620
00372 #define MSR_MAX_RING_RATIO_LIMIT_MASK                                 0x7F
00373 #define MSR_CONFIG_TDP_NOMINAL                                        0x648
00374 #define CONFIG_TDP_NOMINAL_RATIO_MASK                                 0xFF
00375 #define MSR_CONFIG_TDP_LVL1                                           0x649
00376 #define CONFIG_TDP_LVL1_RATIO_OFFSET                                  16
00377 #define CONFIG_TDP_LVL1_RATIO_MASK                                    (0xFF << 16)
00378 #define CONFIG_TDP_LVL1_PKG_TDP_MASK                                  (0x7FFF)
00379 #define MSR_CONFIG_TDP_LVL2                                           0x64A
00380 #define CONFIG_TDP_LVL2_RATIO_OFFSET                                  16
00381 #define CONFIG_TDP_LVL2_RATIO_MASK                                    (0xFF << 16)
00382 #define CONFIG_TDP_LVL2_PKG_TDP_MASK                                  (0x7FFF)
00383 #define MSR_CONFIG_TDP_CONTROL                                        0x64B
00384 #define CONFIG_TDP_CONTROL_LOCK                                       (1 << 31)
00385 #define CONFIG_TDP_CONTROL_LVL_MASK                                   0x3
00386 #define CONFIG_TDP_NOMINAL                                            0
00387 #define CONFIG_TDP_LEVEL1                                             1
00388 #define CONFIG_TDP_LEVEL2                                             2
00389 #define MSR_TURBO_ACTIVATION_RATIO                                    0x64C
00390 #define MSR_TURBO_ACTIVATION_RATIO_LOCK                               (1 << 31)
00391 #define MSR_TURBO_ACTIVATION_RATIO_MASK                               0xFF
00392 #define SMRR_PHYS_BASE                                                0x000001F2
00393 #define SMRR_PHYS_MASK                                                0x000001F3
00394 #define EMRR_PHYS_BASE                                                0x000001F4
00395 #define EMRR_PHYS_MASK                                                0x000001F5
00396 #define B_MSR_EMRR_PHYS_MASK_EN                                       BIT11
00397 #define B_MSR_EMRR_PHYS_MASK_LOCK                                     BIT10
00398 #define V_MAXIMUM_VARIABLE_MTRR_NUMBER                                10
00399 #define CACHE_VARIABLE_MTRR_BASE                                      0x00000200
00400 #define V_FIXED_MTRR_NUMBER                                           11
00401 #define IA32_MTRR_FIX64K_00000                                        0x00000250
00402 #define IA32_MTRR_FIX16K_80000                                        0x00000258
00403 #define IA32_MTRR_FIX16K_A0000                                        0x00000259
00404 #define IA32_MTRR_FIX4K_C0000                                         0x00000268
00405 #define IA32_MTRR_FIX4K_C8000                                         0x00000269
00406 #define IA32_MTRR_FIX4K_D0000                                         0x0000026A
00407 #define IA32_MTRR_FIX4K_D8000                                         0x0000026B
00408 #define IA32_MTRR_FIX4K_E0000                                         0x0000026C
00409 #define IA32_MTRR_FIX4K_E8000                                         0x0000026D
00410 #define IA32_MTRR_FIX4K_F0000                                         0x0000026E
00411 #define IA32_MTRR_FIX4K_F8000                                         0x0000026F
00412 #define MSR_IA32_CR_PAT                                               0x00000277
00413 #define CACHE_IA32_MTRR_DEF_TYPE                                      0x000002FF
00414 #define B_CACHE_MTRR_VALID                                            BIT11
00415 #define B_CACHE_FIXED_MTRR_VALID                                      BIT10
00416 #define NO_EVICT_MODE                                                 0x000002E0
00417 #define B_NO_EVICT_MODE_SETUP                                         BIT0
00418 #define B_NO_EVICT_MODE_RUN                                           BIT1
00419 #define UNCORE_CR_MEMLOCK_COMMANDS                                    0x000002E2
00420 #define B_LOCK_MEM_CFG                                                BIT1
00421 #define EFI_PCIEXBAR                                                  0x00000300
00422 #define B_PCIEXBAR_EN                                                 BIT0
00423 #define B_PCIEXBAR_SIZE                                               (BIT1 | BIT2 | BIT3)
00424 #define N_PCIEXBAR_SIZE                                               1
00425 #define IA32_MC0_CTL                                                  0x00000400
00426 #define IA32_MC0_STATUS                                               0x00000401
00427 #define IA32_MC0_ADDR                                                 0x00000402
00428 #define IA32_MC0_MISC                                                 0x00000403
00429 #define IA32_MC8_CTL                                                  (IA32_MC0_CTL + (8 * 4))
00430 #define IA32_MC5_STATUS                                               (IA32_MC0_STATUS + (5 * 4))
00431 #define IA32_MC6_STATUS                                               (IA32_MC0_STATUS + (6 * 4))
00432 #define IA32_MC7_STATUS                                               (IA32_MC0_STATUS + (7 * 4))
00433 #define IA32_MC8_STATUS                                               (IA32_MC0_STATUS + (8 * 4))
00434 #define MSR_IA32_VMX_BASIC                                            0x00000480
00435 #define MSR_IA32_VMX_MISC                                             0x00000485
00436 #define APIC_GLOBAL_ENABLE                                            0x00000800
00437 #define EXT_XAPIC_LOGICAL_APIC_ID                                     0x00000802
00438 #define EXT_XAPIC_VERSION                                             0x00000803
00439 #define EXT_XAPIC_SVR                                                 0x0000080F
00440 #define EXT_XAPIC_ICR                                                 0x00000830
00441 #define MSR_EXT_XAPIC_LVT_THERM                                       0x00000833
00442 #define EXT_XAPIC_LVT_LINT0                                           0x00000835
00443 #define EXT_XAPIC_LVT_LINT1                                           0x00000836
00444 #define MSR_IA32_DEBUG_INTERFACE                                      0x00000C80
00445 #define B_DEBUG_INTERFACE_ENABLE                                      BIT0
00446 #define B_DEBUG_INTERFACE_LOCK                                        BIT30
00447 #define B_DEBUG_INTERFACE_DEBUG_STATUS                                BIT31
00448 #define NUM_TENTHS_TO_PERCENTAGE                                      1000
00449 #define FIVR_SSC_LOCK_BIT                                             BIT31
00450 #define MAX_FIVR_SSC_PERCENT                                          60
00451 //
00452 // MSRs for SMM State Save Register
00453 //
00454 #define MSR_SMM_MCA_CAP                                               0x17D
00455 #define B_TARGETED_SMI                                                BIT56
00456 #define N_TARGETED_SMI                                                56
00457 #define B_SMM_CPU_SVRSTR                                              BIT57
00458 #define N_SMM_CPU_SVRSTR                                              57
00459 #define B_SMM_CODE_ACCESS_CHK                                         BIT58
00460 #define N_SMM_CODE_ACCESS_CHK                                         58
00461 #define B_LONG_FLOW_INDICATION                                        BIT59
00462 #define N_LONG_FLOW_INDICATION                                        59
00463 #define MSR_SMM_FEATURE_CONTROL                                       0x4E0
00464 #define B_SMM_FEATURE_CONTROL_LOCK                                    BIT0
00465 #define B_SMM_CPU_SAVE_EN                                             BIT1
00466 #define B_SMM_CODE_CHK_EN                                             BIT2
00467 #define MSR_SMM_ENABLE                                                0x4E1
00468 #define MSR_SMM_DELAYED                                               0x4E2
00469 #define MSR_SMM_BLOCKED                                               0x4E3
00470 #define MSR_CR0                                                       0xC00
00471 #define MSR_CR3                                                       0xC01
00472 #define MSR_EFLAGS                                                    0xC02
00473 #define MSR_RIP                                                       0xC04
00474 #define MSR_DR6                                                       0xC05
00475 #define MSR_DR7                                                       0xC06
00476 #define MSR_TR_LDTR                                                   0xC07
00477 #define MSR_GS_FS                                                     0xC08
00478 #define MSR_DS_SS                                                     0xC09
00479 #define MSR_CS_ES                                                     0xC0A
00480 #define MSR_IO_MISC_INFO                                              0xC0B
00481 #define MSR_IO_MEM_ADDR                                               0xC0C
00482 #define MSR_RDI                                                       0xC0D
00483 #define MSR_RSI                                                       0xC0E
00484 #define MSR_RBP                                                       0xC0F
00485 #define MSR_RSP                                                       0xC10
00486 #define MSR_RBX                                                       0xC11
00487 #define MSR_RDX                                                       0xC12
00488 #define MSR_RCX                                                       0xC13
00489 #define MSR_RAX                                                       0xC14
00490 #define MSR_R8                                                        0xC15
00491 #define MSR_R9                                                        0xC16
00492 #define MSR_R10                                                       0xC17
00493 #define MSR_R11                                                       0xC18
00494 #define MSR_R12                                                       0xC19
00495 #define MSR_R13                                                       0xC1A
00496 #define MSR_R14                                                       0xC1B
00497 #define MSR_R15                                                       0xC1C
00498 #define MSR_EVENT_CTL_HLT_IO                                          0xC1F
00499 #define MSR_SMBASE                                                    0xC20
00500 #define MSR_SMM_REVID                                                 0xC21
00501 #define MSR_IEDBASE                                                   0xC22
00502 #define MSR_EPTP_ENABLE                                               0xC23
00503 #define MSR_EPTP                                                      0xC24
00504 #define MSR_LDTR_BASE                                                 0xC2C
00505 #define MSR_IDTR_BASE                                                 0xC2D
00506 #define MSR_GDTR_BASE                                                 0xC2E
00507 #define MSR_CR4                                                       0xC37
00508 #define MSR_IO_RSI                                                    0xC40
00509 #define MSR_IO_RCX                                                    0xC41
00510 #define MSR_IO_RIP                                                    0xC42
00511 #define MSR_IO_RDI                                                    0xC43
00512 #define MSR_BC_PBEC                                                   0x139
00513 #define B_STOP_PBET                                                   BIT0
00514
00515 #define MSR_BOOT_GUARD_SACM_INFO                                      0x13A
00516 #define B_NEM_INIT                                                    BIT0
00517 #define V_TPM_PRESENT_MASK                                            0x06
00518 #define V_TPM_PRESENT_NO_TPM                                          0
00519 #define V_TPM_PRESENT_DTPM_12                                         1
00520 #define V_TPM_PRESENT_DTPM_20                                         2
00521 #define V_TPM_PRESENT_PTT                                             3
00522 #define B_TPM_SUCCESS                                                 BIT3
00523 #define B_MEASURED                                                    BIT5
00524 #define B_VERIFIED                                                    BIT6
00525 #define TXT_PUBLIC_BASE                                               0xFED30000
00526 #define R_CPU_BOOT_GUARD_ERRORCODE                                    0x30
00527 #define R_CPU_BOOT_GUARD_BOOTSTATUS                                   0xA0
00528 #define R_CPU_BOOT_GUARD_ACM_STATUS                                   0x328
00529 #define V_CPU_BOOT_GUARD_LOAD_ACM_SUCCESS                             0x8000000000000000
00530 #define B_BOOT_GUARD_ACM_ERRORCODE_MASK                               0x00007FF0
00531
00532 //
00533 // Processor Definitions
00534 //
00535 #define CPUID_FULL_STEPPING                   0x0000000F
00536 #define CPUID_FULL_FAMILY_MODEL               0x0FFF0FF0
00537 #define CPUID_FULL_FAMILY_MODEL_STEPPING      0x0FFF0FFF
00538 #define CPUID_FULL_FAMILY_MODEL_HASWELL       0x000306C0
00539 #define CPUID_FULL_FAMILY_MODEL_HASWELL_ULT   0x00040650
00540 #define CPUID_FULL_FAMILY_MODEL_CRYSTALWELL   0x00040660
00541
00542 #define CPUID_PROCESSOR_TOPOLOGY              0xB
00543
00544 typedef enum {
00545   EnumCpuHsw     = CPUID_FULL_FAMILY_MODEL_HASWELL,
00546   EnumCpuHswUlt  = CPUID_FULL_FAMILY_MODEL_HASWELL_ULT,
00547   EnumCpuCrw     = CPUID_FULL_FAMILY_MODEL_CRYSTALWELL,
00548   EnumCpuMax     = CPUID_FULL_FAMILY_MODEL
00549 } CPU_FAMILY;
00550
00551 typedef enum {
00555   EnumHswA0         = 1,
00556   EnumHswB0,
00557   EnumHswC0,
00558   EnumHswD0,
00562   EnumHswUltB0      = 0,
00563   EnumHswUltC0,
00567   EnumCrwB0         = 0,
00568   EnumCrwC0,
00569   EnumCrwD0,
00573   EnumCpuSteppingMax  = CPUID_FULL_STEPPING
00574 } CPU_STEPPING;
00575
00576 typedef enum {
00577   EnumCpuUlt        = 0,
00578   EnumCpuTrad,
00579   EnumCpuUnknown
00580 } CPU_SKU;
00581
00582 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: HtBistHob.h File Reference

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Defines | Variables
HtBistHob.h File Reference

GUID used for HT BIST Status HOB entries in the HOB list. More...

Go to the source code of this file.

Defines

#define | EFI_HT_BIST_HOB_GUID

Variables

EFI_GUID | gEfiHtBistHobGuid

Detailed Description

GUID used for HT BIST Status HOB entries in the HOB list.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Definition in file HtBistHob.h.

Define Documentation

#define EFI_HT_BIST_HOB_GUID
Value:
{ \
    0xbe644001, 0xe7d4, 0x48b1, 0xb0, 0x96, 0x8b, 0xa0, 0x47, 0xbc, 0x7a, 0xe7 \
  }

Definition at line 22 of file HtBistHob.h.


2013 SharkBay Processor Reference Code API: HtBistHob.h Source File

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HtBistHob.h
Go to the documentation of this file.
00001
00019 #ifndef _HT_BIST_HOB_GUID_H_
00020 #define _HT_BIST_HOB_GUID_H_
00021
00022 #define EFI_HT_BIST_HOB_GUID \
00023   { \
00024     0xbe644001, 0xe7d4, 0x48b1, 0xb0, 0x96, 0x8b, 0xa0, 0x47, 0xbc, 0x7a, 0xe7 \
00025   }
00026
00027 extern EFI_GUID gEfiHtBistHobGuid;
00028
00029 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: MpService.h File Reference

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MpService.h File Reference

This protocol produces MP Protocol. More...

#include "LinkedList.h"
#include <EFI_PROTOCOL_CONSUMER(SmmBase)>
#include <EFI_PROTOCOL_CONSUMER (CpuIo)>
Include dependency graph for MpService.h:

Go to the source code of this file.

Classes

union | EFI_MP_HEALTH_FLAGS
struct | EFI_MP_HEALTH
struct | PHYSICAL_LOCATION
struct | EFI_MP_PROC_CONTEXT
struct | _EFI_MP_SERVICES_PROTOCOL
This information is basically from Intel Platform Innovation Framework for EFI Multiprocessor Services Protocol Specification. More...

Defines

#define | EFI_MP_SERVICES_PROTOCOL_GUID
#define | DELIVERY_MODE_FIXED 0x0
#define | DELIVERY_MODE_LOWEST_PRIORITY 0x1
#define | DELIVERY_MODE_SMI 0x2
#define | DELIVERY_MODE_REMOTE_READ 0x3
#define | DELIVERY_MODE_NMI 0x4
#define | DELIVERY_MODE_INIT 0x5
#define | DELIVERY_MODE_SIPI 0x6
#define | DELIVERY_MODE_MAX 0x7
#define | TRIGGER_MODE_EDGE 0x0
#define | TRIGGER_MODE_LEVEL 0x1
#define | EFI_MP_HEALTH_FLAGS_STATUS_HEALTHY 0x0
#define | EFI_MP_HEALTH_FLAGS_STATUS_PERFORMANCE_RESTRICTED 0x1
#define | EFI_MP_HEALTH_FLAGS_STATUS_FUNCTIONALLY_RESTRICTED 0x2

Typedefs

typedef EFI_STATUS(* | EFI_MP_SERVICES_GET_GENERAL_MP_INFO )(IN EFI_MP_SERVICES_PROTOCOL *This, OUT UINTN *NumberOfCPUs, OUT UINTN *MaximumNumberOfCPUs, OUT UINTN *NumberOfEnabledCPUs, OUT UINTN *RendezvousIntNumber, OUT UINTN *RendezvousProcLength)
typedef EFI_STATUS(* | EFI_MP_SERVICES_GET_PROCESSOR_CONTEXT )(IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN OUT UINTN *BufferLength, IN OUT EFI_MP_PROC_CONTEXT *ProcessorContextBuffer)
typedef EFI_STATUS(* | EFI_MP_SERVICES_STARTUP_ALL_APS )(IN EFI_MP_SERVICES_PROTOCOL *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroSecs OPTIONAL, IN OUT VOID *ProcArguments OPTIONAL, OUT UINTN *FailedCPUList OPTIONAL)
typedef EFI_STATUS(* | EFI_MP_SERVICES_STARTUP_THIS_AP )(IN EFI_MP_SERVICES_PROTOCOL *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroSecs OPTIONAL, IN OUT VOID *ProcArguments OPTIONAL)
typedef EFI_STATUS(* | EFI_MP_SERVICES_SWITCH_BSP )(IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
typedef EFI_STATUS(* | EFI_MP_SERVICES_SEND_IPI )(IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN UINTN VectorNumber, IN UINTN DeliveryMode)
typedef EFI_STATUS(* | EFI_MP_SERVICES_ENABLEDISABLEAP )(IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN BOOLEAN NewAPState, IN EFI_MP_HEALTH *HealthState)
typedef EFI_STATUS(* | EFI_MP_SERVICES_WHOAMI )(IN EFI_MP_SERVICES_PROTOCOL *This, OUT UINTN *ProcessorNumber)

Enumerations

enum | EFI_CPU_DESIGNATION

Functions

EFI_FORWARD_DECLARATION (EFI_MP_SERVICES_PROTOCOL)

Variables

EFI_GUID | gEfiMpServiceProtocolGuid

Detailed Description

This protocol produces MP Protocol.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Definition in file MpService.h.

Define Documentation

#define EFI_MP_SERVICES_PROTOCOL_GUID
Value:
{ \
    0xf33261e7, 0x23cb, 0x11d5, 0xbd, 0x5c, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
  }

Definition at line 28 of file MpService.h.


2013 SharkBay Processor Reference Code API: MpService.h Source File

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MpService.h
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00001
00019 #ifndef _MP_H_
00020 #define _MP_H_
00021
00022 #include "LinkedList.h"
00023
00024 #include EFI_PROTOCOL_CONSUMER(SmmBase) // added for EFI_AP_PROCEDURE
00025
00026 #include EFI_PROTOCOL_CONSUMER (CpuIo)
00027
00028 #define EFI_MP_SERVICES_PROTOCOL_GUID \
00029   { \
00030     0xf33261e7, 0x23cb, 0x11d5, 0xbd, 0x5c, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
00031   }
00032
00033 EFI_FORWARD_DECLARATION (EFI_MP_SERVICES_PROTOCOL);
00034
00035 #ifndef DELIVERY_MODE_FIXED
00036 #define DELIVERY_MODE_FIXED           0x0
00037 #define DELIVERY_MODE_LOWEST_PRIORITY 0x1
00038 #define DELIVERY_MODE_SMI             0x2
00039 #define DELIVERY_MODE_REMOTE_READ     0x3
00040 #define DELIVERY_MODE_NMI             0x4
00041 #define DELIVERY_MODE_INIT            0x5
00042 #define DELIVERY_MODE_SIPI            0x6
00043 #define DELIVERY_MODE_MAX             0x7
00044
00045 #define TRIGGER_MODE_EDGE             0x0
00046 #define TRIGGER_MODE_LEVEL            0x1
00047 #endif
00048
00049 typedef union {
00050   struct {
00051     UINT32 Status                   : 2;
00052     UINT32 Tested                   : 1;
00053     UINT32 Reserved1                : 13;
00054     UINT32 VirtualMemoryUnavailable : 1;
00055     UINT32 Ia32ExecutionUnavailable : 1;
00056     UINT32 FloatingPointUnavailable : 1;
00057     UINT32 MiscFeaturesUnavailable  : 1;
00058     UINT32 Reserved2                : 12;
00059   } Bits;
00060   UINT32 Uint32;
00061 } EFI_MP_HEALTH_FLAGS;
00062
00063 #define EFI_MP_HEALTH_FLAGS_STATUS_HEALTHY                  0x0
00064 #define EFI_MP_HEALTH_FLAGS_STATUS_PERFORMANCE_RESTRICTED   0x1
00065 #define EFI_MP_HEALTH_FLAGS_STATUS_FUNCTIONALLY_RESTRICTED  0x2
00066
00067 typedef struct {
00068   EFI_MP_HEALTH_FLAGS Flags;
00069   UINT32              TestStatus;
00070 } EFI_MP_HEALTH;
00071
00072 typedef enum {
00073   EfiCpuAP                = 0,
00074   EfiCpuBSP,
00075   EfiCpuDesignationMaximum
00076 } EFI_CPU_DESIGNATION;
00077
00078 typedef struct {
00079   UINT32 Package;
00080   UINT32 Die;
00081   UINT32 Core;
00082   UINT32 Thread;
00083 } PHYSICAL_LOCATION;
00084
00085 typedef struct {
00086   UINT32              ApicID;
00087   BOOLEAN             Enabled;
00088   EFI_CPU_DESIGNATION Designation;
00089   EFI_MP_HEALTH       Health;
00090   UINTN               PackageNumber;
00091   UINTN               NumberOfCores;
00092   UINTN               NumberOfThreads;
00093   UINT64              ProcessorPALCompatibilityFlags;
00094   UINT64              ProcessorTestMask;
00095 } EFI_MP_PROC_CONTEXT;
00096
00097 typedef
00098 EFI_STATUS
00099 (EFIAPI *EFI_MP_SERVICES_GET_GENERAL_MP_INFO)(
00100   IN EFI_MP_SERVICES_PROTOCOL *This,
00101   OUT UINTN                   *NumberOfCPUs,
00102   OUT UINTN                   *MaximumNumberOfCPUs,
00103   OUT UINTN                   *NumberOfEnabledCPUs,
00104   OUT UINTN                   *RendezvousIntNumber,
00105   OUT UINTN                   *RendezvousProcLength
00106   );
00107
00108 typedef
00109 EFI_STATUS
00110 (EFIAPI *EFI_MP_SERVICES_GET_PROCESSOR_CONTEXT)(
00111   IN EFI_MP_SERVICES_PROTOCOL *This,
00112   IN UINTN                    ProcessorNumber,
00113   IN OUT UINTN                *BufferLength,
00114   IN OUT EFI_MP_PROC_CONTEXT  *ProcessorContextBuffer
00115   );
00116
00117 typedef
00118 EFI_STATUS
00119 (EFIAPI *EFI_MP_SERVICES_STARTUP_ALL_APS)(
00120   IN EFI_MP_SERVICES_PROTOCOL *This,
00121   IN EFI_AP_PROCEDURE         Procedure,
00122   IN BOOLEAN                  SingleThread,
00123   IN EFI_EVENT WaitEvent      OPTIONAL,
00124   IN UINTN TimeoutInMicroSecs OPTIONAL,
00125   IN OUT VOID *ProcArguments  OPTIONAL,
00126   OUT UINTN *FailedCPUList    OPTIONAL
00127   );
00128
00129 typedef
00130 EFI_STATUS
00131 (EFIAPI *EFI_MP_SERVICES_STARTUP_THIS_AP)(
00132   IN EFI_MP_SERVICES_PROTOCOL *This,
00133   IN EFI_AP_PROCEDURE         Procedure,
00134   IN UINTN                    ProcessorNumber,
00135   IN EFI_EVENT WaitEvent      OPTIONAL,
00136   IN UINTN TimeoutInMicroSecs OPTIONAL,
00137   IN OUT VOID *ProcArguments  OPTIONAL
00138   );
00139
00140 typedef
00141 EFI_STATUS
00142 (EFIAPI *EFI_MP_SERVICES_SWITCH_BSP)(
00143   IN EFI_MP_SERVICES_PROTOCOL *This,
00144   IN UINTN                    ProcessorNumber,
00145   IN BOOLEAN                  EnableOldBSP
00146   );
00147
00148 typedef
00149 EFI_STATUS
00150 (EFIAPI *EFI_MP_SERVICES_SEND_IPI)(
00151   IN EFI_MP_SERVICES_PROTOCOL *This,
00152   IN UINTN                    ProcessorNumber,
00153   IN UINTN                    VectorNumber,
00154   IN UINTN                    DeliveryMode
00155   );
00156
00157 typedef
00158 EFI_STATUS
00159 (EFIAPI *EFI_MP_SERVICES_ENABLEDISABLEAP)(
00160   IN EFI_MP_SERVICES_PROTOCOL *This,
00161   IN UINTN                    ProcessorNumber,
00162   IN BOOLEAN                  NewAPState,
00163   IN EFI_MP_HEALTH            *HealthState
00164   );
00165
00166 typedef
00167 EFI_STATUS
00168 (EFIAPI *EFI_MP_SERVICES_WHOAMI)(
00169   IN EFI_MP_SERVICES_PROTOCOL *This,
00170   OUT UINTN                   *ProcessorNumber
00171   );
00172
00178 struct _EFI_MP_SERVICES_PROTOCOL {
00182   EFI_MP_SERVICES_GET_GENERAL_MP_INFO   GetGeneralMPInfo;
00186   EFI_MP_SERVICES_GET_PROCESSOR_CONTEXT GetProcessorContext;
00190   EFI_MP_SERVICES_STARTUP_ALL_APS       StartupAllAPs;
00194   EFI_MP_SERVICES_STARTUP_THIS_AP       StartupThisAP;
00198   EFI_MP_SERVICES_SWITCH_BSP            SwitchBSP;
00202   EFI_MP_SERVICES_SEND_IPI              SendIPI;
00206   EFI_MP_SERVICES_ENABLEDISABLEAP       EnableDisableAP;
00211   EFI_MP_SERVICES_WHOAMI                WhoAmI;
00212 };
00213
00214 extern EFI_GUID gEfiMpServiceProtocolGuid;
00215
00216 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: OverclockingLibrary.h File Reference

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OverclockingLibrary.h File Reference

Header file for Cpu Platform Lib implementation. More...

#include "EdkIIGlueBase.h"
Include dependency graph for OverclockingLibrary.h:

Go to the source code of this file.

Classes

struct | OC_LIBRARY_COMMAND
OC Library structures. More...
union | _OC_MAILBOX_COMMAND
struct | _OC_MAILBOX_ITEM
struct | VOLTAGE_FREQUENCY_SETTINGS
struct | VOLTAGE_FREQUENCY_ITEM
struct | SVID_CONFIG_ITEM
struct | OC_CAPABILITIES_ITEM
struct | CORE_RATIO_LIMITS_ITEM
struct | GLOBAL_CONFIG_ITEM
struct | VF_MAILBOX_COMMAND_DATA

Defines

#define | MSR_OC_MAILBOX 0x00000150
#define | OC_LIB_WAIT_TIMEOUT 5000
5 milliseconds
#define | OC_LIB_CMD_GET_OC_CAPABILITIES 0x01
#define | OC_LIB_CMD_GET_PER_CORE_RATIO_LIMIT 0x02
#define | OC_LIB_CMD_GET_VOLTAGE_FREQUENCY 0x10
#define | OC_LIB_CMD_SET_VOLTAGE_FREQUENCY 0x11
#define | OC_LIB_CMD_GET_SVID_CONFIG 0x12
#define | OC_LIB_CMD_SET_SVID_CONFIG 0x13
#define | OC_LIB_CMD_GET_GLOBAL_CONFIG 0x14
#define | OC_LIB_CMD_SET_GLOBAL_CONFIG 0x15
#define | OC_LIB_COMPLETION_CODE_SUCCESS 0x00
#define | OC_LIB_COMPLETION_CODE_OC_LOCKED 0x01
#define | OC_LIB_COMPLETION_CODE_INVALID_DOMAIN 0x02
#define | OC_LIB_COMPLETION_CODE_MAX_RATIO_EXCEEDED 0x03
#define | OC_LIB_COMPLETION_CODE_MAX_VOLTAGE_EXCEEDED 0x04
#define | OC_LIB_COMPLETION_CODE_OC_NOT_SUPPORTED 0x05
#define | OC_LIB_COMPLETION_CODE_WRITE_FAILED 0x06
#define | OC_LIB_COMPLETION_CODE_READ_FAILED 0x07
#define | OC_LIB_DOMAIN_ID_IA_CORE 0x00
#define | OC_LIB_DOMAIN_ID_GT 0x01
#define | OC_LIB_DOMAIN_ID_CLR 0x02
#define | OC_LIB_DOMAIN_ID_UNCORE 0x03
#define | OC_LIB_DOMAIN_ID_IOA 0x04
#define | OC_LIB_DOMAIN_ID_IOD 0x05
#define | FIXED_POINT_SIGN_BIT_MASK 0x0400
#define | INT16_SIGN_BIT_MASK 0x8000
#define | MILLIVOLTS_PER_VOLT 1000
#define | MAX_TARGET_MV 4095
#define | MAX_OFFSET_MV 500
#define | CONVERT_TO_FIXED_POINT_VOLTS 0
#define | CONVERT_TO_BINARY_MILLIVOLT 1
#define | BIT0_MASK 0x1
#define | MAX_RATIO_MASK 0x000000FF
#define | VOLTAGE_TARGET_MASK 0x000FFF00
#define | VOLTAGE_TARGET_OFFSET 8
#define | VOLTAGE_MODE_MASK 0x00100000
#define | VOLTAGE_MODE_OFFSET 20
#define | VOLTAGE_OFFSET_MASK 0xFFE00000
#define | VOLTAGE_OFFSET_OFFSET 21
#define | SVID_DISABLE_MASK 0x80000000
#define | SVID_DISABLE_OFFSET 31
#define | SVID_VOLTAGE_MASK 0x00000FFF
#define | FIVR_FAULTS_MASK 0x00000001
#define | FIVR_EFFICIENCY_MASK 0x00000002
#define | FIVR_EFFICIENCY_OFFSET 1
#define | OC_CAPS_MAX_RATIO_MASK 0x000000FF
#define | OC_CAPS_RATIO_SUPPORT_MASK 0x00000100
#define | OC_CAPS_RATIO_SUPPORT_OFFSET 8
#define | OC_CAPS_OVERRIDE_SUPPORT_MASK 0x00000200
#define | OC_CAPS_OVERRIDE_SUPPORT_OFFSET 9
#define | OC_CAPS_OFFSET_SUPPORT_MASK 0x00000400
#define | OC_CAPS_OFFSET_SUPPORT_OFFSET 10
#define | OC_LIB_OFFSET_ADAPTIVE 0
#define | OC_LIB_OFFSET_OVERRIDE 1
#define | OC_LIB_VOLTAGE_DO_NOT_UPDATE 0xFFFF

Typedefs

typedef union _OC_MAILBOX_COMMAND | OC_MAILBOX_COMMAND
typedef struct _OC_MAILBOX_ITEM | OC_MAILBOX_ITEM

Enumerations

enum | CPU_DOMAIN_ID

Functions

EFI_STATUS | GetVoltageFrequencyItem (OUT VOLTAGE_FREQUENCY_ITEM *VfSettings, OUT UINT32 *LibStatus)
OC Library Function Prototypes.
EFI_STATUS | SetVoltageFrequencyItem (IN VOLTAGE_FREQUENCY_ITEM VfSettings, OUT UINT32 *LibStatus)
Sets the Voltage and Frequency information for a given CPU domain.
EFI_STATUS | GetFivrConfig (OUT GLOBAL_CONFIG_ITEM *FivrConfig, OUT UINT32 *LibStatus)
Get the global FIVR Configuration information.
EFI_STATUS | SetFivrConfig (IN GLOBAL_CONFIG_ITEM FivrConfig, OUT UINT32 *LibStatus)
Set the Global FIVR Configuration information.
EFI_STATUS | GetSvidConfig (OUT SVID_CONFIG_ITEM *SvidConfig, OUT UINT32 *LibStatus)
Get the SVID Configuration information.
EFI_STATUS | SetSvidConfig (IN SVID_CONFIG_ITEM SvidConfig, OUT UINT32 *LibStatus)
Set the SVID Configuration information.
EFI_STATUS | GetOcCapabilities (OUT OC_CAPABILITIES_ITEM *OcCapabilities, OUT UINT32 *LibStatus)
Get the overclocking capabilities for a given CPU Domain.
VOID | ConvertVoltageTarget (IN UINT16 InputVoltageTarget, OUT UINT16 *OutputVoltageTarget, IN UINT8 ConversionType)
Converts the input voltage target to the fixed point U12.2.10 Volt format or the Binary millivolts representation based on the ConversionType.
VOID | ConvertVoltageOffset (IN INT16 InputVoltageOffset, OUT INT16 *OutputVoltageOffset, IN UINT8 ConversionType)
Converts the input votlage Offset to the fixed point S11.0.10 Volt format or to Binary illivolts representation based on the ConversionType.
VOID | ConvertToMailboxFormat (IN VOID *InputData, OUT OC_MAILBOX_ITEM *MailboxData, IN UINT32 CommandId)
Converts the input data to valid mailbox command format based on CommandID.

Detailed Description

Header file for Cpu Platform Lib implementation.

Copyright:
Copyright (c) 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement

Definition in file OverclockingLibrary.h.

Function Documentation

VOID ConvertToMailboxFormat | ( | IN VOID * | InputData,
 |  | OUT OC_MAILBOX_ITEM * | MailboxData,
 |  | IN UINT32 | CommandId
 | ) |  |

Converts the input data to valid mailbox command format based on CommandID.

Parameters:
IN] | InputData
OUT] | *MailboxData
IN] | CommandId
VOID ConvertVoltageOffset | ( | IN INT16 | InputVoltageOffset,
 |  | OUT INT16 * | OutputVoltageOffset,
 |  | IN UINT8 | ConversionType
 | ) |  |

Converts the input votlage Offset to the fixed point S11.0.10 Volt format or to Binary illivolts representation based on the ConversionType.

Parameters:
IN] | InputVoltageTarget
OUT] | *OutputVoltageTarget
IN] | ConversionType - 0:fixed point, 1:Signed Binary millivolts
VOID ConvertVoltageTarget | ( | IN UINT16 | InputVoltageTarget,
 |  | OUT UINT16 * | OutputVoltageTarget,
 |  | IN UINT8 | ConversionType
 | ) |  |

Converts the input voltage target to the fixed point U12.2.10 Volt format or the Binary millivolts representation based on the ConversionType.

Parameters:
IN] | InputVoltageTarget
OUT] | *OutputVoltageTarget
IN] | ConversionType - 0:fixed point, 1:Binary millivolts
EFI_STATUS GetFivrConfig | ( | OUT GLOBAL_CONFIG_ITEM * | FivrConfig,
 |  | OUT UINT32 * | LibStatus
 | ) |  |

Get the global FIVR Configuration information.

Parameters:
OUT] | *FivrConfig
OUT] | *LibStatus
Return values:
EFI_STATUS
EFI_STATUS GetOcCapabilities | ( | OUT OC_CAPABILITIES_ITEM * | OcCapabilities,
 |  | OUT UINT32 * | LibStatus
 | ) |  |

Get the overclocking capabilities for a given CPU Domain.

Parameters:
OUT] | *OcCapabilities
OUT] | *LibStatus
Return values:
EFI_STATUS
EFI_STATUS GetSvidConfig | ( | OUT SVID_CONFIG_ITEM * | SvidConfig,
 |  | OUT UINT32 * | LibStatus
 | ) |  |

Get the SVID Configuration information.

Parameters:
OUT] | *SvidConfig
OUT] | *LibStatus
Return values:
EFI_STATUS
EFI_STATUS GetVoltageFrequencyItem | ( | OUT VOLTAGE_FREQUENCY_ITEM * | VfSettings,
 |  | OUT UINT32 * | LibStatus
 | ) |  |

OC Library Function Prototypes.

Gets the Voltage and Frequency information for a given CPU domain

Parameters:
OUT] | *VfSettings
OUT] | *LibStatus
Return values:
EFI_STATUS
EFI_STATUS SetFivrConfig | ( | IN GLOBAL_CONFIG_ITEM | FivrConfig,
 |  | OUT UINT32 * | LibStatus
 | ) |  |

Set the Global FIVR Configuration information.

Parameters:
IN] | FivrConfig
OUT] | *LibStatus
Return values:
EFI_STATUS
EFI_STATUS SetSvidConfig | ( | IN SVID_CONFIG_ITEM | SvidConfig,
 |  | OUT UINT32 * | LibStatus
 | ) |  |

Set the SVID Configuration information.

Parameters:
IN] | SvidConfig
OUT] | *LibStatus
Return values:
EFI_STATUS
EFI_STATUS SetVoltageFrequencyItem | ( | IN VOLTAGE_FREQUENCY_ITEM | VfSettings,
 |  | OUT UINT32 * | LibStatus
 | ) |  |

Sets the Voltage and Frequency information for a given CPU domain.

Parameters:
IN] | *VfSettings
OUT] | *LibStatus
Return values:
EFI_STATUS
Generated on Thu Jun 20 2013 01:47:38 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: OverclockingLibrary.h Source File

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OverclockingLibrary.h
Go to the documentation of this file.
00001
00019 #ifndef _OVERCLOCKING_LIBRARY_H_
00020 #define _OVERCLOCKING_LIBRARY_H_
00021
00022 #if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
00023 #include "EdkIIGlueBase.h"
00024 #endif
00025
00026 //
00027 //  OC Mailbox MSR
00028 //
00029 #define MSR_OC_MAILBOX        0x00000150
00030 #define OC_LIB_WAIT_TIMEOUT   5000                     ///< 5 milliseconds
00031
00032 //
00033 //  OC Mailbox commands
00034 //
00035 #define OC_LIB_CMD_GET_OC_CAPABILITIES              0x01
00036 #define OC_LIB_CMD_GET_PER_CORE_RATIO_LIMIT         0x02
00037 #define OC_LIB_CMD_GET_VOLTAGE_FREQUENCY            0x10
00038 #define OC_LIB_CMD_SET_VOLTAGE_FREQUENCY            0x11
00039 #define OC_LIB_CMD_GET_SVID_CONFIG                  0x12
00040 #define OC_LIB_CMD_SET_SVID_CONFIG                  0x13
00041 #define OC_LIB_CMD_GET_GLOBAL_CONFIG                0x14
00042 #define OC_LIB_CMD_SET_GLOBAL_CONFIG                0x15
00043
00044 //
00045 //  OC Mailbox completion codes
00046 //
00047 #define OC_LIB_COMPLETION_CODE_SUCCESS              0x00
00048 #define OC_LIB_COMPLETION_CODE_OC_LOCKED            0x01
00049 #define OC_LIB_COMPLETION_CODE_INVALID_DOMAIN       0x02
00050 #define OC_LIB_COMPLETION_CODE_MAX_RATIO_EXCEEDED   0x03
00051 #define OC_LIB_COMPLETION_CODE_MAX_VOLTAGE_EXCEEDED 0x04
00052 #define OC_LIB_COMPLETION_CODE_OC_NOT_SUPPORTED     0x05
00053 #define OC_LIB_COMPLETION_CODE_WRITE_FAILED         0x06
00054 #define OC_LIB_COMPLETION_CODE_READ_FAILED          0x07
00055
00056 //
00057 // Domain ID definitions
00058 //
00059 #define OC_LIB_DOMAIN_ID_IA_CORE    0x00
00060 #define OC_LIB_DOMAIN_ID_GT         0x01
00061 #define OC_LIB_DOMAIN_ID_CLR        0x02
00062 #define OC_LIB_DOMAIN_ID_UNCORE     0x03
00063 #define OC_LIB_DOMAIN_ID_IOA        0x04
00064 #define OC_LIB_DOMAIN_ID_IOD        0x05
00065
00066 //
00067 // Bit 10 is the S11.0.10V sign bit
00068 //
00069 #define FIXED_POINT_SIGN_BIT_MASK 0x0400
00070 #define INT16_SIGN_BIT_MASK       0x8000
00071
00072 //
00073 //  Voltage Conversion defines
00074 //
00075 #define MILLIVOLTS_PER_VOLT  1000
00076 #define MAX_TARGET_MV      4095
00077 #define MAX_OFFSET_MV      500
00078
00079 #define CONVERT_TO_FIXED_POINT_VOLTS  0
00080 #define CONVERT_TO_BINARY_MILLIVOLT   1
00081
00082 //
00083 // Masks and offsets
00084 //
00085 #define BIT0_MASK             0x1
00086 #define MAX_RATIO_MASK        0x000000FF
00087 #define VOLTAGE_TARGET_MASK   0x000FFF00
00088 #define VOLTAGE_TARGET_OFFSET 8
00089 #define VOLTAGE_MODE_MASK     0x00100000
00090 #define VOLTAGE_MODE_OFFSET   20
00091 #define VOLTAGE_OFFSET_MASK   0xFFE00000
00092 #define VOLTAGE_OFFSET_OFFSET 21
00093
00094 #define SVID_DISABLE_MASK     0x80000000
00095 #define SVID_DISABLE_OFFSET   31
00096 #define SVID_VOLTAGE_MASK     0x00000FFF
00097
00098 #define FIVR_FAULTS_MASK        0x00000001
00099 #define FIVR_EFFICIENCY_MASK    0x00000002
00100 #define FIVR_EFFICIENCY_OFFSET  1
00101
00102 #define OC_CAPS_MAX_RATIO_MASK          0x000000FF
00103 #define OC_CAPS_RATIO_SUPPORT_MASK      0x00000100
00104 #define OC_CAPS_RATIO_SUPPORT_OFFSET    8
00105 #define OC_CAPS_OVERRIDE_SUPPORT_MASK   0x00000200
00106 #define OC_CAPS_OVERRIDE_SUPPORT_OFFSET 9
00107 #define OC_CAPS_OFFSET_SUPPORT_MASK     0x00000400
00108 #define OC_CAPS_OFFSET_SUPPORT_OFFSET   10
00109
00110 //
00111 // Voltage offset definitions
00112 //
00113 #define OC_LIB_OFFSET_ADAPTIVE  0
00114 #define OC_LIB_OFFSET_OVERRIDE  1
00115 #define OC_LIB_VOLTAGE_DO_NOT_UPDATE  0xFFFF
00116
00120 typedef struct {
00121   UINT32 CommandData;
00122   UINT8  CommandCompletion : 8;
00123   UINT8  Param1            : 8;
00124   UINT8  Param2            : 8;
00125   UINT8  Reserved          : 7;
00126   UINT8  RunBusy           : 1;
00127 } OC_LIBRARY_COMMAND;
00128
00129 typedef union _OC_MAILBOX_COMMAND {
00130   UINT32 InterfaceData;
00131   struct {
00132     UINT8 CommandCompletion : 8;
00133     UINT8 Param1            : 8;
00134     UINT8 Param2            : 8;
00135     UINT8 Reserved          : 7;
00136     UINT8 RunBusy           : 1;
00137   } Fields;
00138 } OC_MAILBOX_COMMAND;
00139
00140 typedef struct _OC_MAILBOX_ITEM {
00141   UINT32             Data;
00142   OC_MAILBOX_COMMAND Interface;
00143 } OC_MAILBOX_ITEM;
00144
00145 typedef struct {
00146   UINT8  MaxOcRatio;
00147   UINT8  VoltageTargetMode;
00148   UINT16 VoltageTarget;
00149   INT16  VoltageOffset;
00150 } VOLTAGE_FREQUENCY_SETTINGS;
00151
00152 typedef struct {
00153   VOLTAGE_FREQUENCY_SETTINGS VfSettings;
00154   UINT8                      DomainId;
00155 } VOLTAGE_FREQUENCY_ITEM;
00156
00157 typedef enum {
00158   IaCore,
00159   Gt,
00160   Clr,
00161   Uncore
00162 } CPU_DOMAIN_ID;
00163
00164 typedef struct {
00165   UINT16  VoltageTarget;
00166   BOOLEAN SvidDisable;
00167 } SVID_CONFIG_ITEM;
00168
00169 typedef struct {
00170   UINT8   MaxOcRatioLimit;
00171   BOOLEAN RatioOcSupported;
00172   BOOLEAN VoltageOverridesSupported;
00173   BOOLEAN VoltageOffsetSupported;
00174   UINT8   DomainId;
00175 } OC_CAPABILITIES_ITEM;
00176
00177 typedef struct {
00178   UINT8 MaxOcRatioLimit1C;
00179   UINT8 MaxOcRatioLimit2C;
00180   UINT8 MaxOcRatioLimit3C;
00181   UINT8 MaxOcRatioLimit4C;
00182   UINT8 Index;
00183 } CORE_RATIO_LIMITS_ITEM;
00184
00185 typedef struct {
00186   UINT8 DisableFivrFaults;
00187   UINT8 DisableFivrEfficiency;
00188 } GLOBAL_CONFIG_ITEM;
00189
00190 typedef struct {
00191   UINT32 MaxOcRatio       : 8;
00192   UINT32 VoltageTargetU12 : 12;
00193   UINT32 TargetMode       : 1;
00194   UINT32 VoltageOffsetS11 : 11;
00195 } VF_MAILBOX_COMMAND_DATA;
00196
00200 EFI_STATUS
00201 EFIAPI GetVoltageFrequencyItem (
00202   OUT VOLTAGE_FREQUENCY_ITEM *VfSettings,
00203   OUT UINT32                 *LibStatus
00204   )
00213 ;
00214
00215 EFI_STATUS
00216 EFIAPI SetVoltageFrequencyItem (
00217   IN VOLTAGE_FREQUENCY_ITEM VfSettings,
00218   OUT UINT32                *LibStatus
00219   )
00228 ;
00229
00230 EFI_STATUS
00231 EFIAPI GetFivrConfig (
00232   OUT GLOBAL_CONFIG_ITEM *FivrConfig,
00233   OUT UINT32             *LibStatus
00234   )
00243 ;
00244
00245 EFI_STATUS
00246 EFIAPI SetFivrConfig (
00247   IN GLOBAL_CONFIG_ITEM FivrConfig,
00248   OUT UINT32            *LibStatus
00249   )
00258 ;
00259
00260 EFI_STATUS
00261 EFIAPI GetSvidConfig (
00262   OUT SVID_CONFIG_ITEM *SvidConfig,
00263   OUT UINT32           *LibStatus
00264   )
00273 ;
00274
00275 EFI_STATUS
00276 EFIAPI SetSvidConfig (
00277   IN SVID_CONFIG_ITEM SvidConfig,
00278   OUT UINT32          *LibStatus
00279   )
00288 ;
00289
00290 EFI_STATUS
00291 EFIAPI GetOcCapabilities (
00292   OUT OC_CAPABILITIES_ITEM *OcCapabilities,
00293   OUT UINT32               *LibStatus
00294   )
00303 ;
00304
00305 VOID
00306 ConvertVoltageTarget (
00307   IN UINT16  InputVoltageTarget,
00308   OUT UINT16 *OutputVoltageTarget,
00309   IN UINT8   ConversionType
00310   )
00319 ;
00320
00321 VOID
00322 ConvertVoltageOffset (
00323   IN INT16  InputVoltageOffset,
00324   OUT INT16 *OutputVoltageOffset,
00325   IN UINT8  ConversionType
00326   )
00335 ;
00336
00337 VOID
00338 ConvertToMailboxFormat (
00339   IN VOID             *InputData,
00340   OUT OC_MAILBOX_ITEM *MailboxData,
00341   IN UINT32           CommandId
00342   )
00350 ;
00351
00352 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: Pfat.h File Reference

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Classes | Defines | Typedefs | Variables
Pfat.h File Reference

This file defines the PFAT Protocol which implements the Intel(R) PFAT Host Controller Compatibility Interface. More...

Go to the source code of this file.

Classes

struct | _PFAT_PROTOCOL
This protocol provides all the services required for flash writes/erases via PFAT PFAT Module can only be launched from SMM, this means that all flash writes & erases that BIOS needs to do must flow thru SMI Handler and so dependency on SMM_BASE_PROTOCOL for installing PFAT Protocol. More...

Defines

#define | SMM_PFAT_PROTOCOL_GUID
GUID to locate PFAT SMM Protocol.

Typedefs

typedef struct _PFAT_PROTOCOL | PFAT_PROTOCOL
typedef EFI_STATUS(* | PFAT_EXECUTE )(IN PFAT_PROTOCOL *This, IN BOOLEAN BiosUpdate)
This service will write PFAT_DIRECTORY MSR and invoke the PFAT Module by writing to PLAT_FRMW_PROT_TRIGGER MSR for writing/erasing to flash.
typedef VOID(* | PFAT_WRITE )(IN PFAT_PROTOCOL *This, IN UINTN Address, IN UINT32 DataByteCount, IN OUT UINT8 *Buffer)
This service fills PFAT script buffer for flash writes.
typedef VOID(* | PFAT_ERASE )(IN PFAT_PROTOCOL *This, IN UINTN Address)
This service fills PFAT script buffer for erasing blocks in flash.

Variables

EFI_GUID | gSmmPfatProtocolGuid
Extern the GUID for protocol users.

Detailed Description

This file defines the PFAT Protocol which implements the Intel(R) PFAT Host Controller Compatibility Interface.

Copyright:
Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement

Definition in file Pfat.h.

Define Documentation

#define SMM_PFAT_PROTOCOL_GUID
Value:
{ \
    0xc3e156e4, 0x27b3, 0x4dff, 0xb8, 0x96, 0xfb, 0x11, 0x3b, 0x2e, 0x68, 0xb5 \
  }

GUID to locate PFAT SMM Protocol.

Definition at line 27 of file Pfat.h.

Typedef Documentation

typedef VOID( * PFAT_ERASE)(IN PFAT_PROTOCOL *This, IN UINTN Address)

This service fills PFAT script buffer for erasing blocks in flash.

BIOS should invoke this function prior to calling PFAT_PROTOCOL.Execute() with all the relevant data required for flash erase. This function will not invoke PFAT module, only create script required for erasing each block in the flash. This function would be called by runtime driver, please do not use any MMIO macro here.

Parameters:
[in] | This | Pointer to the PFAT_PROTOCOL instance.
[in] | Address | This value specifies the offset from the start of the SPI Flash component where BIOS Image is located.

Definition at line 111 of file Pfat.h.

typedef EFI_STATUS( * PFAT_EXECUTE)(IN PFAT_PROTOCOL *This, IN BOOLEAN BiosUpdate)

This service will write PFAT_DIRECTORY MSR and invoke the PFAT Module by writing to PLAT_FRMW_PROT_TRIGGER MSR for writing/erasing to flash.

BIOS should invoke PFAT_PROTOCOL.Write() or PFAT_PROTOCOL.Erase() function prior to calling PFAT_PROTOCOL.Execute() for flash writes/erases (except for BiosUpdate). Write()/Erase() function will render PFAT script during execution. Execute() function will implement the following steps:

  1. Update PFAT directory with address of PUP.
  2. All the AP's except the master thread are put to sleep.
  3. PFAT module is invoked from BSP to execute desired operation. If BiosUpdate flag is set to true, PUP (PUP Header + PFAT Script + Update data) is part of data that is passed to SMI Handler. SMI Handler invokes PFAT module to process the update. This function would be called by runtime driver, please do not use any MMIO macro here.
Parameters:
[in] | This | Pointer to the PFAT_PROTOCOL instance.
[in] | BiosUpdate | Flag to indicate flash update is requested by the Tool
Return values:
EFI_SUCCESS | Successfully completed flash operation.
EFI_INVALID_PARAMETER | The parameters specified are not valid.
EFI_UNSUPPORTED | The CPU or SPI memory is not supported.
EFI_DEVICE_ERROR | Device error, command aborts abnormally.

Definition at line 75 of file Pfat.h.

typedef VOID( * PFAT_WRITE)(IN PFAT_PROTOCOL *This, IN UINTN Address, IN UINT32 DataByteCount, IN OUT UINT8 *Buffer)

This service fills PFAT script buffer for flash writes.

BIOS should invoke this function prior to calling PFAT_PROTOCOL.Execute() with all the relevant data required for flash write. This function will not invoke PFAT Module, only create script required for writing to flash. This function would be called by runtime driver, please do not use any MMIO macro here.

Parameters:
[in] | This | Pointer to the PFAT_PROTOCOL instance.
[in] | Address | This value specifies the offset from the start of the SPI Flash component where BIOS Image is located.
[in] | DataByteCount | Number of bytes in the data portion.
[in] | Buffer | Pointer to caller-allocated buffer containing the dada sent.

Definition at line 93 of file Pfat.h.


2013 SharkBay Processor Reference Code API: Pfat.h Source File

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Pfat.h
Go to the documentation of this file.
00001
00020 #ifndef _PFAT_H_
00021 #define _PFAT_H_
00022
00023 #if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
00024
00025
00026
00027 #define SMM_PFAT_PROTOCOL_GUID \
00028   { \
00029     0xc3e156e4, 0x27b3, 0x4dff, 0xb8, 0x96, 0xfb, 0x11, 0x3b, 0x2e, 0x68, 0xb5 \
00030   }
00031 #else
00032
00033
00034
00035 #define SMM_PFAT_PROTOCOL_GUID \
00036   { \
00037     0xc3e156e4, 0x27b3, 0x4dff, \
00038     { \
00039       0xb8, 0x96, 0xfb, 0x11, 0x3b, 0x2e, 0x68, 0xb5 \
00040     } \
00041   }
00042 #endif
00043
00047 extern EFI_GUID gSmmPfatProtocolGuid;
00048
00049 //
00050 // Forward reference for ANSI C compatibility
00051 //
00052 typedef struct _PFAT_PROTOCOL PFAT_PROTOCOL;
00053
00073 typedef
00074 EFI_STATUS
00075 (EFIAPI *PFAT_EXECUTE)(
00076   IN PFAT_PROTOCOL *This,
00077   IN BOOLEAN       BiosUpdate
00078   );
00079
00091 typedef
00092 VOID
00093 (EFIAPI *PFAT_WRITE)(
00094   IN PFAT_PROTOCOL *This,
00095   IN UINTN         Address,
00096   IN UINT32        DataByteCount,
00097   IN OUT UINT8     *Buffer
00098   );
00099
00109 typedef
00110 VOID
00111 (EFIAPI *PFAT_ERASE)(
00112   IN PFAT_PROTOCOL *This,
00113   IN UINTN         Address
00114   );
00115
00123 struct _PFAT_PROTOCOL {
00124   PFAT_WRITE   Write;
00125   PFAT_ERASE   Erase;
00126   PFAT_EXECUTE Execute;
00127 };
00128
00129 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: PfatDefinitions.h File Reference

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Classes | Defines | Enumerations
PfatDefinitions.h File Reference

Describes the functions visible to the rest of the Pfat. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | SFAM_DATA
struct | PPDT
PFAT Platform Data Table (PPDT) Provides platform specific data required by PFAT Module. More...
struct | PUP_HEADER
PFAT Update Package Header. More...
struct | PUP
struct | PFAT_LOG
PFAT Log The logging facility is used to communicate detailed information regarding the execution of a PFAT script from the SMI handler which invoked the PFAT module itself. More...
struct | PFAT_HOB
HOB used to pass data through every phase of PFAT Bios PFAT Bios code is executed in PEI, DXE and SMM and HOB is the only method to properly pass data between every phase. More...

Defines

#define | ALIGN_256KB 0x00040000
#define | EFI_PAGE_SIZE 0x00001000
#define | PFAT_COMMAND_NOP 0x00
PFAT Module Commands.
#define | PFAT_COMMAND_BEGIN 0x01
PFAT Begin.
#define | PFAT_COMMAND_WRITE_INDEX 0x10
PFAT Write Index.
#define | PFAT_COMMAND_WRITE_IMM 0x11
PFAT Write Inmediate.
#define | PFAT_COMMAND_READ_INDEX 0x12
PFAT Read Index.
#define | PFAT_COMMAND_READ_IMM 0x13
PFAT Read Inmediate.
#define | PFAT_COMMAND_ERASE_BLK 0x14
PFAT Erase Block.
#define | PFAT_COMMAND_EC_CMD_WR_INDEX 0x20
EC_CMD Write Index.
#define | PFAT_COMMAND_EC_CMD_WR_IMM 0x21
EC_CMD Write Inmediate.
#define | PFAT_COMMAND_EC_STS_RD 0x22
EC_CMD Read Status.
#define | PFAT_COMMAND_EC_DATA_WR_INDEX 0x23
EC_DATA Write Index.
#define | PFAT_COMMAND_EC_DATA_WR_IMM 0x24
EC_DATA Write Inmediate.
#define | PFAT_COMMAND_EC_DATA_RD 0x25
EC_DATA Read.
#define | PFAT_COMMAND_SET_BUFFER_INDEX 0x53
PFAT Set Buffer Index.
#define | PFAT_COMMAND_SET_FLASH_INDEX 0x55
PFAT Set Flash Index.
#define | PFAT_COMMAND_END 0xFF
PFAT End.
#define | ERR_OK 0x0000
PFAT Module Error Codes.
#define | ERR_UNSUPPORTED_CPU 0x0001
PFAT module detected an incompatibility with the installed CPU.
#define | ERR_BAD_DIRECTORY 0x0002
PFAT_DIRECTORY check failed.
#define | ERR_BAD_PPDT 0x0003
A pre-execution check of the PPDT failed.
#define | ERR_BAD_PUP 0x0004
An inconsistency was found in the update package.
#define | ERR_SCRIPT_SYNTAX 0x0005
Unknown operator or name, or invalid syntax found in script.
#define | ERR_UNDEFINED_FLASH_OBJECT 0x0006
An unimplemented flash object was referenced.
#define | ERR_INVALID_LINE 0x0007
A JMP, JE, JNE, JG, JGE, JL, or JLE operator has a target that is not within the script buffer (between BEGIN and END inclusive)
#define | ERR_BAD_PUPC 0x0008
PUPC inconsistency found.
#define | ERR_BAD_SVN 0x0009
PFAT module SVN is lower than required by PPDT.
#define | ERR_UNEXPECTED_OPCODE 0x000A
An EC related opcode found in a script when the PPDT indicates there is no EC in the system.
#define | ERR_RANGE_VIOLATION 0x8001
Buffer or flash operation exceeded object bounds.
#define | ERR_SFAM_VIOLATION 0x8002
An unsigned script attempted to write or erase a bock of flash that overlaps with the SFAM.
#define | ERR_OVERFLOW 0x8003
An integer overflow occurred.
#define | ERR_EXEC_LIMIT 0x8004
Total number of script opcodes retired exceeds either platform limit, or global limit.
#define | ERR_INTERNAL_ERROR 0x8005
An internal consistency check failed within the PFAT module.
#define | ERR_LAUNCH_FAIL 0xFFFF
CPU detected an error and did not execute the PFAT module.
#define | PFAT_F0_INDEX 0
#define | PFAT_B0_INDEX 0
#define | EC_PRESENT BIT1
#define | EC_PFAT_PROTECTED BIT2
#define | PEG_DMI_FIX BIT24;
#define | MAX_SPI_COMPONENTS 8
#define | PFAT_MEMORY_PAGES 64
PFAT Module needs 256KB of reserved memory (64 pages of 4KB each one)
#define | ALIGNMENT_IN_PAGES 64
PFAT requires 256KB alignment (64 pages of 4KB each one)
#define | PUP_BUFFER_SIZE 0x00014000
16KB Script + 64KB Flash Block
#define | PPDT_MAJOR_VERSION 1
#define | PPDT_MINOR_VERSION 0
#define | PFAT_SVN 0x10001
#define | PUP_HDR_VERSION 1
#define | PSL_MAJOR_VERSION 1
#define | PSL_MINOR_VERSION 0
#define | PFAT_LOG_VERSION 1
#define | PFAT_LOG_OPT_STEP_TRACE BIT0
#define | PFAT_LOG_OPT_BRANCH_TRACE BIT1
#define | PFAT_LOG_OPT_FLASH_WRITE BIT2
#define | PFAT_LOG_OPT_FLASH_ERASE BIT3
#define | PFAT_LOG_OPT_FLASH_ERROR BIT4
#define | PFAT_LOG_OPT_DEBUG BIT5
#define | PFAT_MODULE_GUID
GUID to locate PFAT Module.
#define | PFAT_HOB_GUID
GUID to locate PFAT HOB.
#define | SPI_SIZE_BASE_512KB 0x80000
#define | MIN_SFAM_COUNT 1
#define | MAX_SFAM_COUNT 64
#define | PUPC_MEMORY_OFFSET 0x00028000
Memory location for PUPC and PFAT LOG inside PFAT DPR allocated memory for Tool interface.
#define | PFAT_LOG_MEMORY_OFFSET 0x00020000
PfatMemAddress + PfatMemSize - 128KB.
#define | MAX_PFAT_LOG_PAGE ((PFAT_LOG_MEMORY_OFFSET / EFI_PAGE_SIZE) - 2)
30 4KB Pages

Enumerations

enum | SPI_COMPONENT_SIZE

Detailed Description

Describes the functions visible to the rest of the Pfat.

Copyright:
Copyright (c) 2011 - 2013 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file PfatDefinitions.h.

Define Documentation

#define ERR_OK 0x0000

PFAT Module Error Codes.

Operation completed without error

Definition at line 54 of file PfatDefinitions.h.

#define PFAT_COMMAND_NOP 0x00

PFAT Module Commands.

NOP

Definition at line 34 of file PfatDefinitions.h.

#define PFAT_HOB_GUID
Value:
{ \
    0x66F0C42D, 0x0D0E, 0x4C23, 0x93, 0xC0, 0x2D, 0x52, 0x95, 0xDC, 0x5E, 0x21 \
  }

GUID to locate PFAT HOB.

Definition at line 110 of file PfatDefinitions.h.

#define PFAT_MODULE_GUID
Value:
{ \
    0x7934156D, 0xCFCE, 0x460E, 0x92, 0xF5, 0xA0, 0x79, 0x09, 0xA5, 0x9E, 0xCA \
  }

GUID to locate PFAT Module.

Definition at line 103 of file PfatDefinitions.h.

#define PUPC_MEMORY_OFFSET 0x00028000

Memory location for PUPC and PFAT LOG inside PFAT DPR allocated memory for Tool interface.

PfatMemAddress + PfatMemSize - 160KB

Definition at line 276 of file PfatDefinitions.h.


2013 SharkBay Processor Reference Code API: PfatDefinitions.h Source File

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PfatDefinitions.h
Go to the documentation of this file.
00001
00021 #ifndef _PFAT_DEFINITIONS_H_
00022 #define _PFAT_DEFINITIONS_H_
00023
00024 #ifndef ALIGN_256KB
00025 #define ALIGN_256KB    0x00040000
00026 #endif
00027 #ifndef EFI_PAGE_SIZE
00028 #define EFI_PAGE_SIZE  0x00001000
00029 #endif
00030
00034 #define PFAT_COMMAND_NOP              0x00             ///< NOP
00035 #define PFAT_COMMAND_BEGIN            0x01             ///< PFAT Begin
00036 #define PFAT_COMMAND_WRITE_INDEX      0x10             ///< PFAT Write Index
00037 #define PFAT_COMMAND_WRITE_IMM        0x11             ///< PFAT Write Inmediate
00038 #define PFAT_COMMAND_READ_INDEX       0x12             ///< PFAT Read Index
00039 #define PFAT_COMMAND_READ_IMM         0x13             ///< PFAT Read Inmediate
00040 #define PFAT_COMMAND_ERASE_BLK        0x14             ///< PFAT Erase Block
00041 #define PFAT_COMMAND_EC_CMD_WR_INDEX  0x20             ///< EC_CMD Write Index
00042 #define PFAT_COMMAND_EC_CMD_WR_IMM    0x21             ///< EC_CMD Write Inmediate
00043 #define PFAT_COMMAND_EC_STS_RD        0x22             ///< EC_CMD Read Status
00044 #define PFAT_COMMAND_EC_DATA_WR_INDEX 0x23             ///< EC_DATA Write Index
00045 #define PFAT_COMMAND_EC_DATA_WR_IMM   0x24             ///< EC_DATA Write Inmediate
00046 #define PFAT_COMMAND_EC_DATA_RD       0x25             ///< EC_DATA Read
00047 #define PFAT_COMMAND_SET_BUFFER_INDEX 0x53             ///< PFAT Set Buffer Index
00048 #define PFAT_COMMAND_SET_FLASH_INDEX  0x55             ///< PFAT Set Flash Index
00049 #define PFAT_COMMAND_END              0xFF             ///< PFAT End
00050
00054 #define ERR_OK                      0x0000             ///< Operation completed without error
00055 #define ERR_UNSUPPORTED_CPU         0x0001             ///< PFAT module detected an incompatibility with the installed CPU
00056 #define ERR_BAD_DIRECTORY           0x0002             ///< PFAT_DIRECTORY check failed
00057 #define ERR_BAD_PPDT                0x0003             ///< A pre-execution check of the PPDT failed
00058 #define ERR_BAD_PUP                 0x0004             ///< An inconsistency was found in the update package
00059 #define ERR_SCRIPT_SYNTAX           0x0005             ///< Unknown operator or name, or invalid syntax found in script
00060 #define ERR_UNDEFINED_FLASH_OBJECT  0x0006             ///< An unimplemented flash object was referenced
00061 #define ERR_INVALID_LINE            0x0007             ///< A JMP, JE, JNE, JG, JGE, JL, or JLE operator has a target that is not within the script buffer (between BEGIN and END inclusive)
00062 #define ERR_BAD_PUPC                0x0008             ///< PUPC inconsistency found
00063 #define ERR_BAD_SVN                 0x0009             ///< PFAT module SVN is lower than required by PPDT
00064 #define ERR_UNEXPECTED_OPCODE       0x000A             ///< An EC related opcode found in a script when the PPDT indicates there is no EC in the system
00065 #define ERR_RANGE_VIOLATION         0x8001             ///< Buffer or flash operation exceeded object bounds
00066 #define ERR_SFAM_VIOLATION          0x8002             ///< An unsigned script attempted to write or erase a bock of flash that overlaps with the SFAM
00067 #define ERR_OVERFLOW                0x8003             ///< An integer overflow occurred
00068 #define ERR_EXEC_LIMIT              0x8004             ///< Total number of script opcodes retired exceeds either platform limit, or global limit
00069 #define ERR_INTERNAL_ERROR          0x8005             ///< An internal consistency check failed within the PFAT module
00070 #define ERR_LAUNCH_FAIL             0xFFFF             ///< CPU detected an error and did not execute the PFAT module
00071
00072 #define PFAT_F0_INDEX               0
00073 #define PFAT_B0_INDEX               0
00074
00075 #define EC_PRESENT                  BIT1
00076 #define EC_PFAT_PROTECTED           BIT2
00077 #define PEG_DMI_FIX                 BIT24;
00078
00079 #define MAX_SPI_COMPONENTS          8
00080 #define PFAT_MEMORY_PAGES           64                 ///< PFAT Module needs 256KB of reserved memory (64 pages of 4KB each one)
00081 #define ALIGNMENT_IN_PAGES          64                 ///< PFAT requires 256KB alignment (64 pages of 4KB each one)
00082
00083 #define PUP_BUFFER_SIZE             0x00014000         ///< 16KB Script + 64KB Flash Block
00084 #define PPDT_MAJOR_VERSION          1
00085 #define PPDT_MINOR_VERSION          0
00086 #define PFAT_SVN                    0x10001
00087 #define PUP_HDR_VERSION             1
00088 #define PSL_MAJOR_VERSION           1
00089 #define PSL_MINOR_VERSION           0
00090
00091 #define PFAT_LOG_VERSION            1
00092 #define PFAT_LOG_OPT_STEP_TRACE     BIT0
00093 #define PFAT_LOG_OPT_BRANCH_TRACE   BIT1
00094 #define PFAT_LOG_OPT_FLASH_WRITE    BIT2
00095 #define PFAT_LOG_OPT_FLASH_ERASE    BIT3
00096 #define PFAT_LOG_OPT_FLASH_ERROR    BIT4
00097 #define PFAT_LOG_OPT_DEBUG          BIT5
00098
00099 #if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
00100
00101
00102
00103 #define PFAT_MODULE_GUID \
00104   { \
00105     0x7934156D, 0xCFCE, 0x460E, 0x92, 0xF5, 0xA0, 0x79, 0x09, 0xA5, 0x9E, 0xCA \
00106   }
00107
00108
00109
00110 #define PFAT_HOB_GUID \
00111   { \
00112     0x66F0C42D, 0x0D0E, 0x4C23, 0x93, 0xC0, 0x2D, 0x52, 0x95, 0xDC, 0x5E, 0x21 \
00113   }
00114 #else
00115
00116
00117
00118 #define PFAT_MODULE_GUID \
00119   { \
00120     0x7934156D, 0xCFCE, 0x460E, \
00121     { \
00122       0x92, 0xF5, 0xA0, 0x79, 0x09, 0xA5, 0x9E, 0xCA \
00123     } \
00124   }
00125
00126
00127
00128 #define PFAT_HOB_GUID \
00129   { \
00130     0x66F0C42D, 0x0D0E, 0x4C23, \
00131     { \
00132       0x93, 0xC0, 0x2D, 0x52, 0x95, 0xDC, 0x5E, 0x21 \
00133     } \
00134   }
00135 #endif
00136
00137 #define SPI_SIZE_BASE_512KB  0x80000
00138
00139 typedef enum {
00140   EnumSpiCompSize512KB  = 0,
00141   EnumSpiCompSize1MB,
00142   EnumSpiCompSize2MB,
00143   EnumSpiCompSize4MB,
00144   EnumSpiCompSize8MB,
00145   EnumSpiCompSize16MB,
00146   EnumSpiCompSize32MB,
00147   EnumSpiCompSize64MB,
00148   EnumSpiCompSize128MB
00149 } SPI_COMPONENT_SIZE;
00150
00151 #define MIN_SFAM_COUNT  1
00152 #define MAX_SFAM_COUNT  64
00153
00154 typedef struct {
00155   UINT32 FirstByte;
00156   UINT32 LastByte;
00157 } SFAM_DATA;
00158
00163 typedef struct {
00164   UINT32    PpdtSize;
00165   UINT16    PpdtMajVer;
00166   UINT16    PpdtMinVer;
00167   UINT8     PlatId[16];
00168   UINT8     PkeySlot0[32];
00169   UINT8     PkeySlot1[32];
00170   UINT8     PkeySlot2[32];
00171   UINT32    PfatModSvn;
00172   UINT32    BiosSvn;
00173   UINT32    ExecLim;
00174
00175
00176
00177
00178
00179
00180
00181
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191   UINT32    PlatAttr;
00198   UINT32    EcCmd;
00205   UINT32    EcData;
00212   UINT32    EcCmdGetSvn;
00219   UINT32    EcCmdOpen;
00226   UINT32    EcCmdClose;
00233   UINT32    EcCmdPortTest;
00234   UINT8     Reserved1[4];
00240   UINT8     LastSfam;
00241   UINT8     Reserved2[3];
00242   SFAM_DATA SfamData[MAX_SFAM_COUNT];
00243 } PPDT;
00244
00248 typedef struct {
00249   UINT16 Version;
00250   UINT8  Reserved3[2];
00251   UINT8  PlatId[16];
00252
00253
00254
00255
00256
00257   UINT16 PkgAttributes;
00258   UINT8  Reserved4[2];
00259   UINT16 PslMajorVer;
00260   UINT16 PslMinorVer;
00261   UINT32 ScriptSectionSize;
00262   UINT32 DataSectionSize;
00263   UINT32 BiosSvn;
00264   UINT32 EcSvn;
00265   UINT32 VendorSpecific;
00266 } PUP_HEADER;
00267
00268 typedef struct {
00269   PUP_HEADER PupHeader;
00270   UINT64     PupBuffer[PUP_BUFFER_SIZE / 8];
00271 } PUP;
00272
00276 #define PUPC_MEMORY_OFFSET        0x00028000                                     ///< PfatMemAddress + PfatMemSize - 160KB
00277 #define PFAT_LOG_MEMORY_OFFSET    0x00020000                                     ///< PfatMemAddress + PfatMemSize - 128KB
00278 #define MAX_PFAT_LOG_PAGE         ((PFAT_LOG_MEMORY_OFFSET / EFI_PAGE_SIZE) - 2) ///< 30 4KB Pages
00279
00285 typedef struct {
00286   UINT16 Version;
00287   UINT16 LastPage;
00288
00289
00290
00291
00292
00293
00294
00295
00296
00297
00298
00299   UINT32 LoggingOptions;
00300   UINT8  Reserved5[8];
00301   UINT32 PfatModSvn;
00302   UINT32 NumOfEntriesInLog;
00303 } PFAT_LOG;
00304
00310 typedef struct {
00311   EFI_HOB_GUID_TYPE EfiHobGuidType;
00312   PPDT              Ppdt;
00313
00314
00315
00316   PUP_HEADER        PupHeader;
00317   UINT8             NumSpiComponents;
00318   UINT8             ComponentSize[MAX_SPI_COMPONENTS];
00319   UINT64            PfatToolsIntIoTrapAdd;
00320   PFAT_LOG          PfatLog;
00321 } PFAT_HOB;
00322
00323 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: PiMpService.h File Reference

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Classes | Defines | Typedefs | Variables
PiMpService.h File Reference

Definitions for the PI MP Services Protocol defined in the PI spec. More...

#include <EFI_PROTOCOL_CONSUMER (MpService)>
Include dependency graph for PiMpService.h:

Go to the source code of this file.

Classes

struct | EFI_CPU_PHYSICAL_LOCATION
Structure that describes the pyhiscal location of a logical CPU. More...
struct | EFI_PROCESSOR_INFORMATION
Structure that describes information about a logical CPU. More...
struct | _EFI_PI_MP_SERVICES_PROTOCOL
When installed, the MP Services Protocol produces a collection of services that are needed for MP management. More...

Defines

#define | EFI_PI_MP_SERVICES_PROTOCOL_GUID
Share some definitions from Framework MP Services Protocol.
#define | END_OF_CPU_LIST 0xffffffff
Terminator for a list of failed CPUs returned by StartAllAPs().
#define | PROCESSOR_AS_BSP_BIT 0x00000001
This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and indicates whether the processor is playing the role of BSP.
#define | PROCESSOR_ENABLED_BIT 0x00000002
This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and indicates whether the processor is enabled.
#define | PROCESSOR_HEALTH_STATUS_BIT 0x00000004
This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and indicates whether the processor is healthy.

Typedefs

typedef struct
_EFI_PI_MP_SERVICES_PROTOCOL 		EFI_PI_MP_SERVICES_PROTOCOL
Forward declaration for the EFI_PI_MP_SERVICES_PROTOCOL.
typedef EFI_STATUS(* | EFI_PI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS )(IN EFI_PI_MP_SERVICES_PROTOCOL *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)
This service retrieves the number of logical processor in the platform and the number of those logical processors that are enabled on this boot.
typedef EFI_STATUS(* | EFI_PI_MP_SERVICES_GET_PROCESSOR_INFO )(IN EFI_PI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
Gets detailed MP-related information on the requested processor at the instant this call is made.
typedef EFI_STATUS(* | EFI_PI_MP_SERVICES_STARTUP_ALL_APS )(IN EFI_PI_MP_SERVICES_PROTOCOL *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroSeconds, IN VOID *ProcedureArgument OPTIONAL, OUT UINTN **FailedCpuList OPTIONAL)
This service executes a caller provided function on all enabled APs.
typedef EFI_STATUS(* | EFI_PI_MP_SERVICES_STARTUP_THIS_AP )(IN EFI_PI_MP_SERVICES_PROTOCOL *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT BOOLEAN *Finished OPTIONAL)
This service lets the caller get one enabled AP to execute a caller-provided function.
typedef EFI_STATUS(* | EFI_PI_MP_SERVICES_SWITCH_BSP )(IN EFI_PI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
This service switches the requested AP to be the BSP from that point onward.
typedef EFI_STATUS(* | EFI_PI_MP_SERVICES_ENABLEDISABLEAP )(IN EFI_PI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
This service lets the caller enable or disable an AP from this point onward.
typedef EFI_STATUS(* | EFI_PI_MP_SERVICES_WHOAMI )(IN EFI_PI_MP_SERVICES_PROTOCOL *This, OUT UINTN *ProcessorNumber)
This return the handle number for the calling processor.

Variables

EFI_GUID | gEfiPiMpServiceProtocolGuid

Detailed Description

Definitions for the PI MP Services Protocol defined in the PI spec.

Copyright:
Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Definition in file PiMpService.h.

Define Documentation

#define EFI_PI_MP_SERVICES_PROTOCOL_GUID
Value:
{ \
    0x3fdda605, 0xa76e, 0x4f46, \
    { \
      0xad, 0x29, 0x12, 0xf4, 0x53, 0x1b, 0x3d, 0x08 \
    } \
  }

Share some definitions from Framework MP Services Protocol.

Global ID for the EFI_PI_MP_SERVICES_PROTOCOL.

Definition at line 31 of file PiMpService.h.

#define PROCESSOR_AS_BSP_BIT 0x00000001

This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and indicates whether the processor is playing the role of BSP.

If the bit is 1, then the processor is BSP. Otherwise, it is AP.

Definition at line 54 of file PiMpService.h.

#define PROCESSOR_ENABLED_BIT 0x00000002

This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and indicates whether the processor is enabled.

If the bit is 1, then the processor is enabled. Otherwise, it is disabled.

Definition at line 61 of file PiMpService.h.

#define PROCESSOR_HEALTH_STATUS_BIT 0x00000004

This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and indicates whether the processor is healthy.

If the bit is 1, then the processor is healthy. Otherwise, some fault has been detected for the processor.

Definition at line 68 of file PiMpService.h.

Typedef Documentation

typedef EFI_STATUS( * EFI_PI_MP_SERVICES_ENABLEDISABLEAP)(IN EFI_PI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)

This service lets the caller enable or disable an AP from this point onward.

This service may only be called from the BSP.

This service allows the caller enable or disable an AP from this point onward. The caller can optionally specify the health status of the AP by Health. If an AP is being disabled, then the state of the disabled AP is implementation dependent. If an AP is enabled, then the implementation must guarantee that a complete initialization sequence is performed on the AP, so the AP is in a state that is compatible with an MP operating system. This service may not be supported after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled.

If the enable or disable AP operation cannot be completed prior to the return from this service, then EFI_UNSUPPORTED must be returned.

Parameters:
[in] | This | - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | ProcessorNumber | - The handle number of processor.
[in] | EnableAP | - Indicates whether the newstate of the AP is enabled or disabled.
[in] | HealthFlag | - Indicates new health state of the AP..
Return values:
EFI_SUCCESS | - AP successfully enabled or disabled.
EFI_DEVICE_ERROR | - Caller processor is AP.
EFI_NOT_FOUND | - Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETERS | - ProcessorNumber specifies the BSP.

Definition at line 404 of file PiMpService.h.

typedef EFI_STATUS( * EFI_PI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(IN EFI_PI_MP_SERVICES_PROTOCOL *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)

This service retrieves the number of logical processor in the platform and the number of those logical processors that are enabled on this boot.

This service may only be called from the BSP.

This function is used to retrieve the following information:

  • The number of logical processors that are present in the system.
  • The number of enabled logical processors in the system at the instant this call is made.

Because MP Service Protocol provides services to enable and disable processors dynamically, the number of enabled logical processors may vary during the course of a boot session.

If this service is called from an AP, then EFI_DEVICE_ERROR is returned. If NumberOfProcessors or NumberOfEnabledProcessors is NULL, then EFI_INVALID_PARAMETER is returned. Otherwise, the total number of processors is returned in NumberOfProcessors, the number of currently enabled processor is returned in NumberOfEnabledProcessors, and EFI_SUCCESS is returned.

Parameters:
[in] | This | - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | NumberOfProcessors | - Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[in] | NumberOfEnabledProcessors | - Pointer to the number of enabled logical processors that exist in system, including the BSP.
Return values:
EFI_SUCCESS | - Number of logical processors and enabled logical processors retrieved.
EFI_DEVICE_ERROR | - Caller processor is AP.
EFI_INVALID_PARAMETER | - NumberOfProcessors is NULL.
EFI_INVALID_PARAMETER | - NumberOfEnabledProcessors is NULL.

Definition at line 159 of file PiMpService.h.

typedef EFI_STATUS( * EFI_PI_MP_SERVICES_GET_PROCESSOR_INFO)(IN EFI_PI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)

Gets detailed MP-related information on the requested processor at the instant this call is made.

This service may only be called from the BSP.

This service retrieves detailed MP-related information about any processor on the platform. Note the following:

  • The processor information may change during the course of a boot session.
  • The information presented here is entirely MP related.

Information regarding the number of caches and their sizes, frequency of operation, slot numbers is all considered platform-related information and is not provided by this service.

Parameters:
[in] | This | - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | ProcessorNumber | - The handle number of processor.
[in] | ProcessorInfoBuffer | - A pointer to the buffer where information for the requested processor is deposited.
Return values:
EFI_SUCCESS | - Processor information successfully returned.
EFI_DEVICE_ERROR | - Caller processor is AP.
EFI_INVALID_PARAMETER | - ProcessorInfoBuffer is NULL
EFI_NOT_FOUND | - Processor with the handle specified by ProcessorNumber does not exist.

Definition at line 189 of file PiMpService.h.

typedef EFI_STATUS( * EFI_PI_MP_SERVICES_STARTUP_ALL_APS)(IN EFI_PI_MP_SERVICES_PROTOCOL *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroSeconds, IN VOID *ProcedureArgument OPTIONAL, OUT UINTN **FailedCpuList OPTIONAL)

This service executes a caller provided function on all enabled APs.

APs can run either simultaneously or one at a time in sequence. This service supports both blocking and non-blocking requests. The non-blocking requests use EFI events so the BSP can detect when the APs have finished. This service may only be called from the BSP.

This function is used to dispatch all the enabled APs to the function specified by Procedure. If any enabled AP is busy, then EFI_NOT_READY is returned immediately and Procedure is not started on any AP.

If SingleThread is TRUE, all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. Otherwise, all the enabled APs execute the function specified by Procedure simultaneously.

If WaitEvent is NULL, execution is in blocking mode. The BSP waits until all APs finish or TimeoutInMicroSecs expires. Otherwise, execution is in non-blocking mode, and the BSP returns from this service without waiting for APs. If a non-blocking mode is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, then EFI_UNSUPPORTED must be returned.

If the timeout specified by TimeoutInMicroseconds expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are always available for further calls to EFI_PI_MP_SERVICES_PROTOCOL.StartupAllAPs() and EFI_PI_MP_SERVICES_PROTOCOL.StartupThisAP(). If FailedCpuList is not NULL, its content points to the list of processor handle numbers in which Procedure was terminated.

Note: It is the responsibility of the consumer of the EFI_PI_MP_SERVICES_PROTOCOL.StartupAllAPs() to make sure that the nature of the code that is executed on the BSP and the dispatched APs is well controlled. The MP Services Protocol does not guarantee that the Procedure function is MP-safe. Hence, the tasks that can be run in parallel are limited to certain independent tasks and well-controlled exclusive code. EFI services and protocols may not be called by APs unless otherwise specified.

In blocking execution mode, BSP waits until all APs finish or TimeoutInMicroSeconds expires.

In non-blocking execution mode, BSP is freed to return to the caller and then proceed to the next task without having to wait for APs. The following sequence needs to occur in a non-blocking execution mode:

  1. The caller that intends to use this MP Services Protocol in non-blocking mode creates WaitEvent by calling the EFI CreateEvent() service. The caller invokes EFI_PI_MP_SERVICES_PROTOCOL.StartupAllAPs(). If the parameter WaitEvent is not NULL, then StartupAllAPs() executes in non-blocking mode. It requests the function specified by Procedure to be started on all the enabled APs, and releases the BSP to continue with other tasks.
    1. The caller can use the CheckEvent() and WaitForEvent() services to check the state of the WaitEvent created in step 1.
    2. When the APs complete their task or TimeoutInMicroSecondss expires, the MP Service signals WaitEvent by calling the EFI SignalEvent() function. If FailedCpuList is not NULL, its content is available when WaitEvent is signaled. If all APs returned from Procedure prior to the timeout, then FailedCpuList is set to NULL. If not all APs return from Procedure before the timeout, then FailedCpuList is filled in with the list of the failed APs. The buffer is allocated by MP Service Protocol using AllocatePool(). It is the caller's responsibility to free the buffer with FreePool() service.
    3. This invocation of SignalEvent() function informs the caller that invoked EFI_PI_MP_SERVICES_PROTOCOL.StartupAllAPs() that either all the APs completed the specified task or a timeout occurred. The contents of FailedCpuList can be examined to determine which APs did not complete the specified task prior to the timeout.
Parameters:
[in] | This | - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | Procedure | - A pointer to the function to be run on enabled APs of the system.
[in] | SingleThread | - Indicates whether to execute the function simultaneously or one by one..
[in] | WaitEvent | - The event created by the caller. If it is NULL, then execute in blocking mode. If it is not NULL, then execute in non-blocking mode.
[in] | TimeoutInMicrosecsond | - The time limit in microseconds for this AP to finish the function. Zero means infinity.
[in] | ProcArgument | - Pointer to the optional parameter of the assigned function.
[in] | FailedCpuList | - The list of processor numbers that fail to finish the function before TimeoutInMicrosecsond expires.
Return values:
EFI_SUCCESS | - In blocking mode, all APs have finished before the timeout expired.
EFI_SUCCESS | - In non-blocking mode, function has been dispatched to all enabled APs.
EFI_DEVICE_ERROR | - Caller processor is AP.
EFI_NOT_STARTED | - No enabled AP exists in the system.
EFI_NOT_READY | - Any enabled AP is busy.
EFI_TIMEOUT | - In blocking mode, The timeout expired before all enabled APs have finished.
EFI_INVALID_PARAMETER | - Procedure is NULL.

Definition at line 282 of file PiMpService.h.

typedef EFI_STATUS( * EFI_PI_MP_SERVICES_STARTUP_THIS_AP)(IN EFI_PI_MP_SERVICES_PROTOCOL *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT BOOLEAN *Finished OPTIONAL)

This service lets the caller get one enabled AP to execute a caller-provided function.

The caller can request the BSP to either wait for the completion of the AP or just proceed with the next task by using the EFI event mechanism. See EFI_PI_MP_SERVICES_PROTOCOL.StartupAllAPs() for more details on non-blocking execution support. This service may only be called from the BSP.

This function is used to dispatch one enabled AP to the function specified by Procedure passing in the argument specified by ProcedureArgument. If WaitEvent is NULL, execution is in blocking mode. The BSP waits until the AP finishes or TimeoutInMicroSecondss expires. Otherwise, execution is in non-blocking mode. BSP proceeds to the next task without waiting for the AP. If a non-blocking mode is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, then EFI_UNSUPPORTED must be returned.

If the timeout specified by TimeoutInMicroseconds expires before the AP returns from Procedure, then execution of Procedure by the AP is terminated. The AP is available for subsequent calls to EFI_PI_MP_SERVICES_PROTOCOL.StartupAllAPs() and EFI_PI_MP_SERVICES_PROTOCOL.StartupThisAP().

Parameters:
[in] | This | - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | Procedure | - A pointer to the function to be run on the designated AP.
[in] | ProcessorNumber | - The handle number of AP..
[in] | WaitEvent | - The event created by the caller. If it is NULL, then execute in blocking mode. If it is not NULL, then execute in non-blocking mode.
[in] | TimeoutInMicroseconds | - The time limit in microseconds for this AP to finish the function. Zero means infinity.
[in] | ProcArgument | - Pointer to the optional parameter of the assigned function.
[in] | Finished | - Indicates whether AP has finished assigned function. In blocking mode, it is ignored.
Return values:
EFI_SUCCESS | - In blocking mode, specified AP has finished before the timeout expires.
EFI_SUCCESS | - In non-blocking mode, function has been dispatched to specified AP.
EFI_DEVICE_ERROR | - Caller processor is AP.
EFI_TIMEOUT | - In blocking mode, the timeout expires before specified AP has finished.
EFI_NOT_READY | - Specified AP is busy.
EFI_NOT_FOUND | - Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | - ProcessorNumber specifies the BSP or disabled AP.
EFI_INVALID_PARAMETER | - Procedure is NULL.

Definition at line 335 of file PiMpService.h.

typedef EFI_STATUS( * EFI_PI_MP_SERVICES_SWITCH_BSP)(IN EFI_PI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)

This service switches the requested AP to be the BSP from that point onward.

This service changes the BSP for all purposes. This call can only be performed by the current BSP.

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. The new BSP can take over the execution of the old BSP and continue seamlessly from where the old one left off. This service may not be supported after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled.

If the BSP cannot be switched prior to the return from this service, then EFI_UNSUPPORTED must be returned.

Parameters:
[in] | This | - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | ProcessorNumber | - The handle number of processor.
[in] | EnableOldBSP | - Whether to enable or disable the original BSP.
Return values:
EFI_SUCCESS | - BSP successfully switched.
EFI_DEVICE_ERROR | - Caller processor is AP.
EFI_NOT_FOUND | - Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | - ProcessorNumber specifies the BSP or disabled AP.
EFI_NOT_READY | - Specified AP is busy.

Definition at line 371 of file PiMpService.h.

typedef EFI_STATUS( * EFI_PI_MP_SERVICES_WHOAMI)(IN EFI_PI_MP_SERVICES_PROTOCOL *This, OUT UINTN *ProcessorNumber)

This return the handle number for the calling processor.

This service may be called from the BSP and APs.

This service returns the processor handle number for the calling processor. The returned value is in the range from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved with EFI_PI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors(). This service may be called from the BSP and APs. If ProcessorNumber is NULL, then EFI_INVALID_PARAMETER is returned. Otherwise, the current processors handle number is returned in ProcessorNumber, and EFI_SUCCESS is returned.

Parameters:
[in] | This | - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | ProcessorNumber | - Pointer to the handle number of AP.
Return values:
EFI_SUCCESS | - Processor number successfully returned.
EFI_INVALID_PARAMETER | - ProcessorNumber is NULL

Definition at line 431 of file PiMpService.h.


2013 SharkBay Processor Reference Code API: PiMpService.h Source File

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PiMpService.h
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00001
00020 #ifndef _PI_MP_SERVICES_H_
00021 #define _PI_MP_SERVICES_H_
00022
00026 #include EFI_PROTOCOL_CONSUMER (MpService)
00027
00031 #define EFI_PI_MP_SERVICES_PROTOCOL_GUID \
00032   { \
00033     0x3fdda605, 0xa76e, 0x4f46, \
00034     { \
00035       0xad, 0x29, 0x12, 0xf4, 0x53, 0x1b, 0x3d, 0x08 \
00036     } \
00037   }
00038
00042 typedef struct _EFI_PI_MP_SERVICES_PROTOCOL EFI_PI_MP_SERVICES_PROTOCOL;
00043
00047 #define END_OF_CPU_LIST 0xffffffff
00048
00054 #define PROCESSOR_AS_BSP_BIT  0x00000001
00055
00061 #define PROCESSOR_ENABLED_BIT 0x00000002
00062
00068 #define PROCESSOR_HEALTH_STATUS_BIT 0x00000004
00069
00073 typedef struct {
00077   UINT32 Package;
00081   UINT32 Core;
00085   UINT32 Thread;
00086 } EFI_CPU_PHYSICAL_LOCATION;
00087
00091 typedef struct {
00098   UINT64 ProcessorId;
00117   UINT32 StatusFlag;
00123   EFI_CPU_PHYSICAL_LOCATION Location;
00124 } EFI_PROCESSOR_INFORMATION;
00125
00157 typedef
00158 EFI_STATUS
00159 (EFIAPI *EFI_PI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(
00160   IN EFI_PI_MP_SERVICES_PROTOCOL *This,
00161   OUT UINTN                      *NumberOfProcessors,
00162   OUT UINTN                      *NumberOfEnabledProcessors
00163   );
00164
00187 typedef
00188 EFI_STATUS
00189 (EFIAPI *EFI_PI_MP_SERVICES_GET_PROCESSOR_INFO)(
00190   IN EFI_PI_MP_SERVICES_PROTOCOL *This,
00191   IN UINTN                       ProcessorNumber,
00192   OUT EFI_PROCESSOR_INFORMATION  *ProcessorInfoBuffer
00193   );
00194
00280 typedef
00281 EFI_STATUS
00282 (EFIAPI *EFI_PI_MP_SERVICES_STARTUP_ALL_APS)(
00283   IN EFI_PI_MP_SERVICES_PROTOCOL *This,
00284   IN EFI_AP_PROCEDURE            Procedure,
00285   IN BOOLEAN                     SingleThread,
00286   IN EFI_EVENT WaitEvent         OPTIONAL,
00287   IN UINTN                       TimeoutInMicroSeconds,
00288   IN VOID *ProcedureArgument     OPTIONAL,
00289   OUT UINTN **FailedCpuList      OPTIONAL
00290   );
00291
00333 typedef
00334 EFI_STATUS
00335 (EFIAPI *EFI_PI_MP_SERVICES_STARTUP_THIS_AP)(
00336   IN EFI_PI_MP_SERVICES_PROTOCOL *This,
00337   IN EFI_AP_PROCEDURE            Procedure,
00338   IN UINTN                       ProcessorNumber,
00339   IN EFI_EVENT WaitEvent         OPTIONAL,
00340   IN UINTN                       TimeoutInMicroseconds,
00341   IN VOID *ProcedureArgument     OPTIONAL,
00342   OUT BOOLEAN *Finished          OPTIONAL
00343   );
00344
00369 typedef
00370 EFI_STATUS
00371 (EFIAPI *EFI_PI_MP_SERVICES_SWITCH_BSP)(
00372   IN EFI_PI_MP_SERVICES_PROTOCOL *This,
00373   IN UINTN                       ProcessorNumber,
00374   IN BOOLEAN                     EnableOldBSP
00375   );
00376
00402 typedef
00403 EFI_STATUS
00404 (EFIAPI *EFI_PI_MP_SERVICES_ENABLEDISABLEAP)(
00405   IN EFI_PI_MP_SERVICES_PROTOCOL *This,
00406   IN UINTN                       ProcessorNumber,
00407   IN BOOLEAN                     EnableAP,
00408   IN UINT32 *HealthFlag          OPTIONAL
00409   );
00410
00429 typedef
00430 EFI_STATUS
00431 (EFIAPI *EFI_PI_MP_SERVICES_WHOAMI)(
00432   IN EFI_PI_MP_SERVICES_PROTOCOL *This,
00433   OUT UINTN                      *ProcessorNumber
00434   );
00435
00465 struct _EFI_PI_MP_SERVICES_PROTOCOL {
00470   EFI_PI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;
00474   EFI_PI_MP_SERVICES_GET_PROCESSOR_INFO       GetProcessorInfo;
00478   EFI_PI_MP_SERVICES_STARTUP_ALL_APS          StartupAllAPs;
00482   EFI_PI_MP_SERVICES_STARTUP_THIS_AP          StartupThisAP;
00486   EFI_PI_MP_SERVICES_SWITCH_BSP               SwitchBSP;
00491   EFI_PI_MP_SERVICES_ENABLEDISABLEAP          EnableDisableAP;
00495   EFI_PI_MP_SERVICES_WHOAMI                   WhoAmI;
00496 };
00497
00498 extern EFI_GUID gEfiPiMpServiceProtocolGuid;
00499
00500 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: PowerMgmtAcpiTableStorage.h File Reference

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PowerMgmtAcpiTableStorage.h File Reference

GUID definition for the Power Management ACPI table storage file name. More...

Go to the source code of this file.

Defines

#define | POWER_MGMT_ACPI_TABLE_STORAGE_GUID
Power Mgmt policy provided by platform for ACPI Table Storage {299141BB-211A-48a5-92C0-6F9A0A3A006E}.

Variables

EFI_GUID | gPowerMgmtAcpiTableStorageGuid

Detailed Description

GUID definition for the Power Management ACPI table storage file name.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file PowerMgmtAcpiTableStorage.h.

Define Documentation

#define POWER_MGMT_ACPI_TABLE_STORAGE_GUID
Value:
{ \
    0x299141bb, 0x211a, 0x48a5, 0x92, 0xc0, 0x6f, 0x9a, 0xa, 0x3a, 0x0, 0x6e \
  }

Power Mgmt policy provided by platform for ACPI Table Storage {299141BB-211A-48a5-92C0-6F9A0A3A006E}.

Definition at line 28 of file PowerMgmtAcpiTableStorage.h.


2013 SharkBay Processor Reference Code API: PowerMgmtAcpiTableStorage.h Source File

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00001
00021 #ifndef _POWER_MGMT_ACPI_TABLE_STORAGE_H_
00022 #define _POWER_MGMT_ACPI_TABLE_STORAGE_H_
00023
00028 #define POWER_MGMT_ACPI_TABLE_STORAGE_GUID \
00029   { \
00030     0x299141bb, 0x211a, 0x48a5, 0x92, 0xc0, 0x6f, 0x9a, 0xa, 0x3a, 0x0, 0x6e \
00031   }
00032
00033 extern EFI_GUID gPowerMgmtAcpiTableStorageGuid;
00034
00035 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: PowerMgmtDefinitions.h File Reference

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Defines
PowerMgmtDefinitions.h File Reference

This file contains define definitions specific to Haswell processor. More...

Go to the source code of this file.

Defines

#define | PPM_ENABLE 1
#define | PPM_DISABLE 0
#define | CSTATE_SUPPORTED 0x1
#define | ENHANCED_CSTATE_SUPPORTED 0x2
#define | C6_C7_SHORT_LATENCY_SUPPORTED 0x01
#define | C6_C7_LONG_LATENCY_SUPPORTED 0x02
#define | C7s_SHORT_LATENCY_SUPPORTED 0x03
#define | C7s_LONG_LATENCY_SUPPORTED 0x04
#define | PPM_EIST 0x1
BIT 0 : Enhanced Intel Speed Step Technology.
#define | PPM_C1 0x2
BIT 1 : C1 enabled, supported.
#define | PPM_C1E 0x4
BIT 2 : C1E enabled.
#define | PPM_C3 0x8
BIT 3 : C3 enabled, supported.
#define | PPM_C6 0x10
BIT 4 : C6 enabled, supported.
#define | PPM_C7 0x20
BIT 5 : C7 enabled, supported.
#define | PPM_C7S 0x40
BIT 6 : C7S enabled, supported.
#define | PPM_TM 0x80
BIT 7 : Adaptive Thermal Monitor.
#define | PPM_TURBO 0x100
BIT 8 : Long duration turbo mode.
#define | PPM_CMP 0x200
BIT 9 : CMP.
#define | PPM_TSTATES 0x400
BIT 10: CPU throttling states.
#define | PPM_MWAIT_EXT 0x800
BIT 11: MONITIOR/MWAIT Extensions supported.
#define | PPM_EEPST 0x1000
BIT 12: Energy efficient P-State Feature enabled.
#define | PPM_TSTATE_FINE_GRAINED 0x2000
BIT 13: Fine grained CPU Throttling states.
#define | PPM_CD 0x4000
BIT 14: Deep Cstate - C8/C9/C10.
#define | PPM_TIMED_MWAIT 0x8000
BIT 15: Timed Mwait support.
#define | C6_LONG_LATENCY_ENABLE 0x10000
BIT 16: 1=C6 Long and Short,0=C6 Short only.
#define | C7_LONG_LATENCY_ENABLE 0x20000
BIT 17: 1=C7 Long and Short,0=C7 Short only.
#define | C7s_LONG_LATENCY_ENABLE 0x40000
BIT 18: 1=C7s Long and Short,0=C7s Short only.
#define | PPM_C8 0x80000
Bit 19: 1= C8 enabled/supported.
#define | PPM_C9 0x100000
Bit 20: 1= C9 enabled/supported.
#define | PPM_C10 0x200000
Bit 21: 1= C10 enabled/supported.
#define | PPM_C_STATES 0x7A
PPM_C1 + PPM_C3 + PPM_C6 + PPM_C7 + PPM_C7S.
#define | C3_LATENCY 0x42
#define | C6_C7_SHORT_LATENCY 0x73
#define | C6_C7_LONG_LATENCY 0x91
#define | C8_LATENCY 0xE4
#define | C9_LATENCY 0x145
#define | C10_LATENCY 0x1EF
#define | CPUID_FUNCTION_6 0x00000006
#define | PCH_ACPI_PBLK 0x1810
#define | PCH_ACPI_LV2 0x1814
#define | PCH_ACPI_LV3 0x1815
#define | PCH_ACPI_LV4 0x1816
#define | PCH_ACPI_LV6 0x1818
#define | PCH_ACPI_LV5 0x1817
#define | PCH_ACPI_LV7 0x1819
#define | C1_LATENCY 1
#define | C1_POWER 0x3E8
#define | C3_POWER 0x1F4
#define | C6_POWER 0x15E
#define | C7_POWER 0xC8
#define | C8_POWER 0xC8
#define | C9_POWER 0xC8
#define | C10_POWER 0xC8
#define | MAX_POWER_LIMIT_1_TIME_IN_SECONDS 32767
#define | AUTO 0
#define | END_OF_TABLE 0xFF
#define | CONFIG_TDP_DOWN 1
#define | CONFIG_TDP_UP 2
#define | CONFIG_TDP_DEACTIVATE 0xFF
#define | MMIO_DDR_RAPL_LIMIT 0x58e0
#define | MMIO_TURBO_POWER_LIMIT 0x59A0
#define | MAX_OVERCLOCKING_BINS 0x7
#define | MB_POWER_LIMIT1_TIME_DEFAULT 28
For Mobile, default PL1 time window value is 28 seconds.
#define | DT_POWER_LIMIT1_TIME_DEFAULT 8
For Desktop, default PL1 time window value is 8 second.
#define | PROCESSOR_FLAVOR_MOBILE 0x04
#define | PROCESSOR_FLAVOR_DESKTOP 0x00
#define | PROCESSOR_FLAVOR_MASK (BIT3 | BIT2)
#define | FVID_MAX_POWER 35000
#define | FVID_TURBO_POWER 35000
#define | FVID_SUPERLFM_POWER 12000
#define | FVID_MIN_POWER 15000
#define | SW_SMI_S3_RESTORE_MSR 0x48
S3- MSR restore SW SMI.
#define | VR_CURRENT_DEFAULT 0
VR Current Limit Default.
#define | PSI1_THRESHOLD_DEFAULT 0x14
#define | PSI2_THRESHOLD_DEFAULT 0x05
#define | PSI3_THRESHOLD_DEFAULT 0x01

Detailed Description

This file contains define definitions specific to Haswell processor.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file PowerMgmtDefinitions.h.


2013 SharkBay Processor Reference Code API: PowerMgmtDefinitions.h Source File

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00001
00021 #ifndef _POWER_MGMT_DEFINITIONS_H_
00022 #define _POWER_MGMT_DEFINITIONS_H_
00023
00024 #define PPM_ENABLE  1
00025 #define PPM_DISABLE 0
00026
00027 #define CSTATE_SUPPORTED          0x1
00028 #define ENHANCED_CSTATE_SUPPORTED 0x2
00029 #define C6_C7_SHORT_LATENCY_SUPPORTED 0x01
00030 #define C6_C7_LONG_LATENCY_SUPPORTED  0x02
00031 #define C7s_SHORT_LATENCY_SUPPORTED   0x03
00032 #define C7s_LONG_LATENCY_SUPPORTED    0x04
00033 //
00034 // Platform Power Management Flags Bit Definitions:
00035 //   These defines are also used in CPU0CST.ASL to check platform configuration
00036 //   and build C-state table accordingly.
00037 //
00038 #define PPM_EIST                0x1        ///< BIT 0 : Enhanced Intel Speed Step Technology.
00039 #define PPM_C1                  0x2        ///< BIT 1 : C1 enabled, supported.
00040 #define PPM_C1E                 0x4        ///< BIT 2 : C1E enabled.
00041 #define PPM_C3                  0x8        ///< BIT 3 : C3 enabled, supported.
00042 #define PPM_C6                  0x10       ///< BIT 4 : C6 enabled, supported.
00043 #define PPM_C7                  0x20       ///< BIT 5 : C7 enabled, supported.
00044 #define PPM_C7S                 0x40       ///< BIT 6 : C7S enabled, supported
00045 #define PPM_TM                  0x80       ///< BIT 7 : Adaptive Thermal Monitor.
00046 #define PPM_TURBO               0x100      ///< BIT 8 : Long duration turbo mode
00047 #define PPM_CMP                 0x200      ///< BIT 9 : CMP.
00048 #define PPM_TSTATES             0x400      ///< BIT 10: CPU throttling states
00049 #define PPM_MWAIT_EXT           0x800      ///< BIT 11: MONITIOR/MWAIT Extensions supported.
00050 #define PPM_EEPST               0x1000     ///< BIT 12: Energy efficient P-State Feature enabled
00051 #define PPM_TSTATE_FINE_GRAINED 0x2000     ///< BIT 13: Fine grained CPU Throttling states
00052 #define PPM_CD                  0x4000     ///< BIT 14: Deep Cstate - C8/C9/C10
00053 #define PPM_TIMED_MWAIT         0x8000     ///< BIT 15: Timed Mwait support
00054 #define C6_LONG_LATENCY_ENABLE    0x10000  ///< BIT 16: 1=C6 Long and Short,0=C6 Short only
00055 #define C7_LONG_LATENCY_ENABLE    0x20000  ///< BIT 17: 1=C7 Long and Short,0=C7 Short only
00056 #define C7s_LONG_LATENCY_ENABLE   0x40000  ///< BIT 18: 1=C7s Long and Short,0=C7s Short only
00057 #define PPM_C8                    0x80000  ///< Bit 19: 1= C8 enabled/supported
00058 #define PPM_C9                    0x100000 ///< Bit 20: 1= C9 enabled/supported
00059 #define PPM_C10                   0x200000 ///< Bit 21: 1= C10 enabled/supported
00060
00061 #define PPM_C_STATES            0x7A    ///< PPM_C1 + PPM_C3 + PPM_C6 + PPM_C7 + PPM_C7S
00062 #define C3_LATENCY              0x42
00063 #define C6_C7_SHORT_LATENCY     0x73
00064 #define C6_C7_LONG_LATENCY      0x91
00065 #define C8_LATENCY              0xE4
00066 #define C9_LATENCY              0x145
00067 #define C10_LATENCY             0x1EF
00068
00069 #define CPUID_FUNCTION_6        0x00000006
00070 //
00071 // The following definitions are based on assumed location for the  ACPI
00072 // Base Address.  Modify as necessary base on platform-specific requirements.
00073 //
00074 #define PCH_ACPI_PBLK 0x1810
00075 #define PCH_ACPI_LV2  0x1814
00076 #define PCH_ACPI_LV3  0x1815
00077 #define PCH_ACPI_LV4  0x1816
00078 #define PCH_ACPI_LV6  0x1818
00079 #define PCH_ACPI_LV5  0x1817
00080 #define PCH_ACPI_LV7  0x1819
00081
00082 //
00083 // C-State Latency (µs) and Power (mW) for C1
00084 //
00085 #define C1_LATENCY                        1
00086 #define C1_POWER                          0x3E8
00087 #define C3_POWER                          0x1F4
00088 #define C6_POWER                          0x15E
00089 #define C7_POWER                          0xC8
00090 #define C8_POWER                          0xC8
00091 #define C9_POWER                          0xC8
00092 #define C10_POWER                         0xC8
00093
00094 #define MAX_POWER_LIMIT_1_TIME_IN_SECONDS 32767
00095 #define AUTO                              0
00096 #define END_OF_TABLE                      0xFF
00097
00098 #define CONFIG_TDP_DOWN                   1
00099 #define CONFIG_TDP_UP                     2
00100 #define CONFIG_TDP_DEACTIVATE             0xFF
00101 //
00102 // MMIO definitions
00103 //
00104 #define MMIO_DDR_RAPL_LIMIT     0x58e0
00105 #define MMIO_TURBO_POWER_LIMIT  0x59A0
00106
00107 #define MAX_OVERCLOCKING_BINS   0x7
00108
00112 #define MB_POWER_LIMIT1_TIME_DEFAULT  28
00113
00114
00115
00116 #define DT_POWER_LIMIT1_TIME_DEFAULT  8
00117
00118 #define PROCESSOR_FLAVOR_MOBILE       0x04
00119 #define PROCESSOR_FLAVOR_DESKTOP      0x00
00120 #define PROCESSOR_FLAVOR_MASK         (BIT3 | BIT2)
00121
00122 //
00123 // Power definitions (Based on EMTS V1.0 for standard voltage 2.4-2.6 GHz dual-core parts.)
00124 //
00125 #define FVID_MAX_POWER      35000
00126 #define FVID_TURBO_POWER    35000
00127 #define FVID_SUPERLFM_POWER 12000
00128 //
00129 // Power definitions for LFM and Turbo mode TBD.
00130 //
00131 #define FVID_MIN_POWER  15000
00132
00133
00134
00135 #ifndef SW_SMI_S3_RESTORE_MSR
00136 #define SW_SMI_S3_RESTORE_MSR 0x48
00137 #endif
00138
00139
00140
00141 #define VR_CURRENT_DEFAULT  0
00142 #define PSI1_THRESHOLD_DEFAULT 0x14
00143 #define PSI2_THRESHOLD_DEFAULT 0x05
00144 #define PSI3_THRESHOLD_DEFAULT 0x01
00145 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: PowerMgmtInitDone.h File Reference

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PowerMgmtInitDone.h File Reference

This file defines the PowerMgmtInitDone Protocol. More...

Go to the source code of this file.

Defines

#define | EFI_POWER_MGMT_INIT_DONE_PROTOCOL_GUID
Define PPM INFO protocol GUID.

Typedefs

typedef struct
_EFI_POWER_MGMT_INIT_DONE_PROTOCOL 		EFI_POWER_MGMT_INIT_DONE_PROTOCOL

Variables

EFI_GUID | gEfiPowerMgmtInitDoneProtocolGuid
Extern the GUID for protocol users.

Detailed Description

This file defines the PowerMgmtInitDone Protocol.

Copyright:
Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement

Definition in file PowerMgmtInitDone.h.

Define Documentation

#define EFI_POWER_MGMT_INIT_DONE_PROTOCOL_GUID
Value:
{ \
    0xd71db106, 0xe32d, 0x4225, 0xbf, 0xf4, 0xde, 0x6d, 0x77, 0x87, 0x17, 0x61 \
  }

Define PPM INFO protocol GUID.

EDK and EDKII have different GUID formats

Definition at line 28 of file PowerMgmtInitDone.h.


2013 SharkBay Processor Reference Code API: PowerMgmtInitDone.h Source File

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PowerMgmtInitDone.h
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00001
00019 #ifndef _POWER_MGMT_INIT_DONE_H_
00020 #define _POWER_MGMT_INIT_DONE_H_
00021
00027 #if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
00028 #define EFI_POWER_MGMT_INIT_DONE_PROTOCOL_GUID \
00029   { \
00030     0xd71db106, 0xe32d, 0x4225, 0xbf, 0xf4, 0xde, 0x6d, 0x77, 0x87, 0x17, 0x61 \
00031   }
00032
00033 #else
00034 #define EFI_POWER_MGMT_INIT_DONE_PROTOCOL_GUID \
00035   { \
00036     0xd71db106, 0xe32d, 0x4225, \
00037     { \
00038       0xbf, 0xf4, 0xde, 0x6d, 0x77, 0x87, 0x17, 0x61 \
00039     } \
00040   }
00041 #endif
00042
00043
00044
00045 extern EFI_GUID gEfiPowerMgmtInitDoneProtocolGuid;
00046
00047 //
00048 // Forward reference for ANSI C compatibility
00049 //
00050 typedef struct _EFI_POWER_MGMT_INIT_DONE_PROTOCOL EFI_POWER_MGMT_INIT_DONE_PROTOCOL;
00051
00052 #endif
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2013 SharkBay Processor Reference Code API: PoweronHob.h File Reference

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PoweronHob.h File Reference

GUID for Power On boot mode. More...

Go to the source code of this file.

Defines

#define | EFI_POWER_ON_HOB_GUID

Variables

EFI_GUID | gEfiPowerOnHobGuid

Detailed Description

GUID for Power On boot mode.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Definition in file PoweronHob.h.

Define Documentation

#define EFI_POWER_ON_HOB_GUID
Value:
{ \
    0x468a601, 0xc535, 0x46fd, 0xa9, 0x5d, 0xbb, 0xab, 0x99, 0x1b, 0x17, 0x8c \
  }

Definition at line 22 of file PoweronHob.h.


2013 SharkBay Processor Reference Code API: PoweronHob.h Source File

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PoweronHob.h
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00001
00019 #ifndef _POWER_ON_HOB_GUID_H_
00020 #define _POWER_ON_HOB_GUID_H_
00021
00022 #define EFI_POWER_ON_HOB_GUID \
00023   { \
00024     0x468a601, 0xc535, 0x46fd, 0xa9, 0x5d, 0xbb, 0xab, 0x99, 0x1b, 0x17, 0x8c \
00025   }
00026
00027 extern EFI_GUID gEfiPowerOnHobGuid;
00028
00029 #endif
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2013 SharkBay Processor Reference Code API: PpmGlobalNvsArea.h File Reference

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PpmGlobalNvsArea.h File Reference

Definition of the CPU PM global NVS area protocol. More...

Go to the source code of this file.

Classes

struct | PPM_CTDP_LEVEL_SETTINGS
struct | PPM_GLOBAL_NVS_AREA
Global NVS Area definition. More...
struct | _PPM_GLOBAL_NVS_AREA_PROTOCOL
PPM Global NVS Area Protocol. More...

Defines

#define | EFI_PPM_GLOBAL_NVS_AREA_PROTOCOL_GUID
Processor PM Global NVS Area Protocol GUID - {6C50CDCB-7F46-4dcc-8DDD-D9F0A3C61128}.
#define | PPM_GLOBAL_NVS_AREA_REVISION_1 1
Initial Version.

Functions

EFI_FORWARD_DECLARATION (PPM_GLOBAL_NVS_AREA_PROTOCOL)
Forward reference for pure ANSI compatability.

Variables

EFI_GUID | gPpmGlobalNvsAreaProtocolGuid
Extern the GUID for protocol users.

Detailed Description

Definition of the CPU PM global NVS area protocol.

This protocol publishes the address and format of a global ACPI NVS buffer used as a communications buffer between SMM/DXE/PEI code and ASL code.

Todo:
The format is derived from the ACPI reference code, version 0.95.

Note: Data structures defined in this protocol are not naturally aligned.

Copyright:
Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement

Definition in file PpmGlobalNvsArea.h.

Define Documentation

#define EFI_PPM_GLOBAL_NVS_AREA_PROTOCOL_GUID
Value:
{ \
    0x6c50cdcb, 0x7f46, 0x4dcc, 0x8d, 0xdd, 0xd9, 0xf0, 0xa3, 0xc6, 0x11, 0x28 \
  }

Processor PM Global NVS Area Protocol GUID - {6C50CDCB-7F46-4dcc-8DDD-D9F0A3C61128}.

Definition at line 35 of file PpmGlobalNvsArea.h.


2013 SharkBay Processor Reference Code API: PpmGlobalNvsArea.h Source File

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PpmGlobalNvsArea.h
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00001
00024 #ifndef _PPM_GLOBAL_NVS_AREA_H_
00025 #define _PPM_GLOBAL_NVS_AREA_H_
00026
00030 EFI_FORWARD_DECLARATION (PPM_GLOBAL_NVS_AREA_PROTOCOL);
00031
00035 #define EFI_PPM_GLOBAL_NVS_AREA_PROTOCOL_GUID \
00036   { \
00037     0x6c50cdcb, 0x7f46, 0x4dcc, 0x8d, 0xdd, 0xd9, 0xf0, 0xa3, 0xc6, 0x11, 0x28 \
00038   }
00039
00043 extern EFI_GUID gPpmGlobalNvsAreaProtocolGuid;
00044
00045 //
00046 // Processor Power Management GlobalNvs Revisions
00047 //
00048 #define PPM_GLOBAL_NVS_AREA_REVISION_1  1 ///< Initial Version
00049
00050 #pragma pack(1)
00051
00052 typedef struct {
00053   UINT16 CtdpPowerLimit1;
00054   UINT16 CtdpPowerLimit2;
00055   UINT8  CtdpPowerLimitWindow;
00056   UINT8  CtdpCtc;
00057   UINT8  CtdpTar;
00058   UINT8  CtdpPpc;
00059 } PPM_CTDP_LEVEL_SETTINGS;
00060
00064 typedef struct {
00065   UINT8  Revision;
00066   UINT32 PpmFlags;
00067   UINT8  Reserved;
00068   //
00069   // Thermal Configuration Values
00070   //
00071   UINT8  AutoCriticalTripPoint;
00072   UINT8  AutoPassiveTripPoint;
00073   UINT8  AutoActiveTripPoint;
00074   UINT32 Cpuid;
00075   //
00076   // ConfigTDP Values
00077   //
00078   UINT8 ConfigurablePpc;
00079   //
00080   // ConfigTDP Level settngs
00081   //
00082   UINT8 CustomConfigTdp;
00083   UINT8 CtdpLevelsSupported;
00084   UINT8 ConfigTdpBootModeIndex;
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105   PPM_CTDP_LEVEL_SETTINGS CtdpLevelSettings[3];
00106   //
00107   // Mwait Hints and Latency values for C3/C6/C7/C7S
00108   //
00109   UINT8  C3MwaitValue;
00110   UINT8  C6MwaitValue;
00111   UINT8  C7MwaitValue;
00112   UINT8  CDMwaitValue;
00113   UINT16 C3Latency;
00114   UINT16 C6Latency;
00115   UINT16 C7Latency;
00116   UINT16 CDLatency;
00117   UINT16 CDIOLevel;
00118   UINT16 CDPowerValue;
00119   UINT8  MiscPowerManagementFlags;
00120 } PPM_GLOBAL_NVS_AREA;
00121 #pragma pack()
00122
00123
00124
00125 struct _PPM_GLOBAL_NVS_AREA_PROTOCOL {
00126   PPM_GLOBAL_NVS_AREA *Area;
00127 };
00128
00129 #endif
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2013 SharkBay Processor Reference Code API: SmmThunk.h File Reference

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SmmThunk.h File Reference

This file defines SMM Thunk abstraction protocol. More...

#include <EFI_PROTOCOL_DEFINITION (LegacyBios)>
Include dependency graph for SmmThunk.h:

Go to the source code of this file.

Classes

struct | _EFI_SMM_THUNK_PROTOCOL

Defines

#define | EFI_SMM_THUNK_PROTOCOL_GUID
include LegacyBios Protocol for IA32_REGISTER_SET

Typedefs

typedef BOOLEAN(* | EFI_SMM_FARCALL86 )(IN EFI_SMM_THUNK_PROTOCOL *This, IN UINT16 Segment, IN UINT16 Offset, IN OUT EFI_IA32_REGISTER_SET *Regs OPTIONAL, IN VOID *Stack OPTIONAL, IN UINTN StackSize)
typedef BOOLEAN(* | EFI_SMM_INTCALL86 )(IN EFI_SMM_THUNK_PROTOCOL *This, IN UINT16 Segment, IN UINT16 Offset, IN OUT EFI_IA32_REGISTER_SET *Regs OPTIONAL, IN VOID *Stack OPTIONAL, IN UINTN StackSize)

Functions

EFI_FORWARD_DECLARATION (EFI_SMM_THUNK_PROTOCOL)

Variables

EFI_GUID | gEfiSmmThunkProtocolGuid

Detailed Description

This file defines SMM Thunk abstraction protocol.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file SmmThunk.h.

Define Documentation

#define EFI_SMM_THUNK_PROTOCOL_GUID
Value:
{ \
    0x2a82fce6, 0x8bb6, 0x413e, 0xb9, 0xeb, 0x45, 0xdf, 0xc0, 0x52, 0x2d, 0xf3 \
  }

include LegacyBios Protocol for IA32_REGISTER_SET

Definition at line 30 of file SmmThunk.h.


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00001
00020 #ifndef _SMM_THUNK_H_
00021 #define _SMM_THUNK_H_
00022
00023 EFI_FORWARD_DECLARATION (EFI_SMM_THUNK_PROTOCOL);
00024
00028 #include EFI_PROTOCOL_DEFINITION (LegacyBios)
00029
00030 #define EFI_SMM_THUNK_PROTOCOL_GUID \
00031   { \
00032     0x2a82fce6, 0x8bb6, 0x413e, 0xb9, 0xeb, 0x45, 0xdf, 0xc0, 0x52, 0x2d, 0xf3 \
00033   }
00034
00035 typedef
00036 BOOLEAN
00037 (EFIAPI *EFI_SMM_FARCALL86)(
00038   IN EFI_SMM_THUNK_PROTOCOL          *This,
00039   IN UINT16                          Segment,
00040   IN UINT16                          Offset,
00041   IN OUT EFI_IA32_REGISTER_SET *Regs OPTIONAL,
00042   IN VOID *Stack                     OPTIONAL,
00043   IN UINTN                           StackSize
00044   );
00045
00046 typedef
00047 BOOLEAN
00048 (EFIAPI *EFI_SMM_INTCALL86)(
00049   IN EFI_SMM_THUNK_PROTOCOL          *This,
00050   IN UINT16                          Segment,
00051   IN UINT16                          Offset,
00052   IN OUT EFI_IA32_REGISTER_SET *Regs OPTIONAL,
00053   IN VOID *Stack                     OPTIONAL,
00054   IN UINTN                           StackSize
00055   );
00056
00057 struct _EFI_SMM_THUNK_PROTOCOL {
00058   EFI_SMM_FARCALL86 FarCall86;
00059   EFI_SMM_INTCALL86 IntCall86;
00060 };
00061
00062 extern EFI_GUID gEfiSmmThunkProtocolGuid;
00063
00064 #endif
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2013 SharkBay Processor Reference Code API: SmramCpuDataHeader.h File Reference

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SmramCpuDataHeader.h File Reference

GUIDs used for SMRAM CPU DATA Header signature. More...

Go to the source code of this file.

Defines

#define | SMRAM_CPU_DATA_HEADER_GUID
SMRAM CPU DATA Header for search by CpuS3Peim.

Variables

EFI_GUID | gSmramCpuDataHeaderGuid

Detailed Description

GUIDs used for SMRAM CPU DATA Header signature.

Copyright:
Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Definition in file SmramCpuDataHeader.h.

Define Documentation

#define SMRAM_CPU_DATA_HEADER_GUID
Value:
{ \
    0x5848fd2d, 0xd6af, 0x474b, 0x82, 0x75, 0x95, 0xdd, 0xe7, 0x0a, 0xe8, 0x23 \
  }

SMRAM CPU DATA Header for search by CpuS3Peim.

Definition at line 25 of file SmramCpuDataHeader.h.


2013 SharkBay Processor Reference Code API: SmramCpuDataHeader.h Source File

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SmramCpuDataHeader.h
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00001
00019 #ifndef _SMRAM_CPU_DATA_HEADER_H_
00020 #define _SMRAM_CPU_DATA_HEADER_H_
00021
00025 #define SMRAM_CPU_DATA_HEADER_GUID \
00026   { \
00027     0x5848fd2d, 0xd6af, 0x474b, 0x82, 0x75, 0x95, 0xdd, 0xe7, 0x0a, 0xe8, 0x23 \
00028   }
00029
00030 extern EFI_GUID gSmramCpuDataHeaderGuid;
00031
00032 #endif
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2013 SharkBay Processor Reference Code API: SmramCpuDataVariable.h File Reference

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SmramCpuDataVariable.h File Reference

GUIDs used for SMRAM CPU DATA Variable to keep 2 locations for copying data from regular memory to SMM memory. More...

Go to the source code of this file.

Classes

struct | SMRAM_CPU_DATA_ADDRESS

Defines

#define | SMRAM_CPU_DATA_VARIABLE_GUID
CPU Driver will maintain ACPI CPU DATA in regular memory,.
#define | SMRAM_CPU_DATA_VARIABLE L"SmramCpuDataVar"

Variables

EFI_GUID | gSmramCpuDataVariableGuid

Detailed Description

GUIDs used for SMRAM CPU DATA Variable to keep 2 locations for copying data from regular memory to SMM memory.

Copyright:
Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Definition in file SmramCpuDataVariable.h.

Define Documentation

#define SMRAM_CPU_DATA_VARIABLE_GUID
Value:
{ \
    0x429501d9, 0xe447, 0x40f4, 0x86, 0x7b, 0x75, 0xc9, 0x3a, 0x1d, 0xb5, 0x4e \
  }

CPU Driver will maintain ACPI CPU DATA in regular memory,.

  1. CpuInitDxe driver will allocate SMM memory, and normal memory
  2. Save both location in SMRAM_CPU_DATA_VARIABLE
  3. Issue SMM_FROM_CPU_DRIVER_SAVE_INFO SW SMI to ask SMM driver to copy data to SMRAM with signature.
  4. In S3 path, CPUS3 retrieves data by search signature in SMRAM.

Definition at line 31 of file SmramCpuDataVariable.h.


2013 SharkBay Processor Reference Code API: SmramCpuDataVariable.h Source File

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SmramCpuDataVariable.h
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00001
00020 #ifndef _SMRAM_CPU_DATA_VARIABLE_H_
00021 #define _SMRAM_CPU_DATA_VARIABLE_H_
00022
00031 #define SMRAM_CPU_DATA_VARIABLE_GUID \
00032   { \
00033     0x429501d9, 0xe447, 0x40f4, 0x86, 0x7b, 0x75, 0xc9, 0x3a, 0x1d, 0xb5, 0x4e \
00034   }
00035
00036 #define SMRAM_CPU_DATA_VARIABLE L"SmramCpuDataVar"
00037
00038 typedef struct {
00039   EFI_PHYSICAL_ADDRESS LockBoxData;
00040   EFI_PHYSICAL_ADDRESS SmramCpuData;
00041   UINT64               LockBoxSize;
00042 } SMRAM_CPU_DATA_ADDRESS;
00043
00044 extern EFI_GUID gSmramCpuDataVariableGuid;
00045
00046 #endif
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2013 SharkBay Processor Reference Code API: ThunkLib.h File Reference

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ThunkLib.h File Reference

Real Mode Thunk Functions for IA32 and X64. More...

Go to the source code of this file.

Classes

struct | THUNK16_CONTEXT
Byte packed structure for an 16-bit real mode thunks. More...

Defines

#define | THUNK_SAVE_FP_STATE 0x1
#define | THUNK_USER_STACK 0x2
#define | THUNK_INTERRUPT 0x10000

Functions

UINTN | R8AsmThunk16GetProperties (OUT UINTN *MinimumStackSize OPTIONAL)
Returns the properties of this real mode thunk implementation.
THUNK16_CONTEXT * | R8AsmThunk16SetProperties (OUT THUNK16_CONTEXT *ThunkContext, IN VOID *RealModeBuffer, IN UINTN BufferSize)
Tell this real mode thunk implementation the address and size of the real mode buffer needed.
VOID | R8AsmThunk16Destroy (IN OUT THUNK16_CONTEXT *ThunkContext)
Reset all internal states to their initial values.
IA32_REGISTER_SET * | R8AsmThunk16FarCall86 (IN THUNK16_CONTEXT *ThunkContext, IN OUT IA32_REGISTER_SET *RegisterSet, IN UINT32 ThunkFlags)
Make a far call to 16-bit code.
IA32_REGISTER_SET * | R8AsmThunk16Int86 (IN THUNK16_CONTEXT *ThunkContext, IN UINT8 IntNumber, IN OUT IA32_REGISTER_SET *RegisterSet, IN UINT32 ThunkFlags)
Invoke a 16-bit interrupt handler.

Detailed Description

Real Mode Thunk Functions for IA32 and X64.

Copyright:
Copyright (c) 2006 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement

Definition in file ThunkLib.h.

Function Documentation

VOID R8AsmThunk16Destroy ( IN OUT THUNK16_CONTEXT * ThunkContext )

Reset all internal states to their initial values.

The caller should not release the real mode buffer until after a call to this function.

Parameters:
[in] ThunkContext - The thunk context to destroy.
IA32_REGISTER_SET* R8AsmThunk16FarCall86 | ( | IN THUNK16_CONTEXT * | ThunkContext,
 |  | IN OUT IA32_REGISTER_SET * | RegisterSet,
 |  | IN UINT32 | ThunkFlags
 | ) |  |

Make a far call to 16-bit code.

NOTE: This function must be called on TPL_HIGH_LEVEL or with interrupts disabled because of GDTR and IDTR manipulations. This function must be placed in identity mapped pages.

Parameters:
[in] | ThunkContext | - Thunk context to use.
[in] | RegisterSet | - CPU registers would be set to the values contained in this structure before making the far call. Then CPU registers are copied back to this structure. CS:EIP points to the real mode code being called on input. SS:ESP points to the real mode stack if THUNK_USER_STACK is set on input, otherwise ignored. EFlages is ignored on input. On output, values of CS, EIP, SS and ESP should be ignored.
[in] | ThunkFlags | - 2 flags have currently been defined, THUNK_SAVE_FP_STATE and THUNK_USER_STACK. THUNK_SAVE_FP_STATE - FPU state would be saved/restored before/after calling real mode code. THUNK_USER_STACK - The stack specified by SS:ESP would be used instead of the default stack.
Return values:
RegisterSet is returned.
UINTN R8AsmThunk16GetProperties ( OUT UINTN *MinimumStackSize OPTIONAL )

Returns the properties of this real mode thunk implementation.

Currently there are 2 properties has been defined, the minimum real mode buffer size and the minimum stack size.

Parameters:
[in] MinimumStackSize - The minimum size required for a 16-bit stack.
Return values:
The | minimum size of the real mode buffer needed by this thunk implementation
is | returned.
IA32_REGISTER_SET* R8AsmThunk16Int86 | ( | IN THUNK16_CONTEXT * | ThunkContext,
 |  | IN UINT8 | IntNumber,
 |  | IN OUT IA32_REGISTER_SET * | RegisterSet,
 |  | IN UINT32 | ThunkFlags
 | ) |  |

Invoke a 16-bit interrupt handler.

NOTE: This function must be called on TPL_HIGH_LEVEL or with interrupts disabled because of GDTR and IDTR manipulations. This function must be placed in identity mapped pages.

Parameters:
[in] | ThunkContext | - Thunk context to use.
[in] | IntNumber | - The ordinal of the interrupt handler ranging from 0 to 255.
[in] | RegisterSet | - CPU registers would be set to the values contained in this structure before making the far call. Then CPU registers are copied back to this structure. SS:ESP points to the real mode stack if THUNK_USER_STACK is set on input, otherwise ignored. EFlages is ignored on input. On output, values of CS, EIP, SS and ESP should be ignored.
[in] | ThunkFlags | - 2 flags have currently been defined, THUNK_SAVE_FP_STATE and THUNK_USER_STACK. THUNK_SAVE_FP_STATE - FPU state would be saved/restored before/after calling real mode code. THUNK_USER_STACK - The stack specified by SS:ESP would be used instead of the default stack.
Return values:
RegisterSet is returned.
THUNK16_CONTEXT* R8AsmThunk16SetProperties | ( | OUT THUNK16_CONTEXT * | ThunkContext,
 |  | IN VOID * | RealModeBuffer,
 |  | IN UINTN | BufferSize
 | ) |  |

Tell this real mode thunk implementation the address and size of the real mode buffer needed.

Parameters:
[in] | ThunkContext | - The thunk context whose properties to set.
[in] | RealModeBuffer | - The address of the buffer allocated by caller. It should be aligned on a 16-byte boundary. This buffer must be in identity mapped pages.
[in] | BufferSize | - The size of RealModeBuffer. Must be larger than the minimum size required as returned by R8AsmThunk16GetProperties().


2013 SharkBay Processor Reference Code API: ThunkLib.h Source File

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ThunkLib.h
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00001
00019 #ifndef __THUNK_LIB__
00020 #define __THUNK_LIB__
00021
00025 typedef struct {
00026   UINT32 RealModeBuffer;
00027   UINT32 DefaultStack;
00028 } THUNK16_CONTEXT;
00029
00030 //
00031 // 16-bit thunking services
00032 //
00033 #define THUNK_SAVE_FP_STATE 0x1
00034 #define THUNK_USER_STACK    0x2
00035 #define THUNK_INTERRUPT     0x10000
00036
00037 //
00038 // Function Prototypes
00039 //
00050 UINTN
00051 EFIAPI
00052 R8AsmThunk16GetProperties (
00053   OUT UINTN *MinimumStackSize OPTIONAL
00054   );
00055
00067 THUNK16_CONTEXT *
00068 EFIAPI
00069 R8AsmThunk16SetProperties (
00070   OUT THUNK16_CONTEXT *ThunkContext,
00071   IN VOID             *RealModeBuffer,
00072   IN UINTN            BufferSize
00073   );
00074
00081 VOID
00082 EFIAPI
00083 R8AsmThunk16Destroy (
00084   IN OUT THUNK16_CONTEXT *ThunkContext
00085   );
00086
00112 IA32_REGISTER_SET *
00113 EFIAPI
00114 R8AsmThunk16FarCall86 (
00115   IN THUNK16_CONTEXT       *ThunkContext,
00116   IN OUT IA32_REGISTER_SET *RegisterSet,
00117   IN UINT32                ThunkFlags
00118   );
00119
00145 IA32_REGISTER_SET *
00146 EFIAPI
00147 R8AsmThunk16Int86 (
00148   IN THUNK16_CONTEXT       *ThunkContext,
00149   IN UINT8                 IntNumber,
00150   IN OUT IA32_REGISTER_SET *RegisterSet,
00151   IN UINT32                ThunkFlags
00152   );
00153
00154 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: TpmInitialized.h File Reference

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TpmInitialized.h File Reference

Tpm Initialized PPI definition, used to notify any code after TPM initialized. More...

Go to the source code of this file.

Defines

#define | PEI_TPM_INITIALIZED_PPI_GUID

Variables

EFI_GUID | gPeiTpmInitializedPpiGuid

Detailed Description

Tpm Initialized PPI definition, used to notify any code after TPM initialized.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement

Definition in file TpmInitialized.h.

Define Documentation

#define PEI_TPM_INITIALIZED_PPI_GUID
Value:
{ \
    0xe9db0d58, 0xd48d, 0x47f6, 0x9c, 0x6e, 0x6f, 0x40, 0xe8, 0x6c, 0x7b, 0x41 \
  }

Definition at line 22 of file TpmInitialized.h.


2013 SharkBay Processor Reference Code API: TpmInitialized.h Source File

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TpmInitialized.h
Go to the documentation of this file.
00001
00019 #ifndef _PEI_TPM_INITIALIZED_PPI_H_
00020 #define _PEI_TPM_INITIALIZED_PPI_H_
00021
00022 #define PEI_TPM_INITIALIZED_PPI_GUID \
00023   { \
00024     0xe9db0d58, 0xd48d, 0x47f6, 0x9c, 0x6e, 0x6f, 0x40, 0xe8, 0x6c, 0x7b, 0x41 \
00025   }
00026
00027 extern EFI_GUID gPeiTpmInitializedPpiGuid;
00028
00029 #endif
Generated on Thu Jun 20 2013 01:47:37 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: Txt.h File Reference

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Classes | Defines
Txt.h File Reference

This file contains definitions required to use the TXT BIOS Authenticated Code Module Library. More...

Go to the source code of this file.

Classes

struct | HEAP_EXT_DATA_ELEMENT
struct | HEAP_BIOS_SPEC_VER_ELEMENT
struct | HEAP_BIOSACM_ELEMENT
struct | BIOS_OS_DATA_REGION

Defines

#define | TPM_TIME_OUT 750
#define | TXT_RLP_INIT 1
#define | MmPciAddress(Segment, Bus, Device, Function, Register)
MMIO definition.
#define | TXT_BIOS_SPEC_VER_MAJOR 2
#define | TXT_BIOS_SPEC_VER_MINOR 1
#define | TXT_BIOS_SPEC_VER_REVISION 0
#define | TXT_LAUNCH_SCLEAN 0x00
#define | TXT_RESET_EST_BIT 0x01
#define | TXT_RESET_AUX 0x02
#define | TXT_LAUNCH_SCHECK 0x04
#define | TPM_STATUS_REG_ADDRESS 0xFED40000
#define | TXT_PUBLIC_BASE 0xFED30000
#define | TXT_PRIVATE_BASE 0xFED20000
#define | TXT_CONFIG_SPACE_LENGTH 0x60000
#define | TXT_ERROR_STATUS_REG_OFF 0x8
#define | TXT_SINIT_BASE_REG_OFF 0x270
#define | TXT_SINIT_SIZE_REG_OFF 0x278
#define | TXT_SINIT_SIZE_REG_OFF2 0x27C
#define | TXT_SVMM_JOIN_REG_OFF 0x290
#define | TXT_SVMM_JOIN_REG_OFF2 0x294
#define | TXT_HEAP_BASE_REG_OFF 0x300
#define | TXT_HEAP_SIZE_REG_OFF 0x308
#define | TXT_SCRATCHPAD 0x320
#define | TXT_SCRATCHPAD2 0x324
#define | TXT_SCRATCHPAD3 0x328
#define | TXT_SCRATCHPAD4 0x32C
#define | TXT_DPR_SIZE_REG_OFF 0x330
#define | TXT_E2STS_REG_OFF 0x8F0
#define | TXT_BLOCK_MEM_STS BIT2
#define | TXT_SECRETS_STS BIT1
#define | TXT_SLP_ENTRY_ERROR_STS BIT0
#define | MCU_BASE_ADDR TXT_SINIT_SIZE_REG_OFF
#define | BIOACM_ADDR TXT_SINIT_SIZE_REG_OFF2
#define | APINIT_ADDR TXT_SVMM_JOIN_REG_OFF
#define | SEMAPHORE TXT_SVMM_JOIN_REG_OFF2
#define | PEI_BIOS_ACM_FILE_GUID
GUIDs used by TXT drivers.
#define | PEI_AP_STARTUP_FILE_GUID
#define | CPU_MICROCODE_FILE_GUID
#define | BIOS_OS_DATAREGION_VERSION 4
BIOS OS Data region definitions.
#define | HEAP_EXTDATA_TYPE_BIOS_SPEC_VER 1
BIOS spec version element.
#define | HEAP_EXTDATA_TYPE_BIOSACM 2
BIOS ACM element.
#define | HEAP_EXTDATA_TYPE_END 0
END type.

Detailed Description

This file contains definitions required to use the TXT BIOS Authenticated Code Module Library.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file Txt.h.

Define Documentation

#define CPU_MICROCODE_FILE_GUID
Value:
{ \
    0x17088572, 0x377F, 0x44ef, 0x8F, 0x4E, 0xB0, 0x9F, 0xFF, 0x46, 0xA0, 0x70 \
  }

Definition at line 100 of file Txt.h.

#define MmPciAddress | ( | Segment,
 |  | Bus,
 |  | Device,
 |  | Function,
 |  | Register
 | ) |
Value:
((UINTN) (PciRead32 (PCI_LIB_ADDRESS (0,0,0,0x60)) & 0xFC000000) + \
         (UINTN) (Bus << 20) + \
         (UINTN) (Device << 15) + \
         (UINTN) (Function << 12) + \
         (UINTN) (Register) \
  )

MMIO definition.

Definition at line 33 of file Txt.h.

#define PEI_AP_STARTUP_FILE_GUID
Value:
{ \
    0xD1E59F50, 0xE8C3, 0x4545, 0xBF, 0x61, 0x11, 0xF0, 0x02, 0x23, 0x3C, 0x97 \
  }

Definition at line 95 of file Txt.h.

#define PEI_BIOS_ACM_FILE_GUID
Value:
{ \
    0x2D27C618, 0x7DCD, 0x41F5, 0xBB, 0x10, 0x21, 0x16, 0x6B, 0xE7, 0xE1, 0x43 \
  }

GUIDs used by TXT drivers.

Definition at line 90 of file Txt.h.


2013 SharkBay Processor Reference Code API: Txt.h Source File

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00001
00022 #ifndef _TXT_BIOS_ACM_LIB_H_
00023 #define _TXT_BIOS_ACM_LIB_H_
00024
00025 #define TPM_TIME_OUT  750
00026
00027 #define TXT_RLP_INIT  1
00028
00032 #ifndef MmPciAddress
00033 #define MmPciAddress(Segment, Bus, Device, Function, Register) \
00034         ((UINTN) (PciRead32 (PCI_LIB_ADDRESS (0,0,0,0x60)) & 0xFC000000) + \
00035          (UINTN) (Bus << 20) + \
00036          (UINTN) (Device << 15) + \
00037          (UINTN) (Function << 12) + \
00038          (UINTN) (Register) \
00039   )
00040 #endif
00041 //
00042 // TxT BIOS Spec version
00043 //
00044 #define TXT_BIOS_SPEC_VER_MAJOR     2
00045 #define TXT_BIOS_SPEC_VER_MINOR     1
00046 #define TXT_BIOS_SPEC_VER_REVISION  0
00047
00048 //
00049 // The following are values that are placed in the esi register when
00050 // calling the BIOS ACM.  These constants are used as parameters to the
00051 // TxtSetupandLaunchBiosAcm function.
00052 //
00053 #define TXT_LAUNCH_SCLEAN         0x00
00054 #define TXT_RESET_EST_BIT         0x01
00055 #define TXT_RESET_AUX             0x02
00056 #define TXT_LAUNCH_SCHECK         0x04
00057
00058 #define TPM_STATUS_REG_ADDRESS    0xFED40000
00059 #define TXT_PUBLIC_BASE           0xFED30000
00060 #define TXT_PRIVATE_BASE          0xFED20000
00061 #define TXT_CONFIG_SPACE_LENGTH   0x60000
00062
00063 #define TXT_ERROR_STATUS_REG_OFF  0x8
00064 #define TXT_SINIT_BASE_REG_OFF    0x270
00065 #define TXT_SINIT_SIZE_REG_OFF    0x278
00066 #define TXT_SINIT_SIZE_REG_OFF2   0x27C
00067 #define TXT_SVMM_JOIN_REG_OFF     0x290
00068 #define TXT_SVMM_JOIN_REG_OFF2    0x294
00069 #define TXT_HEAP_BASE_REG_OFF     0x300
00070 #define TXT_HEAP_SIZE_REG_OFF     0x308
00071 #define TXT_SCRATCHPAD          0x320
00072 #define TXT_SCRATCHPAD2         0x324
00073 #define TXT_SCRATCHPAD3         0x328
00074 #define TXT_SCRATCHPAD4         0x32C
00075 #define TXT_DPR_SIZE_REG_OFF    0x330
00076
00077 #define TXT_E2STS_REG_OFF       0x8F0
00078 #define TXT_BLOCK_MEM_STS       BIT2
00079 #define TXT_SECRETS_STS         BIT1
00080 #define TXT_SLP_ENTRY_ERROR_STS BIT0
00081
00082 #define MCU_BASE_ADDR           TXT_SINIT_SIZE_REG_OFF
00083 #define BIOACM_ADDR             TXT_SINIT_SIZE_REG_OFF2
00084 #define APINIT_ADDR             TXT_SVMM_JOIN_REG_OFF
00085 #define SEMAPHORE               TXT_SVMM_JOIN_REG_OFF2
00086
00090 #define PEI_BIOS_ACM_FILE_GUID \
00091   { \
00092     0x2D27C618, 0x7DCD, 0x41F5, 0xBB, 0x10, 0x21, 0x16, 0x6B, 0xE7, 0xE1, 0x43 \
00093   }
00094
00095 #define PEI_AP_STARTUP_FILE_GUID \
00096   { \
00097     0xD1E59F50, 0xE8C3, 0x4545, 0xBF, 0x61, 0x11, 0xF0, 0x02, 0x23, 0x3C, 0x97 \
00098   }
00099
00100 #define CPU_MICROCODE_FILE_GUID \
00101   { \
00102     0x17088572, 0x377F, 0x44ef, 0x8F, 0x4E, 0xB0, 0x9F, 0xFF, 0x46, 0xA0, 0x70 \
00103   }
00104
00105 #pragma pack(push, 1)
00106
00107
00108
00109 #define BIOS_OS_DATAREGION_VERSION  4
00110
00111 typedef struct {
00112   UINT32 Type;
00113   UINT32 Size;
00114 } HEAP_EXT_DATA_ELEMENT;
00115
00119 #define HEAP_EXTDATA_TYPE_BIOS_SPEC_VER 1
00120
00121 typedef struct {
00122   HEAP_EXT_DATA_ELEMENT Header;
00123   UINT16                SpecVerMajor;
00124   UINT16                SpecVerMinor;
00125   UINT16                SpecVerRevision;
00126 } HEAP_BIOS_SPEC_VER_ELEMENT;
00127
00131 #define HEAP_EXTDATA_TYPE_BIOSACM 2
00132 typedef struct {
00133   HEAP_EXT_DATA_ELEMENT Header;
00134   UINT32                NumAcms;
00135 } HEAP_BIOSACM_ELEMENT;
00136
00140 #define HEAP_EXTDATA_TYPE_END 0
00141
00142 typedef struct {
00143   UINT32                Version;
00144   UINT32                BiosSinitSize;
00145   EFI_PHYSICAL_ADDRESS  LcpPdBase;
00146   UINT64                LcpPdSize;
00147   UINT32                NumOfLogicalProcessors;
00148   UINT64                Flags;
00149   HEAP_EXT_DATA_ELEMENT ExtData;
00150 } BIOS_OS_DATA_REGION;
00151
00152 #pragma pack(pop)
00153 #endif
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2013 SharkBay Processor Reference Code API: TxtInfoHob.h File Reference

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TxtInfoHob.h File Reference

This file contains definitions required for creation of TXT Info HOB. More...

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Classes

struct | TXT_INFO_DATA
struct | TXT_INFO_HOB

Defines

#define | TXT_INFO_HOB_GUID
#define | FLAGS0 0x1
#define | TXT_CPU_RESET_REQUIRED 0x2
#define | TPM_INIT_FAILED 0x4
#define | CMOS_INDEX_PORT 0x70
#define | CMOS_DATA_PORT 0x71

Variables

EFI_GUID | gTxtInfoHobGuid

Detailed Description

This file contains definitions required for creation of TXT Info HOB.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file TxtInfoHob.h.

Define Documentation

#define TXT_INFO_HOB_GUID
Value:
{ \
    0x2986883F, 0x88E0, 0x48d0, 0x4B, 0x82, 0x20, 0xC2, 0x69, 0x48, 0xDD, 0xAC \
  }

Definition at line 24 of file TxtInfoHob.h.


2013 SharkBay Processor Reference Code API: TxtInfoHob.h Source File

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TxtInfoHob.h
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00001
00021 #ifndef _TXT_HOB_H_
00022 #define _TXT_HOB_H_
00023
00024 #define TXT_INFO_HOB_GUID \
00025   { \
00026     0x2986883F, 0x88E0, 0x48d0, 0x4B, 0x82, 0x20, 0xC2, 0x69, 0x48, 0xDD, 0xAC \
00027   }
00028
00029 extern EFI_GUID gTxtInfoHobGuid;
00030
00031 #pragma pack(push, 1)
00032
00033 typedef struct {
00034   BOOLEAN              ChipsetIsTxtCapable;
00035   UINT8                TxtMode;
00036   UINT64               PmBase;
00037   UINT64               SinitMemorySize;
00038   UINT64               TxtHeapMemorySize;
00039   EFI_PHYSICAL_ADDRESS TxtDprMemoryBase;
00040   UINT64               TxtDprMemorySize;
00041   EFI_PHYSICAL_ADDRESS BiosAcmBase;
00042   UINT64               BiosAcmSize;
00043   EFI_PHYSICAL_ADDRESS McuUpdateDataAddr;
00044   EFI_PHYSICAL_ADDRESS SinitAcmBase;
00045   UINT64               SinitAcmSize;
00046   UINT64               TgaSize;
00047   EFI_PHYSICAL_ADDRESS TxtLcpPdBase;
00048   UINT64               TxtLcpPdSize;
00049   UINT64 Flags;
00050 } TXT_INFO_DATA;
00051
00052 #define FLAGS0                  0x1
00053 #define TXT_CPU_RESET_REQUIRED  0x2
00054 #define TPM_INIT_FAILED         0x4
00055
00056 #define CMOS_INDEX_PORT         0x70
00057 #define CMOS_DATA_PORT          0x71
00058
00059 typedef struct {
00060   EFI_HOB_GUID_TYPE EfiHobGuidType;
00061   TXT_INFO_DATA     Data;
00062 } TXT_INFO_HOB;
00063 #pragma pack(pop)
00064
00065 #endif
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2013 SharkBay Processor Reference Code API: TxtLibrary.h File Reference

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Functions
TxtLibrary.h File Reference

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. More...

#include "EdkIIGlueBase.h"
Include dependency graph for TxtLibrary.h:

Go to the source code of this file.

Functions

UINT32 CheckSmxCapabilities (VOID)
Execute GETSEC[CAPABILITIES] to report the SMX capabilities.

Detailed Description

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor.

This file may be modified by the user, subject to additional terms of the license agreement.

Copyright:
Copyright (c) 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

TxtLibrary.h

Header file for TXT Lib implementation.

Definition in file TxtLibrary.h.

Function Documentation

UINT32 CheckSmxCapabilities ( VOID )

Execute GETSEC[CAPABILITIES] to report the SMX capabilities.


2013 SharkBay Processor Reference Code API: TxtLibrary.h Source File

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TxtLibrary.h
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00001
00026 #ifndef _TXT_LIBRARY_H_
00027 #define _TXT_LIBRARY_H_
00028
00029 #if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
00030 #include "EdkIIGlueBase.h"
00031 #endif
00032
00033 UINT32
00034 CheckSmxCapabilities (
00035   VOID
00036   )
00042 ;
00043
00044 #endif
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2013 SharkBay Processor Reference Code API: TxtMemoryUnlocked.h File Reference

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TxtMemoryUnlocked.h File Reference

This file contains PPI definition that is installed by TXT PEIM. More...

Go to the source code of this file.

Defines

#define | PEI_TXT_MEMORY_UNLOCKED_PPI_GUID

Variables

EFI_GUID | gPeiTxtMemoryUnlockedPpiGuid

Detailed Description

This file contains PPI definition that is installed by TXT PEIM.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file TxtMemoryUnlocked.h.

Define Documentation

#define PEI_TXT_MEMORY_UNLOCKED_PPI_GUID
Value:
{ \
    0x38cdd10b, 0x767d, 0x4f6e, 0xa7, 0x44, 0x67, 0xee, 0x1d, 0xfe, 0x2f, 0xa5 \
  }

Definition at line 25 of file TxtMemoryUnlocked.h.


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TxtMemoryUnlocked.h
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00001
00022 #ifndef _PEI_TXT_MEMORY_UNLOCKED_PPI_H_
00023 #define _PEI_TXT_MEMORY_UNLOCKED_PPI_H_
00024
00025 #define PEI_TXT_MEMORY_UNLOCKED_PPI_GUID \
00026   { \
00027     0x38cdd10b, 0x767d, 0x4f6e, 0xa7, 0x44, 0x67, 0xee, 0x1d, 0xfe, 0x2f, 0xa5 \
00028   }
00029
00030 extern EFI_GUID gPeiTxtMemoryUnlockedPpiGuid;
00031
00032 #endif
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2013 SharkBay Processor Reference Code API: TxtOneTouch.h File Reference

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TxtOneTouch.h File Reference

This file contains definitions required for One-Touch function. More...

Go to the source code of this file.

Defines

#define | TXT_ONE_TOUCH_GUID
#define | ENABLE_VT 128
#define | DISABLE_VT_TXT 129
#define | ENABLE_VTD 130
#define | DISABLE_VTD_TXT 131
#define | ENABLE_ACTTPM_VT_VTD_TXT_DISABLE_STM 132
#define | ENABLE_ACTTPM_VT_VTD_TXT_STM 133
#define | DISABLE_STM 134
#define | DISABLE_TXT_STM 135
#define | DISABLE_SENTER_VMX 136
optional
#define | ENABLE_VMX_SMX_ONLY 137
optional
#define | ENABLE_VMX_OUTSIDE_SMX 138
optional
#define | ENABLE_VMX 139
optional
#define | ENABLE_SENTER_ONLY 140
optional
#define | ENABLE_SENTER_VMX_IN_SMX 141
optional
#define | ENABLE_SENTER_VMX_OUTSIDE_SMX 142
optional
#define | ENABLE_SENTER_VMX 143
optional
#define | SET_NO_TXT_MAINTENANCE_FALSE 159
#define | SET_NO_TXT_MAINTENANCE_TRUE 160

Variables

EFI_GUID | gTxtOneTouchGuid

Detailed Description

This file contains definitions required for One-Touch function.

Copyright:
Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

This file contains an 'Intel Peripheral Driver' and uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file TxtOneTouch.h.

Define Documentation

#define TXT_ONE_TOUCH_GUID
Value:
{ \
    0x3D989471, 0xCFAC, 0x46B7, 0x9B, 0x1C, 0x8, 0x43, 0x1, 0x9, 0x40, 0x2D \
  }

Definition at line 24 of file TxtOneTouch.h.


2013 SharkBay Processor Reference Code API: TxtOneTouch.h Source File

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TxtOneTouch.h
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00001
00021 #ifndef _TXT_ONE_TOUCH_H_
00022 #define _TXT_ONE_TOUCH_H_
00023
00024 #define TXT_ONE_TOUCH_GUID \
00025   { \
00026     0x3D989471, 0xCFAC, 0x46B7, 0x9B, 0x1C, 0x8, 0x43, 0x1, 0x9, 0x40, 0x2D \
00027   }
00028
00029 extern EFI_GUID gTxtOneTouchGuid;
00030
00031 //
00032 // Operation
00033 //
00034 #define ENABLE_VT                             128
00035 #define DISABLE_VT_TXT                        129
00036 #define ENABLE_VTD                            130
00037 #define DISABLE_VTD_TXT                       131
00038 #define ENABLE_ACTTPM_VT_VTD_TXT_DISABLE_STM  132
00039 #define ENABLE_ACTTPM_VT_VTD_TXT_STM          133
00040 #define DISABLE_STM                           134
00041 #define DISABLE_TXT_STM                       135
00042 #define DISABLE_SENTER_VMX                    136 ///< optional
00043 #define ENABLE_VMX_SMX_ONLY                   137 ///< optional
00044 #define ENABLE_VMX_OUTSIDE_SMX                138 ///< optional
00045 #define ENABLE_VMX                            139 ///< optional
00046 #define ENABLE_SENTER_ONLY                    140 ///< optional
00047 #define ENABLE_SENTER_VMX_IN_SMX              141 ///< optional
00048 #define ENABLE_SENTER_VMX_OUTSIDE_SMX         142 ///< optional
00049 #define ENABLE_SENTER_VMX                     143 ///< optional
00050 #define SET_NO_TXT_MAINTENANCE_FALSE          159
00051 #define SET_NO_TXT_MAINTENANCE_TRUE           160
00052
00053 #endif
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2013 SharkBay Processor Reference Code API: File Members

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- a -

  • ALIGNMENT_IN_PAGES : PfatDefinitions.h
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2013 SharkBay Processor Reference Code API: File Members

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- b -

  • BIOS_OS_DATAREGION_VERSION : Txt.h
  • BIT63 : CommonIncludes.h
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2013 SharkBay Processor Reference Code API: File Members

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- c -

  • C6_LONG_LATENCY_ENABLE : PowerMgmtDefinitions.h
  • C7_LONG_LATENCY_ENABLE : PowerMgmtDefinitions.h
  • C7s_LONG_LATENCY_ENABLE : PowerMgmtDefinitions.h
  • C_STATE_TIME_UNIT : CpuPmConfig.h
  • CheckSmxCapabilities() : TxtLibrary.h
  • ConvertToMailboxFormat() : OverclockingLibrary.h
  • ConvertVoltageOffset() : OverclockingLibrary.h
  • ConvertVoltageTarget() : OverclockingLibrary.h
  • CPU_CAUSE_NOT_DISABLED : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • CPU_PLATFORM_CATEGORY : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • CPU_RC_VERSION : CpuInfo.h
  • CPU_STEPPING : CpuRegs.h
  • CUSTOM_POWER_UNIT : CpuPmConfig.h
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2013 SharkBay Processor Reference Code API: File Members

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Here is a list of all documented file members with links to the documentation:

- d -

  • DEEP_C_STATE : CpuPmConfig.h
  • DISABLE_SENTER_VMX : TxtOneTouch.h
  • DT_POWER_LIMIT1_TIME_DEFAULT : PowerMgmtDefinitions.h
  • DXE_CPU_INFO_REVISION_1 : CpuInfo.h
  • DXE_CPU_PLATFORM_POLICY_PROTOCOL : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_1 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_2 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_3 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_4 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_5 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_6 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_7 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
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2013 SharkBay Processor Reference Code API: File Members

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Here is a list of all documented file members with links to the documentation:

- e -

  • EFI_FORWARD_DECLARATION() : PpmGlobalNvsArea.h
  • EFI_PI_MP_SERVICES_ENABLEDISABLEAP : PiMpService.h
  • EFI_PI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS : PiMpService.h
  • EFI_PI_MP_SERVICES_GET_PROCESSOR_INFO : PiMpService.h
  • EFI_PI_MP_SERVICES_PROTOCOL : PiMpService.h
  • EFI_PI_MP_SERVICES_PROTOCOL_GUID : PiMpService.h
  • EFI_PI_MP_SERVICES_STARTUP_ALL_APS : PiMpService.h
  • EFI_PI_MP_SERVICES_STARTUP_THIS_AP : PiMpService.h
  • EFI_PI_MP_SERVICES_SWITCH_BSP : PiMpService.h
  • EFI_PI_MP_SERVICES_WHOAMI : PiMpService.h
  • EFI_POWER_MGMT_INIT_DONE_PROTOCOL_GUID : PowerMgmtInitDone.h
  • EFI_PPM_GLOBAL_NVS_AREA_PROTOCOL_GUID : PpmGlobalNvsArea.h
  • EFI_SMM_THUNK_PROTOCOL_GUID : SmmThunk.h
  • EfiCpuid() : CpuBaseLib.h
  • EfiCpuidExt() : CpuBaseLib.h
  • EfiCpuVersion() : CpuBaseLib.h
  • EfiDisableCache() : CpuBaseLib.h
  • EfiDisableInterrupts() : CpuBaseLib.h
  • EfiEnableCache() : CpuBaseLib.h
  • EfiEnableInterrupts() : CpuBaseLib.h
  • EfiGetEflags() : CpuBaseLib.h
  • EfiHalt() : CpuBaseLib.h
  • EfiInvd() : CpuBaseLib.h
  • EfiMakeCpuVersion : CpuBaseLib.h
  • EfiReadMsr() : CpuBaseLib.h
  • EfiReadTsc() : CpuBaseLib.h
  • EfiWbinvd() : CpuBaseLib.h
  • EfiWriteMsr() : CpuBaseLib.h
  • ENABLE_SENTER_ONLY : TxtOneTouch.h
  • ENABLE_SENTER_VMX : TxtOneTouch.h
  • ENABLE_SENTER_VMX_IN_SMX : TxtOneTouch.h
  • ENABLE_SENTER_VMX_OUTSIDE_SMX : TxtOneTouch.h
  • ENABLE_VMX : TxtOneTouch.h
  • ENABLE_VMX_OUTSIDE_SMX : TxtOneTouch.h
  • ENABLE_VMX_SMX_ONLY : TxtOneTouch.h
  • END_OF_CPU_LIST : PiMpService.h
  • EnumCpuSteppingMax : CpuRegs.h
  • EnumCrwB0 : CpuRegs.h
  • EnumHswA0 : CpuRegs.h
  • EnumHswUltB0 : CpuRegs.h
  • ERR_BAD_DIRECTORY : PfatDefinitions.h
  • ERR_BAD_PPDT : PfatDefinitions.h
  • ERR_BAD_PUP : PfatDefinitions.h
  • ERR_BAD_PUPC : PfatDefinitions.h
  • ERR_BAD_SVN : PfatDefinitions.h
  • ERR_EXEC_LIMIT : PfatDefinitions.h
  • ERR_INTERNAL_ERROR : PfatDefinitions.h
  • ERR_INVALID_LINE : PfatDefinitions.h
  • ERR_LAUNCH_FAIL : PfatDefinitions.h
  • ERR_OK : PfatDefinitions.h
  • ERR_OVERFLOW : PfatDefinitions.h
  • ERR_RANGE_VIOLATION : PfatDefinitions.h
  • ERR_SCRIPT_SYNTAX : PfatDefinitions.h
  • ERR_SFAM_VIOLATION : PfatDefinitions.h
  • ERR_UNDEFINED_FLASH_OBJECT : PfatDefinitions.h
  • ERR_UNEXPECTED_OPCODE : PfatDefinitions.h
  • ERR_UNSUPPORTED_CPU : PfatDefinitions.h
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2013 SharkBay Processor Reference Code API: File Members

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Here is a list of all documented file members with links to the documentation:

- g -

  • gEfiPowerMgmtInitDoneProtocolGuid : PowerMgmtInitDone.h
  • GetCpuFamily() : CpuPlatformLib.h
  • GetCpuSku() : CpuPlatformLib.h
  • GetCpuStepping() : CpuPlatformLib.h
  • GetFivrConfig() : OverclockingLibrary.h
  • GetOcCapabilities() : OverclockingLibrary.h
  • GetSvidConfig() : OverclockingLibrary.h
  • GetVoltageFrequencyItem() : OverclockingLibrary.h
  • gPpmGlobalNvsAreaProtocolGuid : PpmGlobalNvsArea.h
  • gSmmPfatProtocolGuid : Pfat.h
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2013 SharkBay Processor Reference Code API: File Members

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Here is a list of all documented file members with links to the documentation:

- h -

  • HEAP_EXTDATA_TYPE_BIOS_SPEC_VER : Txt.h
  • HEAP_EXTDATA_TYPE_BIOSACM : Txt.h
  • HEAP_EXTDATA_TYPE_END : Txt.h
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2013 SharkBay Processor Reference Code API: File Members

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Here is a list of all documented file members with links to the documentation:

- i -

  • IsBootGuardSupported() : BootGuardLibrary.h
  • IsCpuSupported() : CpuPlatformLib.h
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2013 SharkBay Processor Reference Code API: File Members

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Here is a list of all documented file members with links to the documentation:

- m -

  • MAILBOX_READ_TIMEOUT : CpuPlatformLib.h
  • MAILBOX_WAIT_STALL : CpuPlatformLib.h
  • MAILBOX_WAIT_TIMEOUT : CpuPlatformLib.h
  • MailboxRead() : CpuPlatformLib.h
  • MailboxWrite() : CpuPlatformLib.h
  • MAX_CUSTOM_CTDP_ENTRIES : CpuPmConfig.h
  • MAX_CUSTOM_RATIO_TABLE_ENTRIES : CpuPmConfig.h
  • MAX_PFAT_LOG_PAGE : PfatDefinitions.h
  • MAX_PKG_C_STATE : CpuPmConfig.h
  • MB_POWER_LIMIT1_TIME_DEFAULT : PowerMgmtDefinitions.h
  • MmPciAddress : Txt.h
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2013 SharkBay Processor Reference Code API: File Members

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Here is a list of all documented file members with links to the documentation:

- o -

  • OC_LIB_WAIT_TIMEOUT : OverclockingLibrary.h
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: File Members

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Here is a list of all documented file members with links to the documentation:

- p -

  • PEI_BIOS_ACM_FILE_GUID : Txt.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_1 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_2 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_3 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_4 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_5 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_6 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_7 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_8 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PFAT_COMMAND_BEGIN : PfatDefinitions.h
  • PFAT_COMMAND_EC_CMD_WR_IMM : PfatDefinitions.h
  • PFAT_COMMAND_EC_CMD_WR_INDEX : PfatDefinitions.h
  • PFAT_COMMAND_EC_DATA_RD : PfatDefinitions.h
  • PFAT_COMMAND_EC_DATA_WR_IMM : PfatDefinitions.h
  • PFAT_COMMAND_EC_DATA_WR_INDEX : PfatDefinitions.h
  • PFAT_COMMAND_EC_STS_RD : PfatDefinitions.h
  • PFAT_COMMAND_END : PfatDefinitions.h
  • PFAT_COMMAND_ERASE_BLK : PfatDefinitions.h
  • PFAT_COMMAND_NOP : PfatDefinitions.h
  • PFAT_COMMAND_READ_IMM : PfatDefinitions.h
  • PFAT_COMMAND_READ_INDEX : PfatDefinitions.h
  • PFAT_COMMAND_SET_BUFFER_INDEX : PfatDefinitions.h
  • PFAT_COMMAND_SET_FLASH_INDEX : PfatDefinitions.h
  • PFAT_COMMAND_WRITE_IMM : PfatDefinitions.h
  • PFAT_COMMAND_WRITE_INDEX : PfatDefinitions.h
  • PFAT_ERASE : Pfat.h
  • PFAT_EXECUTE : Pfat.h
  • PFAT_HOB_GUID : PfatDefinitions.h
  • PFAT_LOG_MEMORY_OFFSET : PfatDefinitions.h
  • PFAT_MEMORY_PAGES : PfatDefinitions.h
  • PFAT_MODULE_GUID : PfatDefinitions.h
  • PFAT_WRITE : Pfat.h
  • PLATFORM_CPU_GET_CPU_INFO : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PLATFORM_CPU_GET_MAX_COUNT : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PLATFORM_CPU_RETRIEVE_MICROCODE : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PollMailboxReady() : CpuPlatformLib.h
  • POWER_MGMT_ACPI_TABLE_STORAGE_GUID : PowerMgmtAcpiTableStorage.h
  • PowerUnit125MilliWatts : CpuPmConfig.h
  • PowerUnitWatts : CpuPmConfig.h
  • PPM_C1 : PowerMgmtDefinitions.h
  • PPM_C10 : PowerMgmtDefinitions.h
  • PPM_C1E : PowerMgmtDefinitions.h
  • PPM_C3 : PowerMgmtDefinitions.h
  • PPM_C6 : PowerMgmtDefinitions.h
  • PPM_C7 : PowerMgmtDefinitions.h
  • PPM_C7S : PowerMgmtDefinitions.h
  • PPM_C8 : PowerMgmtDefinitions.h
  • PPM_C9 : PowerMgmtDefinitions.h
  • PPM_C_STATES : PowerMgmtDefinitions.h
  • PPM_CD : PowerMgmtDefinitions.h
  • PPM_CMP : PowerMgmtDefinitions.h
  • PPM_CUSTOM_CTDP : CpuPmConfig.h
  • PPM_CUSTOM_CTDP_TABLE : CpuPmConfig.h
  • PPM_EEPST : PowerMgmtDefinitions.h
  • PPM_EIST : PowerMgmtDefinitions.h
  • PPM_GLOBAL_NVS_AREA_REVISION_1 : PpmGlobalNvsArea.h
  • PPM_LOCK_ENABLES : CpuPmConfig.h
  • PPM_MWAIT_EXT : PowerMgmtDefinitions.h
  • PPM_TIMED_MWAIT : PowerMgmtDefinitions.h
  • PPM_TM : PowerMgmtDefinitions.h
  • PPM_TSTATE_FINE_GRAINED : PowerMgmtDefinitions.h
  • PPM_TSTATES : PowerMgmtDefinitions.h
  • PPM_TURBO : PowerMgmtDefinitions.h
  • PPM_TURBO_SETTINGS : CpuPmConfig.h
  • PROCESSOR_AS_BSP_BIT : PiMpService.h
  • PROCESSOR_ENABLED_BIT : PiMpService.h
  • PROCESSOR_HEALTH_STATUS_BIT : PiMpService.h
  • PUP_BUFFER_SIZE : PfatDefinitions.h
  • PUPC_MEMORY_OFFSET : PfatDefinitions.h
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2013 SharkBay Processor Reference Code API: File Members

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Here is a list of all documented file members with links to the documentation:

- r -

  • R8AsmThunk16Destroy() : ThunkLib.h
  • R8AsmThunk16FarCall86() : ThunkLib.h
  • R8AsmThunk16GetProperties() : ThunkLib.h
  • R8AsmThunk16Int86() : ThunkLib.h
  • R8AsmThunk16SetProperties() : ThunkLib.h
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2013 SharkBay Processor Reference Code API: File Members

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Here is a list of all documented file members with links to the documentation:

- s -

  • SetFivrConfig() : OverclockingLibrary.h
  • SetSvidConfig() : OverclockingLibrary.h
  • SetVoltageFrequencyItem() : OverclockingLibrary.h
  • SMM_PFAT_PROTOCOL_GUID : Pfat.h
  • SMRAM_CPU_DATA_HEADER_GUID : SmramCpuDataHeader.h
  • SMRAM_CPU_DATA_VARIABLE_GUID : SmramCpuDataVariable.h
  • StopPbeTimer() : BootGuardLibrary.h
  • SW_SMI_S3_RESTORE_MSR : PowerMgmtDefinitions.h
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2013 SharkBay Processor Reference Code API: File Members

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Here is a list of all documented file members with links to the documentation:

- t -

  • TXT_LCP_PD_BASE : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • TXT_LCP_PD_SIZE : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • TXT_SUPPORT : CpuInfo.h
  • TXT_TGA_MEMORY_SIZE : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • TXT_TGR_MEMORY_SIZE : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • TXT_TGTT_MEMORY_SIZE : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
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2013 SharkBay Processor Reference Code API: File Members

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Here is a list of all documented file members with links to the documentation:

- v -

  • V_IO_CAPT_LVL2 : CpuRegs.h
  • V_IO_CAPT_LVL3 : CpuRegs.h
  • V_IO_CAPT_LVL4 : CpuRegs.h
  • V_IO_CAPT_LVL5 : CpuRegs.h
  • V_IO_CAPT_LVL6 : CpuRegs.h
  • V_IO_CAPT_LVL7 : CpuRegs.h
  • VR_CURRENT_DEFAULT : PowerMgmtDefinitions.h
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- c -

  • CheckSmxCapabilities() : TxtLibrary.h
  • ConvertToMailboxFormat() : OverclockingLibrary.h
  • ConvertVoltageOffset() : OverclockingLibrary.h
  • ConvertVoltageTarget() : OverclockingLibrary.h

- e -

  • EFI_FORWARD_DECLARATION() : PpmGlobalNvsArea.h
  • EfiCpuid() : CpuBaseLib.h
  • EfiCpuidExt() : CpuBaseLib.h
  • EfiCpuVersion() : CpuBaseLib.h
  • EfiDisableCache() : CpuBaseLib.h
  • EfiDisableInterrupts() : CpuBaseLib.h
  • EfiEnableCache() : CpuBaseLib.h
  • EfiEnableInterrupts() : CpuBaseLib.h
  • EfiGetEflags() : CpuBaseLib.h
  • EfiHalt() : CpuBaseLib.h
  • EfiInvd() : CpuBaseLib.h
  • EfiReadMsr() : CpuBaseLib.h
  • EfiReadTsc() : CpuBaseLib.h
  • EfiWbinvd() : CpuBaseLib.h
  • EfiWriteMsr() : CpuBaseLib.h

- g -

  • GetCpuFamily() : CpuPlatformLib.h
  • GetCpuSku() : CpuPlatformLib.h
  • GetCpuStepping() : CpuPlatformLib.h
  • GetFivrConfig() : OverclockingLibrary.h
  • GetOcCapabilities() : OverclockingLibrary.h
  • GetSvidConfig() : OverclockingLibrary.h
  • GetVoltageFrequencyItem() : OverclockingLibrary.h

- i -

  • IsBootGuardSupported() : BootGuardLibrary.h
  • IsCpuSupported() : CpuPlatformLib.h

- m -

  • MailboxRead() : CpuPlatformLib.h
  • MailboxWrite() : CpuPlatformLib.h

- p -

  • PollMailboxReady() : CpuPlatformLib.h

- r -

  • R8AsmThunk16Destroy() : ThunkLib.h
  • R8AsmThunk16FarCall86() : ThunkLib.h
  • R8AsmThunk16GetProperties() : ThunkLib.h
  • R8AsmThunk16Int86() : ThunkLib.h
  • R8AsmThunk16SetProperties() : ThunkLib.h

- s -

  • SetFivrConfig() : OverclockingLibrary.h
  • SetSvidConfig() : OverclockingLibrary.h
  • SetVoltageFrequencyItem() : OverclockingLibrary.h
  • StopPbeTimer() : BootGuardLibrary.h
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: File Members

  • File List
  • File Members
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • gEfiPowerMgmtInitDoneProtocolGuid : PowerMgmtInitDone.h
  • gPpmGlobalNvsAreaProtocolGuid : PpmGlobalNvsArea.h
  • gSmmPfatProtocolGuid : Pfat.h
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: File Members

  • File List
  • File Members
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • DXE_CPU_PLATFORM_POLICY_PROTOCOL : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • EFI_PI_MP_SERVICES_ENABLEDISABLEAP : PiMpService.h
  • EFI_PI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS : PiMpService.h
  • EFI_PI_MP_SERVICES_GET_PROCESSOR_INFO : PiMpService.h
  • EFI_PI_MP_SERVICES_PROTOCOL : PiMpService.h
  • EFI_PI_MP_SERVICES_STARTUP_ALL_APS : PiMpService.h
  • EFI_PI_MP_SERVICES_STARTUP_THIS_AP : PiMpService.h
  • EFI_PI_MP_SERVICES_SWITCH_BSP : PiMpService.h
  • EFI_PI_MP_SERVICES_WHOAMI : PiMpService.h
  • PFAT_ERASE : Pfat.h
  • PFAT_EXECUTE : Pfat.h
  • PFAT_WRITE : Pfat.h
  • PLATFORM_CPU_GET_CPU_INFO : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PLATFORM_CPU_GET_MAX_COUNT : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PLATFORM_CPU_RETRIEVE_MICROCODE : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PPM_CUSTOM_CTDP : CpuPmConfig.h
  • PPM_CUSTOM_CTDP_TABLE : CpuPmConfig.h
  • PPM_LOCK_ENABLES : CpuPmConfig.h
  • PPM_TURBO_SETTINGS : CpuPmConfig.h
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: File Members

  • File List
  • File Members
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • C_STATE_TIME_UNIT : CpuPmConfig.h
  • CPU_PLATFORM_CATEGORY : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • CPU_STEPPING : CpuRegs.h
  • CUSTOM_POWER_UNIT : CpuPmConfig.h
  • DEEP_C_STATE : CpuPmConfig.h
  • MAX_PKG_C_STATE : CpuPmConfig.h
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: File Members

  • File List
  • File Members
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • EnumCpuSteppingMax : CpuRegs.h
  • EnumCrwB0 : CpuRegs.h
  • EnumHswA0 : CpuRegs.h
  • EnumHswUltB0 : CpuRegs.h
  • PowerUnit125MilliWatts : CpuPmConfig.h
  • PowerUnitWatts : CpuPmConfig.h
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: File Members

  • File List
  • File Members
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • b
  • c
  • d
  • e
  • h
  • m
  • o
  • p
  • s
  • t
  • v

- a -

  • ALIGNMENT_IN_PAGES : PfatDefinitions.h

- b -

  • BIOS_OS_DATAREGION_VERSION : Txt.h
  • BIT63 : CommonIncludes.h

- c -

  • C6_LONG_LATENCY_ENABLE : PowerMgmtDefinitions.h
  • C7_LONG_LATENCY_ENABLE : PowerMgmtDefinitions.h
  • C7s_LONG_LATENCY_ENABLE : PowerMgmtDefinitions.h
  • CPU_CAUSE_NOT_DISABLED : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • CPU_RC_VERSION : CpuInfo.h

- d -

  • DISABLE_SENTER_VMX : TxtOneTouch.h
  • DT_POWER_LIMIT1_TIME_DEFAULT : PowerMgmtDefinitions.h
  • DXE_CPU_INFO_REVISION_1 : CpuInfo.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_1 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_2 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_3 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_4 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_5 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_6 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
  • DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_7 : Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h

- e -

  • EFI_PI_MP_SERVICES_PROTOCOL_GUID : PiMpService.h
  • EFI_POWER_MGMT_INIT_DONE_PROTOCOL_GUID : PowerMgmtInitDone.h
  • EFI_PPM_GLOBAL_NVS_AREA_PROTOCOL_GUID : PpmGlobalNvsArea.h
  • EFI_SMM_THUNK_PROTOCOL_GUID : SmmThunk.h
  • EfiMakeCpuVersion : CpuBaseLib.h
  • ENABLE_SENTER_ONLY : TxtOneTouch.h
  • ENABLE_SENTER_VMX : TxtOneTouch.h
  • ENABLE_SENTER_VMX_IN_SMX : TxtOneTouch.h
  • ENABLE_SENTER_VMX_OUTSIDE_SMX : TxtOneTouch.h
  • ENABLE_VMX : TxtOneTouch.h
  • ENABLE_VMX_OUTSIDE_SMX : TxtOneTouch.h
  • ENABLE_VMX_SMX_ONLY : TxtOneTouch.h
  • END_OF_CPU_LIST : PiMpService.h
  • ERR_BAD_DIRECTORY : PfatDefinitions.h
  • ERR_BAD_PPDT : PfatDefinitions.h
  • ERR_BAD_PUP : PfatDefinitions.h
  • ERR_BAD_PUPC : PfatDefinitions.h
  • ERR_BAD_SVN : PfatDefinitions.h
  • ERR_EXEC_LIMIT : PfatDefinitions.h
  • ERR_INTERNAL_ERROR : PfatDefinitions.h
  • ERR_INVALID_LINE : PfatDefinitions.h
  • ERR_LAUNCH_FAIL : PfatDefinitions.h
  • ERR_OK : PfatDefinitions.h
  • ERR_OVERFLOW : PfatDefinitions.h
  • ERR_RANGE_VIOLATION : PfatDefinitions.h
  • ERR_SCRIPT_SYNTAX : PfatDefinitions.h
  • ERR_SFAM_VIOLATION : PfatDefinitions.h
  • ERR_UNDEFINED_FLASH_OBJECT : PfatDefinitions.h
  • ERR_UNEXPECTED_OPCODE : PfatDefinitions.h
  • ERR_UNSUPPORTED_CPU : PfatDefinitions.h

- h -

  • HEAP_EXTDATA_TYPE_BIOS_SPEC_VER : Txt.h
  • HEAP_EXTDATA_TYPE_BIOSACM : Txt.h
  • HEAP_EXTDATA_TYPE_END : Txt.h

- m -

  • MAILBOX_READ_TIMEOUT : CpuPlatformLib.h
  • MAILBOX_WAIT_STALL : CpuPlatformLib.h
  • MAILBOX_WAIT_TIMEOUT : CpuPlatformLib.h
  • MAX_CUSTOM_CTDP_ENTRIES : CpuPmConfig.h
  • MAX_CUSTOM_RATIO_TABLE_ENTRIES : CpuPmConfig.h
  • MAX_PFAT_LOG_PAGE : PfatDefinitions.h
  • MB_POWER_LIMIT1_TIME_DEFAULT : PowerMgmtDefinitions.h
  • MmPciAddress : Txt.h

- o -

  • OC_LIB_WAIT_TIMEOUT : OverclockingLibrary.h

- p -

  • PEI_BIOS_ACM_FILE_GUID : Txt.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_1 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_2 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_3 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_4 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_5 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_6 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_7 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PEI_CPU_PLATFORM_POLICY_PPI_REVISION_8 : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • PFAT_COMMAND_BEGIN : PfatDefinitions.h
  • PFAT_COMMAND_EC_CMD_WR_IMM : PfatDefinitions.h
  • PFAT_COMMAND_EC_CMD_WR_INDEX : PfatDefinitions.h
  • PFAT_COMMAND_EC_DATA_RD : PfatDefinitions.h
  • PFAT_COMMAND_EC_DATA_WR_IMM : PfatDefinitions.h
  • PFAT_COMMAND_EC_DATA_WR_INDEX : PfatDefinitions.h
  • PFAT_COMMAND_EC_STS_RD : PfatDefinitions.h
  • PFAT_COMMAND_END : PfatDefinitions.h
  • PFAT_COMMAND_ERASE_BLK : PfatDefinitions.h
  • PFAT_COMMAND_NOP : PfatDefinitions.h
  • PFAT_COMMAND_READ_IMM : PfatDefinitions.h
  • PFAT_COMMAND_READ_INDEX : PfatDefinitions.h
  • PFAT_COMMAND_SET_BUFFER_INDEX : PfatDefinitions.h
  • PFAT_COMMAND_SET_FLASH_INDEX : PfatDefinitions.h
  • PFAT_COMMAND_WRITE_IMM : PfatDefinitions.h
  • PFAT_COMMAND_WRITE_INDEX : PfatDefinitions.h
  • PFAT_HOB_GUID : PfatDefinitions.h
  • PFAT_LOG_MEMORY_OFFSET : PfatDefinitions.h
  • PFAT_MEMORY_PAGES : PfatDefinitions.h
  • PFAT_MODULE_GUID : PfatDefinitions.h
  • POWER_MGMT_ACPI_TABLE_STORAGE_GUID : PowerMgmtAcpiTableStorage.h
  • PPM_C1 : PowerMgmtDefinitions.h
  • PPM_C10 : PowerMgmtDefinitions.h
  • PPM_C1E : PowerMgmtDefinitions.h
  • PPM_C3 : PowerMgmtDefinitions.h
  • PPM_C6 : PowerMgmtDefinitions.h
  • PPM_C7 : PowerMgmtDefinitions.h
  • PPM_C7S : PowerMgmtDefinitions.h
  • PPM_C8 : PowerMgmtDefinitions.h
  • PPM_C9 : PowerMgmtDefinitions.h
  • PPM_C_STATES : PowerMgmtDefinitions.h
  • PPM_CD : PowerMgmtDefinitions.h
  • PPM_CMP : PowerMgmtDefinitions.h
  • PPM_EEPST : PowerMgmtDefinitions.h
  • PPM_EIST : PowerMgmtDefinitions.h
  • PPM_GLOBAL_NVS_AREA_REVISION_1 : PpmGlobalNvsArea.h
  • PPM_MWAIT_EXT : PowerMgmtDefinitions.h
  • PPM_TIMED_MWAIT : PowerMgmtDefinitions.h
  • PPM_TM : PowerMgmtDefinitions.h
  • PPM_TSTATE_FINE_GRAINED : PowerMgmtDefinitions.h
  • PPM_TSTATES : PowerMgmtDefinitions.h
  • PPM_TURBO : PowerMgmtDefinitions.h
  • PROCESSOR_AS_BSP_BIT : PiMpService.h
  • PROCESSOR_ENABLED_BIT : PiMpService.h
  • PROCESSOR_HEALTH_STATUS_BIT : PiMpService.h
  • PUP_BUFFER_SIZE : PfatDefinitions.h
  • PUPC_MEMORY_OFFSET : PfatDefinitions.h

- s -

  • SMM_PFAT_PROTOCOL_GUID : Pfat.h
  • SMRAM_CPU_DATA_HEADER_GUID : SmramCpuDataHeader.h
  • SMRAM_CPU_DATA_VARIABLE_GUID : SmramCpuDataVariable.h
  • SW_SMI_S3_RESTORE_MSR : PowerMgmtDefinitions.h

- t -

  • TXT_LCP_PD_BASE : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • TXT_LCP_PD_SIZE : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • TXT_SUPPORT : CpuInfo.h
  • TXT_TGA_MEMORY_SIZE : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • TXT_TGR_MEMORY_SIZE : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h
  • TXT_TGTT_MEMORY_SIZE : Ppi/CpuPlatformPolicy/CpuPlatformPolicy.h

- v -

  • V_IO_CAPT_LVL2 : CpuRegs.h
  • V_IO_CAPT_LVL3 : CpuRegs.h
  • V_IO_CAPT_LVL4 : CpuRegs.h
  • V_IO_CAPT_LVL5 : CpuRegs.h
  • V_IO_CAPT_LVL6 : CpuRegs.h
  • V_IO_CAPT_LVL7 : CpuRegs.h
  • VR_CURRENT_DEFAULT : PowerMgmtDefinitions.h
Generated on Thu Jun 20 2013 01:47:39 for 2013 SharkBay Processor Reference Code API by doxygen 1.8.0


2013 SharkBay Processor Reference Code API: Graph Legend

Graph Legend

This page explains how to interpret the graphs that are generated by doxygen.

Consider the following example:

/*! Invisible class because of truncation */
class Invisible { };

/*! Truncated class, inheritance relation is hidden */
class Truncated : public Invisible { };

/* Class not documented with doxygen comments */
class Undocumented { };

/*! Class that is inherited using public inheritance */
class PublicBase : public Truncated { };

/*! A template class */
template<class T> class Templ { };

/*! Class that is inherited using protected inheritance */
class ProtectedBase { };

/*! Class that is inherited using private inheritance */
class PrivateBase { };

/*! Class that is used by the Inherited class */
class Used { };

/*! Super class that inherits a number of other classes */
class Inherited : public PublicBase,
                  protected ProtectedBase,
                  private PrivateBase,
                  public Undocumented,
                  public Templ<int>
{
  private:
    Used *m_usedClass;
};

This will result in the following graph:

The boxes in the above graph have the following meaning:

  • A filled gray box represents the struct or class for which the graph is generated.
  • A box with a black border denotes a documented struct or class.
  • A box with a grey border denotes an undocumented struct or class.
  • A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.

The arrows have the following meaning:

  • A dark blue arrow is used to visualize a public inheritance relation between two classes.
  • A dark green arrow is used for protected inheritance.
  • A dark red arrow is used for private inheritance.
  • A purple dashed arrow is used if a class is contained or used by another class. The arrow is labeled with the variable(s) through which the pointed class or struct is accessible.
  • A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labeled with the template parameters of the instance.


2013 SharkBay Processor Reference Code API: Main Page

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2013 SharkBay Processor Reference Code API: Related Pages

Related Pages
Here is a list of all related documentation pages:
  • Todo List
  • Deprecated List