American Megatrends, Inc.

Haswell

Copyright

Release Notes

© American Megatrends, Inc.


Release Notes - NDA Required

Component Information:
Component Title: Intel Haswell
Component Reference Name: Intel Haswell
Component Type: CPU
Release Date: 2015-06-12
Source Control Label: 4651_Haswell_21c-RC_190
Source Control Location: SS:Alaska;$/Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/

Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Intel Haswell CPU module, it includes Intel Haswell CPU reference code and list the features below
Support Haswell
Multi-processor initialize
MSR initialize
MTRR initialize
Cpu microcode update
Cpu power management funciton initialize
SMBIOS type4 type7 creation
This CPU module needs entire Intel RC package, only specific projects can use this

CPU Module Name: Intel Haswell
Filename | Description
HaswellPkg.cif | Haswell CPU module CIF file
Haswell.chm | Haswell CPU module CHM file
Intel Cpu RC PKG | Intel RC CPU module part
AMI Cpu PKG | AMI specific module part

ModulePart Name: HaswellPkg
ModulePart Description: Include Intel Haswell RC package into project.
Filename | Description
HaswellRcPkg.cif | Intel Haswell RC module part CIF file
HaswellRcPkg.sdl | Intel Haswell RC module part SDL file
CpuInitDxe | CpuInitDxe module part
CpuInitPei | CpuInitPei module part
CpuGuidLib | CpuGuidLib module part
CpuProtocolLib | CpuProtocolLib module part
CpuRcInclude | CpuRcInclude module part
CpuPpiLib | CpuPpiLib module part
CpuRcSec | CpuRcSec module part
CpuSmm | CpuSmm module part
ThunkLib | ThunkLib module part
CpuS3Peim | CpuS3Peim module part
Cpu Policy Pei | Cpu Policy Pei module part
Cpu Policy Dxe | Cpu Policy Dxe module part
ModulePart Name: AMI Cpu PKG
ModulePart Description: AMI specific CPU module part package.
Filename | Description
CPU.chm | CHM file
CPU.cif | AMI specific CPU module part CIF file
CPU Board | CpuInitDxe module part
CPU Core | CPU Core module part
SmmPiProtocols | SmmPiProtocols module part
CpuSpSMI | CpuSpSMI module part
SmmPiIncludes | SmmPiIncludes module part
ModulePart Name: CPU Board
ModulePart Description: AMI CPU board module for setup items and AMI specific CPU protocols
Filename | Description
CPUBSP.cif | CIF file
CPU.sdl | SDL file
CPU.mak | MAKE file
CPU.EQU | CPU Equates
CPU.sd | CPU setup Description
CPU.uni | CPU setup strings
CPUSetup.c | CPU setup initialization
CpuSmbios.sdl | SDL file
PlatformCpuLib.h | Platform specific header
PlatformCpuLib.c | Platform specific library functions
CpuPeiDebugger.c | PEI debugger source file
CpuRcPolicyWrap | AMI policy rule module part for Haswell RC
ModulePart Name: CPU Core
ModulePart Description: AMI CPU Core module for AMI specific CPU protocols
Filename | Description
CPU.h | Common Cpu header
CPUCspLib.h | CPU CSP library header
CpuCspLib.c | CPU CSP library code
CpuDxe.c | Cpu DXE initialization framework
CpuDxeFuncs.c | Cpu DXE initialization framework
CpuDxe.dxs | CPU DXE depenency
CpuDxe.h | Cpu DXE header
CpuPei.c | Cpu PEI initialization framework
CpuPeiFuncs.c | Cpu PEI initialization framework
CPUPEI.dxs | CPU PEI depenency
CpuPeiBeforeMem.c | Cpu PEI initialization framework
CpuSmbios.c | CPU SMBIOS creation functions
MBIOSMAC.MAC | Macro define
ResetVector.asm | SEC assembly file
Startup32.asm | SEC assembly file
CPU Hobs | CPU Hob header files
CpuPPIs | CPU PPI header files
CpuProtocols | CPU Protocol header files
MicrocodeUpdate | Microcode update funcitons
CpuTools | CPU tools
ModulePart Name: CpuSp SMI
ModulePart Description: Cpu specific SWSMI functions
Filename | Description
CpuSpSmi.cif | CIF file
CpuSpSmi.sdl | SDL file
CpuSpSmi.mak | MAKE file
CpuSpSmi.c | CpuSpSmi module C source file
CpuSpSmi.h | CpuSpSmi module header file
CpuSpSmi.DXS | CpuSpSmi module depenency
ModulePart Name: Cpu SMM Save Restore
ModulePart Description: Provide SMM enviorment Save and Restore funciton
Filename | Description
CpuSmmSaveRes.cif | CIF file
CpuSmmSaveRes.sdl | SDL file
CpuSmmSaveRes.mak | MAKE file
CpuSmmSaveRes.c | CpuSmmSaveRes module C source file
CpuSmmSaveRes.h | CpuSmmSaveRes module header file
CpuSmmSaveRes.DXS | CpuSmmSaveRes module depenency
AMI Build Tools:
Tools Label: 4.5.5_TOOLS_41, Dated: 2013-04-21
Visual eBios: RSS.5.73.0244, Dated: 2013-03-19
Compiler Tool(s): Microsoft’s Windows Driver Kit (WDK) Ver. 7600.16385.1
RC version used in this label:
Intel Haswell Processor Reference Code 1.9.0
New features added in this label:
None
General Bug Fixes:
None
EIP addressed in this label:
EIP207854
Release History:

Label 4651_Haswell_21c-RC_190
Intel Haswell Processor Reference Code 1.9.0
[TAG]EIP207854
[Category]Bug fix
[Severity]Important
[Symptom]Txt test fail with TCG2 module
[RootCause]Tokne TCG_SUPPORT was removed
[Solution]Add TCG2Support tokne
[Files]AmiTxtDxe.c, AmiTxtPei.c, CpuRcPolicyPei.c, CPU.sd, CpuDxe.c

Label 4651_Haswell_21b-RC_190
Intel Haswell Processor Reference Code 1.9.0
[TAG]EIP215675
[Category]New Feature
[Description]Smm Access Check feature support.

[TAG]EIP219394
[Category]Bug fix
[Severity]Minor
[Symptom]Static code analysis issues found in Aptio4 Intel Haswell module
[RootCause]Didn't update register content.
[Solution]Update register content.
[Files]CpuCspLib.c

Label 4651_Haswell_21a-RC_190
Intel Haswell Processor Reference Code 1.9.0
[TAG]None
[Category]Spec Update
[Severity]Normal
[Description]When Enhanced Intel SpeedStepR Technology (EIST) support is disabled, the BIOS does not disable Turbo too. Intel provide this workaround:BIOS must disable Turbo through MSR 0x1A0 when EIST is disabled. Detail refer to Document Number: 548907.

[TAG]EIPNone
[Category]Bug Fix
[Severity]Minor
[Symptom]PowerConv and TimeConv parameters in AmiInternalFactoryTdcTdp Hob is incorrect.
[RootCause]Read from wrong MSR.
[Solution]The data should read from MSR 0x606.

Label 4651_Haswell_21-RC_190
Intel Haswell Processor Reference Code 1.9.0
[TAG]194526
[Category]Spec Update
[Severity]Important
[Description]Shark Bay Processor Reference Code Production Version 1.9.0 update.

[TAG]None
[Category]Improvement
[Description]Add MPDTable_CREATED token for creating MPDT table.

[TAG]None
[Category]Improvement
[Description]Add new methods to setting MTRRS.

[TAG]None
[Category]Improvement
[Description]Add WbMemMap and UcMemMap vectors size to prevent accessing out of bound.

Label 4651_Haswell_20c-RC_180
Intel Haswell Processor Reference Code 1.8.0
[TAG]169079
[Category]Improvement
[Description]Security Enhancement for SMIHandler in Microcode update SWSMI

[TAG]173454
[Category]Improvement
[Description]Add TSEG address and size in CpuInfoHob

[TAG]None
[Category]Improvement
[Description]Add APIC version CpuInfoHob

Label 4651_Haswell_20b-RC_180
Intel Haswell Processor Reference Code 1.8.0
[TAG]167029
[Category]Improvement
[Description]1. keep the original attribute of "Setup" variable when use SetVariable().2. remove the runtime attribute of variables that no access requirement in runtime.

Label 4651_Haswell_20a-RC_180
Intel Haswell Processor Reference Code 1.8.0
[TAG]158900
[Category]Bug Fix
[Severity]Normal
[Symptom]Read or write the FIVR register may result in the BIOS Mailbox returning a completion error code 0x06.
[RootCause]Please reference Desktop erratum HSD28S and mobile erratum HSM30S in MB/DT 4th Generation Intel Core Processor Family spec Rev. 011 v1.
[Solution]BIOS will retry the read or write command.

Label 4651_Haswell_20-RC_180
Intel Haswell Processor Reference Code 1.8.0
[TAG]158776
[Category]Spec Update
[Severity]Important
[Description]Shark Bay Processor Reference Code Production Version 1.8.0 update.

Label 4651_Haswell_19a-RC_170
Intel Haswell Processor Reference Code 1.7.0
[TAG]None
[Category]Bug Fix
[Severity]Important
[Symptom]System assert at smicpudecode.c. It means this procedure can't find out SMI is invoked by which core.
[RootCause]Timer event is still triggered even if CPU disable IRQ (cli). After check, Cpu IRQ may be enabled (sti) by some EFI services. And it cause timer event is triggered, and Dell software SMI is signal.
[Solution]To avoid this situation, IRQ need to disable from south bridge side as well. After we mask all IRQ of 8259, then this issue can be solved.

[TAG]None
[Category]Bug Fix
[Severity]Important
[Symptom]Change active processor number will cause S3 return has fail rate.
[RootCause]Didn't get latest CPU data in SMRAM.
[Solution]If the active core number in the data we got is not the same with the actual active core number, then this data is not the latest data. Continue search.

[TAG]None
[Category]Spec Update
[Severity]Important
[Description]Intel Trusted Execution Technology ACM for Shark Bay Platforms Production Version 1.5.0 update.

[TAG]EIP145605
[Category]Improvement
[Description]Intel Workaround - custom TDP table implementation. Add a workaround for prevent Windows displays 2 different frequencies brand string within the My Computer -> Properties.

[TAG]None
[Category]Improvement
[Description]Show Txt information in setup->Advanced ->Intel Txt Information page.

Label 4651_Haswell_19-RC_170
Intel Haswell Processor Reference Code 1.7.0
[TAG]142525
[Category]Spec Update
[Severity]Important
[Description]Shark Bay Processor Reference Code Production Version 1.7.0 update.

Label 4651_Haswell_18b-RC_162
Intel Haswell Processor Reference Code 1.6.2
[TAG]137056
[Category]Bug Fix
[Severity]Normal
[Symptom]TXT failed to start.
[RootCause]The total size of microcode we include in our project is bigger than 0x10000, but the the code search region is fixed as 0x10000. Therefore sometimes it won't search MCU successfully and result this issue.
[Solution]Change the search region size dynamically.

[TAG]137873
[Category]Bug Fix
[Severity]Normal
[Symptom]CPU Security Configuration(MSR 4E0[0]) will be changed after S3 resume.
[RootCause]Didn't restore the Cpu MSR 4e0 while S3 resume.
[Solution]Restore the Cpu MSR 0x4E0 while S3 resume.

Label 4651_Haswell_18a-RC_162
Intel Haswell Processor Reference Code 1.6.2
[TAG]134339
[Category]Bug Fix
[Severity]Important
[Symptom][Sharkbay]Build error after update Haswell Cpu module.
[RootCause]If token TCG_SUPPORT is disabled, TpmSupport setup data will not define, then cause built error.
[Solution]Add token TCG_SUPPORT condition when use TpmSupport setup data.

Label 4651_Haswell_18-RC_162
Intel Haswell Processor Reference Code 1.6.2
[TAG]133810
[Category]Spec Update
[Description]Shark Bay Processor Reference Code Production Version 1.6.2 update.

Label 4651_Haswell_17a-RC_161
Intel Haswell Processor Reference Code 1.6.1
[TAG]128396
[Category]Bug Fix
[Severity]Important
[Symptom]Build error when GENERATE_CC_LISTING_FILE=1.
[RootCause]Didn't give a description block for SecPlatformInformation.OBJ in mak file.
[Solution]Add a description block for SecPlatformInformation.OBJ in mak file.

[TAG]EIP130190
[Category]Spec Update
[Severity]Important
[Description]Intel Trusted Execution Technology ACM for Shark Bay Platforms Production Version 1.4.0 update.

[TAG]EIP131295
[Category]Improvement
[Description]TXT will be disabled and grayed out in Setup when TPM Support is disabled.

[TAG]None
[Category]Improvement
[Description]Smbios CpuMaxSpeed value is from Cpu when token SMBIOS_TYPE_4_MAX_SPEED is zero.

Label 4651_Haswell_17-RC_161
Intel Haswell Processor Reference Code 1.6.1
[TAG]EIP129085
[Category]Spec Update
[Description]Shark Bay Processor Reference Code Production Version 1.6.1 update

Label 4651_Haswell_16a-RC_160
Intel Haswell Processor Reference Code 1.6.0
[TAG]EIP127191
[Category]Spec Update
[Severity]Important
[Description]Intel Trusted Execution Technology ACM for Shark Bay Platforms Production Version 1.3.0 update.

Label 4651_Haswell_16-RC_160
Intel Haswell Processor Reference Code 1.6.0
[TAG]EIP127191
[Category]Spec Update
[Description]Shark Bay Processor Reference Code Production Version 1.6.0 update

Label 4651_Haswell_15a-RC_150
Intel Haswell Processor Reference Code 1.5.0
[TAG]None
[Category]Improvement
[Description][ISCT]Change IASL compiler path.

[TAG]EIP123835
[Category]Spec Update
[Severity]Important
[Description]SBY Performance Tuning Guid rev. 1.1 update.

[TAG]None
[Category]Improvement
[Description]1. Change PLL defatul value to LCPLL2. Modify IA core ratio minimun value. Use "max non turbo ratio(MSR CEh)" instead of "power on turbo default value".3. Remove write MSR 620h due to RC have implemented (EIP123446).

[TAG]None
[Category]Improvement
[Description]1. Fix PLL setting is invalid once PEG/DMI ratio is 1:1.2. Modify IA core ratio minimun value. Use "max non turbo ratio(MSR CEh)" instead of "power on turbo default value".

Label 4651_Haswell_15-RC_150
Intel Haswell Processor Reference Code 1.5.0
[TAG]EIP123499
[Category]Spec Update
[Description]Shark Bay Processor Reference Code Production Version 1.5.0 update

[TAG]EIP123326
[Category]Improvement
[Description]Show "Processor family" and "FSB speed" on CPU Configuration in BIOS setup menu.

[TAG]None
[Category]Improvement
[Description]Display BIOS ACM version in the file name.

Label 4651_Haswell_14-RC_140
Intel Haswell Processor Reference Code 1.4.0
[TAG]EIP120156
[Category]Spec Update
[Description]Shark Bay Processor Reference Code Production Version 1.4.0 update

[TAG]None
[Category]Improvement
[Description]Modify CustomPowerUnit of Haswell RC if add XTU.

[TAG]None
[Category]Improvement
[Description]Keep ring ratio default value in ACPI table when one core ratio has changed.

[TAG]None
[Category]Improvement
[Description]Limit CPU boot performance at Non-Turbo speed when add XTU.

Label 4651_Haswell_13a-RC_130
Intel Haswell Processor Reference Code 1.3.0
[TAG]None
[Category]Improvement
[Description] Change TurboPowerLimitLock default value to enable.

[TAG]EIP119880
[Category]Improvement
[Description] Provide setup items which is related to PowerLimit3.

[TAG]None
[Category]Bug Fix
[Severity]Important
[Symptom]ACPI T state table is not reported.
[RootCause]T state function enable policy in Haswell RC is not correct.
[Solution]Correct the T state function policy.

[TAG]EIP118478
[Category]Bug Fix
[Severity]Normal
[Symptom]AES-NI setup item disappear after set ASN-NI to disable.
[RootCause]We determine AES support from the ASE support bit in CPUID function 1, but it will change with AES MSR.
[Solution]Determine AES support before CPU RC DXE initialize.

Label 4651_Haswell_13-RC_130
Intel Haswell Processor Reference Code 1.3.0
[TAG]EIP118119
[Category]Spec Update
[Description]Shark Bay Processor Reference Code Production Version 1.3.0 update

[TAG]EIP113584
[Category]Bug Fix
[Severity]Important
[Symptom]System hang at POST when install HDD on mini-pcie card.
[RootCause]The reference code didn't save EBDA offset and used size. When other device also use EBDA, the EBDA data structure will fault.
[Solution]Save the EBDA offset and used size in reference code. If we need to use EBDA, change the token "REQUEST_EBDA_SIZE" value to 0x2000.

[TAG]EIP115949
[Category]Spec Update
[Severity]Important
[Description]Intel Trusted Execution Technology ACM for Shark Bay Platforms Production Version 1.1.0 update.

[TAG]None
[Category]Improvement
[Description] Token RC_POLICY_POWER_UNIT create for Haswell RC CustomPowerUnit.

[TAG]None
[Category]Improvement
[Description]Keep the same variable size.

[TAG]EIP116207
[Category]Improvement
[Description]Change VrCurrentLimit from UINT8 to UINT16.

[TAG]None
[Category]Improvement
[Description]Change numeric step value to 1.

[TAG]EIP115822
[Category]Improvement
[Description]Add SMBIOS type7 information for L4 cache if CPU supported and create a token to control this.

[TAG]None
[Category]Improvement
[Description]Use OcSetupData for EIST and Turbo status when PerformanceTunning enable.

Label 4651_Haswell_12-RC_120
Intel Haswell Processor Reference Code 1.2.0
[TAG]EIP115944
[Category]Spec Update
[Description] Shark Bay Processor Reference Code Production Version 1.2.0 update

[TAG]EIP112238
[Category]Improvement
[Description] Refer Intel BIOS and provide setup items for Intel Haswell RC policy.

[TAG]EIP115036
[Category]Bug Fix
[Severity]Important
[Symptom]NULL pointer is used.
[RootCause] Use mCpuPmConfig.ThermalFuncEnables without initialize.
[Solution] Allocate memory for mCpuPmConfig.ThermalFuncEnables.

Label 4651_Haswell_12-RC_110
Intel Haswell Processor Reference Code 1.1.0
[TAG]EIP114918
[Category]Spec Update
[Description] Shark Bay Processor Reference Code Production Version 1.1.0 update

[TAG]EIP112631
[Category]Improvement
[Description] Add IsPowerCycle function.

[TAG]EIP112631
[Category]Improvement
[Description] Add:1. Support IA core and Ring voltage offset negative in OC mailbox.2. Add Filter PLL function, please change "HASWELL_PERFTUNE_CPU_FILTER_PLL_SUPPORT" token if need to use this function.Fixed:1. TDP Time Window is now programmed to 8 seconds by default.2. When cold reset, re-enabling FIVR faults and SVID control. 3. Assign max ring ratio in msr 0x620 with ring ratio max value support.

Label 4651_Haswell_11-RC_100
Intel Haswell Processor Reference Code 1.0.0
[TAG]EIP113554
[Category]Spec Update
[Description] Shark Bay Processor Reference Code Production Version 1.0.0 update

[TAG]None
[Category]Improvement
[Description] Set APs boot P state ratio equal to BSP boot ratio.

[TAG]EIP113016
[Category]Spec Update
[Severity]Improvement
[Description] Intel Trusted Execution Technology ACM for Shark Bay Platforms Production Version 1.0.0 update.

[TAG]None
[Category]Improvement
[Description] Create setup item for BootInLfm.

[TAG]None
[Category]Bug Fix
[Severity]Important
[Symptom]Change C state limit to C10, the system will hang.
[RootCause] BIOS doesn't limit the C state to CPU support.
[Solution] According to the CPU C state support, add C state limit to prevent system hanging and limit the setup item choice.

[TAG]EIP103130
[Category]Bug Fix
[Severity]Important
[Symptom]SHB MB: Passive Trip Point is not Active.
[RootCause] BIOS doesn't correct to disable "AutoThermalReporting" variable in the CPU DXE Platform Policy.
[Solution] Correct the "AutoThermalReporting" variable in ThermalFuncEnables in POWER_MGMT_CONFIG.

[TAG]EIP112381
[Category]Bug Fix
[Severity]Important
[Symptom]TBoot S3 resume fail.
[RootCause] MSR 0x2e7 is not restored.
[Solution] Save and restore MSR 0x2e7 for S3.

Label 4651_Haswell_11-RC_090
Intel Haswell Processor Reference Code 0.9.0
[TAG]EIP112061
[Category]Spec Update
[Description] Shark Bay Processor Reference Code Production Version 0.9.0 update

[TAG]None
[Category]Improvement
[Description] Change Iout Slope default value.

[TAG]EIP111199
[Category]Improvement
[Description] Provide variable data which contains number of P states support.

Label 4651_Haswell_10b-RC_081
Intel Haswell Processor Reference Code 0.8.1
[TAG]EIP108128
[Category]Bug Fix
[Severity]Important
[Symptom]"Max non-turbo ratio" can't show in BIOS setup when first boot after flashing BIOS.
[RootCause] Doesn't initialize max non-turbo ratio value when first boot after flashing BIOS.
[Solution] Add initialize code for max non-turbo ratio.

[TAG]None
[Category]Improvement
[Description] Remove mailbox item limit. Because mailbox item is not be effected by turbo mode support or not.

[TAG]EIP107712
[Category]Bug Fix
[Severity]Important
[Symptom]Change core ratio limit is not effective for oc cpu.
[RootCause] The IA core max ratio in mailbox is not same as active one core ratio limit in MSR 0x1AD
[Solution] Update the IA core max ratio in mailbox according to active one core ratio limit in XTU setting data.

Label 4651_Haswell_10a-RC_081
Intel Haswell Processor Reference Code 0.8.1
[TAG]EIP93180
[Category]Improvement
[Description] Do not create timer callback to clear direction flag, clear direction flag operation is in interrupt entry.

[TAG]None
[Category]Improvement
[Description] Check CPU before lock SMM_FEATURE_CONTROL MSR.

Label 4651_Haswell_10-RC_081
Intel Haswell Processor Reference Code 0.8.1
[TAG]EIP109705
[Category]Spec Update
[Description] Shark Bay Processor Reference Code Beta 0.8.1 update

Label 4651_Haswell_09b-RC_080
Intel Haswell Processor Reference Code 0.8.0
[TAG]EIP107763
[Category]Bug fix
[Symptom]UEFI SCT 2.3.1 Floating Point ABI Test fail
[RootCause]According to UEFI 2.3.1 errata C, Floating-point control word must be initialized to 0x037F
[Solution] Use 0x37f for Floating-point control word

[TAG]None
[Category]Spec Update
[Description] Update by XTU 4.X

[TAG]None
[Category]Improvement
[Description]Lock SMM_FEATURE_CONTROL MSR

[TAG]None
[Category]Improvement
[Description]Add ANC_DEBUG_FLAG flag usage

[TAG]EIP108905
[Category]Improvement
[Description]Need to remove use of GenFFS utility to generate FFS for PI 1.2

[TAG]EIP108401
[Category]Improvement
[Description]Create setup items for VrMiscIoutOffsetSign, VrMiscIoutOffset, VrMiscIoutSlope and LakeTiny

Label 4651_Haswell_09a-RC_080
Intel Haswell Processor Reference Code 0.8.0
[TAG]None
[Category]Bug fix
[Symptom]Ctdp setup item is not displayed in setup menu
[RootCause] The cTDPAvailable value is not initialzied
[Solution] Initial cTDPAvailable value

[TAG]None
[Category]Spec Update
[Description] Update by XTU 4.X

[TAG]EIP105980
[Category]Improvement
[Description]Setup items for Package C State Limit and Energy Performance

Label 4651_Haswell_09-RC_080
Intel Haswell Processor Reference Code 0.8.0
[TAG]EIP107010
[Category]Spec Update
[Description] Shark Bay Processor Reference Code Beta 0.8.0 update

[TAG]EIP105980
[Category]Improvement
[Description]Setup items for Package C State Limit and Energy Performance

Label 4651_Haswell_09-RC_080
Intel Haswell Processor Reference Code 0.8.0
[TAG]EIP107010
[Category]Spec Update
[Description] Shark Bay Processor Reference Code Beta 0.8.0 update

[TAG]EIP105980
[Category]Improvement
[Description]Setup items for Package C State Limit and Energy Performance

Label 4651_Haswell_08a-RC_072
Intel Haswell Processor Reference Code 0.7.2
[TAG]EIP105401
[Category]Bug fix
[Symptom]CpuSignature and FeatureFlags of MPS table are incorrect
[RootCause] Cpu Signature and FeatureFlags in CpuInfo are not initialized
[Solution] Initialize Cpu Signature and FeatureFlags in CpuInfo

[TAG]None
[Category]Improvement
[Description]Include AnchorCove libary

[TAG]None
[Category]Improvement
[Description]L4 Cache support improve

Label 4651_Haswell_08-RC_072
Intel Haswell Processor Reference Code 0.7.2
[TAG]EIP105140
[Category]Spec Update
[Description] Shark Bay Processor Reference Code Beta 0.7.2 update

[TAG]EIP105017
[Category]Improvement
[Description]Implement Setup Options for Debug Interface Enable/Lock

Label 4651_Haswell_07b-RC_071
Intel Haswell Processor Reference Code 0.7.1
[TAG]None
[Category]Bug fix
[Symptom]System crash in SEC
[RootCause]Cache as base address and size do not meet SDL token
[Solution] Caceh as RAM base address and size should depend on SDL token

Label 4651_Haswell_07a-RC_071
Intel Haswell Processor Reference Code 0.7.1
[TAG]None
[Category]Improvement
[Description] Setup items CTDP BIOS, C8, C9 and C10 created

Label 4651_Haswell_07-RC_071
Intel Haswell Processor Reference Code 0.7.1
[TAG]EIP103821
[Category]Spec Update
[Description] Shark Bay Processor Reference Code Beta 0.7.1 update

[TAG]None
[Category]Improvement
[Description] Use SBLib_ExtResetSystem when pRS->ResetSystem does not Global Reset type in project

Label 4651_Haswell_06b-RC_070
Intel Haswell Processor Reference Code 0.7.0
[TAG]EIP103009
[Category]Spec Update
[Description] Intel Trusted Execution Technology ACM for Shark Bay Platforms Beta 0.8.0 update

[TAG]None
[Category]Improvement
[Description] Change the procedure of configuring MTRR

Label 4651_Haswell_06a-RC_070
Intel Haswell Processor Reference Code 0.7.0
[TAG]None
[Category]Improvement
[Description] AMI CPU S3 PEI module is created

Label 4651_Haswell_06-RC_070
Intel Haswell Processor Reference Code 0.7.0
[TAG]EIP102255
[Category]Spec Update
[Description] Shark Bay Processor Reference Code Beta 0.7.0 update

[TAG]EIP101245
[Category]Spec Update
[Description] Intel Trusted Execution Technology ACM for Shark Bay Platforms Alpha 0.7.5 update

Label 4651_Haswell_05d-RC_061
Intel Haswell Processor Reference Code 0.6.1
[TAG]None
[Category]Improvement
[Description]Add DTS setup item

[TAG]EIP97350
[Category]Improvement
[Description]Add AUX index define in TPM NVRAM to avoid system keep reset when TXT enabled

[TAG]None
[Category]Bug fix
[Symptom]Disable TCG support causes BIOS building error
[RootCause]TCG setup data is used in TxtPei and the data is not exist when TCG disabled
[Solution]Do not use the TCG setup data when TCG disabled

Label 4651_Haswell_05c-RC_061
Intel Haswell Processor Reference Code 0.6.1
[TAG]None
[Category]Bug fix
[Symptom]EFI_SMM_CPU_PROTOCOL-> ReadSaveState can't get CR4 value
[RootCause]The index for CR4 is incorrect.
[Solution]Correct the index value

[TAG]None
[Category]Improvement
[Description]Install TPM_INITIALIZED_PPI when TPM device is present TPM enabled in setup

Label 4651_Haswell_05b-RC_061
Intel Haswell Processor Reference Code 0.6.1
[TAG]None
[Category]Bug fix
[Symptom]EFI_SMM_CPU_PROTOCOL-> ReadSaveState can't get CR4 value
[RootCause]The index for CR4 is incorrect.
[Solution]Correct the index value

[TAG]None
[Category]Improvement
[Description]Install TPM_INITIALIZED_PPI when TPM device is present TPM enabled in setup

Label 4651_Haswell_05a-RC_061
Intel Haswell Processor Reference Code 0.6.1
[TAG]EIP98214
[Category]Spec Update
[Description] Shark Bay Processor Reference Code Alpha 2 0.6.1 update

Label 4651_Haswell_05-RC_061
Intel Haswell Processor Reference Code 0.6.1
[TAG]EIP98214
[Category]Spec Update
[Description] Shark Bay Processor Reference Code Alpha 2 0.6.1 update

[TAG]EIP95485
[Category]Improvement
[Description]Configure TXT Feature via setup option

[TAG]EIP97190
[Category]Improvement
[Description]Changes in TXT Configuration require a Powercycle reset

Label 4651_Haswell_04a-RC_060
Intel Haswell Processor Reference Code 0.6.0
[TAG]EIP95549
[Category]Spec Update
[Description]Intel Trusted Execution Technology ACM for Shark Bay Platforms Alpha 0.7.0 update

[TAG]None
[Category]Improvement
[Description]Change VT default value to enable

[TAG]EIP93356
[Category]Improvement
[Description]Use same syntax for all common CPU question

[TAG]EIP95485
[Category]Improvement
[Description]Enable VT when TXT is enabled

[TAG]EIP93180
[Category]Bug fix
[Symptom]Use same syntax for all common CPU question
[RootCause]The save MTRRs action is too early, the saved value is differnet from the value in OS
[Solution]Move the MTRR save action to AMI_LEGACYBOOT event

Label 4651_Haswell_04-RC_060
Intel Haswell Processor Reference Code 0.6.0
[TAG]EIP94360
[Category]Spec Update
[Description]Shark Bay Processor Reference Code Alpha 2 0.6.0 update

Label 4651_Haswell_03d-RC_056
Intel Haswell Processor Reference Code 0.5.6
[TAG]EIP89941
[Category]Improvement
[Description]Add Intel TXT setup item

[TAG]None
[Category]New Feature
[Description]Support Intel Fit module

Label 4651_Haswell_03c-RC_056
Intel Haswell Processor Reference Code 0.5.6
[TAG]EIP91471
[Category]Improvement
[Description]Make MP Services PI compliant.

Label 4651_Haswell_03b-RC_056
Intel Haswell Processor Reference Code 0.5.6
[TAG]None
[Category]Improvement
[Description]Add TXT_SUPPORT_FLAG define

[TAG]None
[Category]Improvement
[Description]Setup page layout change

[TAG]EIP89591
[Category]Improvement
[Description]Make the CPU wakup buffer locatioin depends on token PMM_EBDA_LOMEM_SIZE

Label 4651_Haswell_03a-RC_056
Intel Haswell Processor Reference Code 0.5.6
[TAG]None
[Category]Improvement
[Description] EdkIIGlueBasePciLibPciExpress_LIB is used in PowerMgmtS3 and DTS module part

Label 4651_Haswell_03-RC_056
Intel Haswell Processor Reference Code 0.5.6
[TAG]EIP89950
[Category]Spec Update
[Severity]Important
[Description]Shark Bay Processor Reference Code Alpha 2 0.5.6 update

[TAG]EIP87731
[Category]Improvement
[Description]CpuDbgr.c, CpuDxeDbgr.h and MemoryOperationDbgr.c are crated for AmiRx/Dbgr support

[TAG]EIP89577
[Category]Improvement
[Description]Remove SMRR enable/disable in SMMEntry/Exit.

Label 4651_Haswell_02b-RC_055
Intel Haswell Processor Reference Code 0.5.5
[TAG]None
[Category]Improvement
[Description]TXT and DTS RC added

Label 4651_Haswell_02a-RC_055
Intel Haswell Processor Reference Code 0.5.5
[TAG]None
[Category]Improvement
[Description]Build PEI CpuPlatformLib for SA or other modules

Label 4651_Haswell_02a-RC_055
Intel Haswell Processor Reference Code 0.5.5
[TAG]None
[Category]Improvement
[Description]Build PEI CpuPlatformLib for SA or other modules

Label 4651_Haswell_02-RC_055
Intel Haswell Processor Reference Code 0.5.5
[TAG]EIP86915
[Category]Spec Update
[Severity]Important
[Description]Shark Bay Processor Reference Code Alpha 1 0.5.5 update

Label 4651_Haswell_01b-RC_050
Intel Haswell Processor Reference Code 0.5.0
[TAG]None
[Category]Improvement
[Description]Create setup items for Haswell CPU RC

[TAG]None
[Category]Improvement
[Description]SMBIOS type4 and type7 create

Label 4651_Haswell_01a-RC_050
Intel Haswell Processor Reference Code 0.5.0
[TAG]None
[Category]Improvement
[Description]Support Intel EDK

Label 4651_Haswell_01-RC_050
Intel Haswell Processor Reference Code 0.5.0
[TAG]None
Initial release. For platform power on.

© American Megatrends Inc.


Function by File Name

AMIBIOS Function Reference

By File Name

The following is a list of the source files.
For a list in alphabetical order, see In Alphabetical Order.
For a list by segment, see By Segment.

  • AmiCpuS3Pei.c
  • AmiCpuS3Pei.dxs
  • AmiCpuS3Pei.mak
  • AmiIa32Lib.mak
  • AmiTxtDxe.c
  • AmiTxtDxe.h
  • AmiTxtDxe.mak
  • AmiTxtInfo.h
  • AmiTxtInfoHook.c
  • AmiTxtInfoSetup.c
  • AmiTxtInfoSetup.sd
  • AmiTxtPei.c
  • AmiTxtPei.mak
  • AmiX64Lib.mak
  • CPU.EQU
  • CPU.h
  • CPU.mak
  • CPU.sd
  • CpuCspLib.c
  • CPUCspLib.h
  • CpuDxe.c
  • CpuDxe.dxs
  • CpuDxe.h
  • CpuDxeFuncs.c
  • CpuPei.c
  • CpuPei.dxs
  • CpuPei.h
  • CpuPeiBeforeMem.c
  • CpuPeiDebugger.c
  • CpuPeiFuncs.c
  • CpuRcPolicyDxe.c
  • CpuRcPolicyPei.c
  • CPUSetup.c
  • CpuSmbios.c
  • CpuSpSmi.c
  • CpuSpSmi.DXS
  • CpuSpSmi.h
  • CpuSpSmi.mak
  • CrcSecPpi.c
  • FoundationIa32.mak
  • FoundationIPF.mak
  • Foundationx64.mak
  • FwhFvb.c
  • IA32CLib.c
  • IA32rules.mak
  • MBIOSMAC.MAC
  • Microcode.mak
  • MicrocodeUpdate.c
  • MicrocodeUpdate.h
  • Misc.asm
  • MiscX64Lib.mak
  • PlatformCpuLib.c
  • PlatformCpuLib.h
  • ResetVector.asm
  • Startup32.asm
  • TxtSetup.c
  • TxtSinitAcm.mak
  • x64CLib.c
  • x64rules.mak
Built on 11:00:20 06/12/15


AmiCpuS3Pei.c

Description:

The following functions are used in the file: AmiCpuS3Pei.c.

Function | Description
AmiCpuS3PeiEntry | PEI Entry Point for Intel TXT Driver.

Built on 11:00:20 06/12/15


AmiCpuS3PeiEntry in the AmiCpuS3Pei.c

Function : AmiCpuS3PeiEntry

File: AmiCpuS3Pei.c
Description:
PEI Entry Point for Intel TXT Driver.
Input:
EFI_HANDLE          - ImageHandle
EFI_SYSTEM_TABLE*   - SystemTable
Output:
None.
Built on 11:00:18 06/12/15


AmiCpuS3Pei.dxs

Description:
Dependency expression for CPU PEI component.
Currently it is dependent on the CPU IO & PCI CFG PPI.
Built on 11:00:20 06/12/15


AmiCpuS3Pei.mak

Description:
Makefile for AmiCpuS3Pei module.
Built on 11:00:20 06/12/15


AmiIa32Lib.mak

Description:
Built on 11:00:20 06/12/15


AmiTxtDxe.c

Description:

The following functions are used in the file: AmiTxtDxe.c.

Function | Description
AmiTxtDxeEntry | DXE Entry Point for Intel TXT Driver.
EventUpdateSinitAcmToMemory | This routine copy SINIT ACM to SINIT meory for BIOS-Base SINI AC Module implementation.
GetTxtInfo | Get Txt information
InitAmiTxtInfo | Initialize Txt information
LtDefineTpmNvramSpace | This routine for define the TPM Nvram space.
LtSendTpmCommand | Sends a command to the TPM
TxtTpmNvRamDefine |

Built on 11:00:20 06/12/15


AmiTxtDxeEntry in the AmiTxtDxe.c

Function : AmiTxtDxeEntry

File: AmiTxtDxe.c
Description:
DXE Entry Point for Intel TXT Driver.
Input:
EFI_HANDLE          - ImageHandle
EFI_SYSTEM_TABLE*   - SystemTable
Output:
None.
Built on 11:00:18 06/12/15


EventUpdateSinitAcmToMemory in the AmiTxtDxe.c

Function : EventUpdateSinitAcmToMemory

File: AmiTxtDxe.c
Description:
This routine copy SINIT ACM to SINIT meory for BIOS-Base SINI
AC Module implementation.
Input:
IN EFI_EVENT   Event
IN VOID        *Context
Output:
None
Built on 11:00:19 06/12/15


GetTxtInfo in the AmiTxtDxe.c

Function : GetTxtInfo

File: AmiTxtDxe.c
Description:
Get Txt information
Input:
None
Output:
None.


InitAmiTxtInfo in the AmiTxtDxe.c

Function : InitAmiTxtInfo

File: AmiTxtDxe.c
Description:
Initialize Txt information
Input:
None
Output:
None.


LtDefineTpmNvramSpace in the AmiTxtDxe.c

Function : LtDefineTpmNvramSpace

File: AmiTxtDxe.c
Description:
This routine for define the TPM Nvram space.
Input:
None.
Output:
TURE    - Success.
FALSE   - Failed.


LtSendTpmCommand in the AmiTxtDxe.c

Function : LtSendTpmCommand

File: AmiTxtDxe.c
Description:
Sends a command to the TPM
Input:
*EFI_TCG_PROTOCOL   - Tcg Protocol type.
UINT32              - Tcg Command ordinal.
int                 - cmd datasize.
VOID*               - cmd data.
Output:
UINT32              - TPM_RESULT


TxtTpmNvRamDefine in the AmiTxtDxe.c

Function : TxtTpmNvRamDefine

File: AmiTxtDxe.c
Description:
Input:
None
Output:
None


AmiTxtDxe.h

Description:
AmiTxt Dxe header file.
Built on 11:00:20 06/12/15


AmiTxtDxe.mak

Description:
Makefile for TxtWrapper.
Built on 11:00:20 06/12/15


AmiTxtInfo.h

Description:
Built on 11:00:20 06/12/15


AmiTxtInfoHook.c

Description:
AmiTxtInfo Rountines

The following functions are used in the file: AmiTxtInfoHook.c.

Function | Description
AmiTxtHook | Initialize CPU strings.

Built on 11:00:20 06/12/15


AmiTxtHook in the AmiTxtInfoHook.c

Function : AmiTxtHook

File: AmiTxtInfoHook.c
Description:
Initialize CPU strings.
Input:
IN EFI_HII_HANDLE   HiiHandle
IN UINT16           Class
Output:
VOID
Built on 11:00:18 06/12/15


AmiTxtInfoSetup.c

Description:
CPU Setup Rountines

The following functions are used in the file: AmiTxtInfoSetup.c.

Function | Description
InitAmiTxtInfoStrings | Initialize CPU strings.

Built on 11:00:20 06/12/15


InitAmiTxtInfoStrings in the AmiTxtInfoSetup.c

Function : InitAmiTxtInfoStrings

File: AmiTxtInfoSetup.c
Description:
Initialize CPU strings.
Input:
IN EFI_HII_HANDLE   HiiHandle
IN UINT16           Class
Output:
VOID


AmiTxtInfoSetup.sd

Description:
Setup definition for Intel Txt Info.
Built on 11:00:20 06/12/15


AmiTxtPei.c

Description:

The following functions are used in the file: AmiTxtPei.c.

Function | Description
AmiTxtPeiEntry | PEI Entry Point for Intel TXT Driver.

Built on 11:00:20 06/12/15


AmiTxtPeiEntry in the AmiTxtPei.c

Function : AmiTxtPeiEntry

File: AmiTxtPei.c
Description:
PEI Entry Point for Intel TXT Driver.
Input:
EFI_HANDLE          - ImageHandle
EFI_SYSTEM_TABLE*   - SystemTable
Output:
None.
Built on 11:00:18 06/12/15


AmiTxtPei.mak

Description:
Makefile for AmiTxtPei module.
Built on 11:00:20 06/12/15


AmiX64Lib.mak

Description:
Built on 11:00:20 06/12/15


CPU.EQU

Description:
Equates used by the CPU module.
Built on 11:00:20 06/12/15


CPU.h

Description:
Common header for the CPU.
Built on 11:00:20 06/12/15


CPU.mak

Description:
Make file for the CPU component.
Built on 11:00:20 06/12/15


CPU.sd

Description:
Setup definition for CPU.
Built on 11:00:20 06/12/15


CpuCspLib.c

Description:
Contains the CPU library related functions. These functions can be linked
with various components in the project.

The following functions are used in the file: CpuCspLib.c.

Function | Description
CPU_GetSaveState | This routine is the generic routine used to copy the CPU specific SMM save state to standard save state.
CPU_GetSaveStateId30006 | This routines saves the necessary values from Revison 3006 SMM save state area.
CPU_IsSmrrSupported | Determine if CPU supports Smrr.
CPU_RestoreDefaultSaveState | This routines copies the necessary values from standard SMM save state area to version 0x30003 SMM save state area.
CPU_RestoreSaveState | This routine is the generic routine used to copy the standard SMM save state from CPU specific save state. This routine should make sure it does not change read only areas
CPU_RestoreSaveStateId30006 | This routines restores the necessary values from Revision 3006 SMM save state area.
CPULib_FindMicrocode | Find the microcode address for the CPU calling this.
CPULib_FindMicrocodeInFv | Find the microcode address for the CPU calling this in specific firmware volume.
CPULIB_GetCstateLatency | Get C-state latency.
CPULIB_GetCstatePower | Get C-state power.
CPULib_GetMicrocodeVer | Get Microcode Version
CPULib_IsFeatureControlLocked | Check to see if the MSR_IA32_FEATURE_CONTROL is locked.
CPULIB_IsLocalX2ApicEnabled | Get C-state latency.
CPULib_IsSmrrEnabled | Determine if Smrr is enabled.
CPULib_IsSmxEnabled | Determine if Smx is enabled.
CPULib_IsVmxEnabled | Determine if Vmx is enabled.
CpuLib_SaveCpuState | Save CPU state in SMM.
CPULib_SmmReadSaveState | Read SMM Save state from combination of SMM save state and copy. If frame copy exists, use its data instead from actual save state. A different function gets information for floating point and XMM.
CpuLib_SmmReadSaveStateFxSave | Read SMM Save state for floating point and XMM.
CpuLib_SmmRestoreCpuState | Restore CPU state in SMM.
CPULib_SmmWriteSaveState | Write SMM Save state from combination of SMM save state and copy. If frame copy exists, use its data instead from actual save state. A different function gets information for floating point and XMM.
CpuLib_SmmWriteSaveStateFxSave | Write SMM Save state for floating point and XMM.
CPUProgramPAMRegisters | Program 0xc0000 - 0xfffff regions to Lock/Unlock.
GetCpuFamily | Get the cpu family from signature.
GetCpuModel | Get the cpu model from signature.
GetCpuPlatformId | Get the cpu platform Id.
GetCpuSignature | Get the cpu signature.
GetFIVRConfig | Get the FIVR Configuration information by reading/writing MSR 0x150
GetOcCapability | Get the overclocking capabilities for a given CPU Domain by reading/writing MSR 0x150
GetSmrrBaseMsr | Return the Smrr Base Msr
GetSVIDConfig | Get the SVID Configuration information by reading/writing MSR 0x150
GetVoltFreq | Gets the Voltage and Frequency information for a given CPU domain by reading/writing MSR 0x150
isBCLKRatioSuuported | Determine if CPU supports BCLK coarse ratio support.
IsCore0 | Determine if CPU thread is CPU Core 0 executing.
IsCxInterruptFilteringSupported | Determine if C-state interrupting state supported.
IsEnergyPerfBiasSupported | Determine if Energy Performance Bias supported.
isFullUnlockCpuSuuported | Determine if CPU supports Full unlock.
IsHt0 | Determine if CPU thread is logical CPU 0 executing.
IsHtEnabled | Determine if CPU is HT.
isLimitCpuidSupported | Determine if CPU supports limiting CpuId to 3.
isMachineCheckSupported | Determine if CPU supports machine check.
IsPowerCycle | If Power Cycle is or not.
IsSmxSupported | Determine if CPU supports VT extensions Smx.
IsSwSmiTrigger | This routine checks to see if the cpu caused an software smi.
isTurboModeSupported | Determine if CPU supports Turbo mode.
IsVmxSupported | Determine if CPU supports VT extensions Vmx.
IsX64Supported | Determine if CPU supports X64.
isXDSupported | Determine if CPU supports Execute Disable.
isXECoreRatioLimitSupported | Determine if CPU supports Programmable Core Ratio Limit for the Turbo mode.
isXETdcTdpLimitSupported | Determine if CPU supports Programmable TDC/TDP Limit for the Turbo mode.
NumberOfCpuSocketsPopulated | Returns number of CPU sockets are populated.
NumCpuCores | Returns number of CPU Cores
NumLogicalCpus | Get number of logical CPUs.
NumSupportedCpuCores | Get number of supported Cpu Cores per package.
NumSupportedThreadsPerCore | Get number of supported threads per core.
PchPmTimerStall | Delay N*Usec
PollMailboxReady | Return OC Mailbox is ready or busy.
ReadMSR150 | Return Msr0x150 data
ReadWriteMsr | This function writes the CPU MSR with the value provided.
SmmBaseChangeCopy | This is SMM code copied to 3000:8000 to set the SmmBase and IED.
SmmBaseChangeOnCpu | Execute on each CPU to change its own base.
SmmGetBaseSaveBufferSize | Return about of memory required for the SMM handler change.
SmmRemoveDefaultHandler | Remove default SMM Handler from memory and restore original data.
SmmSetupDefaultHandler | Save original memory, and copy SMM default handler.

Built on 11:00:20 06/12/15


CPU_GetSaveState in the CpuCspLib.c

Function : CPU_GetSaveState

File: CpuCspLib.c
Description:
This routine is the generic routine used to copy the CPU specific SMM
save state to standard save state.
Input:
SmmBase         Pointer to CPU SMM save state.
SstSaveState    Pointer to copied SMM save state
Output:
VOID


CPU_GetSaveStateId30006 in the CpuCspLib.c

Function : CPU_GetSaveStateId30006

File: CpuCspLib.c
Description:
This routines saves the necessary values from Revison 3006
SMM save state area.
Input:
SmmBase         Pointer to CPU SMM save state.
SstSaveState    Pointer to copied SMM save state.
Output:
VOID


CPU_IsSmrrSupported in the CpuCspLib.c

Function : CPU_IsSmrrSupported

File: CpuCspLib.c
Description:
Determine if CPU supports Smrr.
Input:
CPU_FEATURES *Features
Output:
True if Smx supported.


CPU_RestoreDefaultSaveState in the CpuCspLib.c

Function : CPU_RestoreDefaultSaveState

File: CpuCspLib.c
Description:
This routines copies the necessary values from standard
SMM save state area to version 0x30003 SMM save state area.
Input:
SmmBase         Pointer to CPU SMM save state.
SstSaveState    Pointer to copied SMM save state.
Output:
VOID


CPU_RestoreSaveState in the CpuCspLib.c

Function : CPU_RestoreSaveState

File: CpuCspLib.c
Description:
This routine is the generic routine used to copy the standard
SMM save state from CPU specific save state. This routine
should make sure it does not change read only areas
Input:
SmmBase         Pointer to CPU SMM save state.
SstSaveState    Pointer to copied SMM save state
Output:
VOID


CPU_RestoreSaveStateId30006 in the CpuCspLib.c

Function : CPU_RestoreSaveStateId30006

File: CpuCspLib.c
Description:
This routines restores the necessary values from Revision 3006
SMM save state area.
Input:
SmmBase         Pointer to SMM save state
SstSaveState    Standard SMM save state
Output:
VOID


CPULib_FindMicrocode in the CpuCspLib.c

Function : CPULib_FindMicrocode

File: CpuCspLib.c
Description:
Find the microcode address for the CPU calling this.
Input:
VOID
Output:
VOID * -- 0 if not found or the Microcode Address.


CPULib_FindMicrocodeInFv in the CpuCspLib.c

Function : CPULib_FindMicrocodeInFv

File: CpuCspLib.c
Description:
Find the microcode address for the CPU calling this in specific firmware volume.
Input:
VOID *Fv -- Firmware Volume
Output:
VOID * -- 0 if not found or the Microcode Address.


CPULIB_GetCstateLatency in the CpuCspLib.c

Function : CPULIB_GetCstateLatency

File: CpuCspLib.c
Description:
Get C-state latency.
Input:
IN UINT8 Cstate
Output:
UINT32 - C-state latentcy in uS.


CPULIB_GetCstatePower in the CpuCspLib.c

Function : CPULIB_GetCstatePower

File: CpuCspLib.c
Description:
Get C-state power.
Input:
IN UINT8 Cstate
Output:
UINT32 - C-state power in mW.


CPULib_GetMicrocodeVer in the CpuCspLib.c

Function : CPULib_GetMicrocodeVer

File: CpuCspLib.c
Description:
Get Microcode Version
Input:
VOID
Output:
UINT32 - Microcode Version


CPULib_IsFeatureControlLocked in the CpuCspLib.c

Function : CPULib_IsFeatureControlLocked

File: CpuCspLib.c
Description:
Check to see if the MSR_IA32_FEATURE_CONTROL is locked.
Input:
VOID
Output:
BOOLEAN - True if MSR_IA32_FEATURE_CONTROL is locked.


CPULIB_IsLocalX2ApicEnabled in the CpuCspLib.c

Function : CPULIB_IsLocalX2ApicEnabled

File: CpuCspLib.c
Description:
Get C-state latency.
Input:
VOID
Output:
BOOLEAN - True if enabled


CPULib_IsSmrrEnabled in the CpuCspLib.c

Function : CPULib_IsSmrrEnabled

File: CpuCspLib.c
Description:
Determine if Smrr is enabled.
Input:
BOOLEAN
Output:
True if Smrr is enabled.


CPULib_IsSmxEnabled in the CpuCspLib.c

Function : CPULib_IsSmxEnabled

File: CpuCspLib.c
Description:
Determine if Smx is enabled.
Input:
VOID
Output:
True if Smx enabled.


CPULib_IsVmxEnabled in the CpuCspLib.c

Function : CPULib_IsVmxEnabled

File: CpuCspLib.c
Description:
Determine if Vmx is enabled.
Input:
VOID
Output:
True if Vmx enabled.


CpuLib_SaveCpuState in the CpuCspLib.c

Function : CpuLib_SaveCpuState

File: CpuCspLib.c
Description:
Save CPU state in SMM.
Input:
IN OUT CPU_LIB_SMM_SAVE_RESTORE_DATA *State - Track CPU state.
Output:
VOID


CPULib_SmmReadSaveState in the CpuCspLib.c

Function : CPULib_SmmReadSaveState

File: CpuCspLib.c
Description:
Read SMM Save state from combination of SMM save state and copy.
If frame copy exists, use its data instead from actual save state.
A different function gets information for floating point and XMM.
Input:
IN UINT8    *SmmBase         - SmmBase of CPU to read Save State.
IN UINT8    *SstSaveState    - SMM Save state copy for Framework.
IN BOOLEAN  UseSstSaveState  - True if Save state copy exists.
IN UINT8    Width            - Width in Bytes of register.
IN UINT32   Register         - Register Token in PI SMM.
OUT VOID    *Buffer          - Read register into this buffer.
Output:
EFI_STATUS


CpuLib_SmmReadSaveStateFxSave in the CpuCspLib.c

Function : CpuLib_SmmReadSaveStateFxSave

File: CpuCspLib.c
Description:
Read SMM Save state for floating point and XMM.
Input:
IN UINT8    *FxSave          - FxSave buffer.
IN UINT8    Width            - Width in Bytes of register.
IN UINT32   Register         - Register Token in PI SMM.
OUT VOID    *Buffer          - Read register into this buffer.
Output:
EFI_STATUS


CpuLib_SmmRestoreCpuState in the CpuCspLib.c

Function : CpuLib_SmmRestoreCpuState

File: CpuCspLib.c
Description:
Restore CPU state in SMM.
Input:
IN CPU_LIB_SMM_SAVE_RESTORE_DATA *State - Track CPU state.
Output:
VOID


CPULib_SmmWriteSaveState in the CpuCspLib.c

Function : CPULib_SmmWriteSaveState

File: CpuCspLib.c
Description:
Write SMM Save state from combination of SMM save state and copy.
If frame copy exists, use its data instead from actual save state.
A different function gets information for floating point and XMM.
Input:
IN UINT8    *SmmBase         - SmmBase of CPU to read Save State.
IN UINT8    *SstSaveState    - SMM Save state copy for Framework.
IN BOOLEAN  UseSstSaveState  - True if Save state copy exists.
IN UINT8    Width            - Width in Bytes of register.
IN UINT32   Register         - Register Token in PI SMM.
IN VOID    *Buffer           - Write register into this buffer.
Output:
EFI_STATUS


CpuLib_SmmWriteSaveStateFxSave in the CpuCspLib.c

Function : CpuLib_SmmWriteSaveStateFxSave

File: CpuCspLib.c
Description:
Write SMM Save state for floating point and XMM.
Input:
IN UINT8    *FxSave          - FxSave buffer.
IN UINT8    Width            - Width in Bytes of register.
IN UINT32   Register         - Register Token in PI SMM.
IN  VOID    *Buffer          - Write register into this buffer.
Output:
EFI_STATUS


CPUProgramPAMRegisters in the CpuCspLib.c

Function : CPUProgramPAMRegisters

File: CpuCspLib.c
Description:
Program 0xc0000 - 0xfffff regions to Lock/Unlock.
Input:
UINT32 StartAddress
UINT32 Length
UINT8  Setting
UINT32 *Granularity
Output:
EFI_STATUS


GetCpuFamily in the CpuCspLib.c

Function : GetCpuFamily

File: CpuCspLib.c
Description:
Get the cpu family from signature.
Input:
UINT32 CpuSignature
Output:
UINT32 - Cpu Family


GetCpuModel in the CpuCspLib.c

Function : GetCpuModel

File: CpuCspLib.c
Description:
Get the cpu model from signature.
Input:
UINT32 CpuSignature
Output:
UINT32 - Cpu Model


GetCpuPlatformId in the CpuCspLib.c

Function : GetCpuPlatformId

File: CpuCspLib.c
Description:
Get the cpu platform Id.
Input:
VOID
Output:
Cpu Platform Id


GetCpuSignature in the CpuCspLib.c

Function : GetCpuSignature

File: CpuCspLib.c
Description:
Get the cpu signature.
Input:
VOID
Output:
Cpu Signature


GetFIVRConfig in the CpuCspLib.c

Function : GetFIVRConfig

File: CpuCspLib.c
Description:
Get the FIVR Configuration information
by reading/writing MSR 0x150
Input:
UINT64  *MsrBuf
Output:
EFI_STATUS


GetOcCapability in the CpuCspLib.c

Function : GetOcCapability

File: CpuCspLib.c
Description:
Get the overclocking capabilities for a given CPU Domain
by reading/writing MSR 0x150
Input:
UINT8   DomainID (0:IA, 1:GT, 2:Ring, 3:SA, 4:IOD, 5:IOA)
UINT64  *MsrBuf
Output:
EFI_STATUS


GetSmrrBaseMsr in the CpuCspLib.c

Function : GetSmrrBaseMsr

File: CpuCspLib.c
Description:
Return the Smrr Base Msr
Input:
VOID
Output:
SMRR Base


GetSVIDConfig in the CpuCspLib.c

Function : GetSVIDConfig

File: CpuCspLib.c
Description:
Get the SVID Configuration information
by reading/writing MSR 0x150
Input:
UINT64  *MsrBuf
Output:
EFI_STATUS


GetVoltFreq in the CpuCspLib.c

Function : GetVoltFreq

File: CpuCspLib.c
Description:
Gets the Voltage and Frequency information for a given CPU domain
by reading/writing MSR 0x150
Input:
UINT8   DomainID (0:IA, 1:GT, 2:Ring)
UINT64  *MsrBuf
Output:
EFI_STATUS


isBCLKRatioSuuported in the CpuCspLib.c

Function : isBCLKRatioSuuported

File: CpuCspLib.c
Description:
Determine if CPU supports BCLK coarse ratio support.
Input:
None
Output:
True if supported.


IsCore0 in the CpuCspLib.c

Function : IsCore0

File: CpuCspLib.c
Description:
Determine if CPU thread is CPU Core 0 executing.
Input:
VOID
Output:
True if logical CPU 0.


IsCxInterruptFilteringSupported in the CpuCspLib.c

Function : IsCxInterruptFilteringSupported

File: CpuCspLib.c
Description:
Determine if C-state interrupting state supported.
Input:
VOID
Output:
BOOLEAN - True if C-state interrupting supported.


IsEnergyPerfBiasSupported in the CpuCspLib.c

Function : IsEnergyPerfBiasSupported

File: CpuCspLib.c
Description:
Determine if Energy Performance Bias supported.
Input:
VOID
Output:
BOOLEAN - True if Energy Performance Bias supported.


isFullUnlockCpuSuuported in the CpuCspLib.c

Function : isFullUnlockCpuSuuported

File: CpuCspLib.c
Description:
Determine if CPU supports Full unlock.
Input:
None
Output:
True if supported.


IsHt0 in the CpuCspLib.c

Function : IsHt0

File: CpuCspLib.c
Description:
Determine if CPU thread is logical CPU 0 executing.
Input:
VOID
Output:
True if logical CPU 0.


IsHtEnabled in the CpuCspLib.c

Function : IsHtEnabled

File: CpuCspLib.c
Description:
Determine if CPU is HT.
Input:
VOID
Output:
True if HT CPU.


isLimitCpuidSupported in the CpuCspLib.c

Function : isLimitCpuidSupported

File: CpuCspLib.c
Description:
Determine if CPU supports limiting CpuId to 3.
Input:
VOID
Output:
True if supported.


isMachineCheckSupported in the CpuCspLib.c

Function : isMachineCheckSupported

File: CpuCspLib.c
Description:
Determine if CPU supports machine check.
Input:
CPU_FEATURES *Features
Output:
True if supported.


IsPowerCycle in the CpuCspLib.c

Function : IsPowerCycle

File: CpuCspLib.c
Description:
If Power Cycle is or not.
Input:
NULL
Output:
UINT8   ,   0 - Not Power Cycle
   1 - Power Cycle


IsSmxSupported in the CpuCspLib.c

Function : IsSmxSupported

File: CpuCspLib.c
Description:
Determine if CPU supports VT extensions Smx.
Input:
CPU_FEATURES *Features
Output:
True if Smx supported.


IsSwSmiTrigger in the CpuCspLib.c

Function : IsSwSmiTrigger

File: CpuCspLib.c
Description:
This routine checks to see if the cpu caused an software smi.
Input:
UINT8 *SmmBase
UINT16 SwSmiPort
Output:
VOID


isTurboModeSupported in the CpuCspLib.c

Function : isTurboModeSupported

File: CpuCspLib.c
Description:
Determine if CPU supports Turbo mode.
Input:
None
Output:
True if supported.


IsVmxSupported in the CpuCspLib.c

Function : IsVmxSupported

File: CpuCspLib.c
Description:
Determine if CPU supports VT extensions Vmx.
Input:
CPU_FEATURES *Features
Output:
True if Vmx supported.


IsX64Supported in the CpuCspLib.c

Function : IsX64Supported

File: CpuCspLib.c
Description:
Determine if CPU supports X64.
Input:
CPU_FEATURES *Features
Output:
True if supported.


isXDSupported in the CpuCspLib.c

Function : isXDSupported

File: CpuCspLib.c
Description:
Determine if CPU supports Execute Disable.
Input:
CPU_FEATURES *Features
Output:
True if supported.


isXECoreRatioLimitSupported in the CpuCspLib.c

Function : isXECoreRatioLimitSupported

File: CpuCspLib.c
Description:
Determine if CPU supports Programmable Core Ratio Limit for the Turbo mode.
Input:
None
Output:
True if supported.


isXETdcTdpLimitSupported in the CpuCspLib.c

Function : isXETdcTdpLimitSupported

File: CpuCspLib.c
Description:
Determine if CPU supports Programmable TDC/TDP Limit for the Turbo mode.
Input:
None
Output:
True if supported.


NumberOfCpuSocketsPopulated in the CpuCspLib.c

Function : NumberOfCpuSocketsPopulated

File: CpuCspLib.c
Description:
Returns number of CPU sockets are populated.
Input:
VOID
Output:
UINT32 - Number of CPU sockets populated.


NumCpuCores in the CpuCspLib.c

Function : NumCpuCores

File: CpuCspLib.c
Description:
Returns number of CPU Cores
Input:
VOID
Output:
Number of CPU Cores.


NumLogicalCpus in the CpuCspLib.c

Function : NumLogicalCpus

File: CpuCspLib.c
Description:
Get number of logical CPUs.
Input:
VOID
Output:
UINT8 Number of logical CPUs.


NumSupportedCpuCores in the CpuCspLib.c

Function : NumSupportedCpuCores

File: CpuCspLib.c
Description:
Get number of supported Cpu Cores per package.
Input:
VOID
Output:
UINT8 Number of supported Cpu Cores per package.


NumSupportedThreadsPerCore in the CpuCspLib.c

Function : NumSupportedThreadsPerCore

File: CpuCspLib.c
Description:
Get number of supported threads per core.
Input:
VOID
Output:
UINT8 Number of Threads per core.


PchPmTimerStall in the CpuCspLib.c

Function : PchPmTimerStall

File: CpuCspLib.c
Description:
Delay N*Usec
Input:
UINTN Usec
Output:
VOID


PollMailboxReady in the CpuCspLib.c

Function : PollMailboxReady

File: CpuCspLib.c
Description:
Return OC Mailbox is ready or busy.
Input:
UINT64  *MsrBuf
Output:
UINT8 (1: busy, 0: ready)


ReadMSR150 in the CpuCspLib.c

Function : ReadMSR150

File: CpuCspLib.c
Description:
Return Msr0x150 data
Input:
UINT64  *MsrBuf
Output:
EFI_STATUS


ReadWriteMsr in the CpuCspLib.c

Function : ReadWriteMsr

File: CpuCspLib.c
Description:
This function writes the CPU MSR with the value provided.
Input:
Msr     32bit MSR index
Value   64bit OR Value
Mask    64Bit AND Mask Value
Output:
VOID


SmmBaseChangeCopy in the CpuCspLib.c

Function : SmmBaseChangeCopy

File: CpuCspLib.c
Description:
This is SMM code copied to 3000:8000 to set the SmmBase and IED.
Input:
None
Output:
None
Notes:
This is in real mode. To generate 16-bit code opcodes, use a small asm
file to generate a listing.


SmmBaseChangeOnCpu in the CpuCspLib.c

Function : SmmBaseChangeOnCpu

File: CpuCspLib.c
Description:
Execute on each CPU to change its own base.
Input:
VOID *SmmBase
Output:
VOID
Notes:


SmmGetBaseSaveBufferSize in the CpuCspLib.c

Function : SmmGetBaseSaveBufferSize

File: CpuCspLib.c
Description:
Return about of memory required for the SMM handler change.
Input:
VOID
Output:
UINT32 Amount of memory required for SMM handler change.
Notes:
The memory will need to be allocated to use in SmmSetupDefaultHandler.


SmmRemoveDefaultHandler in the CpuCspLib.c

Function : SmmRemoveDefaultHandler

File: CpuCspLib.c
Description:
Remove default SMM Handler from memory and restore original data.
Input:
IN VOID *SmmBaseSaveBuffer
Output:
VOID


SmmSetupDefaultHandler in the CpuCspLib.c

Function : SmmSetupDefaultHandler

File: CpuCspLib.c
Description:
Save original memory, and copy SMM default handler.
Input:
IN VOID     *SmmBaseSaveBuffer
IN SMM_HOB  *SmmHob
Output:
VOID
Notes:


CPUCspLib.h

Description:
Header file for Cpu Csp Lib.
Built on 11:00:20 06/12/15


CpuDxe.c

Description:
Installs CPU Architectural Protocol.
processor interrupt vector table. The CPU Architectural
Protocol enables/disables/get state of interrupts, set
memory range cache type, and installs/uninstalls
interrupt handlers.

The following functions are used in the file: CpuDxe.c.

Function | Description
AddLocalApicCoreEntries | Create Private Ami Cpu Info2 Acpi Data.
AmiCpuMpServiceCallback | Cpu Dxe Entrypoint.
CalculateTimerPeriod | Calculate CPU time period.
CpuSetBootRatio | Adjust CPU boot ratio base on setup item
CreateAcpiData | Create Private Ami Cpu Info2 Acpi Data.
CreateCacheData | Get Cache information.
CreatePrivateAmiCpuInfo1 | Create Private Ami Cpu Info1 structure.
CreatePrivateAmiCpuInfo2 | Create Private Ami Cpu Info2 structure.
DebuggerGetAptioInterruptHandlerHalt |
DebuggerIsItPEIDebugIRQHandlerToHookup |
DebuggerSetupPEIDebuggerExceptionHandlers |
DxeInitializeCpu | Cpu Dxe Entrypoint.
FillAcpiData | Fill ACPI Data structure
FillCacheDesc | Update cache information with CPUID 4.
FillPrivateAmiCpuInfo2 | Fill CPU information in Private Ami Cpu Info structure.
FindPtrToPrivCpuInfoCore | Pointer to internal Core information.
FindPtrToPrivCpuInfoPkg | Pointer to internal Package information.
FindPtrToPrivCpuInfoThread | Pointer to internal Core information.
GetAcpiInfo | Get Cpu ACPI information.
GetApicInfo | Get Apic Number and Version
GetBoardSocketNumber | Get socket number from Apic ID.
GetCacheSharedThreads | Return number of shared threads for a Information.
GetCoreCacheDescr | Get the Core Cache Information
GetCpuInfo | Protocol function to get Cpu Info.
GetCpuPkgCoreThrdByNum | Get CPU Package/Core/Thread by CPU Number. Number sequencial to APIC ID.
GetNumCoresThreads | Get the number of Cores
GetNumPackages | Get the number of packages populated and sockets.
GetNumThreads | Get the number of Threads
GetPackageCacheDescr | Get the package Cache Information
GetPtrToPrivateAmiCpuInfo2Entry | Get pointer to APIC/Cpu Num
GetSbsp | Get SBSP
GlobalDataInitialize | Cpu Dxe Entrypoint.
InterruptHandlerHalt | Default CPU Exception. Halts CPU.
PrepareToBoot | Handler executed before OS.
SizeOfPrivateAmiCpuInfo2 | Size of Private Ami Cpu Info 2 structure to be allocated.

Built on 11:00:20 06/12/15


AddLocalApicCoreEntries in the CpuDxe.c

Function : AddLocalApicCoreEntries

File: CpuDxe.c
Description:
Create Private Ami Cpu Info2 Acpi Data.
Input:
IN UINT32 Package - Processor package
IN UINT32 Thread - Processor thread (usually either 0 or 1 for HT)
Output:
BOOLEAN - TRUE if any entries added.
Built on 11:00:18 06/12/15


AmiCpuMpServiceCallback in the CpuDxe.c

Function : AmiCpuMpServiceCallback

File: CpuDxe.c
Description:
Cpu Dxe Entrypoint.
Input:
IN EFI_EVENT       Event    --
IN VOID *          Context  --
Output:
EFI_STATUS
Built on 11:00:18 06/12/15


CalculateTimerPeriod in the CpuDxe.c

Function : CalculateTimerPeriod

File: CpuDxe.c
Description:
Calculate CPU time period.
Input:
VOID
Output:
UINT64 Timer Period
Built on 11:00:18 06/12/15


CpuSetBootRatio in the CpuDxe.c

Function : CpuSetBootRatio

File: CpuDxe.c
Description:
Adjust CPU boot ratio base on setup item
Input:
None
Output:
None


CreateAcpiData in the CpuDxe.c

Function : CreateAcpiData

File: CpuDxe.c
Description:
Create Private Ami Cpu Info2 Acpi Data.
Input:
VOID
Output:
VOID


CreateCacheData in the CpuDxe.c

Function : CreateCacheData

File: CpuDxe.c
Description:
Get Cache information.
Input:
VOID
Output:
VOID


CreatePrivateAmiCpuInfo1 in the CpuDxe.c

Function : CreatePrivateAmiCpuInfo1

File: CpuDxe.c
Description:
Create Private Ami Cpu Info1 structure.
Input:
VOID
Output:
VOID


CreatePrivateAmiCpuInfo2 in the CpuDxe.c

Function : CreatePrivateAmiCpuInfo2

File: CpuDxe.c
Description:
Create Private Ami Cpu Info2 structure.
Input:
VOID
Output:
VOID


DebuggerGetAptioInterruptHandlerHalt in the CpuDxe.c

Function : DebuggerGetAptioInterruptHandlerHalt

File: CpuDxe.c
Description:
Input:

Output:

VOID


DebuggerIsItPEIDebugIRQHandlerToHookup in the CpuDxe.c

Function : DebuggerIsItPEIDebugIRQHandlerToHookup

File: CpuDxe.c
Description:
Input:

Output:

VOID


DebuggerSetupPEIDebuggerExceptionHandlers in the CpuDxe.c

Function : DebuggerSetupPEIDebuggerExceptionHandlers

File: CpuDxe.c
Description:
Input:

Output:


DxeInitializeCpu in the CpuDxe.c

Function : DxeInitializeCpu

File: CpuDxe.c
Description:
Cpu Dxe Entrypoint.
Input:
IN EFI_HANDLE       ImageHandle   -- Handle assigned to this driver.
IN EFI_SYSTEM_TABLE *SystemTable  -- Efi System table.
Output:
EFI_STATUS


FillAcpiData in the CpuDxe.c

Function : FillAcpiData

File: CpuDxe.c
Description:
Fill ACPI Data structure
Input:
IN ACPI_PROCESSOR_INFO *AcpiProcData
IN UINT32 Package
IN UINT32 Core
IN UINT32 Thread
IN BOOLEAN Bsp
Output:
BOOLEAN -- If filled, return TRUE.


FillCacheDesc in the CpuDxe.c

Function : FillCacheDesc

File: CpuDxe.c
Description:
Update cache information with CPUID 4.
Input:
CACHE_DESCRIPTOR_INFO * CacheInfo - Array to be filled of cache info structures.
Output:
VOID


FillPrivateAmiCpuInfo2 in the CpuDxe.c

Function : FillPrivateAmiCpuInfo2

File: CpuDxe.c
Description:
Fill CPU information in Private Ami Cpu Info structure.
Input:
VOID
Output:
VOID


FindPtrToPrivCpuInfoCore in the CpuDxe.c

Function : FindPtrToPrivCpuInfoCore

File: CpuDxe.c
Description:
Pointer to internal Core information.
Input:
IN UINT32* PkgPtr -- Internal package information.
IN UINT32  Core
Output:
UINT32 * -- Internal Core information.


FindPtrToPrivCpuInfoPkg in the CpuDxe.c

Function : FindPtrToPrivCpuInfoPkg

File: CpuDxe.c
Description:
Pointer to internal Package information.
Input:
IN UINT32  PkgPtr -- Internal package information.
Output:
UINT32 * -- Internal Core information.


FindPtrToPrivCpuInfoThread in the CpuDxe.c

Function : FindPtrToPrivCpuInfoThread

File: CpuDxe.c
Description:
Pointer to internal Core information.
Input:
IN UINT32* CorePtr -- Internal core information.
IN UINT32  Thread
Output:
UINT32 * -- Internal thread information.


GetAcpiInfo in the CpuDxe.c

Function : GetAcpiInfo

File: CpuDxe.c
Description:
Get Cpu ACPI information.
Input:
IN AMI_CPU_INFO_2_PROTOCOL  *This
OUT VOID                    **AcpiData  - ACPI Data
OUT UINT32                  *NumEntries - Number of Entries in data.
Output:
EFI_STATUS


GetApicInfo in the CpuDxe.c

Function : GetApicInfo

File: CpuDxe.c
Description:
Get Apic Number and Version
Input:
IN AMI_CPU_INFO_2_PROTOCOL  *This
IN UINT32                   Package
IN UINT32                   Core
IN UINT32                   Thread
OUT UINT32                  *ApicId
OUT UINT32                  *ApicVer OPTIONAL
Output:
EFI_STATUS


GetBoardSocketNumber in the CpuDxe.c

Function : GetBoardSocketNumber

File: CpuDxe.c
Description:
Get socket number from Apic ID.
Input:
IN UINT32 ApicId
Output:
UINT32 - Physical Socket Id


GetCacheSharedThreads in the CpuDxe.c

Function : GetCacheSharedThreads

File: CpuDxe.c
Description:
Return number of shared threads for a Information.
Input:
IN UINT8 Level - Cache level
Output:
UINT8 - Number of shared threads.


GetCoreCacheDescr in the CpuDxe.c

Function : GetCoreCacheDescr

File: CpuDxe.c
Description:
Get the Core Cache Information
Input:
IN AMI_CPU_INFO_2_PROTOCOL      *This
IN UINT32                       Package - Socket number. Internal socket number (continous)
IN UINT32                       Core - Core number. Internal core number (continous)
OUT AMI_CPU_INFO_2_CACHE_DESCR  **Description - Updates pointer to pointer with pointer to Cache information.
OUT UINT32                      *NumEntries - Number of AMI_CPU_INFO_2_CACHE_DESCR Entries.
Output:
EFI_STATUS


GetCpuInfo in the CpuDxe.c

Function : GetCpuInfo

File: CpuDxe.c
Description:
Protocol function to get Cpu Info.
Input:
IN AMI_CPU_INFO_PROTOCOL    *This
IN UINTN                    Cpu
OUT AMI_CPU_INFO            **Info
Output:
EFI_STATUS


GetCpuPkgCoreThrdByNum in the CpuDxe.c

Function : GetCpuPkgCoreThrdByNum

File: CpuDxe.c
Description:
Get CPU Package/Core/Thread by CPU Number. Number sequencial to APIC ID.
Input:
IN UINT32 CpuNum
OUT UINT32 *Package
OUT UINT32 *Core
OUT UINT32 *Thread
Output:
BOOLEAN -- If found, return TRUE.


GetNumCoresThreads in the CpuDxe.c

Function : GetNumCoresThreads

File: CpuDxe.c
Description:
Get the number of Cores
Input:
IN AMI_CPU_INFO_2_PROTOCOL  *This,
IN UINT32                   Package
OUT UINT32                  *NumEnabledCores
OUT UINT32                  *NumEnabledThreads - This value is total for package.
OUT UINT32                  *NumDisabledCores OPTIONAL -- Flag must be set in Protocol.
OUT UINT32                  *NumEnabledThreads OPTIONAL  -- Flag must be set in Protocol.
Output:
EFI_STATUS


GetNumPackages in the CpuDxe.c

Function : GetNumPackages

File: CpuDxe.c
Description:
Get the number of packages populated and sockets.
Input:
IN AMI_CPU_INFO_2_PROTOCOL  *This
OUT UINT32                  *NumPopulatedPackages
OUT UINT32                  *NumBoardSockets OPTIONAL
Output:
EFI_STATUS


GetNumThreads in the CpuDxe.c

Function : GetNumThreads

File: CpuDxe.c
Description:
Get the number of Threads
Input:
IN AMI_CPU_INFO_2_PROTOCOL  *This
IN UINT32                   Package
IN UINT32                   Core
OUT UINT32                  *NumEnabledThreads
OUT UINT32                  *NumDisabledThreads OPTIONAL  -- Flag must be set if valid
Output:
EFI_STATUS


GetPackageCacheDescr in the CpuDxe.c

Function : GetPackageCacheDescr

File: CpuDxe.c
Description:
Get the package Cache Information
Input:
IN AMI_CPU_INFO_2_PROTOCOL      *This
IN UINT32                       Package - Socket number. Intenal socket number (continous)
OUT AMI_CPU_INFO_2_CACHE_DESCR  **Description - Updates pointer to pointer with pointer to Cache information.
OUT UINT32                      *NumEntries - Number of AMI_CPU_INFO_2_CACHE_DESCR Entries.
Output:
EFI_STATUS


GetPtrToPrivateAmiCpuInfo2Entry in the CpuDxe.c

Function : GetPtrToPrivateAmiCpuInfo2Entry

File: CpuDxe.c
Description:
Get pointer to APIC/Cpu Num
Input:
IN UINT32 Package
IN UINT32 Core
IN UINT32 Thread
Output:
UINT32 *


GetSbsp in the CpuDxe.c

Function : GetSbsp

File: CpuDxe.c
Description:
Get SBSP
Input:
IN AMI_CPU_INFO_2_PROTOCOL  *This
OUT UINT32                  *Package
OUT UINT32                  *Core
OUT UINT32                  *Thread
Output:
EFI_STATUS


GlobalDataInitialize in the CpuDxe.c

Function : GlobalDataInitialize

File: CpuDxe.c
Description:
Cpu Dxe Entrypoint.
Input:
IN EFI_HANDLE       ImageHandle   -- Handle assigned to this driver.
IN EFI_SYSTEM_TABLE *SystemTable  -- Efi System table.
Output:
EFI_STATUS


InterruptHandlerHalt in the CpuDxe.c

Function : InterruptHandlerHalt

File: CpuDxe.c
Description:
Default CPU Exception. Halts CPU.
Input:
IN EFI_EXCEPTION_TYPE   Exception
IN EFI_SYSTEM_CONTEXT   Context
Output:
VOID


PrepareToBoot in the CpuDxe.c

Function : PrepareToBoot

File: CpuDxe.c
Description:
Handler executed before OS.
Input:
IN EFI_EVENT    Event
IN VOID         *Context
Output:
VOID


SizeOfPrivateAmiCpuInfo2 in the CpuDxe.c

Function : SizeOfPrivateAmiCpuInfo2

File: CpuDxe.c
Description:
Size of Private Ami Cpu Info 2 structure to be allocated.
Input:
VOID
Output:
UINT32 -- Size


CpuDxe.dxs

Description:
Dependency expression for Cpu Dxe.
Built on 11:00:20 06/12/15


CpuDxe.h

Description:
Cpu Dxe header file.
Built on 11:00:20 06/12/15


CpuDxeFuncs.c

Description:
Installs CPU Architectural Protocol.
processor interrupt vector table. The CPU Architectural
Protocol enables/disables/get state of interrupts, set
memory range cache type, and installs/uninstalls
interrupt handlers.

The following functions are used in the file: CpuDxeFuncs.c.

Function | Description
CpuDxeMiscFuncs |
CpuPllOverVoltageProgress | CPU pll over voltage initialize code in DXE phase
FillXtuGaciData | Fill CPU information for xtu 3.0 specification
IntelXtuFillCpuDataCallBack | Callback function for Intel XTU data init
NumberOfPStatesSupport | Provide variable data which constains number of P states support
SaveMEFWVersion | CPU pll over voltage initialize code in DXE phase

Built on 11:00:20 06/12/15


CpuDxeMiscFuncs in the CpuDxeFuncs.c

Function : CpuDxeMiscFuncs

File: CpuDxeFuncs.c
Description:
Input:
None
Output:
None


CpuPllOverVoltageProgress in the CpuDxeFuncs.c

Function : CpuPllOverVoltageProgress

File: CpuDxeFuncs.c
Description:
CPU pll over voltage initialize code in DXE phase
Input:
IN EFI_EVENT Event
IN VOID *Context
Output:
EFI_STATUS


FillXtuGaciData in the CpuDxeFuncs.c

Function : FillXtuGaciData

File: CpuDxeFuncs.c
Description:
Fill CPU information for xtu 3.0 specification
Input:
VOID
Output:
VOID


IntelXtuFillCpuDataCallBack in the CpuDxeFuncs.c

Function : IntelXtuFillCpuDataCallBack

File: CpuDxeFuncs.c
Description:
Callback function for Intel XTU data init
Input:
IN EFI_EVENT Event
IN VOID *Context
Output:
EFI_STATUS


NumberOfPStatesSupport in the CpuDxeFuncs.c

Function : NumberOfPStatesSupport

File: CpuDxeFuncs.c
Description:
Provide variable data which constains number of P states support
Input:
VOID
Output:
VOID


SaveMEFWVersion in the CpuDxeFuncs.c

Function : SaveMEFWVersion

File: CpuDxeFuncs.c
Description:
CPU pll over voltage initialize code in DXE phase
Input:
IN EFI_EVENT Event
IN VOID *Context
Output:
EFI_STATUS


CpuPei.c

Description:
This file is the main CPU PEI component file. This component utilizes
CPU I/O & PCI CFG PPI to publish early CPU Init PPI which can be used
by NB PEI to load itself.  Also this file contains a CPU init routine
to be executed in permanent memory present environment. This is handled
by issuing a notifyPPI on permanent memory PPI.

The following functions are used in the file: CpuPei.c.

Function | Description
CpuPeiEntry | AMI CPU PEI driver entry
CreateCpuHobWithDefaults | Create CPU Hob and fill in default data.
NotifyAtPeiEnd | According to resource descriptor HOBs to config system cache.
ReportBistStatusCodes | Report the BIST Status Code.
SetupCache | According to resource descriptor HOBs to config system cache.
UpdateOrCreateCpuHob | Finds or Create Cpu Hob and initialize it.

Built on 11:00:20 06/12/15


CpuPeiEntry in the CpuPei.c

Function : CpuPeiEntry

File: CpuPei.c
Description:
AMI CPU PEI driver entry
Input:
IN EFI_FFS_FILE_HEADER      *FfsHeader
IN EFI_PEI_SERVICES         **PeiServices
Output:
EFI_STATUS


CreateCpuHobWithDefaults in the CpuPei.c

Function : CreateCpuHobWithDefaults

File: CpuPei.c
Description:
Create CPU Hob and fill in default data.
Input:
IN EFI_PEI_SERVICES **PeiServices
IN UINT8            NumCpus
Output:
CPUINFO_HOB *


NotifyAtPeiEnd in the CpuPei.c

Function : NotifyAtPeiEnd

File: CpuPei.c
Description:
According to resource descriptor HOBs to config system cache.
Input:
IN EFI_PEI_SERVICES **PeiServices
IN EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor
IN VOID                         *Ppi
Output:
EFI_STATUS


ReportBistStatusCodes in the CpuPei.c

Function : ReportBistStatusCodes

File: CpuPei.c
Description:
Report the BIST Status Code.
Input:
VOID
Output:
VOID


SetupCache in the CpuPei.c

Function : SetupCache

File: CpuPei.c
Description:
According to resource descriptor HOBs to config system cache.
Input:
IN EFI_PEI_SERVICES **PeiServices
IN EFI_BOOT_MODE BootMode
Output:
VOID


UpdateOrCreateCpuHob in the CpuPei.c

Function : UpdateOrCreateCpuHob

File: CpuPei.c
Description:
Finds or Create Cpu Hob and initialize it.
Input:
IN EFI_PEI_SERVICES **PeiServices
Output:
VOID
Built on 11:00:20 06/12/15


CpuPei.dxs

Description:
Dependency expression for CPU PEI component.
Currently it is dependent on the CPU IO & PCI CFG PPI.
Built on 11:00:20 06/12/15


CpuPei.h

Description:
Cpu PEI header file.
Built on 11:00:20 06/12/15


CpuPeiBeforeMem.c

Description:
This file is the main contains Cpu code that must execute
before memory.

The following functions are used in the file: CpuPeiBeforeMem.c.

Function | Description
CollectOcConfig | Collect Overclocking Config data from MSR 0x150.
CpuPeiBeforeMemEntry | CPU PEI functions before memory ready
CpuPeiPolicyNotify | CPU PEI pollicy PPI notify function
CpuPeiPolicyOverWrite | This function over writes the CPU PEI RC policy
CpuPeiXtuInitBeforeMem | CPU XTU init code in PEI phase
EnablePLLOverVoltage | Enable PLL over voltage for CPU
InitOcMailbox | Initialize Overclocking Config data.
OverlockingConfigUpdate | Update Overclocking Config data.
OverrideNonTurboRatio | Override CPU NonTurbo Ratio Maximum value
PEGDMIRatio | Modify PEG/DMI Ratio for CPU
PLLFilterFunction | Filter PLL setting High(3.2GHz) or lower(1.6GHz)
ReinstallSecPpis | Reinstall PPIs from stack because stack will be lost when cache-as-ram is turned off.

Built on 11:00:20 06/12/15


CollectOcConfig in the CpuPeiBeforeMem.c

Function : CollectOcConfig

File: CpuPeiBeforeMem.c
Description:
Collect Overclocking Config data from MSR 0x150.
Input:
EFI_PEI_SERVICES            **PeiServices
OVERCLOCKING_CONFIG_HOB     *OverclockConfig
Output:
VOID
Built on 11:00:18 06/12/15


CpuPeiBeforeMemEntry in the CpuPeiBeforeMem.c

Function : CpuPeiBeforeMemEntry

File: CpuPeiBeforeMem.c
Description:
CPU PEI functions before memory ready
Input:
IN EFI_FFS_FILE_HEADER		*FfsHeader,
IN EFI_PEI_SERVICES 		**PeiServices
Output:
EFI_STATUS


CpuPeiPolicyNotify in the CpuPeiBeforeMem.c

Function : CpuPeiPolicyNotify

File: CpuPeiBeforeMem.c
Description:
CPU PEI pollicy PPI notify function
Input:
EFI_PEI_SERVICES **PeiServices
EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor
VOID *NullPpi
Output:
EFI_STATUS


CpuPeiPolicyOverWrite in the CpuPeiBeforeMem.c

Function : CpuPeiPolicyOverWrite

File: CpuPeiBeforeMem.c
Description:
This function over writes the CPU PEI RC policy
Input:
EFI_PEI_SERVICES **PeiServices
Output:
None


CpuPeiXtuInitBeforeMem in the CpuPeiBeforeMem.c

Function : CpuPeiXtuInitBeforeMem

File: CpuPeiBeforeMem.c
Description:
CPU XTU init code in PEI phase
Input:
IN EFI_FFS_FILE_HEADER		*FfsHeader,
IN EFI_PEI_SERVICES 		**PeiServices
Output:
EFI_STATUS


EnablePLLOverVoltage in the CpuPeiBeforeMem.c

Function : EnablePLLOverVoltage

File: CpuPeiBeforeMem.c
Description:
Enable PLL over voltage for CPU
Input:
EFI_PEI_SERVICES    **PeiServices
UINT8               NumOfCpuCore
UINT16              *pCoreRatioData
Output:
EFI_STATUS


InitOcMailbox in the CpuPeiBeforeMem.c

Function : InitOcMailbox

File: CpuPeiBeforeMem.c
Description:
Initialize Overclocking Config data.
Input:
EFI_PEI_SERVICES            **PeiServices
OVERCLOCKING_CONFIG_PPI     *OverclockingConfig
Output:
VOID


OverlockingConfigUpdate in the CpuPeiBeforeMem.c

Function : OverlockingConfigUpdate

File: CpuPeiBeforeMem.c
Description:
Update Overclocking Config data.
Input:
EFI_PEI_SERVICES            **PeiServices
BIOS_SETTING_DATA           *SettingData
OVERCLOCKING_CONFIG_PPI     *OverclockingConfig
Output:
EFI_STATUS


OverrideNonTurboRatio in the CpuPeiBeforeMem.c

Function : OverrideNonTurboRatio

File: CpuPeiBeforeMem.c
Description:
Override CPU NonTurbo Ratio Maximum value
Input:
EFI_PEI_SERVICES    **PeiServices
UINT8               ProcessorMul
CPU_CONFIG_PPI      *CpuConfig
Output:
EFI_STATUS


PEGDMIRatio in the CpuPeiBeforeMem.c

Function : PEGDMIRatio

File: CpuPeiBeforeMem.c
Description:
Modify PEG/DMI Ratio for CPU
Input:
EFI_PEI_SERVICES    **PeiServices
BIOS_SETTING_DATA   *SettingData
Output:
EFI_STATUS


PLLFilterFunction in the CpuPeiBeforeMem.c

Function : PLLFilterFunction

File: CpuPeiBeforeMem.c
Description:
Filter PLL setting High(3.2GHz) or lower(1.6GHz)
Input:
EFI_PEI_SERVICES    **PeiServices
BIOS_SETTING_DATA   *SettingData
Output:
EFI_STATUS


ReinstallSecPpis in the CpuPeiBeforeMem.c

Function : ReinstallSecPpis

File: CpuPeiBeforeMem.c
Description:
Reinstall PPIs from stack because stack will be lost when cache-as-ram is turned off.
Input:
IN EFI_PEI_SERVICES 		**PeiServices
Output:
EFI_STATUS


CpuPeiDebugger.c

Description:
This file contains PEI stage board component code for Template CPU module

The following functions are used in the file: CpuPeiDebugger.c.

Function | Description
CPUPEIDBG_Initialize | This eLink function is used to initialize CPU for PEI debugger support

Built on 11:00:20 06/12/15


CPUPEIDBG_Initialize in the CpuPeiDebugger.c

Function : CPUPEIDBG_Initialize

File: CpuPeiDebugger.c
Description:
This eLink function is used to initialize CPU for PEI debugger support
Input:
DbgXportIfStruc		Debug transport interface structure
Output:
EFI_STATUS
Notes:
PORTING REQUIRED


CpuPeiFuncs.c

Description:
This file is the main CPU PEI component file. This file provides
misc functions for CPU PEI drvier usage.

The following functions are used in the file: CpuPeiFuncs.c.

Function | Description
CpuPeiIntelXtuDataInit | Interl XTU utility data initialize in PEI phase
CpuPeiMiscFuncs |
InitMtrrPolicy1 | Config system cache.
InitMtrrPolicy2 | Config system cache.
NumOfOne | Count how many of ones in the binary value.

Built on 11:00:20 06/12/15


CpuPeiIntelXtuDataInit in the CpuPeiFuncs.c

Function : CpuPeiIntelXtuDataInit

File: CpuPeiFuncs.c
Description:
Interl XTU utility data initialize in PEI phase
Input:
IN EFI_PEI_SERVICES                 **PeiServices
IN EFI_PEI_READ_ONLY_VARIABLE_PPI   *ReadOnlyVariablePpi
IN EFI_BOOT_MODE                    BootMode
Output:
EFI_STATUS


CpuPeiMiscFuncs in the CpuPeiFuncs.c

Function : CpuPeiMiscFuncs

File: CpuPeiFuncs.c
Description:
Input:
IN EFI_PEI_SERVICES                 **PeiServices
IN EFI_PEI_READ_ONLY_VARIABLE_PPI   *ReadOnlyVariablePpi
IN EFI_BOOT_MODE                    BootMode
Output:
EFI_STATUS


InitMtrrPolicy1 in the CpuPeiFuncs.c

Function : InitMtrrPolicy1

File: CpuPeiFuncs.c
Description:
Config system cache.
Input:
IN EFI_PEI_SERVICES     **PeiServices
IN PEI_CACHE_PPI        *CachePpi
IN UINT64               Above4GMemoryLength
Output:
EFI_STATUS


InitMtrrPolicy2 in the CpuPeiFuncs.c

Function : InitMtrrPolicy2

File: CpuPeiFuncs.c
Description:
Config system cache.
Input:
IN EFI_PEI_SERVICES     **PeiServices
IN PEI_CACHE_PPI        *CachePpi
IN UINT64               Above4GMemoryLength
Output:
EFI_STATUS


NumOfOne in the CpuPeiFuncs.c

Function : NumOfOne

File: CpuPeiFuncs.c
Description:
Count how many of ones in the binary value.
Input:
IN UINT64 InputValue - Needed count value.
Output:
UINT8 - Number of one.


CpuRcPolicyDxe.c

Description:
DxeCpuPolicyInitList eLink interface & its default child procedure
for setting up DXE_CPU_PLATFORM_POLICY_PROTOCOL.

The following functions are used in the file: CpuRcPolicyDxe.c.

Function | Description
CallDxeCpuPolicyInitList | Get the microcode patch.

Built on 11:00:20 06/12/15


CallDxeCpuPolicyInitList in the CpuRcPolicyDxe.c

Function : CallDxeCpuPolicyInitList

File: CpuRcPolicyDxe.c
Description:
Get the microcode patch.
Input:
IN DXE_CPU_PLATFORM_POLICY_PROTOCOL      *This
IN UINT8                                 **MicrocodeData
Output:
EFI_STATUS
Built on 11:00:18 06/12/15


CpuRcPolicyPei.c

Description:
PeiCpuPolicyInitList eLink interface & its default child procedure
for setting up PEI_CPU_PLATFORM_POLICY_PPI.

The following functions are used in the file: CpuRcPolicyPei.c.

Function | Description
CallPeiCpuPolicyInitList | This function orderly calls functions in PeiCpuPolicyInitListTable for OEM or Custom to override PEI_CPU_PLATFORM_POLICY_PPI.

Built on 11:00:20 06/12/15


CallPeiCpuPolicyInitList in the CpuRcPolicyPei.c

Function : CallPeiCpuPolicyInitList

File: CpuRcPolicyPei.c
Description:
This function orderly calls functions in PeiCpuPolicyInitListTable
for OEM or Custom to override PEI_CPU_PLATFORM_POLICY_PPI.
Built on 11:00:18 06/12/15


CPUSetup.c

Description:
CPU Setup Rountines

The following functions are used in the file: CPUSetup.c.

Function | Description
FillCacheData | Init global cache data varilable
GetBoardSocketNumber | Get socket number from Apic ID.
GetMaxSpeedFromBrandString | Get the max speed from the brand string.
InitCpuInfo | Initialize CPU strings.
LocateCpuInfoProt | Callback on AMI CPU INFO protocol. Then call to init strings.

Built on 11:00:20 06/12/15


FillCacheData in the CPUSetup.c

Function : FillCacheData

File: CPUSetup.c
Description:
Init global cache data varilable
Input:
IN AMI_CPU_INFO_2_CACHE_DESCR *CacheDesc
IN UINT32 NumCacheEntries
Output:
VOID


GetBoardSocketNumber in the CPUSetup.c

Function : GetBoardSocketNumber

File: CPUSetup.c
Description:
Get socket number from Apic ID.
Input:
IN UINT32 ApicId
Output:
UINT32 - Physical Socket Id


GetMaxSpeedFromBrandString in the CPUSetup.c

Function : GetMaxSpeedFromBrandString

File: CPUSetup.c
Description:
Get the max speed from the brand string.
Input:
IN CHAR8    *CpuBrandString - Pointer to CPU brand string.
OUT CHAR8   *CpuMaxSpeedString -Pointer to string with format "9999 MHz"; 9999 can be any 4 digit number.
Output:
BOOLEAN - TRUE if frequency found.


InitCpuInfo in the CPUSetup.c

Function : InitCpuInfo

File: CPUSetup.c
Description:
Initialize CPU strings.
Input:
VOID
Output:
VOID


LocateCpuInfoProt in the CPUSetup.c

Function : LocateCpuInfoProt

File: CPUSetup.c
Description:
Callback on AMI CPU INFO protocol. Then call to init strings.
Input:
IN EFI_EVENT Event - Not used
IN VOID *Context - Not Used
Output:
VOID


CpuSmbios.c

Description:
Installs TYPE 4 and TYPE 7 SMBIOS tables.

The following functions are used in the file: CpuSmbios.c.

Function | Description
AddStrGetTok | Add string to buffer and return token value.
AutodetectFamily | Return family type from Brand String.
CollectCacheInfo | Store cache information in variables.
CpuSmbios | Create CPU SMBIOS Tables. Installs notification on SMBIOS handlers.
CreateCpuSmbiosTables | Create CPU SMBIOS Tables 4 and 7.
CreateSmbiosTable4 | Create SMBIOS Table 4
CreateSmbiosTable7 | Create SMBIOS Table 7
EstablishStringBuffer | Initialize string buffer variables
GetBufferSizeUsed | Get amount storage space used by strings.
GetMaxSpeedFromBrandString | Get the max speed from the brand string.
RemoveStringBuffer | Remove String Buffer structure.

Built on 11:00:20 06/12/15


AddStrGetTok in the CpuSmbios.c

Function : AddStrGetTok

File: CpuSmbios.c
Description:
Add string to buffer and return token value.
Input:
IN SMBIOS_TABLE_STR_BUFFER *StrBuffer - String Buffer structure
IN UINT8 *Str - Pointer to string.
Output:
UINT8 - token of string
Built on 11:00:18 06/12/15


AutodetectFamily in the CpuSmbios.c

Function : AutodetectFamily

File: CpuSmbios.c
Description:
Return family type from Brand String.
Input:
IN CHAR8 *BrandString
Output:
UINT8 - Family
Built on 11:00:18 06/12/15


CollectCacheInfo in the CpuSmbios.c

Function : CollectCacheInfo

File: CpuSmbios.c
Description:
Store cache information in variables.
Input:
VOID
Output:
VOID
Built on 11:00:18 06/12/15


CpuSmbios in the CpuSmbios.c

Function : CpuSmbios

File: CpuSmbios.c
Description:
Create CPU SMBIOS Tables. Installs notification on SMBIOS handlers.
Input:
VOID
Output:
VOID


CreateCpuSmbiosTables in the CpuSmbios.c

Function : CreateCpuSmbiosTables

File: CpuSmbios.c
Description:
Create CPU SMBIOS Tables 4 and 7.
Input:
IN EFI_EVENT Event - Not used
IN VOID *Context - Note Used
Output:
VOID


CreateSmbiosTable4 in the CpuSmbios.c

Function : CreateSmbiosTable4

File: CpuSmbios.c
Description:
Create SMBIOS Table 4
Input:
IN UINT32 PhysSocket
Output:
VOID


CreateSmbiosTable7 in the CpuSmbios.c

Function : CreateSmbiosTable7

File: CpuSmbios.c
Description:
Create SMBIOS Table 7
Input:
IN UINT8 CacheLevel (L1, L2, L3)
Output:
UINT16 - Handle for table.


EstablishStringBuffer in the CpuSmbios.c

Function : EstablishStringBuffer

File: CpuSmbios.c
Description:
Initialize string buffer variables
Input:
IN VOID *Buffer - Buffer address
IN UINT32 Size - Buffer Size
OUT SMBIOS_TABLE_STR_BUFFER **StrBuffer - String Buffer structure
Output:
VOID


GetBufferSizeUsed in the CpuSmbios.c

Function : GetBufferSizeUsed

File: CpuSmbios.c
Description:
Get amount storage space used by strings.
Input:
IN SMBIOS_TABLE_STR_BUFFER *StrBuffer - String Buffer structure
Output:
UINT32 - Size needed for strings.


GetMaxSpeedFromBrandString in the CpuSmbios.c

Function : GetMaxSpeedFromBrandString

File: CpuSmbios.c
Description:
Get the max speed from the brand string.
Input:
IN CHAR8    *CpuBrandString - Pointer to CPU brand string.
Output:
UINT32 - frequency found in MHz.


RemoveStringBuffer in the CpuSmbios.c

Function : RemoveStringBuffer

File: CpuSmbios.c
Description:
Remove String Buffer structure.
Input:
IN SMBIOS_TABLE_STR_BUFFER *StrBuffer - String Buffer structure
Output:
VOID


CpuSpSmi.c

Description:
Provide functions to CPU specific SMI

The following functions are used in the file: CpuSpSmi.c.

Function | Description
CpuSpSmiInit | Initializes CPU specific SMM Drivers.
InSmmFunction | Called from InstallSmiHandler
NotInSmmFunction | If Not In Smm Function
RestoreCpuMsr | This function restores the CPU MSRs during S3 resume.
RestoreMsrOnCpu | This function restores the CPU MSRs during S3 resume.
SaveCpuMsr | This function saves the CPU MSRs for S3 resume usage.

Built on 11:00:20 06/12/15


CpuSpSmiInit in the CpuSpSmi.c

Function : CpuSpSmiInit

File: CpuSpSmi.c
Description:
Initializes CPU specific SMM Drivers.
Input:
Output:
EFI_STATUS
Modified:
Notes:
Here is the control flow of this function:
Referrals:


InSmmFunction in the CpuSpSmi.c

Function : InSmmFunction

File: CpuSpSmi.c
Description:
Called from InstallSmiHandler
Input:

Output:

None

Modified:

Notes:

Referrals:


NotInSmmFunction in the CpuSpSmi.c

Function : NotInSmmFunction

File: CpuSpSmi.c
Description:
If Not In Smm Function
Input:

Output:

None

Modified:

Notes:

Referrals:


RestoreCpuMsr in the CpuSpSmi.c

Function : RestoreCpuMsr

File: CpuSpSmi.c
Description:
This function restores the CPU MSRs during S3 resume.
Input:
DispatchHandle      Handle to the Dispatcher
DispatchContext     SW SMM dispatcher context
Output:
None
Modified:
Notes:

Referrals:


RestoreMsrOnCpu in the CpuSpSmi.c

Function : RestoreMsrOnCpu

File: CpuSpSmi.c
Description:
This function restores the CPU MSRs during S3 resume.
Input:
None
Output:
None
Modified:
Notes:

Referrals:


SaveCpuMsr in the CpuSpSmi.c

Function : SaveCpuMsr

File: CpuSpSmi.c
Description:
This function saves the CPU MSRs for S3 resume usage.
Input:
DispatchHandle      Handle to the Dispatcher
DispatchContext     SW SMM dispatcher context
Output:
None
Modified:
Notes:

Referrals:


CpuSpSmi.DXS

Description:
Dependency file for the CpuSp SMI
Built on 11:00:20 06/12/15


CpuSpSmi.h

Description:
This file contains the Includes, Definitions, typedefs,
        Variable and External Declarations, Structure and
function prototypes needed for the CpuSpSMI Component
Built on 11:00:20 06/12/15


CpuSpSmi.mak

Description:
Make file for the CpuSpSMI component
Built on 11:00:20 06/12/15


CrcSecPpi.c

The following functions are used in the file: CrcSecPpi.c.

Function | Description
CrcSecPlatformInformationPpi | Install SecPlatformInformation PPI that Intel Ivybridge CPU reference code needs. (conveys state information out of the SEC phase into PEI)

Built on 11:00:20 06/12/15


CrcSecPlatformInformationPpi in the CrcSecPpi.c

Function : CrcSecPlatformInformationPpi

File: CrcSecPpi.c
Description:
Install SecPlatformInformation PPI that Intel Ivybridge CPU reference code needs.
(conveys state information out of the SEC phase into PEI)
Input:
IN EFI_FFS_FILE_HEADER *FfsHeader - pointer to the header of the current firmware file system
IN EFI_PEI_SERVICES **PeiServices - pointer to the PeiServices Table
Output:
EFI_SUCCESS
Notes:


FoundationIa32.mak

Description:
Built on 11:00:20 06/12/15


FoundationIPF.mak

Description:
Built on 11:00:20 06/12/15


Foundationx64.mak

Description:
Built on 11:00:20 06/12/15


FwhFvb.c

Description:
This file contains code for flash update used by the MicrocodeUpdate module.

The following functions are used in the file: FwhFvb.c.

Function | Description
FwhFvbErase | This function erases a block of NVRAM.
FwhWrite | This function writes a block of NVRAM.

Built on 11:00:20 06/12/15


FwhFvbErase in the FwhFvb.c

Function : FwhFvbErase

File: FwhFvb.c
Description:
This function erases a block of NVRAM.
Input:
Address - Address of the block to erase
Output:
Return Status based on errors that occurred while erasing.


FwhWrite in the FwhFvb.c

Function : FwhWrite

File: FwhFvb.c
Description:
This function writes a block of NVRAM.
Input:
Address       - Address of the block to write.
Buffer        - Pointer to a buffer containing data to write.
NumberOfBytes - The number of bytes to write
Output:
Return Status based on errors that occurred while writing.


IA32CLib.c

Description:
Generic CPU library functions for the IA32 architecture.   See function
definitions in the x64 library;  most IA32 functions have been removed
from help builder output to fix a name collision issue.

The following functions are used in the file: IA32CLib.c.

Function | Description
InitLongMode | VOID InitLongMode(IN EFI_PEI_SERVICES **PeiServices, IN VOID *Function, IN VOID *Parameter1, IN VOID *Parameter2) initializes memory page mapping, enables long mode and jumps to a provided function.
InitLongModeExt | VOID InitLongMode(IN EFI_PEI_SERVICES **PeiServices, IN VOID *Function, IN VOID *Parameter1, IN VOID *Parameter2) initializes memory page mapping, enables long mode and jumps to a provided function.
memcpy | VOID memcpy(OUT VOID *pDestination, IN VOID *pSource, IN UINTN Count) is a wrapper for memcpy, which copies Count bytes of memory from Source to Destination.

Built on 11:00:20 06/12/15


InitLongMode in the IA32CLib.c

Function : InitLongMode

File: IA32CLib.c
Description:
VOID InitLongMode(IN EFI_PEI_SERVICES **PeiServices, IN VOID *Function,
IN VOID *Parameter1, IN VOID *Parameter2) initializes memory page mapping,
enables long mode and jumps to a provided function.
Input:
IN EFI_PEI_SERVICES **PeiServices
Double pointer to the PEI Services table.

IN VOID *Function
Pointer to a function for EnableLongMode to call.

IN VOID *Parameter1
First parameter to provide the Function to be called.

IN VOID *Parameter2
Second parameter to provide the Function to be called.
Output:
VOID.
Modified:
Notes:
Referrals:
FindNextHobByType
EFI_ERROR
GetPageTableNumPages
FillPageTable
EnableLongMode


InitLongModeExt in the IA32CLib.c

Function : InitLongModeExt

File: IA32CLib.c
Description:
VOID InitLongMode(IN EFI_PEI_SERVICES **PeiServices, IN VOID *Function,
IN VOID *Parameter1, IN VOID *Parameter2) initializes memory page mapping,
enables long mode and jumps to a provided function.
Input:
IN EFI_PEI_SERVICES **PeiServices
Double pointer to the PEI Services table.

IN VOID *Function
Pointer to a function for EnableLongMode to call.

IN VOID *Parameter1
First parameter to provide the Function to be called.

IN VOID *Parameter2
Second parameter to provide the Function to be called.
Output:
VOID.
Modified:
Notes:
Referrals:
FindNextHobByType
EFI_ERROR
GetPageTableNumPages
FillPageTable
EnableLongMode


memcpy in the IA32CLib.c

Function : memcpy

File: IA32CLib.c
Description:
VOID memcpy(OUT VOID *pDestination, IN VOID *pSource, IN UINTN Count) is
a wrapper for memcpy, which copies Count bytes of memory from Source to
Destination.
Input:
OUT VOID *pDestination
Memory address where data shall be copied.  User is responsible for
allocating the necessary memory resources.

IN VOID *pSource
Memory address from where data shall be copied.

IN UINTN Count
Number of bytes to copy from pSource.
Output:
VOID.
Modified:
Notes:
memcpy checks for overlapping of source and destination and selects copy
direction that prevents memory corruption.
Referrals:
memcpy


IA32rules.mak

Description:
Defines IA32-specific build rules.
This file is included into the template makefile rules.mak
Built on 11:00:20 06/12/15


MBIOSMAC.MAC

Description:
Assembly Macros

The following functions are used in the file: MBIOSMAC.MAC.

Function | Description
mBODY_CALL_PROC_FAR | Call far macro.
mBODY_CALL_PROC_NEAR | Call near macro.
mBODY_ID_AND_TBL_ENTRY_FAR |
mBODY_ID_AND_TBL_ENTRY_NEAR | Start ID Table Entry macro.
mBODY_JMP_PROC_FAR | jmp far macro with return label to jump back to.
mBODY_JMP_PROC_NEAR | Jump Near Macro. Provide a return label to jump to.
mBODY_JMP_PROC_NEAR32 | Jump near 32-bit macro. Provide a return label to jump to.
mBODY_TBL_ENTRY_FAR |
mBODY_TBL_ENTRY_NEAR | Start table enty macro.
mEND_PROC_FAR | Ret procedure macro. Last in a group.
mEND_PROC_NEAR | End near procedure macro. Last in a group.
mEND_PROC_WITH_JMP_FAR | End procedure macro. Last in agroup.
mEND_PROC_WITH_JMP_NEAR | End of procedure and jump near macro. Last procedure in a group.
mEND_PROC_WITH_JMP_NEAR32 | Jump Near 32-bit macro. Last macro in a group.
mEND_TBL |
mEXTERN_FAR | External Far macro
mEXTERN_NEAR | External Near macro
mEXTERN_NEAR32 | External Near 32 Macro
mSTART_PROC_FAR | Far procedure macro.
mSTART_PROC_NEAR | Start Near procedure macro.
mSTART_PROC_NEAR32 | Start Near 32-bit procedure macro.
mSTART_TBL | Start table macro.

Built on 11:00:20 06/12/15


mBODY_CALL_PROC_FAR in the MBIOSMAC.MAC

Function : mBODY_CALL_PROC_FAR

File: MBIOSMAC.MAC
Description:
Call far macro.
Input:
LabelID
LabelName


mBODY_CALL_PROC_NEAR in the MBIOSMAC.MAC

Function : mBODY_CALL_PROC_NEAR

File: MBIOSMAC.MAC
Description:
Call near macro.
Input:
LabelID
LabelName


mBODY_ID_AND_TBL_ENTRY_FAR in the MBIOSMAC.MAC

Function : mBODY_ID_AND_TBL_ENTRY_FAR

File: MBIOSMAC.MAC
Description:
Input:
LabelID
LabelName


mBODY_ID_AND_TBL_ENTRY_NEAR in the MBIOSMAC.MAC

Function : mBODY_ID_AND_TBL_ENTRY_NEAR

File: MBIOSMAC.MAC
Description:
Start ID Table Entry macro.
Input:
LabelID
LabelName


mBODY_JMP_PROC_FAR in the MBIOSMAC.MAC

Function : mBODY_JMP_PROC_FAR

File: MBIOSMAC.MAC
Description:
jmp far macro with return label to jump back to.
Input:
LabelID
LabelName


mBODY_JMP_PROC_NEAR in the MBIOSMAC.MAC

Function : mBODY_JMP_PROC_NEAR

File: MBIOSMAC.MAC
Description:
Jump Near Macro. Provide a return label to jump to.
Input:
LabelID
LabelName


mBODY_JMP_PROC_NEAR32 in the MBIOSMAC.MAC

Function : mBODY_JMP_PROC_NEAR32

File: MBIOSMAC.MAC
Description:
Jump near 32-bit macro. Provide a return label to jump to.
Input:
LabelID
LabelName


mBODY_TBL_ENTRY_FAR in the MBIOSMAC.MAC

Function : mBODY_TBL_ENTRY_FAR

File: MBIOSMAC.MAC
Description:
Input:
LabelID
LabelName


mBODY_TBL_ENTRY_NEAR in the MBIOSMAC.MAC

Function : mBODY_TBL_ENTRY_NEAR

File: MBIOSMAC.MAC
Description:
Start table enty macro.
Input:
LabelID
LabelName


mEND_PROC_FAR in the MBIOSMAC.MAC

Function : mEND_PROC_FAR

File: MBIOSMAC.MAC
Description:
Ret procedure macro. Last in a group.
Input:
LabelName


mEND_PROC_NEAR in the MBIOSMAC.MAC

Function : mEND_PROC_NEAR

File: MBIOSMAC.MAC
Description:
End near procedure macro. Last in a group.
Input:
LabelName


mEND_PROC_WITH_JMP_FAR in the MBIOSMAC.MAC

Function : mEND_PROC_WITH_JMP_FAR

File: MBIOSMAC.MAC
Description:
End procedure macro. Last in agroup.
Input:
LabelName


mEND_PROC_WITH_JMP_NEAR in the MBIOSMAC.MAC

Function : mEND_PROC_WITH_JMP_NEAR

File: MBIOSMAC.MAC
Description:
End of procedure and jump near macro. Last procedure in a group.
Input:
LabelName


mEND_PROC_WITH_JMP_NEAR32 in the MBIOSMAC.MAC

Function : mEND_PROC_WITH_JMP_NEAR32

File: MBIOSMAC.MAC
Description:
Jump Near 32-bit macro. Last macro in a group.
Input:
LabelName


mEND_TBL in the MBIOSMAC.MAC

Function : mEND_TBL

File: MBIOSMAC.MAC
Description:
Input:
LabelName


mEXTERN_FAR in the MBIOSMAC.MAC

Function : mEXTERN_FAR

File: MBIOSMAC.MAC
Description:
External Far macro
Input:
LabelName


mEXTERN_NEAR in the MBIOSMAC.MAC

Function : mEXTERN_NEAR

File: MBIOSMAC.MAC
Description:
External Near macro
Input:
LabelName


mEXTERN_NEAR32 in the MBIOSMAC.MAC

Function : mEXTERN_NEAR32

File: MBIOSMAC.MAC
Description:
External Near 32 Macro
Input:
LabelName


mSTART_PROC_FAR in the MBIOSMAC.MAC

Function : mSTART_PROC_FAR

File: MBIOSMAC.MAC
Description:
Far procedure macro.
Input:
LabelName


mSTART_PROC_NEAR in the MBIOSMAC.MAC

Function : mSTART_PROC_NEAR

File: MBIOSMAC.MAC
Description:
Start Near procedure macro.
Input:
LabelName


mSTART_PROC_NEAR32 in the MBIOSMAC.MAC

Function : mSTART_PROC_NEAR32

File: MBIOSMAC.MAC
Description:
Start Near 32-bit procedure macro.
Input:
LabelName


mSTART_TBL in the MBIOSMAC.MAC

Function : mSTART_TBL

File: MBIOSMAC.MAC
Description:
Start table macro.
Input:
LabelName


Microcode.mak

Description:
Build the microcode file.
Built on 11:00:20 06/12/15


MicrocodeUpdate.c

Description:
Microcode Update SMI handler.
This file contains code for processing Interrupt 15 function
D042h, and for registering the callback that does the processing.

The following functions are used in the file: MicrocodeUpdate.c.

Function | Description
CheckAddressRange | Check address range to avoid TSEG area.
CopyToFlashBuffer | Copy data to the buffer. When the buffer is full, write to the flash, and continues to copy data.
CountBlks | Count blocks taken by microcode in FFS.
FillBufferAndFlush | Fill the rest of the buffer of a size of the flash block, then update the flash.
FillMicrocodeBlkMap | Update gMcodeBlkMap with data for microcode.
FindMicrocodeFfs | Find Micorode FFS in FV.
FindMicrocodeOfStepping | Search the microcode in the firmware for the cpu signature or earlier steping.
FlushBufferToFlash | Helper function to write the buffer to the flash and reset the buffer.
GetInstalledMicrocodeRevision | Get the installed microcode revision on the cpu.
InitializeFlashBuffer | Initialize the flash buffer before using.
InitializeMicrocodeSmm | This function registers the INT15 D042 SW SMI handler This is the driver entry pOoint.
InitMcodeBlkMap | Initialize gMcodeBlkMap and related globals for all microcode FFS.
InitMicrocodeVariables | Initialize global variables used by the driver.
InSmmFunction | This function is called from the InitSmmHandler if driver is in SMM.
IsValidChecksum | Validate the checksum.
IsValidHeader | Check if the header is valid.
LoadMicrocode | Load the microcode onto the CPU.
LoadMicrocodeEachCpu | Load the microcode on each CPU.
MicrocodeUpdateCallback | This notification function is called when an SMM Mode is invoked through SMI. This may happen during RT, so it must be RT safe. Interrupt 15h, function D042h is processed here.
PresenceTest | Execute the presence test function for int 15h.
ReadUpdateData | Read microcode using int15h.
SMI_UC_DWORD_REGS | Write microcode to flash and load microcode into each CPU.
UpdateControl | Execute the update control for int 15h.
WriteValueToFlashBuffer | Fill part of the buffer with a value. When the buffer is full, write to the flash, and continue to update the beginning of the buffer with a value.

Built on 11:00:20 06/12/15


CheckAddressRange in the MicrocodeUpdate.c

Function : CheckAddressRange

File: MicrocodeUpdate.c
Description:
Check address range to avoid TSEG area.
Input:
Address - starting address
Range   - length of the area
Output:
EFI_SUCCESS         - Access granted
EFI_ACCESS_DENIED   - Access denied!
Built on 11:00:18 06/12/15


CopyToFlashBuffer in the MicrocodeUpdate.c

Function : CopyToFlashBuffer

File: MicrocodeUpdate.c
Description:
Copy data to the buffer. When the buffer is full, write to the flash,
and continues to copy data.
Input:
IN UINT8 Data - Start of data to write.
IN UINT32 Size - Amount to Write.
Output:
VOID
Built on 11:00:18 06/12/15


CountBlks in the MicrocodeUpdate.c

Function : CountBlks

File: MicrocodeUpdate.c
Description:
Count blocks taken by microcode in FFS.
Input:
IN UINT8 *McodeStart - Start of microcode in FFS.
IN UINT32 McodeSize - Size of microcode and empty space in FFS.
IN BOOLEAN CountEmpty - TRUE if calculate blocks for empty space.
Output:
UINT16 - Number of blocks needed.


FillBufferAndFlush in the MicrocodeUpdate.c

Function : FillBufferAndFlush

File: MicrocodeUpdate.c
Description:
Fill the rest of the buffer of a size of the flash block, then update the flash.
Input:
IN UINT8 *Data - Pointer to starting of data to write to the flash.
Output:
VOID


FillMicrocodeBlkMap in the MicrocodeUpdate.c

Function : FillMicrocodeBlkMap

File: MicrocodeUpdate.c
Description:
Update gMcodeBlkMap with data for microcode.
Input:
IN OUT   *BlkStart - On Input: Start update with this block. Output: Next call use this value.
IN UINT8 *McodeStart - Start of microcode in FFS.
IN UINT32 McodeSize - Size of microcode and empty space in FFS.
IN BOOLEAN CountEmpty - TRUE if update blocks for empty space.
Output:
VOID


FindMicrocodeFfs in the MicrocodeUpdate.c

Function : FindMicrocodeFfs

File: MicrocodeUpdate.c
Description:
Find Micorode FFS in FV.
Input:
IN EFI_FIRMWARE_VOLUME_HEADER *FvHdr - Firmware volume to search
Output:
UINT8 * - Return FFS.


FindMicrocodeOfStepping in the MicrocodeUpdate.c

Function : FindMicrocodeOfStepping

File: MicrocodeUpdate.c
Description:
Search the microcode in the firmware for the cpu signature
   or earlier steping.
Input:
UINT8 *Mcode - Address of Mcode Header.
UINT8 *End       - Mcode End.
UINT32 CpuSignature - Signature of CPU to find.
Output:
VOID


FlushBufferToFlash in the MicrocodeUpdate.c

Function : FlushBufferToFlash

File: MicrocodeUpdate.c
Description:
Helper function to write the buffer to the flash and reset the buffer.
Input:
VOID
Output:
VOID


GetInstalledMicrocodeRevision in the MicrocodeUpdate.c

Function : GetInstalledMicrocodeRevision

File: MicrocodeUpdate.c
Description:
Get the installed microcode revision on the cpu.
Input:
VOID
Output:
UINT32 - Revision of microcode currently installed on CPU.


InitializeFlashBuffer in the MicrocodeUpdate.c

Function : InitializeFlashBuffer

File: MicrocodeUpdate.c
Description:
Initialize the flash buffer before using.
Input:
IN UINT8* FirstFlashBlk - Address of first block to flash.
IN UINT8* FlashBuffer - Flash Buffer.
Output:
VOID


InitializeMicrocodeSmm in the MicrocodeUpdate.c

Function : InitializeMicrocodeSmm

File: MicrocodeUpdate.c
Description:
This function registers the INT15 D042 SW SMI handler
This is the driver entry pOoint.
Input:
ImageHandle   - Pointer to the loaded image protocol for this driver
SystemTable   - Pointer to the EFI System Table
Output:
EFI_STATUS


InitMcodeBlkMap in the MicrocodeUpdate.c

Function : InitMcodeBlkMap

File: MicrocodeUpdate.c
Description:
Initialize gMcodeBlkMap and related globals for all microcode FFS.
Input:
VOID
Output:
VOID


InitMicrocodeVariables in the MicrocodeUpdate.c

Function : InitMicrocodeVariables

File: MicrocodeUpdate.c
Description:
Initialize global variables used by the driver.
Input:
VOID
Output:
VOID


InSmmFunction in the MicrocodeUpdate.c

Function : InSmmFunction

File: MicrocodeUpdate.c
Description:
This function is called from the InitSmmHandler if driver is in SMM.
Input:
ImageHandle   - Pointer to the loaded image protocol for this driver
SystemTable   - Pointer to the EFI System Table
Output:
EFI_STATUS


IsValidChecksum in the MicrocodeUpdate.c

Function : IsValidChecksum

File: MicrocodeUpdate.c
Description:
Validate the checksum.
Input:
VOID *Microcode - Address of Microcode Header.
UINT32 Size     - Microcode Size.
Output:
BOOLEAN -- TRUE if checksum is valid.


IsValidHeader in the MicrocodeUpdate.c

Function : IsValidHeader

File: MicrocodeUpdate.c
Description:
Check if the header is valid.
Input:
MICROCODE_HEADER *uHeader -- Address of Microcode Header.
Output:
BOOLEAN -- TRUE if microcode header is valid.


LoadMicrocode in the MicrocodeUpdate.c

Function : LoadMicrocode

File: MicrocodeUpdate.c
Description:
Load the microcode onto the CPU.
Input:
VOID *Mcode - Address of Microcode Header.
Output:
VOID


LoadMicrocodeEachCpu in the MicrocodeUpdate.c

Function : LoadMicrocodeEachCpu

File: MicrocodeUpdate.c
Description:
Load the microcode on each CPU.
Input:
EFI_SMI_CPU_SAVE_STATE *CpuSaveState
Output:
VOID


MicrocodeUpdateCallback in the MicrocodeUpdate.c

Function : MicrocodeUpdateCallback

File: MicrocodeUpdate.c
Description:
This notification function is called when an SMM Mode
is invoked through SMI. This may happen during RT,
so it must be RT safe.
Interrupt 15h, function D042h is processed here.
Input:
DispatchHandle  - EFI Handle
DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
Output:
Status code returned to function D042h caller.


PresenceTest in the MicrocodeUpdate.c

Function : PresenceTest

File: MicrocodeUpdate.c
Description:
Execute the presence test function for int 15h.
Input:
SMI_UC_DWORD_REGS *Regs

AX - D042h
BL - 00h i.e., PRESCENCE_TEST
Output:
VOID

CF  NC - All return values are valid
CY - Failure, AH contains status.

AH  Return code
AL  Additional OEM information
EBX Part one of the signature 'INTE'.
ECX Part two of the signature 'LPEP'.
EDX Version number of the BIOS update loader
SI  Number of update blocks system can record in NVRAM (1 based).
Notes:


ReadUpdateData in the MicrocodeUpdate.c

Function : ReadUpdateData

File: MicrocodeUpdate.c
Description:
Read microcode using int15h.
Input:
SMI_UC_DWORD_REGS *Regs

AX  - D042h
BL  - 03h i.e., READ_UPDATE_DATA
ES:DI - Real Mode Pointer to the Intel Update structure.
SS:SP - Stack pointer (32K minimum)
SI    - Update number, the index number of the update block to be read.
This number is zero based and must be less than the update
count returned from the prescence test function.
Output:
VOID

AH  Return code
AL  Additional OEM information
BL  Update status Disable or Enable.
Notes:


SMI_UC_DWORD_REGS in the MicrocodeUpdate.c

Function : SMI_UC_DWORD_REGS

File: MicrocodeUpdate.c
Description:
Write microcode to flash and load microcode into each CPU.
Input:
EFI_SMI_CPU_SAVE_STATE *Regs

AX    - D042h
BL    - 01h i.e., WRITE_UPDATE_DATA
ES:DI - Real Mode Pointer to the Intel Update structure.
CX    - Scratch Pad1 (Real Mode Scratch segment 64K in length)
DX    - Scratch Pad2 (Real Mode Scratch segment 64K in length)
SI    - Scratch Pad3 (Real Mode Scratch segment 64K in length)
SS:SP - Stack pointer (32K minimum)
Output:
VOID

CF  NC - All return values are valid
CY - Failure, AH contains status.

AH  Return code
AL  Additional OEM information


UpdateControl in the MicrocodeUpdate.c

Function : UpdateControl

File: MicrocodeUpdate.c
Description:
Execute the update control for int 15h.
Input:
SMI_UC_DWORD_REGS *Regs

AX - D042h
BL - 02h i.e., UPDATE_CONTROL
BH - Task
1 - Enable the update loading at initialization time.
2 - Determine the current state of the update control without changing its status.
Output:
VOID

AH  Return code
AL  Additional OEM information
BL  Update status Disable or Enable.
Notes:

Built on 11:00:20 06/12/15


WriteValueToFlashBuffer in the MicrocodeUpdate.c

Function : WriteValueToFlashBuffer

File: MicrocodeUpdate.c
Description:
Fill part of the buffer with a value. When the buffer is full, write to the flash,
and continue to update the beginning of the buffer with a value.
Input:
IN UINT8 Value - Value to write.
IN UINT32 Size - Amount to Write.
Output:
VOID
Built on 11:00:20 06/12/15


MicrocodeUpdate.h

Description:
Header file for Microcode Update SMI handler.
Built on 11:00:20 06/12/15


Misc.asm

Description:
Built on 11:00:20 06/12/15


MiscX64Lib.mak

Description:
Built on 11:00:20 06/12/15


PlatformCpuLib.c

Description:
Platform CPU Lib C source file

The following functions are used in the file: PlatformCpuLib.c.

Function | Description
DxeInitPlatformCpuLib | Initialize DXE Init Platform Cpu Lib.
DxePlatformCpuSaveSupportedData | This functions saves the CPU supported data.
GetPlatformCpuBootRatio | Get the platform policy of for boot ratio.
GetPlatformCpuGroup | Get the CPU group for the platform policy.
GetPlatformCpuLimitCpuidEnable | Get the platform policy of limiting Cpuid.
GetPlatformCpuVtEnable | Get the platform policy of enable VT.
GetPlatformCpux2ApicEnable | Get the platform policy of enable x2Apic.
GetPlatformCpuXdEnable | Get the platform policy of enable XD.
GetPlatformNumCores | Get the maximum number of cores supported by processor.
PeiInitPlatformCpuLib | Init platform policy in PEI.
PlatformCpuAesSupport | Set if supported by platform.
PlatformCpuC10Support | Set if supported by platform.
PlatformCpuC3Support | Set if supported by platform.
PlatformCpuC6Support | Set if supported by platform.
PlatformCpuC7Support | Set if supported by platform.
PlatformCpuC8Support | Set if supported by platform.
PlatformCpuC9Support | Set if supported by platform.
PlatformCpuCtdpSupport | Set if supported by platform.
PlatformCpuCurrentLimitSupport | Set if supported by platform.
PlatformCpuEistSupport | Set if supported by platform.
PlatformCpuHtSupport | Set if supported by platform.
PlatformCpuLimitCpuidSupport | Set if supported by platform.
PlatformCpuLocalx2ApicSupport | Set if supported by platform.
PlatformCpuMismatch | Report is populated CPU combination is not supported.
PlatformCpuMultiCoreSupport | Set if supported by platform.
PlatformCpuMultiSocketPopulated | Set if supported by platform.
PlatformCpuMultiSocketSupport | Set if supported by platform.
PlatformCpuPkgCStateDemotionSupport | Set if supported by platform. Available only in 4th Generation Intelr CoreT processors with signature greater than 000306C1h.
PlatformCpuPwrLimitConfigSupport | Set if supported by platform.
PlatformCpuSmxSupport | Set if supported by platform.
PlatformCpuSocketSetPopulated | Set sockets populated.
PlatformCpuTurboModeSupport | Set if supported by platform.
PlatformCpuVtSupport | Set if supported by platform.
PlatformCpuXdSupport | Set if supported by platform.
PlatformCpuXeCoreRatioLimitSupport | Set if supported by platform.
PlatformTpmDevicePresent | Set if Tpm device is present.

Built on 11:00:20 06/12/15


DxeInitPlatformCpuLib in the PlatformCpuLib.c

Function : DxeInitPlatformCpuLib

File: PlatformCpuLib.c
Description:
Initialize DXE Init Platform Cpu Lib.
Input:
IN EFI_BOOT_SERVICES       *Bs
IN EFI_RUNTIME_SERVICES    *Rs
OUT VOID                   **Handle
Output:
EFI_STATUS


DxePlatformCpuSaveSupportedData in the PlatformCpuLib.c

Function : DxePlatformCpuSaveSupportedData

File: PlatformCpuLib.c
Description:
This functions saves the CPU supported data.
Input:
IN EFI_RUNTIME_SERVICES    *Rs
Output:
EFI_STATUS


GetPlatformCpuBootRatio in the PlatformCpuLib.c

Function : GetPlatformCpuBootRatio

File: PlatformCpuLib.c
Description:
Get the platform policy of for boot ratio.
Input:
IN VOID *Handle
Output:
UINT32 Boot Ratio


GetPlatformCpuGroup in the PlatformCpuLib.c

Function : GetPlatformCpuGroup

File: PlatformCpuLib.c
Description:
Get the CPU group for the platform policy.
Input:
IN VOID *Handle
Output:
UINT32 Cpu Group


GetPlatformCpuLimitCpuidEnable in the PlatformCpuLib.c

Function : GetPlatformCpuLimitCpuidEnable

File: PlatformCpuLib.c
Description:
Get the platform policy of limiting Cpuid.
Input:
IN VOID *Handle
Output:
BOOLEAN -- True Limit CPU ID.


GetPlatformCpuVtEnable in the PlatformCpuLib.c

Function : GetPlatformCpuVtEnable

File: PlatformCpuLib.c
Description:
Get the platform policy of enable VT.
Input:
IN VOID *Handle
Output:
BOOLEAN -- True Enable VT


GetPlatformCpux2ApicEnable in the PlatformCpuLib.c

Function : GetPlatformCpux2ApicEnable

File: PlatformCpuLib.c
Description:
Get the platform policy of enable x2Apic.
Input:
IN VOID *Handle
Output:
BOOLEAN -- True Enable x2Apic


GetPlatformCpuXdEnable in the PlatformCpuLib.c

Function : GetPlatformCpuXdEnable

File: PlatformCpuLib.c
Description:
Get the platform policy of enable XD.
Input:
IN VOID *Handle
Output:
BOOLEAN -- True Enable XD.


GetPlatformNumCores in the PlatformCpuLib.c

Function : GetPlatformNumCores

File: PlatformCpuLib.c
Description:
Get the maximum number of cores supported by processor.
Input:
IN VOID     *Handle
IN UINT32   Package - Package number. If question applies to all packages, use 0.
Output:
UINT8 - Number of cores
Output may be CPU specific, since this is handled by CPU specific model.


PeiInitPlatformCpuLib in the PlatformCpuLib.c

Function : PeiInitPlatformCpuLib

File: PlatformCpuLib.c
Description:
Init platform policy in PEI.
Input:
IN EFI_PEI_SERVICES **PeiServices
Output:
VOID **Handle


PlatformCpuAesSupport in the PlatformCpuLib.c

Function : PlatformCpuAesSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuC10Support in the PlatformCpuLib.c

Function : PlatformCpuC10Support

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuC3Support in the PlatformCpuLib.c

Function : PlatformCpuC3Support

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuC6Support in the PlatformCpuLib.c

Function : PlatformCpuC6Support

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuC7Support in the PlatformCpuLib.c

Function : PlatformCpuC7Support

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuC8Support in the PlatformCpuLib.c

Function : PlatformCpuC8Support

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuC9Support in the PlatformCpuLib.c

Function : PlatformCpuC9Support

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuCtdpSupport in the PlatformCpuLib.c

Function : PlatformCpuCtdpSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuCurrentLimitSupport in the PlatformCpuLib.c

Function : PlatformCpuCurrentLimitSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuEistSupport in the PlatformCpuLib.c

Function : PlatformCpuEistSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuHtSupport in the PlatformCpuLib.c

Function : PlatformCpuHtSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuLimitCpuidSupport in the PlatformCpuLib.c

Function : PlatformCpuLimitCpuidSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuLocalx2ApicSupport in the PlatformCpuLib.c

Function : PlatformCpuLocalx2ApicSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuMismatch in the PlatformCpuLib.c

Function : PlatformCpuMismatch

File: PlatformCpuLib.c
Description:
Report is populated CPU combination is not supported.
Input:
IN VOID *Handle - Setup Handle
IN BOOLEAN Mismatch - TRUE if CPU combination not supported. Default: Not populated.
Output:
VOID


PlatformCpuMultiCoreSupport in the PlatformCpuLib.c

Function : PlatformCpuMultiCoreSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuMultiSocketPopulated in the PlatformCpuLib.c

Function : PlatformCpuMultiSocketPopulated

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Populated
Output:
VOID


PlatformCpuMultiSocketSupport in the PlatformCpuLib.c

Function : PlatformCpuMultiSocketSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuPkgCStateDemotionSupport in the PlatformCpuLib.c

Function : PlatformCpuPkgCStateDemotionSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
        Available only in 4th Generation Intelr CoreT
        processors with signature greater than 000306C1h.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuPwrLimitConfigSupport in the PlatformCpuLib.c

Function : PlatformCpuPwrLimitConfigSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuSmxSupport in the PlatformCpuLib.c

Function : PlatformCpuSmxSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuSocketSetPopulated in the PlatformCpuLib.c

Function : PlatformCpuSocketSetPopulated

File: PlatformCpuLib.c
Description:
Set sockets populated.
Input:
IN VOID *Handle - Setup Handle
IN UINT32 Socket - Socket (0-based)
IN BOOLEAN Populated - TRUE if populated. Default: Not populated.
Output:
VOID


PlatformCpuTurboModeSupport in the PlatformCpuLib.c

Function : PlatformCpuTurboModeSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuVtSupport in the PlatformCpuLib.c

Function : PlatformCpuVtSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuXdSupport in the PlatformCpuLib.c

Function : PlatformCpuXdSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuXeCoreRatioLimitSupport in the PlatformCpuLib.c

Function : PlatformCpuXeCoreRatioLimitSupport

File: PlatformCpuLib.c
Description:
Set if supported by platform.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformTpmDevicePresent in the PlatformCpuLib.c

Function : PlatformTpmDevicePresent

File: PlatformCpuLib.c
Description:
Set if Tpm device is present.
Input:
IN VOID *Handle
IN BOOLEAN Supported
Output:
VOID


PlatformCpuLib.h

Description:
Platform CPU library.
Built on 11:00:20 06/12/15


ResetVector.asm

Description:
Reset Vector. Fixup will update code to jump to EntryPoint of Startup32.asm.
Built on 11:00:20 06/12/15


Startup32.asm

Description:
Switch CPU to protected mode, INIT CAR and setup stack.

The following functions are used in the file: Startup32.asm.

Function | Description
CPU_START | Switch CPU to protected mode, INIT CAR and setup stack.
FindMicrocode | This routine searches the file volume for a microcode update and returns the address if found.

Built on 11:00:20 06/12/15


CPU_START in the Startup32.asm

Function : CPU_START

File: Startup32.asm
Segment: STARTUP_SEG
Description:
Switch CPU to protected mode, INIT CAR and setup stack.
Input:
None
Output:
None


FindMicrocode in the Startup32.asm

Function : FindMicrocode

File: Startup32.asm
Segment: STARTUP_SEG
Description:
This routine searches the file volume for a microcode update
and returns the address if found.
Input:
None
Output:
eax = Pointer to microcode. 0 if not found.
Notes:
This routine can not use stack. It can be called from rom or ram.
If called from rom, a hard coded stack must be exist in rom.


TxtSetup.c

Description:

The following functions are used in the file: TxtSetup.c.

Function | Description
TxtExitSetupEvent | This routine for calling global reset if necessary.

Built on 11:00:20 06/12/15


TxtExitSetupEvent in the TxtSetup.c

Function : TxtExitSetupEvent

File: TxtSetup.c
Description:
This routine for calling global reset if necessary.
Input:
EFI_EVENT   - Efi event.
VOID*       - Image handle.
Output:
None.


TxtSinitAcm.mak

Description:
Built on 11:00:20 06/12/15


x64CLib.c

Description:
Generic CPU library functions for the x64 architecture.

The following functions are used in the file: x64CLib.c.

Function | Description
Div64 | UINT64 Div64(IN UINT64 Dividend, IN UINTN Divisor, OUT UINTN *Remainder OPTIONAL) divides a 64-bit number, Dividend, by the Divisor, which can be up to 31-bits.
memset | VOID memset(IN VOID *pBuffer, IN UINT8 Value, IN UINTN Count) is a wrapper for memset which fills Count bytes of memory in pBuffer with Value.
Mul64 | UINT64 Mul64(IN UINT64 Value64, IN UINTN Value32) multiplies a 64-bit number by a 32-bit number and returns the 64-bit result.
Shl64 | UINT64 Shl64(IN UINT64 Value, IN UINT8 Shift) shifts the 64-bit Value left the provided number of bits, Shift.
Shr64 | UINT64 Shr64(IN UINT64 Value, IN UINT8 Shift) shifts the 64-bit Value right the provided number of bits, Shift.

The following descriptions are used in the file: x64CLib.c.

Header | Description
CPU_Functions | CPU related functions defined in the AMI library.
Math_64_Bit_Functions | Math functions involving 64-bit input parameters designed to be usable on both 32-bit and 64-bit platforms.

Built on 11:00:20 06/12/15


CPU_Functions in the x64CLib.c

General : CPU_Functions

File: x64CLib.c
Fields:

Header | Function | Description
None | CPULib_CpuID | Perform the cpuid assembly instruction.
None | CPULib_DisableInterrupt | Disable interrupts.
None | CPULib_EnableInterrupt | Enable interrupts.
None | CPULib_GetInterruptState | Get current interrupt state (enabled or disabled).
None | CPULIB_GetPageTable | Retrieve address of the page table.
None | CPULib_LoadGdt | Load GDT.
None | CPULib_LoadIdt | Load IDT.
None | CPULib_LockByteDec | Lock preceeding byte.
None | CPULib_LockByteInc | Lock following byte.
None | CPULib_Pause | Pause CPU.
None | CPULib_SaveGdt | Save GDT at provided location.
None | CPULib_SaveIdt | Save IDT at provided location.
None | DisableCacheInCR0 | Disable CPU cache using CR0.
None | EnableCacheInCR0 | Enable CPU cache using CR0.
None | EnableMachineCheck | Enable machine check exception bit in CR4.
AmiLib | GetCpuTimer | Retrieve the CPU timer's value.
None | GetCsSegment | Retrieve the code segment.
None | HltCpu | Halt the CPU.
None | WaitForever | Perform infinite loop.
None | WaitForSemaphore | Wait for semaphore to become available. then take control.
None | WaitUntilZero32 | Wait until a 32-bit memory region becomes zero.
None | WaitUntilZero8 | Wait until an 8-bit meomry region becomes zero.
None | WriteMsr | Write a value to a MSR.
None | ReadMsr | Read value from a MSR.
AmiLib | WriteCr3 | Write a value to CR3.
AmiLib | ReadCr3 | Read value from CR3.
None | ReadRtdsc | Retrieve the time stamp counter.

Description:
CPU related functions defined in the AMI library.
Notes:
Header details which header file contains the function prototype for
the above functions.  Append .h to the given name.


Div64 in the x64CLib.c

Function : Div64

File: x64CLib.c
Description:
UINT64 Div64(IN UINT64 Dividend, IN UINTN Divisor,
OUT UINTN *Remainder OPTIONAL) divides a 64-bit number, Dividend, by the
Divisor, which can be up to 31-bits.
Input:
IN UINT64 Dividend
The 64-bit number to be divided.

IN UINT Divisor
The number to divide Dividend by; may not exceed 31-bits in size.

OUT UINTN *Remainder OPTIONAL
The remainder of the division.  Provide NULL if undesired; otherwise user
is responsible for handling the necessary memory resources.
Output:
UINT64 result of dividing Dividend by Divisor.
Modified:
Notes:
Referrals:


Math_64_Bit_Functions in the x64CLib.c

General : Math_64_Bit_Functions

File: x64CLib.c
Fields:

Header | Function | Description
AmiLib | Shr64 | Shift 64-bit value right.
AmiLib | Shl64 | Shift 64-bit value left.
AmiLib | Div64 | Divide 64-bit value by a 31-bit value.
AmiLib | Mul64 | Multiply 64-bit value by a 32-bit value.
AmiLib | GetPowerOfTwo64 | Determine the highest set bit in a 64-bit value.

Description:
Math functions involving 64-bit input parameters designed to be usable on
both 32-bit and 64-bit platforms.
Notes:
Header details which header file contains the function prototype for
the above functions.  Append .h to the given name.


memset in the x64CLib.c

Function : memset

File: x64CLib.c
Description:
VOID memset(IN VOID *pBuffer, IN UINT8 Value, IN UINTN Count) is a
wrapper for memset which fills Count bytes of memory in pBuffer with
Value.
Input:
IN VOID *pBuffer
The starting location in memory where to begin filling.

IN UINT8 Value
The value to fill memory with starting at pBuffer.

IN UINTN Count
The number of bytes to fill with Value.
Output:
VOID.
Modified:
Notes:
Referrals:
memset


Mul64 in the x64CLib.c

Function : Mul64

File: x64CLib.c
Description:
UINT64 Mul64(IN UINT64 Value64, IN UINTN Value32) multiplies a 64-bit
number by a 32-bit number and returns the 64-bit result.
Input:
IN UINTN64 Value64
The 64-bit number to multiply by.

IN UINTN Value32
The 32-bit number to multiply by.
Output:
UINT64 result of multiplying Value64 by Value32.
Modified:
Notes:
Referrals:


Shl64 in the x64CLib.c

Function : Shl64

File: x64CLib.c
Description:
UINT64 Shl64(IN UINT64 Value, IN UINT8 Shift) shifts the 64-bit Value
left the provided number of bits, Shift.
Input:
IN UINT64 Value
The value to be shifted left.

IN UINT8 Shift
The number of bits to shift.
Output:
UINT64 Value shifted left Shift number of bits.
Modified:
Notes:
Referrals:


Shr64 in the x64CLib.c

Function : Shr64

File: x64CLib.c
Description:
UINT64 Shr64(IN UINT64 Value, IN UINT8 Shift) shifts the 64-bit Value
right the provided number of bits, Shift.
Input:
IN UINT64 Value
The value to be shifted.

IN UINT8 Shift
The number of bits to shift right.
Output:
UINT64 Value shifted right Shift number of bits.
Modified:
Notes:
Referrals:


x64rules.mak

Description:
Defines x64-specific build rules.
This file is included into the template makefile rules.mak
Built on 11:00:20 06/12/15


Function by Segment

By Segment

The following is a list of the segments.
For a list in alphabetical order, see In Alphabetical Order.
For a list by file name, see By File Name.

  • STARTUP_SEG
Built on 11:00:20 06/12/15


STARTUP_SEG

The following functions are used in the segment: STARTUP_SEG.

Function | Description
CPU_START | Switch CPU to protected mode, INIT CAR and setup stack.
FindMicrocode | This routine searches the file volume for a microcode update and returns the address if found.

Built on 11:00:20 06/12/15


Functions in Alphabetical Order

In Alphabetical Order

The following topics provide a list in alphabetical order.
For a list by file name, see By File Name.
For a list by segment, see By Segment.

  • A
  • C
  • D
  • E
  • F
  • G
  • I
  • L
  • M
  • N
  • O
  • P
  • R
  • S
  • T
  • U
  • W
Built on 11:00:18 06/12/15


Functions in Alphabetical Order

A

Function | Description
AddLocalApicCoreEntries | Create Private Ami Cpu Info2 Acpi Data.
AddStrGetTok | Add string to buffer and return token value.
AmiCpuMpServiceCallback | Cpu Dxe Entrypoint.
AmiCpuS3PeiEntry | PEI Entry Point for Intel TXT Driver.
AmiTxtDxeEntry | DXE Entry Point for Intel TXT Driver.
AmiTxtHook | Initialize CPU strings.
AmiTxtPeiEntry | PEI Entry Point for Intel TXT Driver.
AutodetectFamily | Return family type from Brand String.

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

C

Function | Description
CalculateTimerPeriod | Calculate CPU time period.
CallDxeCpuPolicyInitList | Get the microcode patch.
CallPeiCpuPolicyInitList | This function orderly calls functions in PeiCpuPolicyInitListTable for OEM or Custom to override PEI_CPU_PLATFORM_POLICY_PPI.
CheckAddressRange | Check address range to avoid TSEG area.
CollectCacheInfo | Store cache information in variables.
CollectOcConfig | Collect Overclocking Config data from MSR 0x150.
CopyToFlashBuffer | Copy data to the buffer. When the buffer is full, write to the flash, and continues to copy data.
CountBlks | Count blocks taken by microcode in FFS.
CPU_GetSaveState | This routine is the generic routine used to copy the CPU specific SMM save state to standard save state.
CPU_GetSaveStateId30006 | This routines saves the necessary values from Revison 3006 SMM save state area.
CPU_IsSmrrSupported | Determine if CPU supports Smrr.
CPU_RestoreDefaultSaveState | This routines copies the necessary values from standard SMM save state area to version 0x30003 SMM save state area.
CPU_RestoreSaveState | This routine is the generic routine used to copy the standard SMM save state from CPU specific save state. This routine should make sure it does not change read only areas
CPU_RestoreSaveStateId30006 | This routines restores the necessary values from Revision 3006 SMM save state area.
CPU_START | Switch CPU to protected mode, INIT CAR and setup stack.
CpuDxeMiscFuncs |
CPULib_FindMicrocode | Find the microcode address for the CPU calling this.
CPULib_FindMicrocodeInFv | Find the microcode address for the CPU calling this in specific firmware volume.
CPULIB_GetCstateLatency | Get C-state latency.
CPULIB_GetCstatePower | Get C-state power.
CPULib_GetMicrocodeVer | Get Microcode Version
CPULib_IsFeatureControlLocked | Check to see if the MSR_IA32_FEATURE_CONTROL is locked.
CPULIB_IsLocalX2ApicEnabled | Get C-state latency.
CPULib_IsSmrrEnabled | Determine if Smrr is enabled.
CPULib_IsSmxEnabled | Determine if Smx is enabled.
CPULib_IsVmxEnabled | Determine if Vmx is enabled.
CpuLib_SaveCpuState | Save CPU state in SMM.
CPULib_SmmReadSaveState | Read SMM Save state from combination of SMM save state and copy. If frame copy exists, use its data instead from actual save state. A different function gets information for floating point and XMM.
CpuLib_SmmReadSaveStateFxSave | Read SMM Save state for floating point and XMM.
CpuLib_SmmRestoreCpuState | Restore CPU state in SMM.
CPULib_SmmWriteSaveState | Write SMM Save state from combination of SMM save state and copy. If frame copy exists, use its data instead from actual save state. A different function gets information for floating point and XMM.
CpuLib_SmmWriteSaveStateFxSave | Write SMM Save state for floating point and XMM.
CpuPeiBeforeMemEntry | CPU PEI functions before memory ready
CPUPEIDBG_Initialize | This eLink function is used to initialize CPU for PEI debugger support
CpuPeiEntry | AMI CPU PEI driver entry
CpuPeiIntelXtuDataInit | Interl XTU utility data initialize in PEI phase
CpuPeiMiscFuncs |
CpuPeiPolicyNotify | CPU PEI pollicy PPI notify function
CpuPeiPolicyOverWrite | This function over writes the CPU PEI RC policy
CpuPeiXtuInitBeforeMem | CPU XTU init code in PEI phase
CpuPllOverVoltageProgress | CPU pll over voltage initialize code in DXE phase
CPUProgramPAMRegisters | Program 0xc0000 - 0xfffff regions to Lock/Unlock.
CpuSetBootRatio | Adjust CPU boot ratio base on setup item
CpuSmbios | Create CPU SMBIOS Tables. Installs notification on SMBIOS handlers.
CpuSpSmiInit | Initializes CPU specific SMM Drivers.
CrcSecPlatformInformationPpi | Install SecPlatformInformation PPI that Intel Ivybridge CPU reference code needs. (conveys state information out of the SEC phase into PEI)
CreateAcpiData | Create Private Ami Cpu Info2 Acpi Data.
CreateCacheData | Get Cache information.
CreateCpuHobWithDefaults | Create CPU Hob and fill in default data.
CreateCpuSmbiosTables | Create CPU SMBIOS Tables 4 and 7.
CreatePrivateAmiCpuInfo1 | Create Private Ami Cpu Info1 structure.
CreatePrivateAmiCpuInfo2 | Create Private Ami Cpu Info2 structure.
CreateSmbiosTable4 | Create SMBIOS Table 4
CreateSmbiosTable7 | Create SMBIOS Table 7

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

D

Function | Description
DebuggerGetAptioInterruptHandlerHalt |
DebuggerIsItPEIDebugIRQHandlerToHookup |
DebuggerSetupPEIDebuggerExceptionHandlers |
Div64 | UINT64 Div64(IN UINT64 Dividend, IN UINTN Divisor, OUT UINTN *Remainder OPTIONAL) divides a 64-bit number, Dividend, by the Divisor, which can be up to 31-bits.
DxeInitializeCpu | Cpu Dxe Entrypoint.
DxeInitPlatformCpuLib | Initialize DXE Init Platform Cpu Lib.
DxePlatformCpuSaveSupportedData | This functions saves the CPU supported data.

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

E

Function | Description
EnablePLLOverVoltage | Enable PLL over voltage for CPU
EstablishStringBuffer | Initialize string buffer variables
EventUpdateSinitAcmToMemory | This routine copy SINIT ACM to SINIT meory for BIOS-Base SINI AC Module implementation.

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

F

Function | Description
FillAcpiData | Fill ACPI Data structure
FillBufferAndFlush | Fill the rest of the buffer of a size of the flash block, then update the flash.
FillCacheData | Init global cache data varilable
FillCacheDesc | Update cache information with CPUID 4.
FillMicrocodeBlkMap | Update gMcodeBlkMap with data for microcode.
FillPrivateAmiCpuInfo2 | Fill CPU information in Private Ami Cpu Info structure.
FillXtuGaciData | Fill CPU information for xtu 3.0 specification
FindMicrocode | This routine searches the file volume for a microcode update and returns the address if found.
FindMicrocodeFfs | Find Micorode FFS in FV.
FindMicrocodeOfStepping | Search the microcode in the firmware for the cpu signature or earlier steping.
FindPtrToPrivCpuInfoCore | Pointer to internal Core information.
FindPtrToPrivCpuInfoPkg | Pointer to internal Package information.
FindPtrToPrivCpuInfoThread | Pointer to internal Core information.
FlushBufferToFlash | Helper function to write the buffer to the flash and reset the buffer.
FwhFvbErase | This function erases a block of NVRAM.
FwhWrite | This function writes a block of NVRAM.

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

G

Function | Description
GetAcpiInfo | Get Cpu ACPI information.
GetApicInfo | Get Apic Number and Version
GetBoardSocketNumber | Get socket number from Apic ID.
GetBoardSocketNumber | Get socket number from Apic ID.
GetBufferSizeUsed | Get amount storage space used by strings.
GetCacheSharedThreads | Return number of shared threads for a Information.
GetCoreCacheDescr | Get the Core Cache Information
GetCpuFamily | Get the cpu family from signature.
GetCpuInfo | Protocol function to get Cpu Info.
GetCpuModel | Get the cpu model from signature.
GetCpuPkgCoreThrdByNum | Get CPU Package/Core/Thread by CPU Number. Number sequencial to APIC ID.
GetCpuPlatformId | Get the cpu platform Id.
GetCpuSignature | Get the cpu signature.
GetFIVRConfig | Get the FIVR Configuration information by reading/writing MSR 0x150
GetInstalledMicrocodeRevision | Get the installed microcode revision on the cpu.
GetMaxSpeedFromBrandString | Get the max speed from the brand string.
GetMaxSpeedFromBrandString | Get the max speed from the brand string.
GetNumCoresThreads | Get the number of Cores
GetNumPackages | Get the number of packages populated and sockets.
GetNumThreads | Get the number of Threads
GetOcCapability | Get the overclocking capabilities for a given CPU Domain by reading/writing MSR 0x150
GetPackageCacheDescr | Get the package Cache Information
GetPlatformCpuBootRatio | Get the platform policy of for boot ratio.
GetPlatformCpuGroup | Get the CPU group for the platform policy.
GetPlatformCpuLimitCpuidEnable | Get the platform policy of limiting Cpuid.
GetPlatformCpuVtEnable | Get the platform policy of enable VT.
GetPlatformCpux2ApicEnable | Get the platform policy of enable x2Apic.
GetPlatformCpuXdEnable | Get the platform policy of enable XD.
GetPlatformNumCores | Get the maximum number of cores supported by processor.
GetPtrToPrivateAmiCpuInfo2Entry | Get pointer to APIC/Cpu Num
GetSbsp | Get SBSP
GetSmrrBaseMsr | Return the Smrr Base Msr
GetSVIDConfig | Get the SVID Configuration information by reading/writing MSR 0x150
GetTxtInfo | Get Txt information
GetVoltFreq | Gets the Voltage and Frequency information for a given CPU domain by reading/writing MSR 0x150
GlobalDataInitialize | Cpu Dxe Entrypoint.

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

I

Function | Description
InitAmiTxtInfo | Initialize Txt information
InitAmiTxtInfoStrings | Initialize CPU strings.
InitCpuInfo | Initialize CPU strings.
InitializeFlashBuffer | Initialize the flash buffer before using.
InitializeMicrocodeSmm | This function registers the INT15 D042 SW SMI handler This is the driver entry pOoint.
InitLongMode | VOID InitLongMode(IN EFI_PEI_SERVICES **PeiServices, IN VOID *Function, IN VOID *Parameter1, IN VOID *Parameter2) initializes memory page mapping, enables long mode and jumps to a provided function.
InitLongModeExt | VOID InitLongMode(IN EFI_PEI_SERVICES **PeiServices, IN VOID *Function, IN VOID *Parameter1, IN VOID *Parameter2) initializes memory page mapping, enables long mode and jumps to a provided function.
InitMcodeBlkMap | Initialize gMcodeBlkMap and related globals for all microcode FFS.
InitMicrocodeVariables | Initialize global variables used by the driver.
InitMtrrPolicy1 | Config system cache.
InitMtrrPolicy2 | Config system cache.
InitOcMailbox | Initialize Overclocking Config data.
InSmmFunction | This function is called from the InitSmmHandler if driver is in SMM.
InSmmFunction | Called from InstallSmiHandler
IntelXtuFillCpuDataCallBack | Callback function for Intel XTU data init
InterruptHandlerHalt | Default CPU Exception. Halts CPU.
isBCLKRatioSuuported | Determine if CPU supports BCLK coarse ratio support.
IsCore0 | Determine if CPU thread is CPU Core 0 executing.
IsCxInterruptFilteringSupported | Determine if C-state interrupting state supported.
IsEnergyPerfBiasSupported | Determine if Energy Performance Bias supported.
isFullUnlockCpuSuuported | Determine if CPU supports Full unlock.
IsHt0 | Determine if CPU thread is logical CPU 0 executing.
IsHtEnabled | Determine if CPU is HT.
isLimitCpuidSupported | Determine if CPU supports limiting CpuId to 3.
isMachineCheckSupported | Determine if CPU supports machine check.
IsPowerCycle | If Power Cycle is or not.
IsSmxSupported | Determine if CPU supports VT extensions Smx.
IsSwSmiTrigger | This routine checks to see if the cpu caused an software smi.
isTurboModeSupported | Determine if CPU supports Turbo mode.
IsValidChecksum | Validate the checksum.
IsValidHeader | Check if the header is valid.
IsVmxSupported | Determine if CPU supports VT extensions Vmx.
IsX64Supported | Determine if CPU supports X64.
isXDSupported | Determine if CPU supports Execute Disable.
isXECoreRatioLimitSupported | Determine if CPU supports Programmable Core Ratio Limit for the Turbo mode.
isXETdcTdpLimitSupported | Determine if CPU supports Programmable TDC/TDP Limit for the Turbo mode.

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

L

Function | Description
LoadMicrocode | Load the microcode onto the CPU.
LoadMicrocodeEachCpu | Load the microcode on each CPU.
LocateCpuInfoProt | Callback on AMI CPU INFO protocol. Then call to init strings.
LtDefineTpmNvramSpace | This routine for define the TPM Nvram space.
LtSendTpmCommand | Sends a command to the TPM

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

M

Function | Description
mBODY_CALL_PROC_FAR | Call far macro.
mBODY_CALL_PROC_NEAR | Call near macro.
mBODY_ID_AND_TBL_ENTRY_FAR |
mBODY_ID_AND_TBL_ENTRY_NEAR | Start ID Table Entry macro.
mBODY_JMP_PROC_FAR | jmp far macro with return label to jump back to.
mBODY_JMP_PROC_NEAR | Jump Near Macro. Provide a return label to jump to.
mBODY_JMP_PROC_NEAR32 | Jump near 32-bit macro. Provide a return label to jump to.
mBODY_TBL_ENTRY_FAR |
mBODY_TBL_ENTRY_NEAR | Start table enty macro.
memcpy | VOID memcpy(OUT VOID *pDestination, IN VOID *pSource, IN UINTN Count) is a wrapper for memcpy, which copies Count bytes of memory from Source to Destination.
memset | VOID memset(IN VOID *pBuffer, IN UINT8 Value, IN UINTN Count) is a wrapper for memset which fills Count bytes of memory in pBuffer with Value.
mEND_PROC_FAR | Ret procedure macro. Last in a group.
mEND_PROC_NEAR | End near procedure macro. Last in a group.
mEND_PROC_WITH_JMP_FAR | End procedure macro. Last in agroup.
mEND_PROC_WITH_JMP_NEAR | End of procedure and jump near macro. Last procedure in a group.
mEND_PROC_WITH_JMP_NEAR32 | Jump Near 32-bit macro. Last macro in a group.
mEND_TBL |
mEXTERN_FAR | External Far macro
mEXTERN_NEAR | External Near macro
mEXTERN_NEAR32 | External Near 32 Macro
MicrocodeUpdateCallback | This notification function is called when an SMM Mode is invoked through SMI. This may happen during RT, so it must be RT safe. Interrupt 15h, function D042h is processed here.
mSTART_PROC_FAR | Far procedure macro.
mSTART_PROC_NEAR | Start Near procedure macro.
mSTART_PROC_NEAR32 | Start Near 32-bit procedure macro.
mSTART_TBL | Start table macro.
Mul64 | UINT64 Mul64(IN UINT64 Value64, IN UINTN Value32) multiplies a 64-bit number by a 32-bit number and returns the 64-bit result.

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

N

Function | Description
NotifyAtPeiEnd | According to resource descriptor HOBs to config system cache.
NotInSmmFunction | If Not In Smm Function
NumberOfCpuSocketsPopulated | Returns number of CPU sockets are populated.
NumberOfPStatesSupport | Provide variable data which constains number of P states support
NumCpuCores | Returns number of CPU Cores
NumLogicalCpus | Get number of logical CPUs.
NumOfOne | Count how many of ones in the binary value.
NumSupportedCpuCores | Get number of supported Cpu Cores per package.
NumSupportedThreadsPerCore | Get number of supported threads per core.

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

O

Function | Description
OverlockingConfigUpdate | Update Overclocking Config data.
OverrideNonTurboRatio | Override CPU NonTurbo Ratio Maximum value

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

P

Function | Description
PchPmTimerStall | Delay N*Usec
PEGDMIRatio | Modify PEG/DMI Ratio for CPU
PeiInitPlatformCpuLib | Init platform policy in PEI.
PlatformCpuAesSupport | Set if supported by platform.
PlatformCpuC10Support | Set if supported by platform.
PlatformCpuC3Support | Set if supported by platform.
PlatformCpuC6Support | Set if supported by platform.
PlatformCpuC7Support | Set if supported by platform.
PlatformCpuC8Support | Set if supported by platform.
PlatformCpuC9Support | Set if supported by platform.
PlatformCpuCtdpSupport | Set if supported by platform.
PlatformCpuCurrentLimitSupport | Set if supported by platform.
PlatformCpuEistSupport | Set if supported by platform.
PlatformCpuHtSupport | Set if supported by platform.
PlatformCpuLimitCpuidSupport | Set if supported by platform.
PlatformCpuLocalx2ApicSupport | Set if supported by platform.
PlatformCpuMismatch | Report is populated CPU combination is not supported.
PlatformCpuMultiCoreSupport | Set if supported by platform.
PlatformCpuMultiSocketPopulated | Set if supported by platform.
PlatformCpuMultiSocketSupport | Set if supported by platform.
PlatformCpuPkgCStateDemotionSupport | Set if supported by platform. Available only in 4th Generation Intelr CoreT processors with signature greater than 000306C1h.
PlatformCpuPwrLimitConfigSupport | Set if supported by platform.
PlatformCpuSmxSupport | Set if supported by platform.
PlatformCpuSocketSetPopulated | Set sockets populated.
PlatformCpuTurboModeSupport | Set if supported by platform.
PlatformCpuVtSupport | Set if supported by platform.
PlatformCpuXdSupport | Set if supported by platform.
PlatformCpuXeCoreRatioLimitSupport | Set if supported by platform.
PlatformTpmDevicePresent | Set if Tpm device is present.
PLLFilterFunction | Filter PLL setting High(3.2GHz) or lower(1.6GHz)
PollMailboxReady | Return OC Mailbox is ready or busy.
PrepareToBoot | Handler executed before OS.
PresenceTest | Execute the presence test function for int 15h.

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Functions in Alphabetical Order

R

Function | Description
ReadMSR150 | Return Msr0x150 data
ReadUpdateData | Read microcode using int15h.
ReadWriteMsr | This function writes the CPU MSR with the value provided.
ReinstallSecPpis | Reinstall PPIs from stack because stack will be lost when cache-as-ram is turned off.
RemoveStringBuffer | Remove String Buffer structure.
ReportBistStatusCodes | Report the BIST Status Code.
RestoreCpuMsr | This function restores the CPU MSRs during S3 resume.
RestoreMsrOnCpu | This function restores the CPU MSRs during S3 resume.

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

S

Function | Description
SaveCpuMsr | This function saves the CPU MSRs for S3 resume usage.
SaveMEFWVersion | CPU pll over voltage initialize code in DXE phase
SetupCache | According to resource descriptor HOBs to config system cache.
Shl64 | UINT64 Shl64(IN UINT64 Value, IN UINT8 Shift) shifts the 64-bit Value left the provided number of bits, Shift.
Shr64 | UINT64 Shr64(IN UINT64 Value, IN UINT8 Shift) shifts the 64-bit Value right the provided number of bits, Shift.
SizeOfPrivateAmiCpuInfo2 | Size of Private Ami Cpu Info 2 structure to be allocated.
SMI_UC_DWORD_REGS | Write microcode to flash and load microcode into each CPU.
SmmBaseChangeCopy | This is SMM code copied to 3000:8000 to set the SmmBase and IED.
SmmBaseChangeOnCpu | Execute on each CPU to change its own base.
SmmGetBaseSaveBufferSize | Return about of memory required for the SMM handler change.
SmmRemoveDefaultHandler | Remove default SMM Handler from memory and restore original data.
SmmSetupDefaultHandler | Save original memory, and copy SMM default handler.

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

T

Function | Description
TxtExitSetupEvent | This routine for calling global reset if necessary.
TxtTpmNvRamDefine |

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

U

Function | Description
UpdateControl | Execute the update control for int 15h.
UpdateOrCreateCpuHob | Finds or Create Cpu Hob and initialize it.

Built on 11:00:18 06/12/15


Functions in Alphabetical Order

W

Function | Description
WriteValueToFlashBuffer | Fill part of the buffer with a value. When the buffer is full, write to the flash, and continue to update the beginning of the buffer with a value.

Built on 11:00:18 06/12/15


General Information

Header | Description
CPU_Functions | CPU related functions defined in the AMI library.
Math_64_Bit_Functions | Math functions involving 64-bit input parameters designed to be usable on both 32-bit and 64-bit platforms.

Built on 11:00:20 06/12/15


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