1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
|
//*************************************************************************
//*************************************************************************
//** **
//** (C)Copyright 1985-2013, American Megatrends, Inc. **
//** **
//** All Rights Reserved. **
//** **
//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
//** **
//** Phone: (770)-246-8600 **
//** **
//*************************************************************************
//*************************************************************************
//*************************************************************************
// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB.ASL 7 7/15/13 3:19a Scottyang $
//
// $Revision: 7 $
//
// $Date: 7/15/13 3:19a $
//*************************************************************************
// Revision History
// ----------------
// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB.ASL $
//
// 7 7/15/13 3:19a Scottyang
// [TAG] EIP129089
// [Category] Improvement
// [Description] Update PCH RC 1.6.1.
// [Files] SBDxe.c, SB.asl, ..\ReferenceCode\Chipset\LynxPoint\*.*
//
// 6 4/24/13 6:00a Scottyang
// [TAG] EIP121262
// [Category] Bug Fix
// [Severity] Normal
// [Symptom] WOL BSOD
// [RootCause] When resume to OS hardware signal not ready. That made a
// dead loop in OS.
// [Solution] Remove while loop and add sychnorized the object in asl
// code.
// [Files] SB.asl, PchPcie.asl
//
// 5 4/08/13 2:51a Wesleychen
// [TAG] EIP118045
// [Category] Improvement
// [Description] Creat tokens to support Power Button Notify
// for misc events.
// [Files] SB.SDL; SB.ASL
//
// 4 1/11/13 5:10a Scottyang
// [TAG] None
// [Category] Improvement
// [Description] Remove EIP105442 temp solution.
// [Files] SB.ASL, Pch.asl
//
// 3 11/26/12 12:39a Scottyang
// [TAG] EIP105442
// [Category] Bug Fix
// [Severity] Normal
// [Symptom] After S3 resum cannot use FPT win64
// [RootCause] The SPI HSFS register "Access Error Log" bit has been
// set.
// [Solution] Clear "Access Error Log" bit after resume.
// [Files] SB.ASL, Pch.asl
//
// 2 8/13/12 10:24a Victortu
// [TAG] None
// [Category] Improvement
// [Description] Update definition in ASL code for building when
// disabled PCI objects.
// [Files] SB.ASL
//
// 1 2/08/12 8:24a Yurenlai
// Intel Lynx Point/SB eChipset initially releases.
//
//*************************************************************************
//<AMI_FHDR_START>
//
// Name: SB.asl
//
// Description: The ASL file is for South Bridge specific function.
//
//<AMI_FHDR_END>
//*************************************************************************
Scope(\_SB.PCI0.LPCB)
{
OperationRegion(CPSB, SystemMemory, 0xC0000000, 16) // Relocatable
Field(CPSB, AnyAcc, NoLock, Preserve) //Field
{
RTCX, 1,
SBB0, 7,
SBB1, 8,
SBB2, 8,
SBB3, 8,
SBB4, 8,
SBB5, 8,
SBB6, 8,
SBB7, 8,
SBB8, 8,
SBB9, 8,
SBBA, 8,
SBBB, 8,
SBBC, 8,
SBBD, 8,
SBBE, 8,
SBBF, 8,
}
/*
;<AMI_PHDR_START>
;------------------------------------------------------------------------
;
; Procedure: SPTS
; Description: METHOD IS CALLED BY OS PRIOR TO ENTER ANY SLEEP STATE
; Input: Arg0 = Arg0 = Sleep state System about to enter
; Output: Nothing
;
;-------------------------------------------------------------------------
;<AMI_PHDR_END>
*/
Method (SPTS, 1) {
Store(One, SLPX) // Clear SLP_SMI Status
Store(One, SLPE) // Enable SLP_SMI
#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1)
Store(Zero, \_SB.PCI0.RP01.RPAV)
#endif
#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1)
Store(Zero, \_SB.PCI0.RP02.RPAV)
#endif
#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1)
Store(Zero, \_SB.PCI0.RP03.RPAV)
#endif
#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1)
Store(Zero, \_SB.PCI0.RP04.RPAV)
#endif
#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1)
Store(Zero, \_SB.PCI0.RP05.RPAV)
#endif
#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1)
Store(Zero, \_SB.PCI0.RP06.RPAV)
#endif
#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1)
Store(Zero, \_SB.PCI0.RP07.RPAV)
#endif
#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1)
Store(Zero, \_SB.PCI0.RP08.RPAV)
#endif
}
/*
;<AMI_PHDR_START>
;------------------------------------------------------------------------
;
; Procedure: SWAK
; Description: METHOD CALLED ON WAKE UP FROM ANY SLEEP STATE
; Input: Arg0 = Sleep state System is resuming from
; Output: Nothing
;
;------------------------------------------------------------------------
;<AMI_PHDR_END>
*/
Method (SWAK, 1) {
Store(Zero, SLPE) // Disable SLP_SMI
#if defined ASL_SX_NOTIFY_PWRB && ASL_SX_NOTIFY_PWRB == 1
If (RTCS) {}
Else {Notify(\_SB.PWRB, 0x02)}
#endif
}
OperationRegion (SMIE, SystemIO, PMBS, 4)
Field (SMIE, ByteAcc,NoLock,Preserve) {
,10,
RTCS, 1,
, 3,
PEXS, 1,
WAKS, 1,
, 8,
PWBT, 1,
, 7,
}
OperationRegion (SLPR, SystemIO, SMCR, 8)
Field (SLPR, ByteAcc,NoLock,Preserve) {
, 4,
SLPE,1,
,31,
SLPX,1,
,27,
}
}//Scope(\_SB.PCI0.LPCB)
#if defined (ASL_RC_PORT_0) && (ASL_RC_PORT_0==1)
Scope(\_SB.PCI0.RP01)
{
//
// Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes.
//
Method(_INI)
{
Store (LTR1, LTRE)
Store (PML1, LMSL)
Store (PNL1, LNSL)
Store (OBF1, OBFF)
}
Method(_PRW, 0) { Return(GPRW(0x09, 4)) }
}//Scope(\_SB.PCI0.RP01)
#endif
#if defined (ASL_RC_PORT_1) && (ASL_RC_PORT_1==1)
Scope(\_SB.PCI0.RP02)
{
//
// Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes.
//
Method(_INI)
{
Store (LTR2, LTRE)
Store (PML2, LMSL)
Store (PNL2, LNSL)
Store (OBF2, OBFF)
}
Method(_PRW, 0) { Return(GPRW(0x09, 4)) }
}//Scope(\_SB.PCI0.RP02)
#endif
#if defined (ASL_RC_PORT_2) && (ASL_RC_PORT_2==1)
Scope(\_SB.PCI0.RP03)
{
//
// Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes.
//
Method(_INI)
{
Store (LTR3, LTRE)
Store (PML3, LMSL)
Store (PNL3, LNSL)
Store (OBF3, OBFF)
}
Method(_PRW, 0) { Return(GPRW(0x09, 4)) }
}//Scope(\_SB.PCI0.RP03)
#endif
#if defined (ASL_RC_PORT_3) && (ASL_RC_PORT_3==1)
Scope(\_SB.PCI0.RP04)
{
//
// Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes.
//
Method(_INI)
{
Store (LTR4, LTRE)
Store (PML4, LMSL)
Store (PNL4, LNSL)
Store (OBF4, OBFF)
}
Method(_PRW, 0) { Return(GPRW(0x09, 4)) }
}//Scope(\_SB.PCI0.RP04)
#endif
#if defined (ASL_RC_PORT_4) && (ASL_RC_PORT_4==1)
Scope(\_SB.PCI0.RP05)
{
//
// Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes.
//
Method(_INI)
{
Store (LTR5, LTRE)
Store (PML5, LMSL)
Store (PNL5, LNSL)
Store (OBF5, OBFF)
}
Method(_PRW, 0) { Return(GPRW(0x09, 4)) }
}//Scope(\_SB.PCI0.RP05)
#endif
#if defined (ASL_RC_PORT_5) && (ASL_RC_PORT_5==1)
Scope(\_SB.PCI0.RP06)
{
//
// Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes.
//
Method(_INI)
{
Store (LTR6, LTRE)
Store (PML6, LMSL)
Store (PNL6, LNSL)
Store (OBF6, OBFF)
}
Method(_PRW, 0) { Return(GPRW(0x09, 4)) }
}//Scope(\_SB.PCI0.RP06)
#endif
#if defined (ASL_RC_PORT_6) && (ASL_RC_PORT_6==1)
Scope(\_SB.PCI0.RP07)
{
//
// Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes.
//
Method(_INI)
{
Store (LTR7, LTRE)
Store (PML7, LMSL)
Store (PNL7, LNSL)
Store (OBF7, OBFF)
}
Method(_PRW, 0) { Return(GPRW(0x09, 4)) }
}//Scope(\_SB.PCI0.RP07)
#endif
#if defined (ASL_RC_PORT_7) && (ASL_RC_PORT_7==1)
Scope(\_SB.PCI0.RP08)
{
//
// Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes.
//
Method(_INI)
{
Store (LTR8, LTRE)
Store (PML8, LMSL)
Store (PNL8, LNSL)
Store (OBF8, OBFF)
}
Method(_PRW, 0) { Return(GPRW(0x09, 4)) }
}//Scope(\_SB.PCI0.RP08)
#endif
//*************************************************************************
//*************************************************************************
//** **
//** (C)Copyright 1985-2013, American Megatrends, Inc. **
//** **
//** All Rights Reserved. **
//** **
//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
//** **
//** Phone: (770)-246-8600 **
//** **
//*************************************************************************
//*************************************************************************
|
