summaryrefslogtreecommitdiff
path: root/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Pcie.asl
blob: d560c2c483f1011075a1da968042a6f96e636c98 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
/**************************************************************************;
;*                                                                        *;
;*    Intel Confidential                                                  *;
;*                                                                        *;
;*    Intel Corporation - ACPI Reference Code for the Sandy Bridge        *;
;*    Family of Customer Reference Boards.                                *;
;*                                                                        *;
;*                                                                        *;
;*    Copyright (c)  1999 - 2013 Intel Corporation. All rights reserved   *;
;*    This software and associated documentation (if any) is furnished    *;
;*    under a license and may only be used or copied in accordance        *;
;*    with the terms of the license. Except as permitted by such          *;
;*    license, no part of this software or documentation may be           *;
;*    reproduced, stored in a retrieval system, or transmitted in any     *;
;*    form or by any means without the express written consent of         *;
;*    Intel Corporation.                                                  *;
;*                                                                        *;
;*                                                                        *;
;**************************************************************************/
/*++
  This file contains a 'Sample Driver' and is licensed as such  
  under the terms of your license agreement with Intel or your  
  vendor.  This file may be modified by the user, subject to    
  the additional terms of the license agreement                 
--*/

    Name(WKEN, 0)

    Method(_S0W, 0)
    { // PMEs can be generated from D3hot
        Return(3) //For ULT
    } // End _S0W

    Method(_DSW, 3)
    {
      If(Arg1)
      { // Entering Sx, need to disable WAKE# from generating runtime PME
        Store(0, WKEN)
      } Else {  // Staying in S0
        If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake
        { // Set PME
          Store(1, WKEN)
        } Else { // Disable runtime PME, either because staying in D0 or disabling wake 
          Store(0, WKEN)
        }
      }
    } // End _DSW
    
    // Define a power resource for PCIe RP D0-D3hot
    PowerResource(PXP, 0, 0)
    {
      Method(_STA, 0)
      {
        if(LAND(LEqual(\_SB.RDGP(PWRG),PONP), LEqual(\_SB.RDGP(RSTG),RONP))){
          Return (1)
        } Else {
          Return (0)
        }
      }
      Method(_ON) // Turn on core power to PCIe Slot
      {

        // Power ON for Slot
        // Dont enable power for NGFF because NGFF only has AUX power
        If(LNot(NGFF)) {
          \_SB.WTGP(PWRG,PONP)
          Sleep(PEP0)     // Sleep for programmable delay
        }

        // Enable PCIe Src Clock
        While(LEqual(PMFS,1)){ // PMC message serviced?
          Stall(10)
        }
        Store(Or(ShiftLeft(SCLK, 24), ShiftLeft(SCLK, 16)), Local1)  // Set Bit and Mask
        Or(Local1, 4, Local1)  // OCKEN command
        Store(Local1, \CKEN)   // Enable Source Clock
        While(LEqual(PMFS,1)){ // PMC message serviced?
          Stall(10)
        }

        \_SB.WTGP(RSTG,RONP) // De-Assert Reset Pin
        Store(1, L23R) // Set L23_Rdy to Detect Transition  (L23R2DT)
        Sleep(16)
        Store(0, Local0)
        // Wait up to 12 ms for transition to Detect
        While(L23R) {
          If(Lgreater(Local0, 4))    // Debug - Wait for 5 ms
          {
            Break
          }
          Sleep(16)
          Increment(Local0)
        }
        // Once in Detect, wait up to 124 ms for Link Active (typically happens in under 70ms)
        // Worst case per PCIe spec from Detect to Link Active is:
        // 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config (24+2+2+2+2)
        Store(0, Local0)
        While(LEqual(LASX,0)) {
          If(Lgreater(Local0, 123))
          {
            Break
          }
          Sleep(16)
          Increment(Local0)
        }
        // ADBG(Local0) // uncomment to print the timeout value for debugging
        Store(0, LEDM) // PCIEDBG.DMIL1EDM (324[3]) = 0
      }
      Method(_OFF) // Turn off core power to PCIe Slot
      {
        // Set L23_Rdy Entry Request (L23ER)
        Store(1, L23E)
        Sleep(16)
        Store(0, Local0)
        While(L23E) {
          If(Lgreater(Local0, 4)){ // Debug - Wait for 5 ms
            Break
          }
          Sleep(16)
          Increment(Local0)
        }
        Store(1, LEDM) // PCIEDBG.DMIL1EDM (324[3]) = 1

        While(LEqual(PMFS,1)){ // PMC message serviced?
          Stall(10)
        }
        // Disable PCIe Src Clock
        Store(Or(ShiftLeft(SCLK, 24), 4), Local1)  // Set Mask, OCKEN command
        Store(Local1, \CKEN)     // Disable Source Clock
        While(LEqual(PMFS,1)){ // PMC message serviced?
          Stall(10)
        }

        \_SB.WTGP(RSTG,Not(RONP)) // Assert Reset Pin
        
        If(LNot(NGFF)) { // Dont disable power for NGFF because NGFF only has AUX power
          \_SB.WTGP(PWRG,Not(PONP)) //Power OFF for Slot
        }

        Store(1, LDIS)
        Store(0, LDIS) //toggle link disable

        If(WKEN) {
          Switch(SLOT){
            Case(0x3){ // Root Port 3
              Store(1, \GS08) //Clear GPE STATUS
              Store(0, \GO08) //GPIO_OWN to ACPI Driver
            }
            Case(0x4){ // Root Port 4
              Store(1, \GS45) //Clear GPE STATUS
              Store(0, \GO45) //GPIO_OWN to ACPI Driver
            }
            Case(0x5){ // Root Port 5
              Store(1, \GS51) //Clear GPE STATUS
              Store(0, \GO51) //GPIO_OWN to ACPI Driver
            }
            Default{
            }
          }
        }
      } // End of Method_OFF
    } // End PXP

    Name(_PR0, Package(){PXP})