summaryrefslogtreecommitdiff
path: root/src/usb.c
blob: 881cae6bb6f3d75de8eeb903a27bbdcb801f3542 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
void finalize_ehci()
{
	if (pch_is_lp()) {
		if (EHCI dev is disabled) {
			RCBA32_OR(0x3a84, 5);
		}
	}
	pch_iobp_update(0xe5004001,0xffffffff,0xc0);

	if (EHCI1_DEV is disabled) {
		pci_or_config32(EHCI1_DEV, 0xdc, 0x28);
	} else {
		pci_or_config32(EHCI1_DEV, 0xdc, 0x27);
	}
	pci_or_config32(EHCI1_DEV, 0x78, 3);

	if (!pch_is_lp()) {
		if (EHCI2_DEV is disabled) {
			pci_or_config32(EHCI2_DEV, 0xdc, 0x28);
		} else {
			pci_or_config32(EHCI2_DEV, 0xdc, 0x27);
		}
		pci_or_config32(EHCI2_DEV, 0x78, 3);
	}
}

void finalize_usb()
{
	finalize_ehci();

	pch_iobp_update(0xe5004001,0xffffffff,0xc0);

	uint32_t xhcc = pci_read_config32(XHCI_DEV, 0x40);

	pci_write_config32(XHCI_DEV, 0x40, xhcc | 0x100);
	/* D3IL1E | xHCIL1E | IIL1E >= 1024 bb_cclk */
	pci_write_config8(XHCI_DEV, 0x42, ((xhcc >> 16) & 0x7f) | 0x36);
	pci_or_config16(XHCI_DEV, 0x44, 0x288);

	uint32_t orval;
	if (!pch_is_lp()) {
		orval = 0x40;
	} else {
		if (!is_wildcat_point_lp()) {
			orval = 0x40000;
		} else {
			orval = 0x40040;
		}
	}

	pci_or_config32(XHCI_DEV, 0xa0, orval);

	if (!is_wildcat_point_lp()) {
		if (!pch_is_lp()) {
			orval = 0;
		} else {
			orval = 0x1800;
		}
	} else {
		orval = xhcc;
	}

	pch_update_config32(XHCI_DEV, 0xa4, 0xffffdfff, orval);
}