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authorArthur Heymans <arthur@aheymans.xyz>2017-09-08 23:56:29 +0200
committerMartin Roth <martinroth@google.com>2017-09-16 16:23:44 +0000
commit4ea66e6b6fd04308a0864ebc21cdf814a57f83ac (patch)
treed2204297cdc93db62eac2b3a32d33e7abcb8ff57
parent18f8f622d5fa1694b1d12ce496f95fef1ea8cf58 (diff)
downloadcoreboot-4ea66e6b6fd04308a0864ebc21cdf814a57f83ac.tar.xz
device/dram/ddr2: Fix decoding tRR
Bit 7 is set on all options so only the default option in the switch statement is returned. Change-Id: I6a698ec9c15a2611a34c5965edf93638553775f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/device/dram/ddr2.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c
index 326b1410fa..76524ceada 100644
--- a/src/device/dram/ddr2.c
+++ b/src/device/dram/ddr2.c
@@ -181,17 +181,20 @@ static u32 spd_decode_tRR_time(u8 c)
{
switch (c) {
default:
- case 0:
+ printk(BIOS_WARNING,
+ "Unknown tRR value, using default of 15.6us.");
+ /* Fallthrough */
+ case 0x80:
return 15625 << 8;
- case 1:
+ case 0x81:
return 15625 << 6;
- case 2:
+ case 0x82:
return 15625 << 7;
- case 3:
+ case 0x83:
return 15625 << 9;
- case 4:
+ case 0x84:
return 15625 << 10;
- case 5:
+ case 0x85:
return 15625 << 11;
}
}