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authorSubrata Banik <subrata.banik@intel.com>2020-07-05 19:13:15 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-07-09 12:44:26 +0000
commit8104effa0dc25bac4693e8d76c1e10039dd47bad (patch)
treeedc8e60e8acc569b90df57145458801ff670d403
parent96dec04207604fdd58ab2f76f8667542c03902e4 (diff)
downloadcoreboot-8104effa0dc25bac4693e8d76c1e10039dd47bad.tar.xz
mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
Refer to commit 7736bfc TEST=Able to build and boot TGLRVP. Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb2
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb2
-rw-r--r--src/soc/intel/tigerlake/chip.h10
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params.c3
4 files changed, 2 insertions, 15 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 401077229a..1396d3ac82 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -38,8 +38,6 @@ chip soc/intel/tigerlake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
- register "PrmrrSize" = "0x10000000"
-
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[8]" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index d095ff39c9..c3e41a2644 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -38,8 +38,6 @@ chip soc/intel/tigerlake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
- register "PrmrrSize" = "0x10000000"
-
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[8]" = "1"
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 26ed64e0f1..fee7105245 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -192,16 +192,6 @@ struct soc_intel_tigerlake_config {
/* Enable C6 DRAM */
uint8_t enable_c6dram;
- /*
- * PRMRR size setting with below options
- * Disable: 0x0
- * 32MB: 0x2000000
- * 64MB: 0x4000000
- * 128 MB: 0x8000000
- * 256 MB: 0x10000000
- * 512 MB: 0x20000000
- */
- uint32_t PrmrrSize;
uint8_t PmTimerDisabled;
/*
* SerialIO device mode selection:
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 1f60b52656..662ca06928 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -4,6 +4,7 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <fsp/util.h>
+#include <intelblocks/cpulib.h>
#include <soc/gpio_soc_defs.h>
#include <soc/iomap.h>
#include <soc/msr.h>
@@ -63,7 +64,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
sizeof(config->PcieClkSrcClkReq));
- m_cfg->PrmrrSize = config->PrmrrSize;
+ m_cfg->PrmrrSize = get_prmrr_size();
m_cfg->EnableC6Dram = config->enable_c6dram;
/* Disable BIOS Guard */
m_cfg->BiosGuard = 0;