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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-07 12:00:31 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-14 18:13:24 +0000 |
| commit | ffa520fc13da3504efb2e9a8d50f5fbd91580a09 (patch) | |
| tree | 43d218a8382f4f75cfb4fed9c7128f7e57095590 | |
| parent | 1cfafe25e37d3a396a19bfe524af16284ff41070 (diff) | |
| download | coreboot-ffa520fc13da3504efb2e9a8d50f5fbd91580a09.tar.xz | |
intel/sandybridge,bd82x6x: Move enable_smbus() call
Change-Id: Icc6b572fea0c2097a7ed19b3f76c1e658cf32a9a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch.c | 3 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 079e1b13ba..7d1c019207 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -82,9 +82,6 @@ void mainboard_romstage_entry(void) mainboard_early_init(s3resume); - /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - post_code(0x39); perform_raminit(s3resume); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index b19216b9ec..6f06a57129 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -327,4 +327,7 @@ void early_pch_init(void) pch_enable_gbe(); setup_pch_gpios(&mainboard_gpio_map); + + if (ENV_ROMSTAGE) + enable_smbus(); } |