diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2021-05-13 11:25:59 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-18 10:09:52 +0000 |
| commit | a7bf0df24f7aca50309232d185366eb94355f34f (patch) | |
| tree | d1148ed2c665400f4c4dae040668f0c1b04e8d0f | |
| parent | 8e7facf3437d633af747f6163cd66525ea14860e (diff) | |
| download | coreboot-a7bf0df24f7aca50309232d185366eb94355f34f.tar.xz | |
mb/google/brya: Enable HECI1 communication
The patch enables HECI1 interface to allow OS applications to communicate
with CSE.
TEST=Verify PCI device 0:16.0 exposed in the lspci output
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54210
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 16678cb816..5f736719ff 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -25,6 +25,9 @@ chip soc/intel/alderlake .tdp_pl2_override = 55, }" + # Enable heci communication + register "HeciEnabled" = "1" + # This disabled autonomous GPIO power management, otherwise # old cr50 FW only supports short pulses; need to clarify # the minimum PCH IRQ pulse width with Intel, b/180111628 |