diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-03-24 16:49:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-03-27 04:23:31 +0000 |
| commit | f9650771d3cb7e0244ef6caa5b7f7c67d5425a40 (patch) | |
| tree | 28a29fb3caf822edb341e0bcd6055246b3bacfe1 | |
| parent | 2ccc0a4d9fc91a57e1dec8913e6d999402e927a2 (diff) | |
| download | coreboot-f9650771d3cb7e0244ef6caa5b7f7c67d5425a40.tar.xz | |
mb/intel/adlrvp: Allow GPIO PM override to disable dynamic GPIO PM
This patch allows overriding GPIO PM miscconfig register for each
GPIO community to avoid dynamic clock gating.
TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0]
are set to '0'.
Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index f78fe2c3ee..cade987313 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -40,6 +40,16 @@ chip soc/intel/alderlake register "gen3_dec" = "0x00fc0901" register "gen4_dec" = "0x000c0081" + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + register "PrmrrSize" = "0" # Enable PCH PCIE RP 5 using CLK 2 |