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| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2020-05-28 21:16:34 +0800 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-06-24 12:43:20 +0000 |
| commit | ab3947a021c8fc5cde16875e79481555fd406a82 (patch) | |
| tree | 7ba719592ce7fcce9eaea597be4d8eb192e192f5 | |
| parent | 34053fab2163f9acb2d0abab565edbc08c362573 (diff) | |
| download | coreboot-ab3947a021c8fc5cde16875e79481555fd406a82.tar.xz | |
soc/amd/picasso: Add UPD xhci0_force_gen1
Adding xhci0_force_gen1 UPD to force USB3 port to gen1.
BUG=b:156314787
BRANCH=trembyle-bringup
TEST=Build.
Cq-Depend: chrome-internal:3013435
Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2217662
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42216
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/fsp_params.c | 7 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index e52751a2eb..f5fbe0fc2e 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -103,6 +103,8 @@ struct soc_amd_picasso_config { SD_EMMC_EMMC_HS400, SD_EMMC_EMMC_HS300, } sd_emmc_config; + + uint8_t xhci0_force_gen1; }; typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 67fe7d8e97..9decbbf57b 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -95,6 +95,12 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg) fill_ddi_descriptors(scfg, fsp_ddi, num_ddi); } +static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg, + const struct soc_amd_picasso_config *cfg) +{ + scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; +} + void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { const struct soc_amd_picasso_config *cfg; @@ -103,4 +109,5 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) cfg = config_of_soc(); fsps_update_emmc_config(scfg, cfg); fsp_fill_pcie_ddi_descriptors(scfg); + fsp_usb_oem_customization(scfg, cfg); } |