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| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-05-05 13:54:27 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-10 18:31:04 +0000 |
| commit | 9fb3d792be3319cf232ac6e3adfef0a44996a350 (patch) | |
| tree | 381fb2a780d20af1c3fdf44876eda65282384405 | |
| parent | 214c719eed83967b8f0564feca65eebb3d83f5bc (diff) | |
| download | coreboot-9fb3d792be3319cf232ac6e3adfef0a44996a350.tar.xz | |
mb/google/dedede: Enable S0ix support
Change-Id: I4cadfe69e36f959b54e374800c32629a7481ea94
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 0b69f7d5cf..8b68beb8c3 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -119,6 +119,9 @@ chip soc/intel/jasperlake # SD card power enable polarity register "SdCardPowerEnableActiveHigh" = "1" + # Enable S0ix support + register "s0ix_enable" = "1" + # Display related UPDs # Select eDP for port A register "DdiPortAConfig" = "1" |