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authorFelix Held <felix-coreboot@felixheld.de>2021-05-07 21:23:21 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-05-08 19:35:40 +0000
commit07eb01bc02ac121fb0a208c8f6a53a8123691c93 (patch)
tree77ffd1d93fd8f24849606fe05b38c1fb24e427d8 /Documentation
parentcd922f528fb55dbe512927107d282ef1a05185dc (diff)
downloadcoreboot-07eb01bc02ac121fb0a208c8f6a53a8123691c93.tar.xz
doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne addition
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I72a9056edfddb4e2cd2e6412cb5ea72cf965f9c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53924 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/releases/coreboot-4.14-relnotes.md9
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diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md
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--- a/Documentation/releases/coreboot-4.14-relnotes.md
+++ b/Documentation/releases/coreboot-4.14-relnotes.md
@@ -52,4 +52,13 @@ scenarios.
Significant changes
-------------------
+### AMD SoC cleanup and initial Cezanne APU support
+
+There's initial support for the AMD Cezanne APUs in the tree. This code
+hasn't started as a copy of the previous generation, but was based on a
+slightly modified version of the example/min86 SoC. During the cleanup
+of the existing Picasso SoC code the common parts of the code were
+moved to the common AMD SoC code, so that they could be used by the
+Cezanne code instead of adding another slightly different copy.
+
### Add significant changes here