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| author | Philipp Hug <philipp@hug.cx> | 2018-07-11 13:22:34 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-10 15:05:11 +0000 |
| commit | ea81928e948a01dde897b90e8e7454a71d9c0788 (patch) | |
| tree | 082c4b2fc86f3f60fd4b084742109525bf5becf5 /Documentation | |
| parent | 3b8ef2b01d80124982155620dec283ecc91cb221 (diff) | |
| download | coreboot-ea81928e948a01dde897b90e8e7454a71d9c0788.tar.xz | |
soc/sifive/fu540: Add driver for OTP memory
Provides minimal functionality to read the SOC s/n from the NeoFuse
one time programmable memory.
Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/mainboard/sifive/hifive-unleashed.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md index 62ee82401c..c5c015ddc1 100644 --- a/Documentation/mainboard/sifive/hifive-unleashed.md +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -18,7 +18,7 @@ The following things are still missing from this coreboot port: - Placing the ramstage in DRAM - Starting the U54 cores - FU540 PIN configuration and GPIO access macros -- FU540 OTP driver and serial number read-out +- Provide serial number to payload (e.g. in device tree) - Support for booting Linux on RISC-V |