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| author | Furquan Shaikh <furquan@google.com> | 2014-08-27 12:16:16 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-21 13:35:42 +0100 |
| commit | 635b45d60878887fba7425f61870cf2a9a6f3102 (patch) | |
| tree | 39eeec5d39550823157390b162bf056e125fbf7e /payloads/libpayload/arch/arm64/cache.c | |
| parent | 3b1ee0387c70f0b31307f50a5efa5a2b584a3635 (diff) | |
| download | coreboot-635b45d60878887fba7425f61870cf2a9a6f3102.tar.xz | |
libpayload arm64: Add library helpers
Add library helpers to access standard arm64 registers. This library also
provides functions to directly read/write register based on current el. So, rest
of the code doesnt need to keep checking the el and call appropriate function
based on that.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Libpayload and depthcharge compile successfully for ryu
Change-Id: Ibc0ca49f158362d4b7ab2045bf0fbd58ada79360
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ca6da580cb51b4c23abdaf04fee2785e5780510
Original-Change-Id: I9b63e04aa26a98bbeb34fdef634776d49454ca8d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214575
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8784
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads/libpayload/arch/arm64/cache.c')
| -rw-r--r-- | payloads/libpayload/arch/arm64/cache.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c index 05d6fb20ca..e89d49e4c8 100644 --- a/payloads/libpayload/arch/arm64/cache.c +++ b/payloads/libpayload/arch/arm64/cache.c @@ -34,6 +34,7 @@ #include <stdint.h> #include <arch/cache.h> +#include <arch/lib_helpers.h> void tlb_invalidate_all(void) { @@ -60,7 +61,7 @@ unsigned int dcache_line_bytes(void) if (line_bytes) return line_bytes; - ccsidr = read_ccsidr(); + ccsidr = raw_read_ccsidr_el1(); /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */ line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */ line_bytes *= sizeof(unsigned int); /* bytes per word */ @@ -126,18 +127,18 @@ void dcache_mmu_disable(void) uint32_t sctlr; dcache_clean_invalidate_all(); - sctlr = read_sctlr_el3(); + sctlr = raw_read_sctlr_el3(); sctlr &= ~(SCTLR_C | SCTLR_M); - write_sctlr_el3(sctlr); + raw_write_sctlr_el3(sctlr); } void dcache_mmu_enable(void) { uint32_t sctlr; - sctlr = read_sctlr_el3(); + sctlr = raw_read_sctlr_el3(); sctlr |= SCTLR_C | SCTLR_M; - write_sctlr_el3(sctlr); + raw_write_sctlr_el3(sctlr); } void cache_sync_instructions(void) |