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authorXiang Wang <wxjstz@126.com>2018-08-29 17:21:19 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-09-05 10:04:57 +0000
commit21ed107958b3a2525f01875162d5a83a7900d4b4 (patch)
treea598872bb0270788b51f748f7f5bc3e3e8abf282 /src/arch/riscv/include
parent384e9aed8c477922c960e2cbd429bd3a15b371de (diff)
downloadcoreboot-21ed107958b3a2525f01875162d5a83a7900d4b4.tar.xz
riscv: add entry assembly file for RAMSTAGE
RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling needs to be moved to ddr memory. So add a assembly file to do this. Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/riscv/include')
-rw-r--r--src/arch/riscv/include/arch/header.ld4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld
index 3e078d8b90..4b1104778c 100644
--- a/src/arch/riscv/include/arch/header.ld
+++ b/src/arch/riscv/include/arch/header.ld
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <rules.h>
+
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_ARCH(riscv)
@@ -21,7 +23,7 @@ PHDRS
to_load PT_LOAD;
}
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK || ENV_RAMSTAGE
ENTRY(_start)
#else
ENTRY(stage_entry)