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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-12-23 07:22:59 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-12-30 12:30:55 +0000 |
| commit | 1c105903078f85dd1be805c737b4e4da6dea0618 (patch) | |
| tree | e5ea20e0c52aafe2850c6df8c310378cc2bc5e47 /src/arch/x86/bootblock_romcc.S | |
| parent | 3ba79b319ef5d47b0d16482a254de7c5c740e415 (diff) | |
| download | coreboot-1c105903078f85dd1be805c737b4e4da6dea0618.tar.xz | |
arch/x86: Use a common timestamp.inc with romcc bootblocks
The same file was replicated three times for certain
soc/intel bootblocks, yet there are no indications or need to do
chipset-specific initialisation.
There is no harm in storing the TSC values in MMX registers
even when they would not be used.
Change-Id: Iec6fa0889f5887effca1d99ef830d383fb733648
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/arch/x86/bootblock_romcc.S')
| -rw-r--r-- | src/arch/x86/bootblock_romcc.S | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S index 6c1723a4c1..bfcc1e61a9 100644 --- a/src/arch/x86/bootblock_romcc.S +++ b/src/arch/x86/bootblock_romcc.S @@ -19,7 +19,7 @@ * - reset16.inc: the reset vector * - entry16.inc: protected mode setup * - entry32.inc: segment descriptor setup - * - CONFIG_CHIPSET_BOOTBLOCK_INCLUDE: chipset-specific initialization + * - timestamp.inc: store TSC in MMX registers * - generated/bootblock.inc: ROMCC part of the bootblock * * This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it @@ -35,9 +35,7 @@ #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> -#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE -#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE -#endif +#include <arch/x86/timestamp.inc> #if IS_ENABLED(CONFIG_SSE) #include <cpu/x86/sse_enable.inc> |