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author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/cpu/amd/agesa/family15tn/udelay.c | |
parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
download | coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/cpu/amd/agesa/family15tn/udelay.c')
-rw-r--r-- | src/cpu/amd/agesa/family15tn/udelay.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c index 3d40fc3b33..7ff4c5c7a8 100644 --- a/src/cpu/amd/agesa/family15tn/udelay.c +++ b/src/cpu/amd/agesa/family15tn/udelay.c @@ -21,6 +21,7 @@ */ #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include <cpu/x86/tsc.h> #include <delay.h> #include <stdint.h> @@ -36,11 +37,11 @@ void udelay(uint32_t us) tsc_start = rdtscll(); /* Get the P-state. This determines which MSR to read */ - msr = rdmsr(0xc0010063); + msr = rdmsr(PS_STS_REG); pstate_idx = msr.lo & 0x07; /* Get FID and VID for current P-State */ - msr = rdmsr(0xc0010064 + pstate_idx); + msr = rdmsr(PSTATE_0_MSR + pstate_idx); /* Extract the FID and VID values */ fid = msr.lo & 0x3f; |