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| author | Zheng Bao <zheng.bao@amd.com> | 2011-03-28 04:29:14 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2011-03-28 04:29:14 +0000 |
| commit | 2ca2f177245fdfa34ae7bd732052c8984e2b8b7d (patch) | |
| tree | b6852663c5c29001ed76241c73b5c7d135510a1d /src/cpu/amd/socket_C32/Kconfig | |
| parent | c3422235b14d97c16bd13113c522827d1cfda9b4 (diff) | |
| download | coreboot-2ca2f177245fdfa34ae7bd732052c8984e2b8b7d.tar.xz | |
Add AMD C32 support.
It is based on other existing Fam10 code.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/socket_C32/Kconfig')
| -rw-r--r-- | src/cpu/amd/socket_C32/Kconfig | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig new file mode 100644 index 0000000000..7ffa374962 --- /dev/null +++ b/src/cpu/amd/socket_C32/Kconfig @@ -0,0 +1,42 @@ +config CPU_AMD_SOCKET_C32 + bool + select CPU_AMD_MODEL_10XXX + select HT3_SUPPORT + select PCI_IO_CFG_EXT + select CACHE_AS_RAM + +config CPU_SOCKET_TYPE + hex + default 0x14 + depends on CPU_AMD_SOCKET_C32 + +config EXT_RT_TBL_SUPPORT + bool + default n + depends on CPU_AMD_SOCKET_C32 + +config EXT_CONF_SUPPORT + bool + default n + depends on CPU_AMD_SOCKET_C32 + +config CBB + hex + default 0x0 + depends on CPU_AMD_SOCKET_C32 + +config CDB + hex + default 0x18 + depends on CPU_AMD_SOCKET_C32 + +config XIP_ROM_BASE + hex + default 0xfff80000 + depends on CPU_AMD_SOCKET_C32 + +config XIP_ROM_SIZE + hex + default 0x80000 + depends on CPU_AMD_SOCKET_C32 + |