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| author | Martin Roth <gaumless@gmail.com> | 2017-10-15 15:06:48 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-15 23:25:12 +0000 |
| commit | 264566c177dac98e67c2a4765fe08c5d8de10753 (patch) | |
| tree | 34cfe5ba3958d14dd976bd7f2a2fb58a3920c74d /src/cpu/intel/ep80579/Kconfig | |
| parent | f6af8943e23b8ffa27df6ddb8e4a654387be0cb6 (diff) | |
| download | coreboot-264566c177dac98e67c2a4765fe08c5d8de10753.tar.xz | |
Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M
Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton
Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel/ep80579/Kconfig')
| -rw-r--r-- | src/cpu/intel/ep80579/Kconfig | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig deleted file mode 100644 index dc19ae1c30..0000000000 --- a/src/cpu/intel/ep80579/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -config CPU_INTEL_EP80579 - bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SSE - select SUPPORT_CPU_UCODE_IN_CBFS - -if CPU_INTEL_EP80579 - -# These are just dummy values to keep build happy. -# This CPU does not have tested cache_as_ram.inc. - -config DCACHE_RAM_BASE - hex - default 0xfefc0000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - -endif |