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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-15 06:07:55 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 00:18:28 +0200 |
| commit | 465eff61f4f0f730476aa7afe8819f1e6b118068 (patch) | |
| tree | 4ae32266340d37f38103e5275ad4c9e1dce82d88 /src/cpu/intel/haswell | |
| parent | bec853e9ad6a0734764b9179e0558bbf149b7b28 (diff) | |
| download | coreboot-465eff61f4f0f730476aa7afe8819f1e6b118068.tar.xz | |
Fix some cbmem.h includes
Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15196
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/cache_as_ram.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 2 |
2 files changed, 1 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index ddbffbbc60..e09e74b6c2 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -17,7 +17,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -#include <cbmem.h> /* The full cache-as-ram size includes the cache-as-ram portion from coreboot * and the space used by the reference code. These 2 values combined should diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9932a508e5..9c08aa16ba 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -28,7 +28,7 @@ #include <arch/stages.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> -#include <cbfs.h> +#include <cbmem.h> #include <romstage_handoff.h> #include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> |