diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-07-31 23:47:09 +0300 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2012-08-27 15:39:29 +0200 |
| commit | 0a78f91fa378879ee0bd202aca3c839eed6c24be (patch) | |
| tree | 5ad1aaf726bd20aa8eeea5d9bba138b3a0c1cb7b /src/cpu/intel/model_106cx | |
| parent | c33f1e9261adbe3921d305274e34ddab9101bc4e (diff) | |
| download | coreboot-0a78f91fa378879ee0bd202aca3c839eed6c24be.tar.xz | |
Intel model_106cx: change CAR to HT-capable
There are hyper-threading Atom CPUs, those would not enable L2
cache with model_6ex CAR code. Switch to code that can handle
different number of threads and cores.
Change-Id: I57328c231f8998f45f7b0d26c63b24585f8476dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1384
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: James Laird <jhl@mafipulation.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_106cx')
| -rw-r--r-- | src/cpu/intel/model_106cx/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_106cx/Makefile.inc | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 7a75ec1ba3..e26bf1fea5 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -3,6 +3,7 @@ config CPU_INTEL_MODEL_106CX select SMP select SSE2 select UDELAY_LAPIC + select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 018febc621..0b506b3807 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,4 +1,4 @@ driver-y += model_106cx_init.c subdirs-y += ../../x86/name -cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc |