diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2017-11-23 21:23:44 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-11-30 17:21:17 +0000 |
| commit | 242ea84b017b7f2812a4a1ba4b4996e5f1bb35ab (patch) | |
| tree | bd104e859220d84d30f56c3acb689ff7e0ca17b9 /src/cpu/intel/model_6ex | |
| parent | 3df9dbe8864adf6d41df2fe617c8818d1bad9d42 (diff) | |
| download | coreboot-242ea84b017b7f2812a4a1ba4b4996e5f1bb35ab.tar.xz | |
intel: Replace msr(0x198) with msr(IA32_PERF_STATUS)
Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/22585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/model_6ex')
| -rw-r--r-- | src/cpu/intel/model_6ex/model_6ex_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 6e5b339444..96830c495d 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -86,7 +86,7 @@ static void configure_misc(void) wrmsr(IA32_MISC_ENABLE, msr); // set maximum CPU speed - msr = rdmsr(IA32_PERF_STS); + msr = rdmsr(IA32_PERF_STATUS); int busratio_max = (msr.hi >> (40-32)) & 0x1f; msr = rdmsr(IA32_PLATFORM_ID); |