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authorEric Biederman <ebiederm@xmission.com>2004-10-14 19:29:29 +0000
committerEric Biederman <ebiederm@xmission.com>2004-10-14 19:29:29 +0000
commitfcd5ace00b333ce31b11b02a2243dfbf39307f10 (patch)
treed686d752ccea9b185b0008c70d8523749b26e2dd /src/cpu/x86/sse
parent98e619b1cefcb9871185f4cc3db85fa430dcdbce (diff)
downloadcoreboot-fcd5ace00b333ce31b11b02a2243dfbf39307f10.tar.xz
- Add new cvs code to cvs
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/x86/sse')
-rw-r--r--src/cpu/x86/sse/Config.lb0
-rw-r--r--src/cpu/x86/sse/disable_sse.inc18
-rw-r--r--src/cpu/x86/sse/enable_sse.inc14
3 files changed, 32 insertions, 0 deletions
diff --git a/src/cpu/x86/sse/Config.lb b/src/cpu/x86/sse/Config.lb
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/cpu/x86/sse/Config.lb
diff --git a/src/cpu/x86/sse/disable_sse.inc b/src/cpu/x86/sse/disable_sse.inc
new file mode 100644
index 0000000000..a18ea18643
--- /dev/null
+++ b/src/cpu/x86/sse/disable_sse.inc
@@ -0,0 +1,18 @@
+ /*
+ * Put the processor back into a reset state
+ * with respect to the xmm registers.
+ */
+
+ xorps %xmm0, %xmm0
+ xorps %xmm1, %xmm1
+ xorps %xmm2, %xmm2
+ xorps %xmm3, %xmm3
+ xorps %xmm4, %xmm4
+ xorps %xmm5, %xmm5
+ xorps %xmm6, %xmm6
+ xorps %xmm7, %xmm7
+
+ /* Disable sse instructions */
+ movl %cr4, %eax
+ andl $~(3<<9), %eax
+ movl %eax, %cr4
diff --git a/src/cpu/x86/sse/enable_sse.inc b/src/cpu/x86/sse/enable_sse.inc
new file mode 100644
index 0000000000..95724b71f7
--- /dev/null
+++ b/src/cpu/x86/sse/enable_sse.inc
@@ -0,0 +1,14 @@
+ /* preserve BIST in %eax */
+ movl %eax, %ebp
+
+ /*
+ * Enable the use of the xmm registers
+ */
+
+ /* Enable sse instructions */
+ movl %cr4, %eax
+ orl $(1<<9), %eax
+ movl %eax, %cr4
+
+ movl %ebp, %eax
+