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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-11-27 22:29:44 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-29 09:00:16 +0000
commita3ce27d3dd65fd937ed9a8c5b9230bcace5b356f (patch)
tree2650ed979bbb4f13d3255b36cab3ce834245205f /src/cpu
parentf3db2aea85623cbbacdeb29cd175005cfdb05189 (diff)
downloadcoreboot-a3ce27d3dd65fd937ed9a8c5b9230bcace5b356f.tar.xz
cpu/amd/{agesa,pi}/Kconfig: select SSE2
SSE2 instructions are supported by family14 and newer. SSE will be automatically enabled in bootblock_crt0 for platforms that migrate to C bootblock. Because of that family specific CAR setup may avoid additional code. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I19f1793112439f0c706ebb066f9807364ad8c5a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37292 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/agesa/Kconfig1
-rw-r--r--src/cpu/amd/pi/Kconfig1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index ddfe707d79..9956579c69 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -29,6 +29,7 @@ config CPU_AMD_AGESA
select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME
select SMM_ASEG
select NO_FIXED_XIP_ROM_SIZE
+ select SSE2
if CPU_AMD_AGESA
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index d18f873332..728c7b1ce7 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -28,6 +28,7 @@ config CPU_AMD_PI
select SPI_FLASH if HAVE_ACPI_RESUME
select SMM_ASEG
select NO_FIXED_XIP_ROM_SIZE
+ select SSE2
if CPU_AMD_PI