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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-03-18 15:26:48 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-03-27 08:26:16 +0000
commitf5cf60f25b8c77e0c90094e3326c5bc0e37cb383 (patch)
tree63967d01ebab0c1cdb41c58d4c52fea1d45616a4 /src/cpu
parent12724d6ad6fd6ab0ca8ea5d258c0ca7cce807441 (diff)
downloadcoreboot-f5cf60f25b8c77e0c90094e3326c5bc0e37cb383.tar.xz
Move calls to quick_ram_check() before CBMEM init
After raminit completes, do a read-modify-write test just below CBMEM top address. If test fails, die(). Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/haswell/romstage.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index ee87effc87..0426bb4cea 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -20,7 +20,6 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
-#include <lib.h>
#include <timestamp.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
@@ -121,9 +120,6 @@ void romstage_common(const struct romstage_params *params)
intel_early_me_status();
- quick_ram_check();
- post_code(0x3e);
-
if (!wake_from_s3) {
cbmem_initialize_empty();
/* Save data returned from MRC on non-S3 resumes. */