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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-02-21 12:42:51 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-03-09 19:33:08 +0100 |
| commit | bf62b2ddb074c22738b5c9e8dc6c1ecb5d2e5e97 (patch) | |
| tree | fd9de8c29a036c266ed085350359fdf573b999b5 /src/device/Kconfig | |
| parent | 991a71d55c3099b01acb4b42e97d72aa64816898 (diff) | |
| download | coreboot-bf62b2ddb074c22738b5c9e8dc6c1ecb5d2e5e97.tar.xz | |
AMD fam10: Drop PCI_BUS_SEGN_BITS
All boards in tree use 0. Looks like this is all work that was
never completed and tested.
We also have static setting sysconf.segbit=0 which would conflict
with PCI_BUS_SEGN_BITS>0.
Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support
to cover over 255 buses.
Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/device/Kconfig')
| -rw-r--r-- | src/device/Kconfig | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/device/Kconfig b/src/device/Kconfig index 42a68d296a..7f43888838 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -259,10 +259,6 @@ config PCIEXP_CLK_PM help Detect and enable Clock Power Management on PCIe. -config PCI_BUS_SEGN_BITS - int - default 0 - config EARLY_PCI_BRIDGE bool "Early PCI bridge" depends on PCI |